JP2019213166A - Signal processing apparatus and method - Google Patents

Abstract

To reduce the influence of duty deviation during signal processing.SOLUTION: A signal processing device that processes a differential input signal includes a receiving unit that amplifies the input differential input signal and outputs a differential output signal, a first edge detection circuit that detects a transition in one direction of one signal of the differential output signals and outputs a first edge detection signal in which a signal value is switched according to the detection of the transition, a second edge detection circuit that detects a transition in the one direction of the other signal of the differential output signals and outputs a second edge detection signal in which the signal value is switched according to the detection of the transition, and a generation circuit that generates an output signal corresponding to the differential input signal on the basis of the first edge detection signal and the second edge detection signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a signal processing apparatus and method, and more particularly to a signal processing technique for processing a differential signal in serial transmission.

  As semiconductor integrated circuits have higher performance, larger capacity, and higher speed, there is a need for higher speed data transmission between semiconductor chips. In a receiving circuit for data transmission that has been speeded up, fluctuations in the time axis direction of the waveform cause a deterioration in reception characteristics (for example, bit error rate) of data transmission. Causes of fluctuation in the time axis direction include, for example, a noise component in the time axis direction called random jitter, or a duty shift due to a difference between the rise time and fall time of the data waveform. The cause of the duty shift in the receiving circuit includes, for example, a difference in driving power of the PMOS / NMOS transistor in the electronic circuit, a mismatch in the differential single circuit, and the like caused by fluctuations in power supply voltage and temperature. In particular, when high-speed transmission exceeds several Gbps, fluctuation in the time axis direction in picosecond (ps) units leads to deterioration of reception characteristics.

  Patent Document 1 proposes a configuration in which a waveform is formed by using only the rising edge or the falling edge of a differential signal that is an input signal as a receiving circuit for reducing such a duty shift. In Patent Document 1, a rising (or falling) transition of each differential signal is detected to generate a short pulse, and the short pulse is input to an SR (set reset) latch circuit to generate a waveform. . According to Patent Document 1, since only the rising edge (or falling edge) of a differential signal is detected and a waveform is generated, the influence of a duty deviation caused by the delay difference between the rising edge and the falling edge of the differential signal is reduced.

JP 2003-037484 A

  However, in Patent Document 1, a short pulse is generated for edge detection. Therefore, it is necessary to generate a short pulse that operates at a speed higher than the transmission rate, and it is difficult to adapt to high-speed transmission. In addition, when the configuration of Patent Document 1 is used, a duty shift generated in the SR latch circuit itself of the waveform generation circuit can be a cause of reception characteristic deterioration.

  It is an object of the present invention to reduce the influence of duty deviation during signal processing.

A receiving circuit according to one embodiment of the present invention has the following configuration. That is,
A signal processing device for processing a differential input signal,
Receiving means for amplifying the input differential input signal and outputting a differential output signal;
First edge detection means for detecting a transition of one signal of the differential output signal in one direction and outputting a first edge detection signal whose signal value is switched according to the detection of the transition;
Second edge detection means for detecting a transition of the other signal of the differential output signal in the one direction and outputting a second edge detection signal whose signal value is switched in accordance with the detection of the transition;
Generating means for generating an output signal corresponding to the differential input signal based on the first edge detection signal and the second edge detection signal.

  According to the present invention, the influence of duty deviation during signal processing is reduced.

The block diagram which shows the structural example of the receiving circuit which concerns on 1st Embodiment. The figure which shows the signal waveform in the receiver circuit which concerns on 1st Embodiment. The block diagram which shows the structural example of the receiving circuit which concerns on 2nd Embodiment. The figure which shows the signal waveform in the receiver circuit which concerns on 2nd Embodiment. The block diagram which shows the structural example of the receiving circuit which concerns on 3rd Embodiment. The figure which shows the signal waveform in the receiver circuit which concerns on 3rd Embodiment. The figure which shows the signal waveform in the receiver circuit which concerns on 3rd Embodiment. The block diagram which shows the structural example of the phase calculation circuit which concerns on 4th Embodiment. The figure which shows the signal waveform in the receiver circuit which concerns on 4th Embodiment.

  Several embodiments of the present invention will be described below with reference to the accompanying drawings. The following embodiments do not limit the present invention according to the claims, and all combinations of features described in the following embodiments are not necessarily essential to the solution means of the present invention. Absent.

<First Embodiment>
Hereinafter, a receiving circuit as an example of a signal processing apparatus for processing a differential input signal according to the first embodiment will be described. FIG. 1 is a block diagram illustrating a configuration example of a receiving circuit 100 according to the first embodiment. The reception circuit 100 receives the differential input signal 120 output from the transmission circuit 10, generates an output signal 125 corresponding to the differential input signal 120, and outputs the output signal 125.

  The receiving unit 101 receives the differential input signal 120 transmitted from the transmission circuit 10, amplifies it, and outputs a differential output signal OUTP121 and a differential output signal OUTN122. Note that the transmission circuit 10 and the reception circuit 100 may be provided in separate devices, or may be provided in one device. In any case, signal transmission using a differential signal can be performed between the transmission circuit 10 and the reception circuit 100. For example, the receiving circuit 100 can be applied to high-speed serial transmission between devices connected by a cable and high-speed serial transmission in a bus connecting circuits in one device. It is also possible to perform source synchronous parallel transmission between the transmission circuit 10 and the reception circuit 100.

  The first edge detection circuit 102 detects a transition (for example, rising) in one direction of the differential output signal OUTP121 as an input signal, and generates a first edge detection signal 123 whose signal value switches according to the detection of the transition. Output. In the present embodiment, an example in which the first edge detection circuit 102 includes a D flip-flop (hereinafter, DFF 111a) is shown. The first edge detection circuit 102 of the present embodiment inputs the differential output signal OUTP121 as an input signal to the clock terminal (CL) of the DFF 111a, and inputs the inverted signal (QB) of the output to the data terminal (D). The first edge detection signal 123 (output Q) is output. As a result, the first edge detection signal 123 is a signal whose output is inverted (High and Low are switched) in response to the detection of the rising edge of the differential output signal OUTP121.

  The second edge detection circuit 103 detects a unidirectional transition (for example, rising) of the differential output signal OUTN122 as an input signal, and outputs a second edge detection signal 124 whose signal value is switched according to the detection of the transition. To do. In the present embodiment, as in the case of the first edge detection circuit 102, an example in which the second edge detection circuit 103 is configured by a D flip-flop (hereinafter referred to as DFF 111b) is shown. The second edge detection circuit 103 inputs the first edge detection signal 123 to the data terminal (D) of the DFF 111b, inputs the differential output signal OUTN122 to the clock terminal (CL) of the DFF 111b, and outputs the second edge detection signal 124 ( Q) is output. As a result, the second edge detection signal 124 reflects the state of the first edge detection signal 123 at that time according to the detection of the rising edge of the differential output signal OUTN122. In addition, although the first edge detection circuit 102 and the second edge detection circuit 103 of the present embodiment have shown an example in which the rising edge of the input signal is detected, a falling signal may be used. Further, the differential output signal OUTP121 may be input to the clock terminal of the DFF 111b, and the differential output signal OUTN122 may be input to the clock terminal of the DFF 111a.

  The generation circuit 104 is a circuit that generates and outputs an output signal 125 based on two edge detection signals of the first edge detection signal 123 and the second edge detection signal 124. The generation circuit 104 according to the first embodiment includes an exclusive OR (hereinafter referred to as XOR 112), and outputs an exclusive OR of the first edge detection signal 123 and the second edge detection signal 124 as an output signal 125.

  Next, the operation of the receiving circuit 100 for reducing the influence of duty deviation according to the first embodiment will be described. FIG. 2 is a timing chart for explaining the operation of the receiving circuit 100 according to the first embodiment. In the present embodiment, a duty shift occurs due to the delay difference between the rise and fall of the output of the receiving unit 101, and a duty shift occurs at the fall with reference to the rise of the differential output signal OUTP121 and the differential output signal OUTN122. An example is shown. In the present embodiment, the output signal 125 that is not affected by the duty deviation is generated by generating a waveform using only the rising edge (or only the falling edge) of the operation output signal of the receiving unit 101.

  The phase shift (jitter) in the time direction of the waveform includes “fixed jitter” that occurs due to semiconductor variations during manufacturing, and “random jitter” that occurs randomly due to noise during operation. In this embodiment, the influence of fixed jitter is reduced. In FIG. 2, the differential output signal OUTP121 rises at times T1 and T3 and falls at times T2 and T4. In the first embodiment, the differential output signal OUTP121 has an influence of duty shift on the falling edge of the signal, and the falling timing is shown to be fixedly shifted with respect to the times T2 and T4. Similarly, the differential output signal OUTN122 rises at times T2 and T4 and falls at times T1 and T3. In the first embodiment, the differential output signal OUTN122 has an effect of duty shift on the falling edge, and the falling timing is fixedly shifted with respect to the times T1 and T3.

  The differential output signal OUTP121 rises at times T1 and T3. The first edge detection circuit 102 inverts the first edge detection signal 123 when detecting the rising edge of the differential output signal OUTP121. Further, the differential output signal OUTN122 rises at times T2 and T4. The second edge detection circuit 103 holds the value of the first edge detection signal 123 in response to the detection of the rising edge of the differential output signal OUTN122, and outputs this as the second edge detection signal 124. The output signal 125 outputs an exclusive OR of the two signals of the first edge detection signal 123 and the second edge detection signal 124. That is, the output signal 125 becomes High when one of the first edge detection signal 123 and the second edge detection signal 124 is High and the other is Low, and becomes Low in other states.

  As described above, in the receiving circuit 100 of the first embodiment, the rising edges of the differential output signal OUTP121 and the differential output signal OUTN122 are detected to generate waveforms. As a result, the output signal 125 is generated without being affected by (or reducing the influence of) the duty shift that exists in one or both of the differential output signal OUTP121 and the differential output signal OUTN122.

  In the first embodiment, the first edge detection circuit 102 and the second edge detection circuit 103 are configured by using the DFF 111a and the DFF 111b, respectively, and the generation circuit 104 is configured by using the XOR 112. According to the configuration of the first embodiment, the first edge detection signal 123 and the second edge detection signal 124 do not transition faster than the differential input signal 120. Therefore, compared to a known duty correction circuit that detects an edge, generates a short pulse, and inputs the output to the SR latch circuit, this embodiment does not need to generate a high-speed signal and can easily increase the speed. is there. That is, the receiving circuit 100 of this embodiment has a circuit configuration suitable for high-speed input signals (high-speed serial transmission). As described above, according to the receiving circuit 100 of the first embodiment, the output signal 125 generated from the differential input signal 120 is not affected or reduced by the duty deviation generated in the receiving unit 101. Become.

  The configuration of the first embodiment is a circuit configuration based on the premise that rising and falling of two signals are alternately generated by two inputs like a differential signal, for example, and a configuration in which a transition continuously occurs on one side. The waveform cannot be generated.

Second Embodiment
In the first embodiment, even if the duty of either or both of the differential output signal OUTP121 and the differential output signal OUTN122 is lost in the receiving circuit 100, the difference in duty is detected by detecting the rising edge of the differential. An example to suppress is shown. On the other hand, in the first embodiment, the generation circuit 104 forms the output signal 125 by the exclusive OR (XOR) of the first edge detection signal 123 and the second edge detection signal 124. Also in the generation circuit 104, a duty shift occurs due to a difference in driving force between rising and falling edges. Such a deviation in duty in the generation circuit 104 affects reception characteristics in high-speed transmission in which the data rate exceeds several Gbps. Therefore, it is desirable to reduce the influence of the duty shift caused by the difference in driving force between the rise and fall of the signal of the generation circuit 104. Therefore, the second embodiment shows a circuit configuration that reduces or eliminates the influence of the duty deviation generated in the generation circuit 104 in addition to reducing or eliminating the influence of the duty deviation in the receiving unit 101.

  The deterioration of the reception characteristics due to the duty shift occurs when the input signal to be sampled by the clock has a duty shift. Since the timing of the signal sampled by the clock can be managed by the clock in the digital circuit, the duty deviation generated after sampling does not affect the reception characteristics if the timing management is correct. Therefore, in the second embodiment, the first edge detection signal 123 and the second edge detection signal 124 in which the duty deviation is reduced or eliminated are sampled with a clock, so that the influence of the duty deviation in the output signal of the generation circuit 104 is affected. Reduce or eliminate.

  Hereinafter, the receiving circuit 100 according to the second embodiment will be described with reference to FIG. FIG. 3 is a block diagram illustrating a configuration example of the receiving circuit 100 in the high-speed serial transmission as the signal processing device according to the second embodiment. The reception circuit 100 receives the differential signal output from the transmission circuit 10 (not shown) as the differential input signal 120 and outputs an output signal 125. In the receiving circuit 100 of the second embodiment shown in FIG. 3, the same reference numerals as those in FIG. 1 are assigned to components having the same functions as those of the first embodiment.

  As shown in FIG. 3, in the receiving circuit 100, a sampling circuit 105 is provided between the first edge detection circuit 102 and the second edge detection circuit 103 and the generation circuit 104. The sampling circuit 105 has a DFF 111 c that samples the first edge detection signal 123 with the clock 126 and outputs the first sampling signal 130. The sampling circuit 105 includes a DFF 111 d that samples the second edge detection signal 124 with the clock 126 and outputs the second sampling signal 131. The generation circuit 104 receives the first sampling signal 130 and the second sampling signal 131 as inputs, and outputs an exclusive OR (XOR 112) thereof as an output signal 125. In the second embodiment, the clock 126 is adjusted to rise at a timing at which the edge detection signal does not transition. An example of such clock phase adjustment will be described in detail in the third embodiment. In the second embodiment, the sampling circuit 105 samples the edge detection signal at the rising edge of the clock 126. However, the edge detection signal may be sampled at the falling edge of the clock 126.

  FIG. 4 is a timing chart showing the operation of the receiving circuit 100 according to the second embodiment. As in the first embodiment, the signal (value) of the first edge detection signal 123 is inverted in response to the detection of the rising edge of the differential output signal OUTP121 that rises at times T1 and T3. Further, the second edge detection signal 124 transitions to the value (state) of the first edge detection signal 123 in response to the detection of the rising edge of the differential output signal OUTN122 rising at the times T2 and T4. The first sampling signal 130 is a waveform obtained by the DFF 111c sampling the first edge detection signal 123 at the rising edge of the clock 126, and the waveform transitions at time T5 and T7 (the signal is inverted). The second sampling signal 131 is a waveform obtained by the DFF 111d sampling the second edge detection signal 124 at the rising edge of the clock 126, and the waveform transitions at times T6 and T8. The output signal 125 is an exclusive OR (output of the XOR 112) of two signals of the first sampling signal 130 and the second sampling signal 131. That is, the output signal 125 becomes High when one of the first sampling signal 130 and the second sampling signal 131 is High and the other is Low, and the output signal 125 becomes Low in the other state.

  As described at the beginning of the second embodiment, one of the factors that degrade the reception characteristics is a duty shift superimposed on a waveform at the time of sampling. On the other hand, in the second embodiment, the first edge detection signal 123 and the second edge detection signal 124 generated by the rising signal of the differential signal are sampled. That is, by sampling the signals (123, 124) in which the duty deviation is reduced or eliminated, the influence of the duty deviation is reduced or eliminated. The generation circuit 104 generates the waveform of the output signal after sampling with the clock 126, so that the influence of the duty deviation generated when the output signal of the reception circuit 100 is generated can be reduced.

  As described above, in the second embodiment, similarly to the first embodiment, the differential output signal OUTP121 and the differential output generated in the reception unit 101 by using only the rising edge (or only the falling edge) of the differential signal. The influence of the duty deviation of the signal OUTN122 is reduced or eliminated. In addition, in the second embodiment, the waveform of the output signal 125 is generated based on the signal after sampling the first edge detection signal 123 and the second edge detection signal 124. Thereby, according to the second embodiment, it is possible to further reduce or eliminate the influence of the duty deviation generated in the generation circuit 104 and improve the reception characteristics.

<Third Embodiment>
In the second embodiment, in addition to suppressing the influence of the duty deviation of the receiving unit 101 of the first embodiment, an example of a circuit configuration that reduces the influence of the duty deviation generated in the generation circuit 104 has been shown. In the second embodiment, a clock 126 used for sampling the first edge detection signal 123 and the second edge detection signal 124 is supplied from the outside of the reception circuit 100. In the third embodiment, an example will be described in which a circuit for generating a clock for sampling the first edge detection signal 123 and the second edge detection signal 124 is provided in the reception circuit 100.

  FIG. 5 is a block diagram illustrating a configuration example of a receiving circuit 100 as a signal processing device according to the third embodiment. The reception circuit 100 receives the differential input signal 120 output by high-speed serial transmission from the transmission circuit 10 (not shown), and outputs an output signal 125. In the receiving circuit 100 of the third embodiment (FIG. 5), blocks having the same functions as those of the receiving circuit 100 shown in the second embodiment (FIG. 3) are denoted by the same reference numerals as in FIG. It is.

The reception circuit 100 according to the third embodiment includes a phase calculation circuit 106 and a clock generation circuit 107 for generating and adjusting a clock for sampling the first edge detection signal 123 and the second edge detection signal 124. The sampling circuit 105 holds and outputs the value of the input signal at the rising or falling timing of the phase-adjusted clock (reproduced clock 152). The sampling circuit 105 performs the following four operations.
(1) The first edge detection signal 123 is sampled at the rising timing of the reproduction clock 152 and the first sampling signal 130 is output.
(2) The second edge detection signal 124 is sampled at the rising timing of the reproduction clock 152 and the second sampling signal 131 is output.
(3) The first edge detection signal 123 is sampled at the fall timing of the reproduction clock 152 and the third sampling signal 153 is output.
(4) The second edge detection signal 124 is sampled at the fall timing of the reproduction clock 152, and the fourth sampling signal 154 is output.

  The generation circuit 104 inputs the first sampling signal 130 and the second sampling signal 131 to the XOR 112a and outputs an output signal 125. Further, the generation circuit 104 inputs the third sampling signal 153 and the fourth sampling signal 154 to the XOR 112b and outputs the phase calculation signal 155. The output signal 125 is a signal generated from the differential input signal 120 with the recovered clock 152 as a reference, and the logic coincides with the differential input signal 120 when the clock recovery is operating correctly.

  The phase calculation circuit 106 calculates the phase relationship between the output signal 125 and the phase calculation signal 155 and outputs phase information 151 instructing to advance and delay the phase of the recovered clock 152. In the third embodiment, the phase relationship between the output signal 125 and the phase calculation signal 155 is that the two edge detection signals (the first edge detection signal 123 and the second edge detection signal 124) input to the sampling circuit 105 are reproduced. The phase relationship of the clock 152 is the same. Therefore, the phase information 151 has information on the phase relationship between the two edge detection signals input to the sampling circuit 105 and the recovered clock 152.

  The clock generation circuit 107 adjusts the phase of the recovered clock 152 based on the phase information 151 and outputs it. The clock generation circuit 107 can be composed of, for example, a loop filter and a voltage controlled oscillator. The clock generation circuit 107 of the third embodiment adjusts the phase of the recovered clock 152 so that it matches the two edge detection signals input to the sampling circuit 105 by the clock generation circuit 107.

  6 and 7 are timing charts showing the operation of the third embodiment. The timing chart of FIG. 6 shows an example in which the phase of the recovered clock 152 is advanced from the edge detection signal (123, 124). The timing chart of FIG. 7 shows an example in which the phase of the recovered clock 152 is delayed from the edge detection signals (123, 124). Hereinafter, differences from the second embodiment will be mainly described.

  6 and 7, the first sampling signal 130 is a waveform obtained by sampling the first edge detection signal 123 at the rising edge of the reproduction clock 152, and the waveform transitions at time T5 and T7 (the signal value is inverted). . The second sampling signal 131 is a waveform obtained by sampling the second edge detection signal 124 at the rising edge of the reproduction clock 152, and the waveform transitions at times T6 and T8 (the signal value is inverted). The third sampling signal 153 is a waveform obtained by sampling the first edge detection signal 123 at the falling edge of the reproduction clock 152, and the waveform transitions at times T2 and T9 (the signal value is inverted). The fourth sampling signal 154 is a waveform obtained by sampling the second edge detection signal 124 at the falling edge of the reproduction clock 152, and the waveform transitions at times T3 and T10 (the signal value is inverted).

  The generation circuit 104 inputs the first sampling signal 130 and the second sampling signal 131 to the XOR 112 a that outputs the exclusive OR of the two signals, and obtains the output of the XOR 112 a as the output signal 125. That is, the output signal 125 becomes High when either the first sampling signal 130 or the second sampling signal 131 is High and the other is Low. In addition, the generation circuit 104 inputs the third sampling signal 153 and the fourth sampling signal 154 to the XOR 112b that outputs the exclusive OR of the two signals, and obtains the output of the XOR 112b as the phase calculation signal 155. That is, the phase calculation signal 155 becomes High when one of the third sampling signal 153 and the fourth sampling signal 154 is High and the other is Low.

  Specifically, the phase relationship between the edge detection signal and the recovered clock 152 will be described below. The rising edge of the first edge detection signal 123 occurs in the period between T1 and T5, and the falling edge occurs in the period between T3 and T7. The rising edge of the second edge detection signal 124 occurs in the period between T2 and T6, and the falling edge occurs in the period between T4 and T8. The clock generation circuit 107 operates so as to match the falling signal of the recovered clock 152 with the transition of the two edge detection signals. Taking time T 1 as an example, it can be seen that the falling phase of the recovered clock 152 is advanced with respect to the first edge detection signal 123.

  At this time, when the first edge detection signal 123 is sampled at the fall of the reproduction clock 152, Low is held at the stage of time T1, and the third sampling signal rises at time T2, which is the subsequent fall timing. As described above, when the phase of the recovered clock 152 is advanced from the edge detection signal, the timing for detecting the transition is delayed at the fall of the recovered clock 152. As a result, the phase of the phase calculation signal 155 is delayed as compared with the output signal 125 as shown in FIG.

  On the contrary, as shown in FIG. 7, when the phase of the recovered clock 152 is delayed compared to the edge detection signal, for example, when the rising edge of the first edge detection signal 123 is between the times T0 and T1, after the transition at T1 The third sampling signal 153 is obtained. Therefore, the third sampling signal 153 rises at T1, and as a result, the phase calculation signal 155 is in a phase earlier than the output signal 125. The phase calculation circuit 106 obtains the phase relationship between the edge detection signal and the reproduction clock 152 from the phase relationship between the output signal 125 and the phase calculation signal 155 and outputs it as phase information 151.

  As described above, according to the third embodiment, the first edge detection signal 123 and the second edge detection signal 124 in which the influence of the duty shift is reduced or eliminated are sampled by the reproduction clock 152. The duty deviation superimposed on the signal sampled by the reproduction clock 152, that is, the four sampling signals (130, 131, 153, 154) output from the sampling circuit 105 does not affect the reception characteristics. In addition, since the timing of the signal sampled by the reproduction clock 152 can be managed, the deviation of the duty caused by the output signal 125 and the phase calculation signal 155 does not affect the reception characteristics. Therefore, according to the third embodiment, it is possible to reduce or eliminate the deterioration of the reception characteristics due to the duty shift, and it is possible to reduce the influence of the duty shift in the phase adjustment of the recovered clock 152.

<Fourth embodiment>
In the fourth embodiment, a specific configuration example of the phase calculation circuit 106 shown in the third embodiment will be described. The phase calculation circuit 106 is a circuit that generates phase information 151 from the phase relationship between the output signal 125 and the phase calculation signal 155. In the fourth embodiment, a configuration using a configuration of a Bang-Bang type phase comparator is shown as a specific example of the phase calculation circuit 106. The Bang-Bang type phase comparator itself is a known technique. In the Bang-Bang type phase comparator, data is sampled at the rising edge and falling edge of the clock, and the phase is detected depending on the timing at which the data transitions.

  FIG. 8 is a diagram illustrating a circuit configuration example of the phase calculation circuit 106 according to the fourth embodiment. The phase calculation circuit 106 samples the output signal 125 and the phase calculation signal 155 with the reproduction clock 152 and outputs them as an output delay signal 180 and a phase calculation delay signal 181, respectively. The phase information DOWN signal 182 that is the output of the XOR 112c is an exclusive OR of the output signal 125 and the phase calculation delay signal 181, and becomes High when the phase of the recovered clock 152 is ahead of the edge detection signal. The phase information UP signal 183 that is the output of the XOR 112d is an exclusive OR of the output delay signal 180 and the phase calculation delay signal 181, and is a signal that becomes High when the phase of the reproduction clock 152 is delayed from the edge detection signal. is there.

  FIG. 9 is a diagram for explaining the operation of the receiving circuit 100 according to the fourth embodiment. FIG. 9A is a timing chart when the phase of the recovered clock 152 is advanced from the edge detection signal. Signals not shown in FIG. 9A (differential output signals, edge detection signals, etc.) are the same as those in FIG. FIG. 9B is a timing chart when the phase of the reproduction clock 152 is delayed from the edge detection signal. In FIG. 9B, signals not shown (differential output signals, edge detection signals, etc.) are the same as those in FIG.

  The output delay signal 180 is a signal obtained by delaying the output signal 125 by one period of the reproduction clock 152. The phase calculation delay signal 181 is a signal obtained by delaying the phase calculation signal 155 by a half cycle of the reproduction clock 152. The phase information DOWN signal 182 is an output of the exclusive OR (XOR 112c) of the two signals of the output signal 125 and the phase calculation delay signal 181. The phase information DOWN signal 182 becomes High when one of the output signal 125 and the phase calculation delay signal 181 is High and the other is Low, and becomes Low at other timings. The phase information UP signal 183 is an output of the exclusive OR (XOR 112d) of the two signals of the output delay signal 180 and the phase calculation delay signal 181. The phase information UP signal 183 becomes High when one of the output delay signal 180 and the phase calculation delay signal 181 is High and the other is Low, and becomes Low at other timings.

  As shown in FIG. 9A, when the phase of the recovered clock 152 is ahead of the edge detection signal, the output signal 125 and the phase calculation delay signal 181 are shifted. Therefore, the phase information DOWN signal 182 becomes High during a period in which the values of both signals do not match. Further, since the output delay signal 180 and the phase calculation delay signal 181 have the same waveform, the phase information UP signal 183 is Low. On the other hand, as shown in FIG. 9B, when the phase of the recovered clock 152 is delayed from the edge detection signal, the output delay signal 180 and the phase calculation delay signal 181 are shifted. Therefore, the phase information UP signal 183 becomes High during a period in which the values of both signals do not match. Further, since the output signal 125 and the phase calculation delay signal 181 have the same waveform, the phase information DOWN signal 182 becomes Low.

  The phase information 151 includes a phase information DOWN signal 182 and a phase information UP signal 183. The clock generation circuit 107 receives the phase information 151 and adjusts the phase of the recovered clock 152 to be delayed when the phase information DOWN signal 182 is High. Further, the clock generation circuit 107 adjusts so that the phase of the recovered clock 152 advances when the phase information UP signal 183 is High. By performing the above operation, the clock generation circuit 107 adjusts the phase of the recovered clock 152 (the fall of the recovered clock 152) to match the phase of the received data so that the transmitted data can be received. Thus, the reproduction clock 152 is adjusted to rise at a timing at which the edge detection signal does not transition. As described above, the phase calculation circuit 106 generates the phase information 151 from the phase relationship between the output signal 125 and the phase calculation signal 155.

  As described above, according to the fourth embodiment, in addition to suppressing the influence of the duty deviation of the receiving unit, the influence of the duty deviation is mixed in the phase information, and the phase adjustment of the recovered clock 152 does not match. It is possible to suppress the deterioration of reception characteristics due to the above. As a result, the receiving circuit 100 according to the fourth embodiment can more effectively reduce or eliminate the influence of the duty shift and improve the receiving characteristics.

100: receiving circuit, 101: receiving unit, 102: first edge detecting circuit, 103: second edge detecting circuit, 104: generating circuit, 120: differential input signal, 121: differential output signal OUTP, 122: differential Output signal OUTN, 123: first edge detection signal, 124: second edge detection signal, 125: output signal

Claims (12)

A signal processing device for processing a differential input signal,
Receiving means for amplifying the input differential input signal and outputting a differential output signal;
First edge detection means for detecting a transition of one signal of the differential output signal in one direction and outputting a first edge detection signal whose signal value is switched according to the detection of the transition;
Second edge detection means for detecting a transition of the other signal of the differential output signal in the one direction and outputting a second edge detection signal whose signal value is switched in accordance with the detection of the transition;
A signal processing apparatus comprising: generating means for generating an output signal corresponding to the differential input signal based on the first edge detection signal and the second edge detection signal.   The signal processing apparatus according to claim 1, wherein the first edge detection unit inverts the output of the first edge detection signal in response to detection of rising or falling of the one signal.   The second edge detection means outputs the first edge detection signal output from the first edge detection means as the second edge detection signal in response to detection of rising or falling of the other signal. The signal processing apparatus according to claim 2.   4. The signal processing according to claim 1, wherein the generation unit outputs an exclusive OR of the first edge detection signal and the second edge detection signal as an output signal. 5. apparatus. The generating means includes
Sampling means for sampling each of the first edge detection signal and the second edge detection signal with a clock,
The output signal is generated based on the sampling signals of the first edge detection signal and the second edge detection signal obtained by the sampling unit, respectively. The signal processing apparatus as described.   The signal processing apparatus according to claim 5, wherein the generation unit outputs an exclusive OR of the sampling signals of the first edge detection signal and the second edge detection signal as an output signal. .   The signal processing apparatus according to claim 5, further comprising a clock generation unit configured to generate the clock.   The clock generation means adjusts the phase of the clock based on a signal obtained by sampling the first edge detection signal and the second edge detection signal at the rising edge and falling edge of the clock. 8. The signal processing device according to 7.   The clock generation means includes a first signal obtained by exclusive OR of a signal obtained by sampling the first edge detection signal and the second edge detection signal at a rising edge of the clock, and the first edge The phase of the clock is adjusted based on the phase relationship between the detection signal and the second signal obtained by exclusive OR of the signals obtained by sampling the second edge detection signal at the falling edge of the clock. The signal processing apparatus according to claim 8.   10. The signal according to claim 9, further comprising phase calculation means for generating phase information instructing to advance and delay the phase of the clock based on the first signal and the second signal. Processing equipment.   The signal processing apparatus according to claim 10, wherein the phase calculation unit includes a Bang-Bang type phase comparator. A signal processing method for processing a differential input signal,
A receiving step of amplifying the input differential input signal and outputting a differential output signal;
A first edge detection step of detecting a transition in one direction of one of the differential output signals and outputting a first edge detection signal whose signal value is switched according to the detection of the transition;
A second edge detection step of detecting a transition of the other signal of the differential output signal in the one direction and outputting a second edge detection signal whose signal value is switched in accordance with the detection of the transition;
And a generation step of generating an output signal corresponding to the differential input signal based on the first edge detection signal and the second edge detection signal.

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