JP2019204969A - Light-emitting element, light-emitting element package and method for manufacturing light-emitting element - Google Patents

Abstract

To provide: a light-emitting element which can simplify a manufacturing process and which can endure the manufacturing process; a light-emitting element package including the light-emitting element; and a method for manufacturing the light-emitting element.SOLUTION: A light-emitting element comprises: a first semiconductor layer; a first ITO layer formed in a first region of a surface of the first semiconductor layer; a first metal layer formed on the first ITO layer; a luminescent layer formed in a second region other than the first region in the surface of the first semiconductor layer; a second semiconductor layer formed on the luminescent layer; a second ITO layer formed on the second semiconductor layer; and a second metal layer formed on the second ITO layer. The first metal layer includes: a first Cr layer laminated on the first ITO layer; and a first Au layer laminated on the first Cr layer. The second metal layer includes: a second Cr layer laminated on the second ITO layer; and a second Au layer laminated on the second Cr layer. The first and second ITO layers contain Cr.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a light emitting device, a light emitting device package including the light emitting device, and a method for manufacturing the light emitting device.

  A semiconductor light emitting device according to one prior art is disclosed in Patent Document 1. In this semiconductor light emitting device, a low-temperature buffer layer, a high-temperature buffer layer, an n-type layer, a superlattice layer, an active layer, a p-type layer, and a light-transmitting conductive layer are laminated in this order from the sapphire substrate side. ing. The translucent conductive layer is made of ZnO, and a p-side electrode having a laminated structure of Ti and Au is formed on a part of the transparent conductive layer. An n-side electrode having a laminated structure of Al, Ni, and Au is formed on the exposed portion of the n-type layer.

JP 2005-354040 A

An object of the present invention is to provide a light emitting device capable of simplifying the manufacturing process, a light emitting device package including the light emitting device, and a method for manufacturing the light emitting device.
Another object of the present invention is to provide a light emitting device that can withstand a manufacturing process, a light emitting device package including the light emitting device, and a method for manufacturing the light emitting device.

  The invention according to claim 1 is a substrate, a first semiconductor layer of a first conductivity type formed on the substrate, a first ITO layer formed in a first region on the surface of the first semiconductor layer, A first metal layer formed on the first ITO layer; a light-emitting layer formed in a second region other than the first region on the surface of the first semiconductor layer apart from the first ITO layer; and the light-emitting layer A second semiconductor layer of a second conductivity type different from the first conductivity type, a second ITO layer formed on the second semiconductor layer, and a second ITO layer formed on the second ITO layer. The first metal layer includes a first Cr layer stacked on the first ITO layer, and a first Au layer stacked on the first Cr layer, and the second metal layer includes: A second Cr layer laminated on the second ITO layer, and a second Cr layer laminated on the second Cr layer; And and a second 2Au layer, said first 1ITO layer and the 2ITO layer comprises Cr, which is a light-emitting element.

  According to a second aspect of the present invention, the first ITO layer is in ohmic contact with the first semiconductor layer, and the second ITO layer is in ohmic contact with the second semiconductor layer. It is a light emitting element. The invention according to claim 3 is the light emitting device according to claim 1 or 2, wherein the first ITO layer and the second ITO layer have the same thickness. The invention according to claim 4 is the light emitting device according to claim 3, wherein the first metal layer and the second metal layer have the same structure. The invention according to claim 5 is the light emitting device according to claim 4, wherein the first Cr layer and the second Cr layer have the same thickness, and the first Au layer and the second Au layer have the same thickness. It is an element. A sixth aspect of the present invention is the light emitting element according to any one of the first to fifth aspects, wherein the first ITO layer is located closer to the substrate than the light emitting layer. The invention according to claim 7 is a light emitting element package including the light emitting element according to any one of claims 1 to 6 and a package covering the light emitting element.

  The invention according to claim 8 is a step of forming a first semiconductor layer of a first conductivity type on a substrate, a step of forming a light emitting layer on the first semiconductor layer, and a second conductivity type on the light emitting layer. Forming a second semiconductor layer, removing a part of the light emitting layer and the second semiconductor layer to expose the first semiconductor layer, and on the first semiconductor layer and the second semiconductor Forming a first ITO layer and a second ITO layer on the layers, respectively, and forming the first ITO layer and the second ITO layer with a first heating temperature after forming the first ITO layer and the second ITO layer. A step of performing a heat treatment, a step of forming a first metal layer and a second metal layer on the first ITO layer and the second ITO layer, respectively, and after forming the first metal layer and the second metal layer, The first metal layer Performing a second heat treatment on the second metal layer, the first ITO layer, and the second ITO layer at a second heating temperature lower than the first heating temperature, and forming the first metal layer The step of forming includes a step of forming a first Cr layer on the first ITO layer and a step of forming a first Au layer on the first Cr layer, and the step of forming the second metal layer includes the step of forming the second ITO layer. Including a step of forming a second Cr layer on the layer and a step of forming a second Au layer on the second Cr layer, and the step of performing the second heat treatment includes the first Cr layer, the second Cr layer, And a step of performing a second heat treatment on the first Au layer, the second Au layer, the first ITO layer, and the second ITO layer at a temperature of 300 ° C. to 350 ° C. as the second heating temperature. Is a manufacturing methodThe invention according to claim 9 is the method for manufacturing a light emitting element according to claim 8, wherein the second heating temperature is 330 ° C. or higher. The invention according to claim 10 is the method for manufacturing a light emitting element according to claim 8 or 9, wherein the first heating temperature is not lower than 600 ° C and not higher than 700 ° C.

FIG. 1 is a schematic plan view of a light emitting device according to an embodiment of the present invention. 2 is a cross-sectional view taken along section line II-II in FIG. FIG. 3 is a cross-sectional view schematically showing the structure of the light emitting device package. FIG. 4 is a flowchart illustrating a method for manufacturing a light emitting device. FIG. 5A is a schematic cross-sectional view showing a method for manufacturing the light-emitting element shown in FIG. FIG. 5B is an illustrative sectional view showing a step subsequent to FIG. 5A. FIG. 5C is an illustrative sectional view showing a step subsequent to FIG. 5B. FIG. 5D is an illustrative sectional view showing a step subsequent to FIG. 5C. FIG. 5E is an illustrative sectional view showing a step subsequent to FIG. 5D. FIG. 6 is a graph showing the relationship between the first heating temperature and the electrical characteristics of the light-emitting element 1. FIG. 7 is a graph showing the relationship between the second heating temperature and the electrical characteristics of the light emitting element 1. FIG. 8 is a graph showing another relationship between the second heating temperature and the electrical characteristics of the light emitting element 1. FIG. 9 is a graph showing the relationship between the second heating temperature and the strength of the light emitting element 1 (light emitting element package 50).

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of a light emitting device according to an embodiment of the present invention. 2 is a cross-sectional view taken along section line II-II in FIG.
Referring to FIG. 2, the light emitting device 1 includes a substrate 2, a first conductive type semiconductor layer 3, a light emitting layer 4, a second conductive type semiconductor layer 5, a first ITO layer 6, and a second ITO layer 7. And a first metal layer 8 and a second metal layer 9.

  The substrate 2 is made of a material (for example, sapphire, GaN, or SiC, in this embodiment, sapphire) that is transparent to the emission wavelength (for example, 450 nm) of the light emitting layer 4. Specifically, “transparent to the emission wavelength” means, for example, a case where the transmittance of the emission wavelength is 60% or more. The shape of the substrate 2 in a plan view (hereinafter simply referred to as “plan view”) viewed from the thickness direction of the substrate 2 (hereinafter simply referred to as “thickness direction”) is a rectangular shape (substantially square in this embodiment). (See FIG. 1). The thickness of the substrate 2 is, for example, 100 μm. In the substrate 2, the upper surface in FIG. 2 is the front surface 2A, and the lower surface in FIG. 2 is the back surface 2B. The front surface 2 </ b> A is a bonding surface with the first conductivity type semiconductor layer 3 in the substrate 2. A plurality of convex portions 17 projecting toward the first conductivity type semiconductor layer 3 are formed on the surface 2A. The plurality of convex portions 17 are discretely arranged. Specifically, the plurality of convex portions 17 may be arranged in a matrix at intervals on the surface 2A, or may be arranged in a staggered manner. Each convex part 17 may be formed of SiN.

  The first conductivity type semiconductor layer 3 is stacked on the substrate 2. The first conductivity type semiconductor layer 3 covers the entire surface 2 </ b> A of the substrate 2. The first conductivity type semiconductor layer 3 is made of n-type GaN (n-GaN) and is transparent to the emission wavelength of the light emitting layer 4. Regarding the first conductivity type semiconductor layer 3, a lower surface covering the back surface 2B of the substrate 2 in FIG. 2 is referred to as a back surface 3A, and an upper surface opposite to the back surface 3A is referred to as a front surface 3B. On the surface 3B, the region on the left side in FIG. 2 partially protrudes, whereby a step 3C along the thickness direction is formed on the surface 3B. In the front surface 3B, a region that is on the right side of the step 3C in FIG. 2 and is lowered toward the back surface 3A side is referred to as a first region 3D, and a region that protrudes to the left of the step 3C in FIG. I will say. In plan view, the first region 3D occupies approximately a quarter of the surface 3B, and the second region 3E has a substantially L shape occupying approximately three-quarters of the surface 3B (FIG. 1). reference).

The light emitting layer 4 is stacked on the second region 3 </ b> E of the first conductivity type semiconductor layer 3. The light emitting layer 4 covers the entire second region 3E on the surface 3B of the first conductivity type semiconductor layer 3. Therefore, the light emitting layer 4 and the second region 3E coincide with each other in plan view. The light emitting layer 4 is made of a nitride semiconductor containing In (for example, InGaN).
The second conductivity type semiconductor layer 5 is stacked on the light emitting layer 4. Thus, the light emitting layer 4 is sandwiched between the first conductive semiconductor layer 3 and the second conductive semiconductor layer 5 from the thickness direction. The second conductivity type semiconductor layer 5 is made of p-type GaN (p-GaN) and is transparent to the emission wavelength of the light emitting layer 4. The second conductivity type semiconductor layer 5 covers the entire surface of the light emitting layer 4 on the side opposite to the first conductivity type semiconductor layer 3 side (upper side in FIG. 2). 5 and the light emitting layer 4 coincide with each other. In the second conductivity type semiconductor layer 5, the side surface opposite to the light emitting layer 4 side (upper side in FIG. 2) is referred to as a surface 5A.

Here, the stacked body of the first conductive type semiconductor layer 3, the light emitting layer 4, and the second conductive type semiconductor layer 5 constitutes a semiconductor stacked structure portion 90.
The first ITO layer 6 is made of ITO (indium tin oxide) and is transparent to the emission wavelength of the light emitting layer 4. The thickness of the first ITO layer 6 is, for example, 1000 to 2000 mm. The first ITO layer 6 is stacked in the first region 3D (the region other than the second region 3E in which the light emitting layer 4 is stacked in the first conductive semiconductor layer 3) on the surface 3B of the first conductive semiconductor layer 3. . Since the first conductivity type semiconductor layer 3 is laminated on the substrate 2, the first ITO layer 6 is laminated on the side opposite to the substrate 2 with respect to the first conductivity type semiconductor layer 3. Since the first ITO layer 6 is formed in a partial region of the first region 3D, it does not cover the entire region of the first region 3D. Specifically, the first ITO layer 6 has a shape similar to the first region 3D in plan view, and is located inside the outline of the first region 3D (see also FIG. 1). In the first ITO layer 6, the side surface on the opposite side (the upper side in FIG. 2) to the first conductive semiconductor layer 3 side is referred to as a surface 6A.

  The second ITO layer 7 is made of the same material (ITO) as the first ITO layer 6 and has the same thickness as the first ITO layer 6. The second ITO layer 7 is laminated on the surface 5 </ b> A of the second conductivity type semiconductor layer 5. Since the second conductivity type semiconductor layer 5 is laminated on the substrate 2 via the first conductivity type semiconductor layer 3 and the light emitting layer 4, the second ITO layer 7 is a substrate with respect to the second conductivity type semiconductor layer 5. 2 is laminated on the opposite side. Since the second ITO layer 7 is formed in a partial region of the surface 5A of the second conductivity type semiconductor layer 5, it does not cover the entire surface 5A. Specifically, the second ITO layer 7 has a shape similar to the second conductivity type semiconductor layer 5 (in other words, a substantially L-shape similar to the second region 3E) in plan view, and is inside the contour of the surface 5A. Located (see also FIG. 1). In the second ITO layer 7, the side surface opposite to the second conductivity type semiconductor layer 5 side (upper side in FIG. 2) is referred to as a surface 7A.

  The first metal layer 8 and the second metal layer 9 are so-called pad metals. The first metal layer 8 is laminated on the first ITO layer 6 (surface 6A of the first ITO layer 6), and the second metal layer 9 is laminated on the second ITO layer 7 (surface 7A of the second ITO layer 7). Has been. The first metal layer 8 and the second metal layer 9 have the same structure. Specifically, each of the first metal layer 8 and the second metal layer 9 is an ITO layer corresponding to the first ITO layer 6 and the second ITO layer 7 (in the case of the first metal layer 8, the first ITO layer 6, In the case of the second metal layer 9, the second ITO layer 7) includes a Cr layer 10 stacked on the Cr layer 10, and an Au layer 11 stacked on the Cr layer 10. That is, in each of the first metal layer 8 and the second metal layer 9, the Cr layer 10 is in contact with the corresponding ITO layer.

  The Cr layer 10 is made of Cr (chromium). The Au layer 11 is made of Au (gold). In the first metal layer 8 and the second metal layer 9, the Cr layers 10 have the same thickness, and the Au layers 11 have the same thickness. In this embodiment, since the thickness of the Cr layer 10 is 300 mm, for example, and the thickness of the Au layer 11 is relatively thick, for example, 2 μm, the Cr of the Cr layer 10 moves to the surface of the Au layer 11. Is prevented.

In plan view, the first metal layer 8 is inside the outline of the first ITO layer 6 and the second metal layer 9 is inside the outline of the second ITO layer 7 (see also FIG. 1). Further, in each of the first metal layer 8 and the second metal layer 9, the Cr layer 10 and the Au layer 11 have a circular shape having the same size in plan view (see also FIG. 1).
Here, in each Au layer 11 of the first metal layer 8 and the second metal layer 9, the side surface opposite to the Cr layer 10 side (upper side in FIG. 2) is referred to as a surface 11A. Further, the first ITO layer 6 and the second ITO layer 7 that are in contact with the Cr layer 10 may contain Cr of the Cr layer 10.

  The first ITO layer 6 and the first metal layer 8 constitute the first electrode 21. Further, the second ITO layer 7 and the second metal layer 9 constitute a second electrode 22. As described above, the first ITO layer 6 and the second ITO layer 7 are formed of the same material and have the same thickness, and the first metal layer 8 and the second metal layer 9 have the same structure. Therefore, the first electrode 21 and the second electrode 22 have the same structure.

FIG. 3 is a cross-sectional view schematically showing the structure of the light emitting device package.
A light emitting device package 50 shown in FIG. 3 includes the light emitting device 1 described above, a support substrate 51, and a package 52.
The support substrate 51 is provided so as to be exposed from both ends of the insulating substrate 53 made of an insulating material, and a pair of metal leads 54 that electrically connect the light emitting element 1 and the outside. And have. The insulating substrate 53 is formed, for example, in a rectangular shape in plan view, and a pair of leads 54 is formed in a strip shape along a pair of opposing sides. Each lead 54 extends along a pair of edges of the insulating substrate 53. For example, each lead 54 is folded back from the upper surface to the lower surface across the side surface, and has a lateral U-shaped cross section.

  In the light emitting element 1, the back surface 2 </ b> B of the substrate 2 is bonded to the main surface 51 </ b> A of the support substrate 51 through a bonding layer 60 made of a paste of Ag (silver) or solder (Ag in this embodiment). Each of the first electrode 21 and the second electrode 22 of the light emitting element 1 is electrically connected to the nearest lead 54 via a bonding wire 61. The bonding wire 61 is connected to the surface 11 </ b> A of the Au layer 11 in each of the first electrode 21 and the second electrode 22.

  The package 52 is a ring-shaped case filled with resin. The light-emitting element 1 is accommodated (covered) inside the package 52 and is fixed to the support substrate 51 in a state of being surrounded and protected from the side. In this state, in the light emitting element 1, the first electrode 21 and the second electrode 22 on the light extraction side are exposed to the outside of the package 52. The inner wall surface of the package 52 forms a reflection surface 52A for reflecting the light emitted from the light emitting element 1 and taking it out to the outside. In this embodiment, the reflecting surface 52A is an inclined surface that is inclined so as to approach the support substrate 51 as it goes inward, and the light from the light emitting element 1 is directed toward the light extraction direction (thickness direction of the substrate 2). It is configured to reflect.

  In the light emitting element package 50, in the light emitting element 1, a forward voltage is applied between the first electrode 21 (first metal layer 8) and the second electrode 22 (second metal layer 9) by energizing each lead 54. When applied, a current flows from the second electrode 22 toward the first electrode 21. The current spreads in the second ITO layer 7 over the entire area in plan view, and then flows through the second conductive semiconductor layer 5, the light emitting layer 4, the first conductive semiconductor layer 3 and the first ITO layer 6 in this order. When the current flows in this manner, electrons are injected from the first conductive type semiconductor layer 3 into the light emitting layer 4, and holes are injected from the second conductive type semiconductor layer 5 into the light emitting layer 4. Are recombined in the light emitting layer 4 to generate blue light having a wavelength of 440 nm to 460 nm. This light is extracted outside the package 52 from the surface 5A of the second conductive semiconductor layer 5, the surface 7A of the second ITO layer 7, and the like. In FIG. 3, the direction in which light travels to the outside is indicated by white arrows.

  At this time, there is also light traveling from the light emitting layer 4 toward the first conductive semiconductor layer 3, and this light passes through the first conductive semiconductor layer 3 and the substrate 2 in this order. Then, this light is reflected at the interface between the substrate 2 and the bonding layer 60, passes through the substrate 2 and the first conductive type semiconductor layer 3, and then the surface 3B (first region 3D) of the first conductive type semiconductor layer 3 Or, it is taken out from the surface 5A of the second conductivity type semiconductor layer 5, the surface 6A of the first ITO layer 6, the surface 7A of the second ITO layer 7, or the like. Here, the plurality of convex portions 17 formed on the front surface 2 </ b> A of the substrate 2 are incident on the back surface 3 </ b> A of the first conductive type semiconductor layer 3 from various angles toward the first conductive type semiconductor layer 3 from the substrate 2. It is possible to suppress the total reflection of light on the back surface 3A toward the substrate 2 side. Moreover, each convex part 17 can also guide the light staying by irregular reflection within the substrate 2 to the first conductivity type semiconductor layer 3 side. Therefore, the light extraction efficiency is improved.

  The sealing resin 62 may be filled inside the ring-shaped package 52. The sealing resin 62 is made of a transparent resin (for example, silicone or epoxy) that is transparent with respect to the emission wavelength of the light emitting element 1 and seals the light emitting element 1 and the bonding wire 61. Some of the resins constituting the sealing resin 62 contain a phosphor or a reflective agent. For example, when the light emitting element 1 emits blue light, the light emitting element package 50 can emit white light by including a yellow phosphor in the resin.

Note that a large number of the light emitting element packages 50 can be used for lighting equipment such as a light bulb, and can also be used for a backlight of a liquid crystal television or a headlamp of an automobile or the like.
FIG. 4 is a flowchart illustrating a method for manufacturing a light emitting device. 5A to 5E are schematic sectional views showing a method for manufacturing the light emitting device shown in FIG.

Next, a method for manufacturing the light-emitting element shown in FIG. 2 will be described with reference to FIGS. 4 and 5A to 5E.
First, as shown in FIG. 5A, a substrate 2 (strictly speaking, a wafer from which the substrate 2 is based) is manufactured.
Next, a SiN layer (SiN layer) is formed on the surface 2A of the substrate 2, and this SiN layer is etched into a plurality of protrusions as shown in FIG. 5B by etching using a resist pattern (not shown) as a mask. Separated into part 17.

Next, the above-described semiconductor laminated structure 90 (laminated body of the first conductive type semiconductor layer 3, the light emitting layer 4, and the second conductive type semiconductor layer 5) is formed on the surface 2A of the substrate 2 (step S1 in FIG. 4). ). Specifically, as shown in FIG. 5B, an n-type GaN layer (n-GaN layer) is formed on the surface 2 </ b> A of the substrate 2. The n-GaN layer is stacked on the substrate 2 as the first conductivity type semiconductor layer 3 and covers all the protrusions 17. Next, as illustrated in FIG. 5C, a nitride semiconductor layer containing In (for example, an In _x Ga _1-X N layer) is formed on the surface 3B of the first conductivity type semiconductor layer 3. This In _x Ga _1-X N layer becomes the light emitting layer 4 laminated on the first conductivity type semiconductor layer 3. The wavelength of light emission in the light emitting layer 4 is controlled to 440 nm to 460 nm by adjusting the composition of In and Ga. Next, as shown in FIG. 5C, a layer made of p-type GaN (p-GaN layer) is formed as the second conductive semiconductor layer 5 on the light emitting layer 4.

  Next, a mesa portion (step 3C for exposing the first conductivity type semiconductor layer 3) is formed (step S2 in FIG. 4). Specifically, the first region 3D of the surface 3B of the first conductivity type semiconductor layer 3 is exposed by etching using a resist pattern (not shown) as a mask, as shown in FIG. 5D. A part of each of the conductive semiconductor layer 3, the light emitting layer 4, and the second conductive semiconductor layer 5 is selectively removed. When the mesa portion is completed, the semiconductor multilayer structure portion 90 is completed.

  Next, an ITO layer (ITO layer) is formed on the completed semiconductor laminated structure 90 (that is, on the side opposite to the substrate 2 with respect to the first conductive semiconductor layer 3 and the second conductive semiconductor layer 5). (Step S3 in FIG. 4). The ITO layer includes a first region 3D on the surface 3B of the first conductivity type semiconductor layer 3, a surface 5A of the second conductivity type semiconductor layer 5, and a first conductivity type semiconductor layer in a step 3C of the first conductivity type semiconductor layer 3. 3, each of the light emitting layer 4 and the end surface of the second conductivity type semiconductor layer 5 is continuously covered.

Next, the ITO layer is formed by, for example, an etch-off method, as shown in FIG. 5E, the first ITO layer 6 on the first region 3D of the first conductivity type semiconductor layer 3 and the second ITO on the second conductivity type semiconductor layer 5. The layer 7 is separated (step S4 in FIG. 4).
Next, at least the first ITO layer 6 and the second ITO layer 7 are subjected to a first heat treatment at a first heating temperature (600 ° C. to 700 ° C., here, 650 ° C.) (step S5 in FIG. 4). Step S5 may be performed before step S4. In short, after the ITO layer is formed, the first heat treatment may be performed on the ITO layer (the first ITO layer 6 and the second ITO layer 7 if separated). By the first heat treatment here, at least one of the first conductive semiconductor layer 3 and the second conductive semiconductor layer 5 (particularly, the p-type second conductive semiconductor layer 5) and the ITO layer (particularly the second ITO layer). 7) can be improved in ohmic characteristics. In order to confirm the improvement of the ohmic characteristics here, a plurality of wafers with different first heating temperatures (wafers on which the light emitting element 1 was formed, the same applies hereinafter) were prepared. Then, the chips of the light emitting elements 1 that are periodically arranged on the wafer surface for each different first heating temperature are extracted at equal intervals, and 20 mA is energized to each chip, so that the forward voltage (VF) in each chip is obtained. Was measured. The measurement result of VF in each light emitting element 1 at each first heating temperature is shown in the graph of FIG. In this graph, the distribution (range) of VF at each first heating temperature is indicated by vertical lines, and the average value of VF at each first heating temperature is indicated by rhombus dots. It shows that the lower the VF, the better the ohmic characteristics. From this graph, when the first heating temperature is between 600 ° C. and 700 ° C. (600 ° C. or more and 700 ° C. or less), VF is lowered and ohmic characteristics are improved as compared with the case where it is less than 600 ° C. I understand.

  Next, a layer made of Cr (Cr layer) and a layer made of Au (Au layer) are formed on the semiconductor multilayer structure 90 in this order by, for example, a lift-off method. Specifically, after resist patterning opened at the top of the first ITO layer 6 and the second ITO layer 7, the Cr layer and the Au layer are formed, and when the resist pattern is removed, the remaining Cr layer and Au layer As shown in FIG. 2, the first metal layer 8 and the second metal layer 9 are formed simultaneously (step S6 in FIG. 4). That is, the metal layers (the first metal layer 8 and the second metal layer 9) are simultaneously formed on the first ITO layer 6 and the second ITO layer 7, respectively, and the first electrode 21 and the second electrode 22 are completed simultaneously. .

  Next, the second heating lower than the first heating temperature is applied to the first electrode 21 (first ITO layer 6 and first metal layer 8) and the second electrode 22 (second ITO layer 7 and second metal layer 9). A second heat treatment is performed at a temperature (from 300 ° C. to 350 ° C., here 350 ° C.) (step S7 in FIG. 4). The electrical characteristics at the interface between the first ITO layer 6 and the first conductive type semiconductor layer 3 are improved by the second heat treatment here, so that the n-type first conductive type semiconductor layer 3 and the first ITO layer 6 are connected to each other. The ohmic characteristics in can be improved. In order to confirm the improvement of the ohmic characteristics here, a plurality of wafers with different second heating temperatures were prepared as in the case of the first heating temperature. Then, periodically arranged chips of the light-emitting elements 1 were taken out at equal intervals in the wafer surface for each different second heating temperature, and 20 mA was applied to each chip to measure VF in each chip. The measurement result of VF in each light emitting element 1 at each second heating temperature is shown in the graph of FIG. In this graph, the distribution (range) of VF at each second heating temperature is indicated by vertical lines, and the average value of VF at each second heating temperature is indicated by rhombus dots. It shows that the lower the VF, the better the ohmic characteristics. From this graph, it can be seen that when the second heating temperature is between 300 ° C. and 350 ° C., the VF is reduced and the ohmic characteristics are improved as compared with the case of less than 300 ° C. (especially less than 250 ° C.). .

  In addition, another evaluation was performed in order to confirm the improvement of the ohmic characteristics related to the second heating temperature. Regarding the ohmic characteristics related to the second heating temperature, there is a concern about an increase in VF at the interface between the first electrode 21 and the first conductivity type semiconductor layer 3. Therefore, the electrical characteristics (IV curve) when energized between the first electrodes 21 (see FIG. 2) of two light emitting elements 1 adjacent (before separation) on the wafer are different from each other at the second heating temperature. Measured every time. The result is shown in FIG. In the graph of FIG. 8, the case before performing the second heat treatment (see the dotted line), the case where the second heating temperature is 200 ° C. (see the one-dot chain line), and the case where the second heating temperature is 250 ° C. (two points). In each of the dotted lines), the first electrode 21 and the first conductivity type semiconductor layer 3 are in Schottky contact, and it can be seen that the resistance is high. On the other hand, when the second heating temperature is 300 ° C. (see the solid line), it can be seen that the first electrode 21 and the first conductivity type semiconductor layer 3 are in ohmic contact, and the resistance rapidly decreases. That is, by performing the second heat treatment in which the second heating temperature is 300 ° C. or more, the contact between the first electrode 21 and the first conductivity type semiconductor layer 3 is changed from the Schottky contact to the ohmic contact, and the resistance value is increased. It turns out that it falls dramatically.

  Note that the value of the second heating temperature of 350 ° C. (described above) indicates the adhesion between the first ITO layer 6 and the first metal layer 8, the adhesion between the second ITO layer 7 and the second metal layer 9, and the first ITO layer. 6 and the first conductivity type semiconductor layer 3 and the adhesion between the second ITO layer 7 and the second conductivity type semiconductor layer 5 are set so as not to affect the adhesion. In addition, Cr of the Cr layer 10 in the first metal layer 8 is mixed into the first ITO layer 6 or Cr of the Cr layer 10 in the second metal layer 9 is mixed into the second ITO layer 7 by the second heat treatment. Therefore, as described above, the first ITO layer 6 and the second ITO layer 7 contain Cr. The presence or absence of Cr in the first ITO layer 6 and the second ITO layer 7 can be determined by elemental analysis using a transmission electron microscope (TEM).

The ITO contained in the first ITO layer 6 and the second ITO layer 7 is not originally good in ohmic characteristics, but the ohmic characteristics are dramatically improved by performing the first heat treatment and the second heat treatment in this way. be able to.
Thus, the structure shown in FIG. 2 is formed. Finally, each light emitting element 1 is formed by dicing or cleaving the wafer of the substrate 2 on which the structure of FIG. 2 is formed in a periodic arrangement.

In the light emitting element 1, each of the electrode portions (the first electrode 21 and the second electrode 22) in each of the first conductive semiconductor layer 3 and the second conductive semiconductor layer 5 has a metal layer stacked on the ITO layer. Thus, these electrode portions can be formed simultaneously (step S6 described above). Thereby, the manufacturing process of the light emitting element 1 can be simplified.
In each of the first electrode 21 and the second electrode 22, the metal layer (the first metal layer 8 and the second metal layer 9) includes a Cr layer 10 on the ITO layer side and an Au layer laminated on the Cr layer 10. 11. As a result, in each of the first electrode 21 and the second electrode 22, the adhesion between the ITO layer and the metal layer can be improved, so that a wire (the above-described bonding wire 61) is bonded to the metal layer. In this case, the metal layer can be prevented from peeling off from the ITO layer. In order to prove this, a test of intentionally pulling the bonding wire 61 after bonding was performed. If there is no problem in the adhesion between the ITO layer and the metal layer, the ITO layer and the metal layer are not peeled off, and instead, the bonding wire 61 having the weakest strength is cut. A plurality of light emitting device packages 50 (the light emitting device 1 in which the bonding wires 61 are simply bonded) whose second heating temperature is changed may be referred to as the number of preparations for each second heating temperature (for example, about 100 to 140). ) Each light emitting device package 50 was prepared and tested. The ratio of the light emitting element package 50 in which the ITO layer and the metal layer are peeled by at least one of the first electrode 21 and the second electrode 22 in the number of preparations at each second heating temperature (pad metal peeling occurs) The result shown in FIG. 9 was obtained. From FIG. 9, when the second heating temperature is between 300 ° C. and 500 ° C., the rate of occurrence of pad metal peeling is extremely low at less than 1%, and when the second heating temperature is between 330 ° C. and 450 ° C. It can be seen that no peeling occurs. In order to achieve both the improvement of the ohmic characteristics and the improvement of adhesion, the second heating temperature is desirably 300 ° C. to 350 ° C. (300 ° C. or more and 350 ° C. or less).

In addition, the first conductive semiconductor layer 3 and the second conductive semiconductor layer 5 and the ITO layer are separated by the first heat treatment (step S5 described above) and the second heat treatment (step S7 described above). Therefore, it is possible to prevent the ITO layer from being peeled off from each of the first conductive type semiconductor layer 3 and the second conductive type semiconductor layer 5 in wire bonding.
Therefore, the light emitting element 1 that can withstand the manufacturing process (specifically, the wire bonding process) can be provided.

In addition to the above, the present invention can be implemented in various forms, and various design changes can be made within the scope of matters described in the claims.
For example, the surface 3B (exposed portion) of the first conductive type semiconductor layer 3, the surface 5A of the second conductive type semiconductor layer 5, and the first ITO layer 6 are formed by a transparent insulating film (passivation) made of SiO ₂ or the like. The surface 6A and the surface 7A of the second ITO layer 7 may be coated for protection. However, it is preferable that the insulating film does not cover (do not mount) the first metal layer 8 and the second metal layer 9.

For example, the structure which does not form the convex part 17 which consists of SiN may be sufficient.
For example, in the above-described embodiment, an example in which the first conductivity type is n-type and the second conductivity type is p-type has been described. However, the first conductivity type is p-type, and the second conductivity type is n-type. May be configured. That is, the structure in which the conductivity type is inverted between the p-type and the n-type in the above-described embodiment is also an embodiment of the present invention. In the above-described embodiment, GaN is exemplified as the nitride semiconductor constituting the first conductive semiconductor layer 3 and the second conductive semiconductor layer 5. However, other examples such as aluminum nitride (AlN) and indium nitride (InN) are used. Nitride semiconductors may be used. A nitride semiconductor can be generally expressed as Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). In addition, the present invention may be applied not only to a nitride semiconductor but also to a light emitting element using another compound semiconductor such as GaAs or a semiconductor material other than the compound semiconductor (for example, diamond).

DESCRIPTION OF SYMBOLS 1 Light emitting element 2 Substrate 2D 1st area | region 2E 2nd area | region 3 1st conductivity type semiconductor layer 4 Light emitting layer 5 2nd conductivity type semiconductor layer 6 1st ITO layer 7 2nd ITO layer 8 1st metal layer 9 2nd metal layer 10 Cr Layer 11 Au layer 50 Light emitting device package 52 Package

Claims (10)

A substrate,
A first semiconductor layer of a first conductivity type formed on the substrate;
A first ITO layer formed in a first region of the surface of the first semiconductor layer;
A first metal layer formed on the first ITO layer;
A light emitting layer formed in a second region other than the first region on the surface of the first semiconductor layer apart from the first ITO layer;
A second semiconductor layer formed on the light emitting layer and having a second conductivity type different from the first conductivity type;
A second ITO layer formed on the second semiconductor layer;
A second metal layer formed on the second ITO layer,
The first metal layer includes a first Cr layer laminated on the first ITO layer, and a first Au layer laminated on the first Cr layer,
The second metal layer includes a second Cr layer stacked on the second ITO layer, and a second Au layer stacked on the second Cr layer,
The light emitting device, wherein the first ITO layer and the second ITO layer contain Cr. The first ITO layer is in ohmic contact with the first semiconductor layer;
The light emitting device according to claim 1, wherein the second ITO layer is in ohmic contact with the second semiconductor layer.   The light emitting device according to claim 1 or 2, wherein the first ITO layer and the second ITO layer have the same thickness.   The light emitting device according to claim 3, wherein the first metal layer and the second metal layer have the same structure.   The light emitting device according to claim 4, wherein the first Cr layer and the second Cr layer have the same thickness, and the first Au layer and the second Au layer have the same thickness.   The light emitting device according to claim 1, wherein the first ITO layer is located closer to the substrate than the light emitting layer. The light emitting device according to any one of claims 1 to 6,
A light emitting device package including a package covering the light emitting device. Forming a first conductivity type first semiconductor layer on a substrate;
Forming a light emitting layer on the first semiconductor layer;
Forming a second conductive type second semiconductor layer on the light emitting layer;
Removing a part of the light emitting layer and the second semiconductor layer to expose the first semiconductor layer;
Forming a first ITO layer and a second ITO layer on the first semiconductor layer and the second semiconductor layer, respectively;
Performing a first heat treatment at a first heating temperature on the first ITO layer and the second ITO layer after the formation of the first ITO layer and the second ITO layer;
Forming a first metal layer and a second metal layer on the first ITO layer and the second ITO layer, respectively;
After the first metal layer and the second metal layer are formed, the second metal layer, the second metal layer, the first ITO layer, and the second ITO layer have a second temperature lower than the first heating temperature. Performing a second heat treatment at a heating temperature,
The step of forming the first metal layer includes a step of forming a first Cr layer on the first ITO layer, and a step of forming a first Au layer on the first Cr layer,
Forming the second metal layer includes forming a second Cr layer on the second ITO layer; and forming a second Au layer on the second Cr layer;
The step of performing the second heat treatment is performed by using 300% as the second heating temperature for the first Cr layer, the second Cr layer, the first Au layer, the second Au layer, the first ITO layer, and the second ITO layer. The manufacturing method of a light emitting element including the process of performing the said 2nd heat processing at the temperature below 350 degreeC.   The method for manufacturing a light-emitting element according to claim 8, wherein the second heating temperature is 330 ° C. or higher.   The method of manufacturing a light emitting element according to claim 8 or 9, wherein the first heating temperature is 600 ° C or higher and 700 ° C or lower.

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