JP2019121786A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

To preferably allow for accurate adjustment of an amount of injection of carriers from a cathode in a diode.SOLUTION: A semiconductor device is provided with a diode region in a semiconductor substrate. The diode region comprises: a base region of a first conductivity type provided exposed on an upper surface of the semiconductor substrate; a cathode region of a second conductivity type provided exposed on a lower surface of the semiconductor substrate; an inter-cathode region of the first conductivity type provided exposed on the lower surface of the semiconductor substrate and alternately arranged with the cathode region in a predetermined direction; and a floating region of the second conductivity type provided above the cathode region and above the inter-cathode region.SELECTED DRAWING: Figure 14

Description

  The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

Conventionally, it is known to provide a P-type buried layer in a diode (see, for example, Patent Document 1). Further, in a semiconductor device having a SJ-MOSFET (Super Junction-Metal Oxide Semiconductor Field Effect Transistor) portion and an IGBT (Insulated Gate Bipolar Transistor) portion in one semiconductor chip, providing a P-type floating region in the SJ-MOSFET portion. Are known (see, for example, Patent Document 2).
[Prior art document]
[Patent Document]
[Patent Document 1] International Publication No. 2014/156849 [Patent Document 2] International Publication No. 2016/063683

  In the diode, it is preferable that the amount of carrier injection from the cathode can be accurately adjusted.

  A first aspect of the present invention provides a semiconductor device in which a diode region is provided on a semiconductor substrate. The diode region may have a base region of the first conductivity type exposed on the top surface of the semiconductor substrate. The diode region may have a cathode region of the second conductivity type exposed on the lower surface of the semiconductor substrate. The diode region may be exposed on the lower surface of the semiconductor substrate and may have an inter-cathode region of the first conductivity type alternately arranged with the cathode region in a predetermined direction. The diode region may have a floating region of the second conductivity type provided above the cathode region and above the inter-cathode region.

  The semiconductor device may be provided with a transistor region provided on the semiconductor substrate and arranged in parallel with the diode region in a top view of the semiconductor substrate.

  The inter-cathode region and the floating region may be spaced apart in the depth direction of the semiconductor substrate.

  The diode region may have a dummy trench portion extended in the extending direction on the upper surface of the semiconductor substrate. The cathode region and the inter-cathode region may be alternately arranged in the extending direction.

  In the diode region, the cathode region may be provided deeper than the inter-cathode region with reference to the lower surface of the semiconductor substrate.

  In the depth direction of the semiconductor substrate, the distance between the upper end of the cathode region and the lower end of the floating region may be smaller than the distance between the upper end of the inter-cathode region and the lower end of the floating region.

  In the top view of the semiconductor substrate, the area of the floating region provided in the diode region may be larger than the area of the cathode region. In the top view of the semiconductor substrate, the area of the inter-cathode area provided in the diode area may be larger than the area of the cathode area.

  A second aspect of the present invention provides a method of manufacturing a semiconductor device. The semiconductor device may have a transistor region and a diode region on one semiconductor substrate. The method of manufacturing the semiconductor device may include an implant stage for the collector region, an implant stage for the cathode region, and an implant stage for the floating region. In the collector region implantation step, a dopant of the first conductivity type may be implanted into the lower surface of the semiconductor substrate to form a collector region in the transistor region. In the cathode region implantation step, a dopant of the second conductivity type may be implanted into the lower surface of the semiconductor substrate to form a cathode region in the diode region. The floating region implant phase may be after the cathode region implant phase. In the floating region implantation step, a dopant of the first conductivity type may be implanted into the lower surface of the semiconductor substrate to form a floating region of the first conductivity type provided in the diode region.

  The injection step for the cathode region may be performed after the injection step for the collector region. Alternatively, the implantation step for the collector region may be performed after the implantation step for the cathode region and the implantation step for the floating region may be performed after the implantation step for the collector region. Alternatively, the implant step for the collector region may be performed after the implant step for the floating region.

  In a third aspect of the present invention, another method of manufacturing a semiconductor device is provided. The semiconductor device may have a transistor region and a diode region on one semiconductor substrate. Another method of manufacturing a semiconductor device may include an implant stage for the collector region, an implant stage for the floating region, and an implant stage for the cathode region. In the collector region implantation step, a dopant of the first conductivity type may be implanted into the lower surface of the semiconductor substrate to form a collector region in the transistor region. In the floating region implantation step, a dopant of the first conductivity type may be implanted into the lower surface of the semiconductor substrate to form a floating region of the first conductivity type provided in the diode region. The implantation step for the cathode region may be after the implantation step for the collector region and the implantation step for the floating region. In the cathode region implantation step, a dopant of the second conductivity type may be implanted into the lower surface of the semiconductor substrate to form a cathode region in the diode region.

  The implantation step for the floating region may be performed after the implantation step for the collector region. Alternatively, the implantation step for the collector region may be performed after the implantation step for the floating region. Alternatively, the collector region implant step may be performed after the cathode region implant step.

  After the collector region implant step, the cathode region implant step and the floating region implant step, the end of the floating region may not reach the boundary between the collector region and the cathode region. The end of the floating region may be the end of the floating region closest to the boundary between the collector region and the cathode region. The end of the floating region may not reach the boundary between the collector region and the cathode region in the direction parallel to the arrangement direction of the cathode region and the collector region from the cathode region to the collector region. The floating region may be located in the diode region.

  Alternatively, after the collector region implant step, the cathode region implant step and the floating region implant step, the end of the floating region may be located at the boundary between the collector region and the cathode region. The end of the floating region may be the end of the floating region closest to the boundary between the collector region and the cathode region. The end of the floating region may be located at the boundary between the collector region and the cathode region in a direction parallel to the arrangement direction of the cathode region and the collector region from the cathode region to the collector region.

  The lower end of the floating region may be closer to the upper surface of the semiconductor substrate than the upper end of the collector region.

  After the collector region implant step, the cathode region implant step and the floating region implant step, at least a portion of the floating region may be located in the cathode region.

  The cathode region may have at least two peaks of electron concentration at different positions in the depth direction from the lower surface to the upper surface. The peak position of the hole concentration in the floating region may be located between two peaks of at least two electron concentration peaks in the cathode region in the depth direction.

  The lower end of the floating region may be spaced apart from the upper end of the cathode region.

  After the collector region implant step, the cathode region implant step and the floating region implant step, the upper end of the cathode region may be closer to the top surface of the semiconductor substrate than the upper end of the collector region.

  Note that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a subcombination of these feature groups can also be an invention.

FIG. 1 is a top view of a semiconductor device 100 according to an embodiment of the present invention. It is a figure which shows the AA cross section of FIG. It is an enlarged view of the area | region B of FIG. FIG. 7 is a flowchart showing a method of manufacturing the semiconductor device 100 in the first embodiment. FIG. 7 is a diagram showing each step of the method of manufacturing the semiconductor device 100 in the first embodiment. FIG. 16 is a flowchart showing a method of manufacturing the semiconductor device 120 in the first modified example of the first embodiment. FIG. 18 is a view showing each step of the method of manufacturing the semiconductor device 120 in the first modified example of the first embodiment. FIG. 16 is a flowchart showing a method of manufacturing the semiconductor device 140 in the second modification of the first embodiment. FIG. 18 is a view showing each step of the method of manufacturing the semiconductor device 140 in the second modified example of the first embodiment. It is a figure which shows density | concentration distribution of the electron and the hole vicinity of the boundary 72 in 1st Embodiment. FIG. 18 is a diagram showing a stage of a method of manufacturing the semiconductor device 160 in the third modified example of the first embodiment. FIG. 18 is a diagram showing a stage of a method of manufacturing the semiconductor device 180 in the fourth modification example of the first embodiment. It is a flowchart which shows the manufacturing method of the semiconductor device 200 in 2nd Embodiment. FIG. 14 is a view showing each step of the method of manufacturing the semiconductor device 200 in the second embodiment. FIG. 21 is a flow chart showing a method of manufacturing the semiconductor device 220 in the first modified example of the second embodiment. FIG. 19 is a view showing each step of the method of manufacturing the semiconductor device 220 in the first modified example of the second embodiment. FIG. 21 is a flow chart showing a method of manufacturing the semiconductor device 240 in the second modified example of the second embodiment. FIG. 19 is a view showing each step of the method of manufacturing the semiconductor device 240 in the second modified example of the second embodiment. It is a flowchart which shows the manufacturing method of the semiconductor device 300 in 3rd Embodiment. FIG. 19 is a diagram showing the stage of the method of manufacturing the semiconductor device 300 according to the third embodiment. It is a figure which shows density | concentration distribution of the electron near the boundary 72 in 3rd Embodiment, and a hole. It is a figure which shows density | concentration distribution of the electron and the hole vicinity of the boundary 72 in the 1st modification of 3rd Embodiment. It is a figure which shows density | concentration distribution of the electron and the hole vicinity of the boundary 72 in the 2nd modification of 3rd Embodiment. It is an upper surface view of FWD field 80 concerning a 4th embodiment. FIG. 15 is a perspective cross-sectional view including a K-K cross section and an L-L cross section in FIG. 14. FIG. 16 is an enlarged top view illustrating an arrangement example of floating region 84, cathode region 82, and inter-cathode region 81. It is a figure which shows the cathode area | region 82 and the area | region 81 between cathodes in YZ surface. It is an upper surface view of FWD field 80 concerning the 1st modification of a 4th embodiment. It is an upper surface view of FWD field 80 concerning the 2nd modification of a 4th embodiment. It is an upper surface view of FWD field 80 concerning the 3rd modification of a 4th embodiment. It is an upper surface view of FWD field 80 concerning the 3rd modification of a 4th embodiment. It is a figure which shows an example of the MM cross section in FIG. It is a flowchart which shows an example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment. FIG. 24 is a view for explaining a collector region injection step S620, a cathode region injection step S632 and a floating region injection step S640 in FIG. 23; It is a flowchart which shows the other example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment. FIG. 26 is a view for explaining a collector region injection step S620, a floating region injection step S642 and a cathode region injection step S634 in FIG. 25. It is a flowchart which shows the other example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment. It is a flowchart which shows the other example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment. It is a flowchart which shows the other example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment. It is a flowchart which shows the other example of the manufacturing method of the semiconductor device which concerns on 4th Embodiment.

  Hereinafter, the present invention will be described through the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Moreover, not all combinations of features described in the embodiments are essential to the solution of the invention.

  In the present specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as “upper”, and the other side is referred to as “lower”. Of the two major faces of the substrate, region, layer or other member, one face is referred to as the upper face and the other face is referred to as the lower face. The directions of “upper” and “lower” are not limited to the gravity direction or the mounting direction when the semiconductor device is mounted on a wiring board or the like.

  In this specification, technical matters may be described using orthogonal coordinate axes of the X axis, the Y axis, and the Z axis. In the present specification, the X-axis, the Y-axis and the Z-axis constitute a right-handed system. In this specification, a plane parallel to the upper surface or the lower surface of the semiconductor substrate is taken as an XY plane, and a depth direction of the semiconductor substrate which is perpendicular to the upper surface or the lower surface of the semiconductor substrate is taken as a Z axis.

  In the present specification, the first conductivity type is P type and the second conductivity type is N type, but the first conductivity type may be N type and the second conductivity type may be P type. In this case, the conductivity types of the substrate, layer, region and the like in each embodiment are opposite to each other. In addition, in the present specification, when described as P + type or N + type, it means that the doping concentration is higher than P type or N type, and when described as P type or N type, it is higher than P type or N type Also means that the doping concentration is low.

  As used herein, doping concentration refers to the concentration of a donor or acceptor impurity. In the present specification, the concentration difference between donor and acceptor may be referred to as net doping concentration or simply doping concentration. Also, the peak value of the doping concentration distribution may be referred to as doping concentration.

  FIG. 1 is a top view of a semiconductor device 100 according to an embodiment of the present invention. That is, FIG. 1 is a view of the semiconductor device 100 viewed from the upper surface side of the semiconductor substrate 10 in parallel to the Z axis. However, in FIG. 1, members such as the emitter electrode and the passivation film are appropriately omitted to facilitate understanding of the arrangement relationship of the respective regions.

  The semiconductor device 100 has a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a nitride semiconductor substrate such as gallium nitride (GaN). The semiconductor substrate 10 in the present embodiment is a silicon substrate. When a silicon substrate is used, the N-type dopant may be one or more elements of phosphorus (P) and arsenic (As), and the P-type dopant is one or more elements of boron (B) and aluminum (Al) It may be.

  The semiconductor device 100 includes an active region 110, an edge termination structure region 90, and a gate runner portion 50. Active region 110 is a transistor region where a main current flows between the upper surface and the lower surface of semiconductor substrate 10 when the transistor provided in semiconductor device 100 is turned on, and the semiconductor substrate when the transistor is turned off It may include a diode region in which a main current flows between the upper surface and the lower surface of 10. Alternatively, active region 110 may be a region provided with an emitter electrode in top view. The active region 110 of the present embodiment is a region excluding the pad region 112 in the region surrounded by the gate runner portion 50 in top view.

  The semiconductor device 100 of the present embodiment has an IGBT region 70 and a free wheeling diode (FWD) region 80 in the active region 110 of one semiconductor substrate 10. That is, the semiconductor device 100 of the present embodiment is an RC-IGBT. The IGBT region 70 is an example of a transistor region, and the FWD region 80 is an example of a diode region. In the present embodiment, the IGBT regions 70 and the FWD regions 80 are alternately arranged in the X-axis direction. In the present embodiment, IGBT regions 70 are provided at both ends of the active region 110 in the X-axis direction.

  The IGBT region 70 may have a P + -type collector region in a region in contact with the lower surface of the semiconductor substrate 10. The IGBT region 70 of the present embodiment is a region located in the active region 110 and provided with a collector region on the lower surface of the semiconductor substrate 10. The IGBT region 70 may periodically have a unit structure including an N + -type emitter region and a P + -type contact region on the upper surface of the semiconductor substrate 10.

  The FWD region 80 of the present embodiment is a region located in the active region 110 and provided with an N + -type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. The cathode region may be retracted to the inside of the active region 110 in the Y-axis direction in the vicinity of the gate runner portion 50 and the pad region 112. For example, the end of the cathode region in the Y-axis direction is located closer to the gate runner portion 50 than the gate runner portion 50 on the inner side of the active region 110. However, even if the end of the cathode region in the Y-axis direction is located inside the active region 110, Y from one end of the gate runner portion 50 because the gate trench portion and the emitter region are not provided. The FWD region 80 may be considered to be the other end opposite to the one end in the axial direction.

  In the present embodiment, the boundary 72 between the IGBT region 70 and the FWD region 80 in the X-axis direction is the boundary between the cathode region and the collector region. In FIG. 1, in consideration of the viewability of the drawing, only the boundary 72 crossed by AA is marked.

  The edge termination structure region 90 may be provided between the active region 110 and the outer peripheral edge of the semiconductor substrate 10 in top view. Edge termination structure region 90 may be arranged to surround active region 110 on the top surface of semiconductor substrate 10. The edge termination structure region 90 of the present embodiment is arranged in a rectangular ring along the outer peripheral edge of the semiconductor substrate 10. The edge termination structure region 90 may have a function of relaxing electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure region 90 may have, for example, a guard ring, a field plate and a resurf, or a combination of two or more of these.

  The gate runner portion 50 of the present embodiment is provided between the active region 110 and the edge termination structure region 90 in top view. Gate runner portion 50 may transmit a gate signal supplied from gate pad 114 to the gate trench portion of IGBT region 70. The gate runner portion 50 may have a laminated structure of a metal layer and a polysilicon layer.

  The metal layer of the gate runner portion 50 may be a metal layer formed of aluminum, aluminum-silicon alloy, or aluminum-silicon-copper (Cu) alloy. The polysilicon layer of the gate runner portion 50 may be a polysilicon layer doped with an impurity such as phosphorus.

  An insulating film may be provided between the polysilicon layer of the gate runner portion 50 and the upper surface of the semiconductor substrate 10. The gate runner portion 50 may be electrically separated from the semiconductor substrate 10 by the insulating film in the portion other than the portion connected to the gate trench portion. In addition, the metal layer of the gate runner portion 50 may be provided on the polysilicon layer. The metal layer may be connected to the polysilicon layer through a predetermined contact region (for example, an opening region of the interlayer insulating film).

  The pad area 112 in the present embodiment is an area in which a part of the active area 110 is cut out. That is, the pad area 112 of the present embodiment is not included in the active area 110. The range of the pad region 112 in top view may be the range of a P + -type well region provided in a region in contact with the top surface of the semiconductor substrate 10. The gate pad 114 may be provided in a narrower range than the P + -type well region. The gate pad 114 of the present embodiment is electrically connected to the gate runner unit 50. The gate signal may be supplied to the gate pad 114 from the outside of the semiconductor device 100.

  FIG. 2 is a view showing an AA cross section of FIG. The AA cross section is a cross section parallel to the XZ plane passing through the boundary 72 between the collector region 22 of the IGBT region 70 and the cathode region 82 of the FWD region 80. In the AA cross section, the semiconductor device 100 has an emitter electrode 52, an interlayer insulating film 38, a semiconductor substrate 10, and a collector electrode 24.

The interlayer insulating film 38 may be formed of one or more materials of silicon dioxide (SiO ₂ ), BPSG (Boro-Phospho Silicate Glass), PSG (Phosphorus Silicate Glass), and BSG (Borosilicate Glass). The interlayer insulating film 38 of the present embodiment is provided on the dummy trench portion 30 and the gate trench portion 40. The interlayer insulating film 38 of the present embodiment has a plurality of openings 54. The opening 54 may function as a contact portion in which the emitter electrode 52 and the upper surface 62 of the semiconductor substrate 10 are electrically connected.

  Emitter electrode 52 and collector electrode 24 may be formed of aluminum, aluminum-silicon alloy, or aluminum-silicon-copper (Cu) alloy. The emitter electrode 52 and the collector electrode 24 may have a barrier metal layer formed of titanium (Ti) or a titanium compound in the lower layer. The upper surface 62 of the semiconductor substrate 10 and the emitter electrode 52 may be directly connected. A plug made of tungsten (W) or the like may be provided in the opening 54. The upper surface 62 of the semiconductor substrate 10 and the emitter electrode 52 may be electrically connected via a plug.

  The semiconductor substrate 10 of the present embodiment has a plurality of trench portions in a region in contact with the upper surface 62. The plurality of trench portions include a gate trench portion 40 and a dummy trench portion 30. The distance between adjacent trench portions in the X-axis direction may be constant.

  A mesa portion 60 is provided between the trench portions. In the present embodiment, the mesa portion 60 is a region from the bottom of the trench portion to the top surface 62, and is a region of the semiconductor substrate 10 sandwiched between two trench portions adjacent in the X-axis direction. The mesa portion 60 may have an N + -type emitter region 12, a P + -type contact region 15, a P − -type base region 14 and an N + -type storage region 16. The mesa unit 60 includes a later-described mesa unit 60-1 and a later-described mesa unit 60-2.

  In the present embodiment, the mesa portions 60 of the IGBT regions 70 are provided alternately in the Y-axis direction, and have emitter regions 12 and contact regions 15 exposed on the upper surface 62 respectively. In the cross section AA, the emitter region 12 is present in the mesa 60-1 of the IGBT region 70, and the contact region 15 is not present.

  In the mesa portion 60-1a of the IGBT region 70 closest to the boundary 72, the emitter region 12 may not be provided to reduce current interference between the IGBT region 70 and the FWD region 80. In the mesa portion 60-1a of the IGBT region 70, the contact region 15 and the P-type base region 14 may be exposed on the upper surface 62 in the Y-axis direction. In the cross section AA, the contact region 15 is present in the mesa 60-1a, and the base region 14 is not present.

  In the mesa portion 60 of the IGBT region 70, the base region 14 is located below the emitter region 12 and the contact region 15 in the range where the emitter region 12 and the contact region 15 exist. The portion of the base region 14 in contact with the gate trench portion 40 may function as a channel formation region. When an on voltage is applied to the gate trench portion 40 as a gate signal, a channel which is a charge inversion layer may be formed in the base region 14. By forming a channel in the base region 14, electrons may flow between the emitter region 12 and the drift region 18.

  The storage region 16 in the present embodiment is provided to cover the entire lower surface of the base region 14 in each of the mesa portions 60. The storage region 16 may be sandwiched between two trench portions in the X-axis direction. The bottom of the storage region 16 may be provided closer to the top surface 62 than the bottom of each trench. That is, the bottom of the storage region 16 may be provided shallower than the bottom of each trench. By providing storage region 16 between drift region 18 and base region 14, the carrier injection promoting effect (IE effect: Injection-Enhancement effect) can be enhanced to reduce the on-voltage in IGBT region 70.

  The gate trench portion 40 has a gate trench 42, a gate insulating film 43 and a gate conductive portion 44. The gate trench 42 may be formed by selectively etching the semiconductor substrate 10 from the top surface 62 to a predetermined depth. The gate insulating film 43 may be provided in contact with the inner wall of the gate trench 42. The gate insulating film 43 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench 42. The gate conductive portion 44 is provided in contact with the gate insulating film 43 and on the inner side of the gate trench 42 than the gate insulating film 43. The gate insulating film 43 may electrically insulate the gate conductive portion 44 and the semiconductor substrate 10. The gate conductive portion 44 may be formed of a conductive material such as polysilicon.

  The dummy trench portion 30 has a dummy trench 32, a dummy trench insulating film 33 and a dummy trench conductive portion 34. The dummy trench insulating film 33 and the dummy trench conductive portion 34 may be formed in the same manner as the gate insulating film 43 and the gate conductive portion 44.

  In the present embodiment, the IGBT region 70 has a plurality of gate trench portions 40 and a plurality of dummy trench portions 30. Two dummy trench portions 30 are provided between the dummy trench portion 30-b located above the boundary 72 and the gate trench portion 40 closest to the dummy trench portion 30-b in the X-axis direction. A set of two dummy trench portions 30 and one gate trench portion 40 may be repeatedly provided in the X-axis direction.

  A dummy trench portion 30-b may be similarly provided above the boundary 72 between the IGBT region 70 and the FWD region 80 in contact with the IGBT region 70 in the negative X-axis direction. Two dummy trench portions 30 may be provided also between the dummy trench portion 30-b and the gate trench portion 40 closest to the dummy trench portion 30-b in the X-axis direction. On the other hand, all the trench portions in the FWD region 80 may be the dummy trench portions 30.

  In the present embodiment, the mesa portion 60-2 of the FWD region 80 has the base region 14 and the contact region 15 exposed on the top surface 62 respectively. In the cross section AA, the base region 14 exists in the mesa portion 60-2.

  In the FWD region 80, the area exposed on the upper surface 62 may be larger in the base region 14 than in the contact region 15. Base region 14 in FWD region 80 may function as an anode region in a diode. The contact region 15 may be partially provided only in a predetermined region (for example, a region near the gate runner portion 50) in the vicinity of the end in the Y-axis direction. In the mesa portion 60-2 in the present embodiment, a storage region 16 is provided so as to cover the entire lower surface of the base region 14.

  In the present embodiment, a structure including the mesa portion 60, the trench portion, the interlayer insulating film 38, and the emitter electrode 52 is referred to as a top surface structure 116. However, the top surface structure 116 may include a lifetime control region in the vicinity of the top surface 62 of the semiconductor substrate 10. The vicinity of the upper surface 62 of the semiconductor substrate 10 may mean above half the thickness of the semiconductor substrate 10 (that is, the length from the upper surface 62 to the lower surface 64 in the Z-axis direction).

  The lifetime control region is a region in which a lifetime killer is intentionally formed by implanting an impurity into the inside of the semiconductor substrate 10 or the like. The lifetime killer may be a carrier recombination center inside the semiconductor substrate 10. Carrier recombination centers include crystal defects, vacancies, double vacancies, complex defects of these with elements constituting the semiconductor substrate 10, dislocations, rare gas elements such as helium and neon, metal elements such as platinum, etc. It may be.

  In this embodiment, a structure including an N + -type field stop (abbreviated as FS hereinafter) region 20, a P-type floating region 84, a P + -type collector region 22 and an N + -type cathode region 82 is The lower surface structure 118 is referred to. The lower surface structure 118 may include a lifetime control region between the position of half of the thickness of the semiconductor substrate 10 and the top of the FS region 20.

  The FS region 20 may have a function of preventing the depletion layer extending from the bottom of the base region 14 to the lower surface 64 from reaching the collector region 22 when the semiconductor device 100 is turned off. The FS region 20 may be an N-type semiconductor region and may have one or more peaks in the doping concentration distribution. The plurality of peaks of the doping concentration distribution in the FS region 20 may be discretely provided in the Z-axis direction.

  Floating region 84 is a P-type region which is in an electrically floating state. The floating region 84 may be provided in the FWD region 80. In the present embodiment, the floating regions 84 are dispersively provided in the entire FWD region 80.

  The electrically floating state means, in principle, a state in which the collector electrode 24 and the emitter electrode 52 are not electrically connected. By providing the floating region 84, injection of electrons from the cathode region 82 can be suppressed. Thereby, the carrier distribution in the depth direction of the semiconductor substrate 10 can be adjusted without providing the lifetime killer on the lower surface 64 side of the semiconductor substrate 10. Therefore, the cost of providing the lifetime control area can be reduced. In addition, the leak current due to the lifetime control region can also be reduced.

Floating region 84 may be located within FWD region 80. In the present embodiment, the end 91 of the floating region 84 does not reach the boundary 72 in the X-axis direction. The end 91 of this embodiment is the end of the floating region 84 closest to the boundary 72. The distance L ₁ between the boundary 72 and the end 91 may be several nm or more and several μm or less. In the present embodiment, the X-axis direction is a direction parallel to the arrangement direction of the cathode region 82 and the collector region 22 from the cathode region 82 toward the collector region 22.

  The floating region 84 of the present embodiment is located in the FS region 20 in the Z-axis direction. That is, in the present embodiment, the upper end of the floating region 84 is closer to the lower surface 64 than the upper end of the FS region 20. In the present embodiment, the lower end of the floating region 84 coincides with the lower end of the FS region 20, but the lower end of the floating region 84 may be closer to the upper surface 62 than the lower end of the FS region 20.

  FIG. 3 is an enlarged view of area B of FIG. The length in the X-axis and Y-axis directions of the semiconductor substrate 10 may be several mm or more and ten or less mm or less. The width of the IGBT region 70 in the X-axis direction may be 1 to 3 times the width of the FWD region 80 in the X-axis direction, or may be 2 to 3 times the width. For example, the width of the IGBT region 70 in the X-axis direction is 1000 μm to 1500 μm, and the width of the FWD region 80 in the X-axis direction is 400 μm to 500 μm. The width in the Y-axis direction of IGBT region 70 and FWD region 80 may be the same.

The area of floating region 84 may be smaller than the area of FWD region 80 in the XY plane. In the XY plane, the floating region 84 may cover a range of 90% or more and less than 100% of the cathode region 82, and may cover a range of 90% or more and 95% or less of the cathode region 82. Each of the floating regions 84 may be island-like regions distributed in the XY plane. Each floating region 84 may be separated by a predetermined same distance L _F in the X-axis and Y-axis directions.

  FIG. 4A is a flowchart showing a method of manufacturing the semiconductor device 100 in the first embodiment. In the manufacturing method of the first embodiment, the upper surface structure 116 formation step (S10), the injection step (S20) for the collector region 22, the injection step (S30) for the cathode region 82, and the injection step (S40) for the floating region 84 , A first annealing step (S50), an implantation step (S60) for the FS region 20, a second annealing step (S70), and a collector electrode 24 forming step (S80). In the first embodiment, each step is performed in ascending order of numbers following S.

  FIG. 4B is a diagram showing each step of the method of manufacturing the semiconductor device 100 in the first embodiment. FIG. 4B (a) shows the step (S10) of forming the top surface structure 116. In step S <b> 10, a trench portion may be formed in the N − -type semiconductor substrate 10. When the dummy trench conductive portion 34 and the gate conductive portion 44 are formed, the polysilicon layer of the gate runner portion 50 may be formed. After forming the trench portion, a P-type dopant for the base region 14 is implanted into the upper surface 62 of the semiconductor substrate 10. The dopant may be accelerated into the ion state by the implanter and implanted into the semiconductor substrate 10. Thereafter, the semiconductor substrate 10 may be annealed at about 1150 ° C. for 3 hours.

  Thereafter, in step S10, an N-type dopant for storage region 16, an N-type dopant for emitter region 12, and a P-type dopant for contact region 15 may be selectively sequentially implanted. However, the order of injection may be changed as appropriate. Thereafter, the semiconductor substrate 10 may be annealed at about 1000 ° C. for 30 minutes. Thereafter, in step S10, the interlayer insulating film 38 may be formed by CVD. Thereafter, the opening 54 may be formed by selectively removing the interlayer insulating film 38 and the thermal oxide film on the upper surface 62 by etching. The thermal oxide film is, for example, an insulating film provided on the upper surface 62 when the gate insulating film 43 and the dummy trench insulating film 33 are formed.

  In step S10, emitter electrode 52 may then be deposited by sputtering. When the emitter electrode 52 is deposited by sputtering, the metal layer of the gate runner portion 50 and the gate pad 114 may also be deposited. After the deposition, the emitter electrode 52, the metal layer of the gate runner portion 50 and the gate pad 114 may be patterned into a predetermined shape. The step S10 may include forming a passivation layer including a predetermined opening on the emitter electrode 52 or the like.

  Note that step S10 of the present embodiment includes grinding the surface of the semiconductor substrate 10 opposite to the upper surface 62 in the Z-axis direction after the upper surface structure 116 is formed. The semiconductor substrate 10 may be thinned to have a thickness corresponding to a predetermined breakdown voltage. The lower surface 64 of the present embodiment is the surface of the semiconductor substrate 10 exposed after thinning.

  (B) of FIG. 4B shows the injection step (S20) for the collector region 22. In step S20, a P-type dopant is implanted into the entire lower surface 64 of the semiconductor substrate 10. Step S20 may be a dopant implantation intended to form the collector region 22 in the IGBT region 70. That is, in step S20, the P-type dopant may be doped at a dose corresponding to the doping concentration of the collector region 22 in the semiconductor device 100.

  (C) of FIG. 4B shows the injection step (S30) for the cathode region 82. In step S30, first, a mask 68 of a photoresist material or the like is formed in contact with the entire lower surface 64. Thereafter, the mask 68-1 is patterned in the range corresponding to the collector region 22 in the XY plane. Thereafter, an N-type dopant is implanted into the lower surface 64 of the semiconductor substrate 10. Step S30 may be a dopant implant aimed at forming cathode region 82 in FWD region 80. That is, in step S30, the N-type dopant may be doped at a dose corresponding to the doping concentration of the cathode region 82 in the semiconductor device 100.

  Thereby, in the range where the mask 68-1 is not provided, the region where the P-type dopant is implanted is counter-doped. In the range where the mask 68-1 is provided, the N-type dopant may not be implanted. After doping, the mask 68-1 may be removed.

  (D) of FIG. 4B shows the implantation step (S40) for the floating region 84. In step S40, a mask 68-2 is provided in the range corresponding to the floating region 84 in the XY plane. The mask 68-2 of the present embodiment is formed in the same manner as the mask 68-1, but provided in a range different from the mask 68-1 in the XY plane.

  Thereafter, a P-type dopant is implanted into the lower surface 64 of the semiconductor substrate 10. Step S40 may be a dopant implantation intended to form P-type floating region 84. That is, in step S40, the P-type dopant may be doped at a dose corresponding to the doping concentration of the floating region 84 in the semiconductor device 100. The implantation depth range of step S40 may be shallower than the implantation depth range of the cathode region 82. After doping, the mask 68-2 may be removed.

  As described above, in steps S30 and S40, multiple mask processes are performed to form, pattern and remove the mask 68. Therefore, the later of the multiple injection steps, the higher the probability of particle 86 generation and adhesion. Then, there is a possibility that defects 88 or scratches may occur in the semiconductor substrate 10 due to particles. The defects 88 and flaws generated in the cathode region 82 directly affect the electrical characteristics of the FWD region 80, so the semiconductor device 100 is greatly affected. For example, if defects 88 or scratches occur in the cathode region 82, effects such as junction leakage, breakdown voltage failure, and deterioration in switching characteristics may occur.

  Therefore, in the present embodiment, the implantation step (S40) for the floating region 84 is performed after the implantation step (S30) for the cathode region 82. Thereby, the implantation step for the cathode region 82 can be performed on the lower surface 64 that is in a cleaner state as compared to the case where the implantation step for the cathode region 82 is performed after the implantation step for the floating region 84. Therefore, the risk of defects 88 or flaws in the cathode region 82 in step S30 can be reduced. Therefore, in the semiconductor device 100, current leak and withstand voltage failure can be reduced. Thus, in the present embodiment, the non-defective rate of the RC-IGBT can be improved.

  In the present embodiment, since the implantation step (S20) for the collector region 22 is performed in a state where the lower surface 64 is clean, defects 88 and scratches in the collector region 22 can also be reduced. Thereby, current leak and withstand voltage failure can be reduced also in the collector region 22. However, in the present embodiment, after the implantation step (S40) for the floating region 84, more defects 88 may be introduced in the floating region 84 than when the implantation step (S30) for the cathode region 82 is performed. . However, the defect 88 introduced into the floating region 84 has less influence on the FWD region 80 than when the defect 88 or a defect is introduced into the cathode region 82. Therefore, in the present embodiment, the defects 88 introduced into the floating region 84 may be considered to be acceptable.

  FIG. 4B (e) shows a first annealing step (S50). In the present embodiment, the semiconductor substrate 10 is annealed at a temperature of 1000 ° C. by irradiating the lower surface 64 with a laser beam. The laser light may have energy higher than the band gap energy of the semiconductor substrate 10. Step S50 can recover the crystal defects generated by the dopant ion implantation and activate the implanted dopant.

  (F) of FIG. 4B shows the injection step (S60) for the FS region 20. In the present embodiment, in order to form the FS region 20, hydrogen is injected from the lower surface 64 to a predetermined depth range. Hydrogen may be implanted into the semiconductor substrate 10 in the state of hydrogen ions (ie, protons). The implantation energy may be changed to implant hydrogen ions in multiple stages into the semiconductor substrate 10 so that a plurality of peaks are provided in the FS region 20 in the Z-axis direction.

  FIG. 4B (g) shows a second annealing step (S70). In the present embodiment, the semiconductor substrate 10 is placed in the heat treatment furnace 150, and the semiconductor substrate 10 is annealed at a temperature of about 400.degree. By annealing the FS region 20 separately from step S50, the temperature is different from that of the P-type and N-type dopants implanted in step S20 to step S40, and at a temperature most suitable for the activation of hydrogen. Hydrogen in the FS region 20 can be activated. In addition, by performing the implantation step for FS region 20 after step S50, the dopant implantation accuracy for FS region 20 is improved as compared to the case where the implantation step for FS region 20 is performed before step S50. Can.

  (H) of FIG. 4B shows the step of forming the collector electrode 24 (S80). In the present embodiment, the collector electrode 24 in contact with the entire lower surface 64 is formed by sputtering. Thus, the semiconductor device 100 is completed. The position of the end portion 91 may be a position after the injection stage for the collector region 22, the injection stage for the cathode region 82, and the injection stage for the floating region 84. The position of the end 91 in this embodiment is the position of the end 91 after step S80.

  FIG. 5A is a flowchart showing a method of manufacturing the semiconductor device 120 according to the first modification of the first embodiment. The semiconductor device 120 is shown in the next drawing. In this embodiment, the implantation step (S20) for the collector region 22 is performed after the implantation step (S12) for the cathode region 82, and the implantation step (S40) for the floating region 84 is performed after the implantation step (S20) for the collector region 22. )I do. The point which concerns is different from 1st Embodiment. The description of the same steps as in the first embodiment is omitted.

  FIG. 5B is a diagram showing each step of the method of manufacturing the semiconductor device 120 according to the first modification of the first embodiment. Step S12 of (a) of FIG. 5B corresponds to step S30 of (c) of FIG. 4B, and step S20 of (b) of FIG. 5B corresponds to step S20 of (b) of FIG. Step S40 of c) corresponds to step S40 of (d) of FIG. 4B, and step S80 of (d) of FIG. 5B corresponds to step S80 of (h) of FIG. 4B. Also in the first modification, the current leak and the withstand voltage failure in the cathode region 82 and the collector region 22 can be reduced, so that the yield rate of the RC-IGBT can be improved.

  FIG. 6A is a flowchart showing a method of manufacturing the semiconductor device 140 in the second modified example of the first embodiment. The semiconductor device 140 is shown in the next drawing. In this embodiment, the implantation step (S40) for the floating region 84 is performed after the implantation step (S30) for the cathode region 82, and the implantation step (S42) for the collector region 22 after the implantation step (S40) for the floating region 84. )I do. The point which concerns is different from 1st Embodiment. The description of the same steps as in the first embodiment is omitted.

  FIG. 6B is a diagram showing each step of the method of manufacturing the semiconductor device 140 in the second modified example of the first embodiment. Step S30 of (a) of FIG. 6B corresponds to step S30 of (c) of FIG. 4B, and step S40 of (b) of FIG. 6B corresponds to step S40 of (d) of FIG. Step S42 of c) corresponds to step S20 of (b) of FIG. 4B, and step S80 of (d) of FIG. 6B corresponds to step S80 of (h) of FIG. 4B. In the second modification, the current leak and the withstand voltage failure in the cathode region 82 can be reduced, so the yield rate of RC-IGBT can be improved.

FIG. 7 is a view showing the concentration distribution of electrons and holes in the vicinity of the boundary 72 in the first embodiment. A partially enlarged view of the vicinity of the boundary 72 in the semiconductor device 100 is shown in the center of FIG. FIG. 7 shows the electron-hole concentration distributions in the CC cross section and the DD cross section of the partial enlarged view, with the partial enlarged view in the vicinity of the boundary 72 interposed therebetween. In the CC cross section and the DD cross section, the horizontal axis is the electron concentration or the hole concentration (cm ⁻³ ), and the vertical axis is the depth position (μm). As used herein, electron concentration and hole concentration are effective (ie, net) concentrations. The effective concentration is, for example, the difference between the electron concentration and the hole concentration.

  The CC cross section passes through the drift region 18, the FS region 20 and the collector region 22 in order of proximity to the top surface 62. Since the drift region 18 and the FS region 20 are N-type regions, they are regions in which electrons are majority carriers. The concentration in the N-type region means the electron concentration. On the other hand, since the collector region 22 is a P-type region, it is a region where holes are majority carriers. The concentration of the P-type region means the concentration of holes. In the depth direction, the peaks of the ion-implanted P-type and N-type dopant concentration distributions may coincide with the peak positions of the hole concentration and the electron concentration, respectively. Note that the concentration peak position of the implanted dopant and the concentration peak position of the electron or hole do not have to completely coincide with each other due to annealing or the like after the dopant implantation. However, the relative positional relationship of each peak may be considered to be approximately the same.

  The DD cross section passes through the drift region 18, the FS region 20, the floating region 84 and the cathode region 82 in order of proximity to the top surface 62. The concentration in the floating region 84 is the hole concentration, and the concentration in the cathode region 82 is the electron concentration.

  FIG. 8 is a diagram showing a stage of a method of manufacturing the semiconductor device 160 in the third modified example of the first embodiment. Step S140 of FIG. 8 (a) corresponds to step S40 of FIG. 4B (d), and step S180 of FIG. 8 (b) corresponds to step S80 of FIG. 4B (h). The description of the same steps as those of the first embodiment will be omitted. The third modification differs from the first embodiment in that the floating region 84 is formed in the cathode region 82. In the third modification, in the cathode region 82 between the upper end of the floating region 84 and the FS region 20, a tail region of the P-type dopant concentration distribution used to form the floating region 84 may be present. Similarly, in the cathode region 82 between the lower end of the floating region 84 and the lower surface 64, a tail region of the P-type dopant concentration distribution used to form the floating region 84 may be present.

  In addition, the peak of the P-type dopant concentration distribution of floating region 84 may be present at a position closer to FS region 20 than half the depth position of cathode region 82. In the third modification, floating region 84 is provided closer to FS region 20 than to lower surface 64. Thereby, the risk of the floating region 84 being exposed to the lower surface 64 of the semiconductor device 120 can be reduced while the floating region 84 is provided in the cathode region 82. The third variation of FIG. 8 may be combined with the first variation of FIGS. 5A and 5B and the second variation of FIGS. 6A and 6B.

FIG. 9 is a diagram showing a stage of a method of manufacturing the semiconductor device 180 in the fourth modified example of the first embodiment. Step S240 of (a) of FIG. 9 corresponds to step S40 of (d) of FIG. 4B, and step S280 of (b) of FIG. 9 corresponds to step S80 of (h) of FIG. 4B. The description of the same steps as in the first embodiment will be omitted. The fourth modification is different from the first embodiment in that the lower end of the floating region 84 is formed above the cathode region 82. In (b) of FIG. 9, it indicates the distance between the upper end of the lower end and the cathode region 82 of the floating region 84 as L _2. In the fourth modification, in the FS region 20 between the lower end of the floating region 84 and the upper end of the cathode region 82, a tail region of the P-type dopant concentration distribution used to form the floating region 84 may be present. Further, as in the first embodiment, a tail region of the P-type dopant concentration distribution used to form the floating region 84 may be present between the upper end of the floating region 84 and the upper end of the FS region 20. The fourth modification of FIG. 9 may be combined with the first modification of FIGS. 5A and 5B and the second modification of FIGS. 6A and 6B.

  FIG. 10A is a flowchart showing a method of manufacturing the semiconductor device 200 in the second embodiment. The semiconductor device 200 is shown in the next figure. The manufacturing method of the second embodiment includes the steps of forming the top surface structure 116 (S410), injecting the collector region 22 (S420), injecting the floating region 84 (S440), and injecting the cathode region 82 (S44). S444), a first annealing step (S450), an implantation step for FS region 20 (S460), a second annealing step (S470), and a collector electrode 24 forming step (S480). Also in the second embodiment, the steps are performed in ascending order of the number following S.

  FIG. 10B is a diagram showing each step of the method of manufacturing the semiconductor device 200 in the second embodiment. Step S410 of (a) of FIG. 10B corresponds to step S10 of (a) of FIG. 4B. Step S420 of (b) of FIG. 10B corresponds to step S20 of (b) of FIG. 4B. Step S440 of (c) of FIG. 10B corresponds to step S40 of (d) of FIG. 4B. Step S444 of (d) of FIG. 10B corresponds to step S30 of (c) of FIG. 4B. Step S450 of (e) of FIG. 10B corresponds to step S50 of (e) of FIG. 4B. Step S460 of (f) of FIG. 10B corresponds to step S60 of (f) of FIG. 4B. Step S470 of (g) of FIG. 10B corresponds to step S70 of (g) of FIG. 4B. Step S480 of (h) of FIG. 10B corresponds to step S80 of (h) of FIG. 4B.

  If the implantation step for floating region 84 is performed after the implantation step for collector region 22 and the implantation step for cathode region 82, the cathode region 82 includes N for the cathode region 82 in addition to the P-type dopant for collector region 22. Type dopant is to be implanted. Therefore, the disorder of crystallinity in the cathode region 82 immediately below the floating region 84 may be large. If the crystalline disorder in the cathode region 82 is large, the implantation range of the P-type dopant for the floating region 84 may vary from the design range. For example, P-type dopants may also vary in the XY plane direction in addition to the Z-axis direction.

  On the other hand, in the second embodiment, after the injection step for the collector region 22 (S420) and the injection step for the floating region 84 (S440), the injection step for the cathode region 82 (S444) is performed. In the second embodiment, the P-type dopant for floating region 84 after the P-type dopant implantation step for collector region 22 (S420) and before the N-type dopant implantation step for cathode region 82 (S444). Since the floating region 84 is injected (S440), the floating region 84 can be provided with better controllability. Thereby, the implantation range of the P-type dopant for floating region 84 can be provided in the design range. Therefore, characteristic variations in the plurality of semiconductor devices 200 can be reduced.

  Furthermore, in the present embodiment, since the implantation step (S420) for the collector region 22 is performed in a state where the lower surface 64 is clean, defects 88 and flaws in the collector region 22 can be reduced. Thus, current leak and withstand voltage failure can be reduced in the semiconductor device 200. Also in the present embodiment, the floating region 84 may be formed in the cathode region 82 as in the semiconductor device 160 of FIG. 8. In addition, as in the semiconductor device 180 of FIG. 9, the lower end of the floating region 84 may be formed above the cathode region 82.

  FIG. 11A is a flowchart showing a method of manufacturing the semiconductor device 220 in the first modified example of the second embodiment. The semiconductor device 220 is shown in the next drawing. In the first modification, the injection step for collector region 22 (S 442) is performed after the injection step for floating region 84 (S 440), and the injection step for cathode region 82 (S 442) is performed after the injection step for collector region 22 (S 442). S444) is performed. The point which concerns is different from 2nd Embodiment.

  FIG. 11B is a diagram showing each step of the method of manufacturing the semiconductor device 220 in the first modified example of the second embodiment. Step S440 of (a) of FIG. 11B corresponds to step S440 of (c) of FIG. 10B. Step S442 of (b) of FIG. 11B corresponds to step S420 of (b) of FIG. 10B. Step S444 of (c) of FIG. 11B corresponds to step S444 of (d) of FIG. 10B. Step S480 of (d) of FIG. 11B corresponds to step S480 of (h) of FIG. 10B. In the first modification, since the floating region 84 is first formed in the formation of the lower surface structure 118, the controllability of the floating region 84 can be further improved as compared with the second embodiment.

  FIG. 12A is a flowchart showing a method of manufacturing the semiconductor device 240 in the second modified example of the second embodiment. The semiconductor device 240 is shown in the next drawing. In the second modification, the implantation step (S444) for the cathode region 82 is performed after the implantation step (S440) for the floating region 84, and the implantation step for the collector region 22 (S444) after the implantation step (S444) for the cathode region 82. S448) is performed. The point which concerns is different from 2nd Embodiment.

  FIG. 12B is a diagram showing each step of the method of manufacturing the semiconductor device 240 in the second modified example of the second embodiment. Step S440 of (a) of FIG. 12B corresponds to step S440 of (c) of FIG. 10B. Step S444 of (b) of FIG. 12B corresponds to step S444 of (d) of FIG. 10B. Step S448 of (c) of FIG. 12B corresponds to step S420 of (b) of FIG. 10B. Step S480 of (d) of FIG. 12B corresponds to step S480 of (h) of FIG. 10B. Also in the second modification, since the floating region 84 is first formed in the formation of the lower surface structure 118, the controllability of the floating region 84 can be further improved compared to the second embodiment.

  Also in the second embodiment, the first modified example of the second embodiment, and the second modified example of the second embodiment, as in the semiconductor device 160 of FIG. You may form. In addition, as in the semiconductor device 180 of FIG. 9, the lower end of the floating region 84 may be formed above the cathode region 82.

  FIG. 13A is a flowchart showing a method of manufacturing the semiconductor device 300 in the third embodiment. The semiconductor device 300 is shown in the next drawing. The third embodiment is different from the above-described embodiment in that the position of the boundary 72 coincides with the end 91 of the floating region 84. The order of the steps shown in FIG. 13A is the same as in FIG. 4A, but steps S520, S530 and S540 may be replaced as appropriate, as in the embodiments of FIGS. 5A, 6A, 10A, 11A and 12A.

  FIGS. 13A and 13B are views showing steps of a method of manufacturing the semiconductor device 300 in the third embodiment. FIG. 13B (a) shows the implantation step (S540) for the floating region 84, and FIG. 13B (b) shows the step of forming the collector electrode 24 (S580). In step S540, the end 69 in the X-axis direction of the mask 68-2 corresponding to the floating region 84 is aligned with the boundary 72. Thereby, as shown in step S580, the end 91 of the floating region 84 in the semiconductor device 300 is located at the boundary 72 in the X-axis direction. Also in the present embodiment, the position of the end 91 is after the injection step for the collector region 22 (S520), the injection step for the cathode region 82 (S530), and the injection step for the floating region 84 (S540). Position in the

  In step S540, a P-type dopant may be implanted in a range closer to the top surface 62 than the cathode region 82. As a result, in the semiconductor device 300, the lower end 94 of the floating region 84 may be separated from the upper end 83 of the cathode region 82.

  In the present embodiment, the floating region 84 can be reliably separated from the collector region 22 in the Z-axis direction while bringing the floating region 84 as close as possible to the IGBT region 70 in the XY plane direction. Therefore, compared to the case where floating region 84 is provided up to IGBT region 70, short circuit between floating region 84 and collector region 22 can be more reliably prevented. In the semiconductor device 300, the upper end 93 of the floating region 84 may be closer to the lower surface 64 than the upper end of the FS region 20. That is, the FS region 20 may exist above the upper end 93 of the floating region 84.

FIG. 13C is a view showing concentration distribution of electrons and holes in the vicinity of the boundary 72 in the third embodiment. A partially enlarged view of the vicinity of the boundary 72 in the semiconductor device 300 is shown in the center of FIG. 13C. FIG. 13C shows the electron-hole concentration distribution in the EE cross section and the FF cross section of the partial enlarged view, with the partial enlarged view in the vicinity of the boundary 72 interposed therebetween. In the EE cross section and the FF cross section, the horizontal axis is the electron concentration or the hole concentration (cm ⁻³ ), and the vertical axis is the depth position (μm).

  The EE cross section is the same as the CC cross section in FIG. The FF cross section is similar to the DD cross section of FIG. However, in the F-F cross section, the FS region 20 is provided between the upper end 83 of the cathode region 82 and the lower end 94 of the floating region 84. The F-F cross section may be the same as (b) of FIG. 9 except for the position of the end 91 of the floating region 84.

  The floating region 84 may be spaced from the top end 83 of the cathode region 82, as shown in FIG. 13C. In the present embodiment in which the positions of the upper end of the cathode region 82 and the collector region 22 are the same in the Z-axis direction, the lower end 94 of the floating region 84 is closer to the upper surface 62 than the upper end 23 of the collector region 22. Further, the upper end 93 of the floating region 84 is located below the upper end of the FS region 20. In the present embodiment, the upper end 83 of the cathode region 82 is closer to the upper surface 62 than the upper end 23 of the collector region 22 in the Z-axis direction, and the floating region 84 is separated from the upper end 83 of the cathode region 82. Good.

  FIG. 13D is a view showing concentration distribution of electrons and holes in the vicinity of the boundary 72 in the first modified example of the third embodiment. A partial enlarged view in the vicinity of the boundary 72 is shown in the center of FIG. 13D, and dopant concentration distributions in the GG section and the HH cross section of the partial enlarged view are shown on the left and right of FIG. 13D, respectively. The horizontal and vertical axes of the GG and HH cross sections are the same as in FIG. 13C.

  In the first modification, the thickness in the Z-axis direction of the cathode region 82 is made thicker than the thickness in the Z-axis direction of the collector region 22. The upper end 83 of the cathode region 82 and the lower end 94 of the floating region 84 are positions where the electron concentration and the hole concentration form a valley. For example, by performing the implantation step S530 for the cathode region 82 for implanting the N-type dopant after the implantation step S520 for the collector region 22 for implanting the P-type dopant into the lower surface 64, the cathode region 82 thicker than the collector region 22 is implemented. Form. Alternatively, the implantation step S530 for the cathode region 82 for implanting the N-type dopant may be performed first, and then the implantation step S520 for the collector region 22 may be performed.

  In the first modification, since the cathode region 82 is thicker than the collector region 22, the upper end 93 of the cathode region 82 is closer to the upper surface 62 than the upper end 23 of the collector region 22. Further, the lower end 94 of the floating region 84 is closer to the upper surface 62 than the upper end 23 of the collector region 22. Thereby, short circuit between floating region 84 and collector region 22 can be reliably prevented. Therefore, the characteristics of the semiconductor device 300 can be made close to the designed characteristics. Further, not only in the third embodiment in which the position of the boundary 72 coincides with the end 91 of the floating region 84, but also in the first and second embodiments, the cathode region 82 is thicker than the collector region 22. In this way, it is easier to manufacture the intended structure, and the reliability can be further improved. The cathode region 82 being thicker than the collector region 22 is not limited to the case where the cathode region 82 is thicker than the collector region 22 due to a slight difference, and the cathode region 82 is clearer than the collector region 22. A thick case may be intended. Specifically, the cathode region 82 may be about 1.2 times thicker than the collector region 22, and preferably the cathode region 82 may be about 1.4 times thicker than the collector region 22, more preferably The cathode region 82 may be about 1.6 times thicker than the collector region 22.

  The implantation step S540 for the floating region 84 may be performed before the implantation step S520 for the collector region 22 and the implantation step S530 for the cathode region 82. Also, the implantation step S540 for the floating region 84 is performed between the implantation step S520 for the collector region 22 and the implantation step S530 for the cathode region 82 or after the implantation step S520 for the collector region 22 and the implantation step S530 for the cathode region 82. You may Also in the first modification, the end 91 of the floating region 84 is located at the boundary 72.

  FIG. 13E is a view showing concentration distribution of electrons and holes in the vicinity of the boundary 72 in the second modified example of the third embodiment. A partial enlarged view in the vicinity of the boundary 72 is shown in the center of FIG. 13E, and in FIG. 13E, the dopant concentration distribution in the I-I cross section and the JJ cross section of the partial enlarged view is shown respectively . The horizontal and vertical axes of the I-I cross section and the JJ cross section are the same as in FIG. 13C.

  Also in the second modification, the thickness in the depth direction of the cathode region 82 is made thicker than the thickness in the Z-axis direction of the collector region 22. The depth direction may be parallel to the direction from the lower surface 64 toward the upper surface 62. In the implantation step for the cathode region 82, N-type ions may be implanted with different acceleration energy. That is, in the implantation step for the cathode region 82, the ion implantation may be performed so that the concentration distribution of the N-type ions has a peak at one position in the depth direction, and the concentration distribution of the N-type ions differs in the depth direction The ion implantation may be performed to have peaks at a plurality of positions.

  When cathode region 82 has peaks at a plurality of different positions in the depth direction, the peak position of the P-type dopant concentration distribution of floating region 84 is provided between the plurality of peaks of the N-type dopant concentration distribution of cathode region 82 You may Each of the plurality of peak concentrations in the N-type dopant concentration distribution of cathode region 82 may be the same, may decrease toward upper surface 62, and may increase toward upper surface 62. Further, the P-type dopant concentration implanted in the implantation step S540 for the floating region 84 may be higher than the N-type dopant concentration implanted in the implantation step S530 for the cathode region 82 in the region of the floating region 84.

  In the second modification, N-type dopant is implanted in step S530 such that the cathode region 82 has two peaks of N-type dopant concentration at different positions in the depth direction. Thus, the cathode region 82 has two electron concentration peaks at different positions in the depth direction. Furthermore, in the second modification, the P-type dopant is implanted in step S540 such that the P-type dopant concentration peak of the floating region 84 is located between the two N-type dopant concentration peaks. Thereby, the peak position of the hole concentration in the floating region 84 is located between the two electron concentration peaks in the cathode region 82 in the depth direction. In the second modification, even if the P-type dopant concentration is reduced in the implantation step for floating region 84 as compared with the case where the peak position of cathode region 82 and the peak position of floating region 84 overlap in the depth direction, A floating region 84 having sufficient P-type characteristics can be obtained.

  In another embodiment, the cathode region 82 may have three or more N-type dopant concentration peaks at different positions in the depth direction. In this case, the peak position of the floating region 84 may be provided between any two peak positions of the cathode region 82.

  In the second modification, the entire range in the Z-axis direction of floating region 84 is located in cathode region 82. Further, the lower end 94 of the floating region 84 is closer to the upper surface 62 than the upper end 23 of the collector region 22. Therefore, floating region 84 can be reliably separated from collector region 22 in the Z-axis direction while floating region 84 is as close as possible to IGBT region 70 in the XY plane direction. However, in other embodiments, at least a portion of floating region 84 may be located in cathode region 82. That is, the lower portion of the floating region 84 may partially overlap the upper portion of the cathode region 82, and the upper end 93 of the floating region 84 may be above the upper end 83 of the cathode region 82. Such a shape is easily formed when the peak of floating region 84 is higher in concentration than the peak of cathode region 82.

  The description of collector region 22, cathode region 82, and floating region 84 in FIGS. 13B to 13E corresponds to the first embodiment and the second embodiment in which end portion 91 of floating region 84 does not reach boundary 72 in the X-axis direction. May also apply.

  FIG. 14 is a top view of the FWD region 80 according to the fourth embodiment. The semiconductor device of the fourth embodiment may have both the FWD region 80 and the IGBT region 70 in one semiconductor substrate 10, and may have only the FWD region 80. The IGBT region 70 is the same as the IGBT region 70 in any of the first to third embodiments. The IGBT region 70 is arranged side by side with the FWD region 80 in top view.

  In this example, a region in which a gate structure including the gate trench portion 40 and the emitter region 12 is periodically arranged is referred to as an IGBT region 70. Further, a region in which the gate structure is not provided and in which the cathode region 82 is periodically arranged on the lower surface 64 of the semiconductor substrate 10 is referred to as an FWD region 80. In the upper surface of each mesa 60 in the FWD region 80, an area of 80% or more may be a P-type region such as the base region 14.

  The FWD region 80 according to the first to third embodiments in that the FWD region 80 of the present embodiment includes the inter-cathode region 81 of the first conductivity type (P + type in this embodiment) exposed on the lower surface 64 of the semiconductor substrate 10. It is different from. The structure other than the inter-cathode region 81 is the same as any one of the first to third embodiments. The doping concentration of the inter-cathode region 81 and the thickness in the Z-axis direction may be the same as that of the collector region 22 of the IGBT region 70.

  The inter-cathode regions 81 are alternately arranged with the cathode regions 82 in a predetermined direction in a plane parallel to the lower surface 64. In the example of FIG. 14, the inter-cathode regions 81 and the cathode regions 82 are alternately arranged along the Y-axis direction. The inter-cathode region 81 and the cathode region 82 may have a band shape extending in the X-axis direction from one end to the other end of the FWD region 80 in the X-axis direction.

  In another example, the inter-cathode regions 81 and the cathode regions 82 may be alternately arranged along a direction different from the Y-axis direction. In addition, the inter-cathode regions 81 and the cathode regions 82 may be alternately arranged in two directions. The inter-cathode regions 81 and the cathode regions 82 may be alternately arranged in both the X-axis direction and the Y-axis direction.

  Floating region 84 is provided above cathode region 82 and above inter-cathode region 81. However, the floating region 84 is not provided above the partial region of the cathode region 82. In addition, the floating region 84 is not provided above the partial region of the inter-cathode region 81.

  By providing the inter-cathode region 81 and the floating region 84 in the FWD region 80, the amount of carriers injected from the cathode region 82 can be adjusted more accurately. Therefore, the characteristics of the semiconductor device can be adjusted more accurately.

  FIG. 15 is a perspective sectional view including the K-K cross section and the L-L cross section in FIG. The KK cross section is an XZ plane, and the LL cross section is a YZ plane. In FIG. 15, the cross section of the semiconductor substrate 10 is shown, and the interlayer insulating film 38, the emitter electrode 52 and the collector electrode 24 are omitted.

  As shown in FIGS. 14 and 15, the floating regions 84 in this example are arranged to overlap with part of the respective cathode regions 82 in the X-axis direction. That is, a part of the cathode region 82 in the X-axis direction does not overlap with the floating region 84. The floating regions 84 may be arranged to overlap with part of the respective inter-cathode regions 81 in the X-axis direction. A part of the inter-cathode region 81 in the X-axis direction may not overlap with the floating region 84. Note that “overlap” means being disposed at opposing positions in the Z-axis direction. As shown in FIG. 14, the floating regions 84 may be discretely arranged in the X-axis direction. Between the two floating regions 84, a drift region 18 or FS region 20 may be provided.

  As shown in FIGS. 14 and 15, the floating region 84 of this example is disposed to overlap the entire cathode region 82 in the Y-axis direction. The floating region 84 in this example extends to a position overlapping a part of the inter-cathode region 81 in the Y-axis direction. As shown in FIG. 14, the floating regions 84 may be discretely arranged in the Y-axis direction. Both ends of each cathode region 82 in the Y-axis direction may overlap with the floating region 84. In another example, floating regions 84 may be arranged to overlap the entire inter-cathode regions 81 in the Y-axis direction. In this case, floating region 84 may extend to a position overlapping a portion of cathode region 82 in the Y-axis direction.

  As shown in FIG. 15, the dummy trench portion 30 is provided to extend in a predetermined extending direction (in this example, the Y-axis direction). The extending direction of the dummy trench portion 30 is the longitudinal direction of the dummy trench portion 30 in a top view. The inter-cathode regions 81 and the cathode regions 82 are alternately arranged along the extension direction (Y-axis direction) of the dummy trench portion 30. Therefore, both of the inter-cathode region 81 and the cathode region 82 are disposed below the respective mesa portions 60-2. Therefore, in each of the mesa portions 60-2, the carrier injection amount from the cathode region 82 can be made uniform.

  Further, the floating region 84 is disposed apart from the inter-cathode region 81 in the depth direction of the semiconductor substrate 10. Thereby, floating region 84 can be prevented from being connected to collector electrode 24 via inter-cathode region 81. FS region 20 or drift region 18 may be provided between inter-cathode region 81 and floating region 84.

  FIG. 16 is an enlarged top view for explaining an arrangement example of floating region 84, cathode region 82 and inter-cathode region 81. Referring to FIG. In this example, the area where the floating area 84 and the inter-cathode area 81 overlap is the first area 101, the area between the cathode 81 is provided, and the area where the floating area 84 is not provided is floating with the second area 102, the cathode area 82. A region where the regions 84 overlap is referred to as a third region 103, and a region where the cathode region 82 is provided and the floating region 84 is not provided is referred to as a fourth region 104. The first region 101 is a region in which the electron injection amount from the lower surface 64 side is the smallest, that is, a region in which the electron injection amount is substantially zero, and the fourth region 104 is a region in which the electron injection amount from the lower surface 64 side is the largest. It is an area. Similarly to the first region 101, the second region 102 is also a region where there is substantially no electron injection. On the other hand, the first region 101 and the second region 102 have an effect of injecting holes at the time of reverse recovery, and the floating region 84 can also adjust the injection amount of holes. The third region 103 is a region where the injection amount of electrons from the lower surface 64 side is larger than that of the first region 101 and the second region 102 and smaller than that of the fourth region 104. The electron injection amount is the injection amount per unit area.

  Thus, by arranging the floating region 84 and the cathode region 82 and the inter-cathode region 81 in an overlapping manner, the first region 101 and the second region 102 for adjusting the injection of carriers (electrons and holes), A third region 103 and a fourth region 104 can be provided. By adjusting the area ratio of these regions, the total injection amount of carriers (electrons and holes) in the FWD region 80 can be accurately adjusted. Further, floating regions 84 are provided for each of the inter-cathode regions 81 in the Y-axis direction, and the width of the floating regions 84 is larger than the width of the inter-cathode regions 81, whereby each of the cathode region 82 and the inter-cathode region 81 is formed. The third area 103 can be arranged at the boundary.

  As an example, the area of floating region 84 in top view may be larger than the area of cathode region 82. The area of the floating region 84 is larger than the area of the first region 101. In addition, the area of the floating region 84 is larger than the area of the third region 103. The area of floating region 84 may be 90% or less of the sum of the areas of cathode region 82 and inter-cathode region 81. In addition, the area of the inter-cathode region 81 may be larger than the area of the cathode region 82. The area of each region indicates the total area of each region in FWD region 80.

  FIG. 17 is a view showing the cathode region 82 and the inter-cathode region 81 in the YZ plane. The cathode region 82 is provided to be deeper than the inter-cathode region 81 with reference to the lower surface 64 of the semiconductor substrate 10. The thickness of the cathode region 82 in the depth direction (Z-axis direction) is Z2, and the thickness of the inter-cathode region 81 is Z1. The thickness Z2 is larger than the thickness Z1.

  The floating region 84 is disposed above the upper end of the cathode region 82. By increasing the thickness Z2 of the cathode region 82, contact between the floating region 84 and the inter-cathode region 81 can be suppressed. The floating region 84 may be in contact with or separated from the cathode region 82.

  FIG. 18 is a top view of the FWD area 80 according to a first modification of the fourth embodiment. In the FWD region 80 of this example, the arrangement of the floating region 84 in the Y-axis direction is different from the example described in FIGS. 14 to 16. The other structure is the same as the example described in FIG. 14 to FIG.

  The floating region 84 in this example overlaps with the whole of the inter-cathode region 81 in the Y-axis direction, and overlaps with a partial region of the cathode region 82 in the Y-axis direction. In the example shown in FIG. 14, the area of the fourth region 104 shown in FIG. 16 can be reduced, and the amount of injected electrons from the cathode region 82 can be reduced. In this example, since the area of the fourth region 104 is increased, the injection amount of electrons from the cathode region 82 is increased. Thus, the amount of injected electrons from the cathode region 82 can be easily adjusted by providing the floating region 84 and the inter-cathode region 81.

  FIG. 19 is a top view of an FWD region 80 according to a second modification of the fourth embodiment. The FWD regions 80 of this example differ from the examples described in FIGS. 14 to 18 in that cathode regions 82 and inter-cathode regions 81 are alternately arranged along the X-axis direction. The other structure is the same as the example described in FIG. 14 to FIG.

  In FIG. 19, floating region 84 is disposed so as to overlap the whole of cathode region 82 in the X-axis direction, and to overlap a partial region of inter-cathode region 81 in the X-axis direction. In another example, floating region 84 may overlap with the whole of inter-cathode region 81 in the X-axis direction, and may overlap with a partial region of cathode region 82 in the X-axis direction. Also in this example, it is possible to control the electron injection amount from the cathode region 82 of the FWD region 80 with high accuracy.

  FIG. 20 is a top view of an FWD region 80 according to a third modification of the fourth embodiment. In the FWD region 80 of this example, the arrangement of the floating region 84 is different from the example described in FIGS. 14 to 19. The other structure is the same as the example described in FIG. 14 to FIG.

  In this example, the width in the X-axis direction of floating region 84 arranged closest to boundary 72 with IGBT region 70 is X1. Further, the width in the X-axis direction of the floating region 84 disposed at the center in the X-axis direction of the FWD region 80 is X2. The width X1 of this example is larger than the width X2. The width X1 may be 1.5 times or more of the width X2 or may be twice or more. Thereby, in the vicinity of the boundary 72 with the IGBT region 70, the injection of electrons from the cathode region 82 can be suppressed. Therefore, carriers flowing from the FWD region 80 to the IGBT region 70 can be reduced. The floating region 84 disposed closest to the boundary 72 with the IGBT region 70 may have the largest width in the X-axis direction in the plurality of floating regions 84.

  In another example, the width X1 may be smaller than the width X2. The width X2 may be 1.5 times or more of the width X1 or may be twice or more. The floating region 84 disposed closest to the boundary 72 with the IGBT region 70 may have a minimum width in the X-axis direction in the plurality of floating regions 84.

  FIG. 21 is a top view of an FWD region 80 according to a third modification of the fourth embodiment. In the FWD region 80 of this example, the arrangement of the floating region 84 is different from the example described in FIGS. 14 to 20. The other structure is the same as the example described in FIGS. 14 to 20.

  The floating region 84 in this example is continuously provided across the entire one or more cathode regions 82 and the entire one or more inter-cathode regions 81 in the Y-axis direction. The floating region 84 may be provided continuously across the plurality of cathode regions 82 and the plurality of inter-cathode regions 81.

  FIG. 22 is a diagram showing an example of the M-M cross section in FIG. FIG. 22 shows a cross section in the vicinity of the lower surface 64 of the semiconductor substrate 10. In this example, the distance in the depth direction (Z-axis direction) between the upper end of the cathode region 82 and the lower end of the floating region 84 is Z5. Further, the distance in the depth direction (Z-axis direction) between the upper end of the inter-cathode region 81 and the lower end of the floating region 84 is taken as Z3.

  Each distance in the depth direction may be measured at the center of the cathode region 82 and the center of the inter-cathode region 81 in the Y-axis direction. Further, the average value of the distance between the cathode region 82 and the floating region 84 may be the distance Z5. Further, the average value of the distance between the inter-cathode region 81 and the floating region 84 may be set as the distance Z3.

  The distance Z5 may be smaller than the distance Z3. As a result, the distance between the cathode region 82 into which electrons are injected and the floating region 84 can be reduced to facilitate the suppression of electron injection. Further, by making the distance Z3 larger than the distance Z5, the floating region 84 can be prevented from contacting the inter-cathode region 81. The distance Z3 may be 1.1 times or more, 1.2 times or more, or 1.5 times or more of the distance Z5. Also, the distance Z5 may be zero and the distance Z3 may be greater than zero.

  In the present embodiment, the shape of the floating region 84 is described using the example shown in FIG. 21. However, the floating region 84 may have the same shape also in the examples shown in FIGS. 14 to 20. In the case where the floating region 84 is formed by implanting a P-type dopant from the lower surface 64 side after forming both the cathode region 82 and the inter-cathode region 81, the distance Z5 is obtained also in the example shown in FIGS. Is smaller than the distance Z3. The shape of such floating region 84 is not limited to the case where floating region 84 is formed across a plurality of cathode regions 82 and a plurality of inter-cathode regions 81 as shown in FIGS. 21 and 22. In the cross section, the shape of the floating region 84 is stepped near the boundary 72, but in another example, the shape of the floating region 84 may be curved near the boundary 72.

  FIG. 23 is a flowchart showing an example of a method of manufacturing a semiconductor device according to the fourth embodiment. In this example, a method of manufacturing a semiconductor device having the FWD region 80 shown in FIG. 22 is shown. Steps S610 and S650-S680 of this example are identical to steps S510 and S550-S580 in FIG. 13A.

  FIG. 24 is a view for explaining the P-type dopant implantation step S620, the cathode region implantation step S632 and the floating region implantation step S640 in FIG. Although only the FWD region 80 is shown in FIG. 24, the semiconductor device may have an IGBT region 70 similar to the first to third embodiments.

  In step S620, the P + -type collector region 22 and the P + -type inter-cathode region 81 are formed. Collector region 22 may be formed on the entire lower surface of IGBT region 70. The inter-cathode region 81 may be formed on the entire lower surface of the FWD region 80. The collector region 22 and the inter-cathode region 81 may be formed in the same step. Next, in step S632, N-type dopant is selectively counterdoped from the lower surface 64 of the semiconductor substrate 10 to the inter-cathode region 81 of the FWD region 80. Thereby, a part of the inter-cathode region 81 of the FWD region 80 is inverted to the N + -type. In the inter-cathode region 81 of the FWD region 80, the region inverted to the N + -type becomes the cathode region 82, and the region remaining as the P + -type remains as the inter-cathode region 81. In step S632, the N-type dopant is selectively implanted such that the cathode regions 82 and the inter-cathode regions 81 are alternately arranged in a predetermined direction. In step S632, the mask 68-1 may be used to select the region into which the N-type dopant is to be implanted.

  Next, in step S640, a P-type dopant for forming the floating region 84 is implanted from the lower surface 64 of the semiconductor substrate 10. Before implanting the P-type dopant, the mask 68-1 may be removed and a new mask 68-2 may be provided on the lower surface 64 of the semiconductor substrate 10. The cathode region 82 includes both a P-type dopant for forming the inter-cathode region 81 and an N-type dopant for forming the cathode region 82. For this reason, in step S640, the P-type dopant passing through the cathode region 82 is easily implanted at a position where the distance from the lower surface 64 is short as compared with the P-type dopant passing through the inter-cathode region 81.

  Therefore, floating region 84 having the shape described in FIG. 22 can be formed by implanting a P-type dopant into cathode region 82 and inter-cathode region 81 under the same conditions. In another example, a mask or the like for shortening the range of the P-type dopant may be selectively provided on the lower surface of the cathode region 82, and then the P-type dopant may be implanted.

  In addition, since the cathode region 82 is formed before the formation of the floating region 84, the possibility of the generation and adhesion of the particles 86 described in FIG. 4B can be reduced. For this reason, it is possible to suppress the influence on junction leak, breakdown voltage failure, switching characteristics and the like.

  FIG. 25 is a flowchart showing another example of the method of manufacturing the semiconductor device according to the fourth embodiment. Steps S610 and S650-S680 of this example are identical to steps S510 and S550-S580 in FIG. 13A. Further, in the manufacturing method of this example, the order of the injection step for the floating region and the injection step for the cathode region is switched with respect to the manufacturing method shown in FIG. 23 and FIG.

  FIG. 26 is a diagram for explaining a P-type dopant implantation step S620, a floating region implantation step S642 and a cathode region implantation step S634 in FIG. Although only the FWD region 80 is shown in FIG. 26, the semiconductor device may have an IGBT region 70 similar to the first to third embodiments.

  In step S620, the P + -type inter-cathode region 81 is formed. Step S620 is identical to step S620 in FIGS. Next, in step S 642, a P-type dopant for forming the floating region 84 is implanted from the lower surface 64 of the semiconductor substrate 10. Before implanting the P-type dopant, the lower surface 64 of the semiconductor substrate 10 may be provided with a mask 68-2.

  Next, in step S634, N-type dopant is selectively counterdoped from the lower surface 64 of the semiconductor substrate 10 to the inter-cathode region 81 of the FWD region 80. Thereby, a part of the inter-cathode region 81 is inverted to the N + -type. In the inter-cathode region 81 of the FWD region 80, the region inverted to the N + -type becomes the cathode region 82, and the region remaining as the P + -type remains as the inter-cathode region 81. Step S634 is similar to step S632 in FIGS.

  In this example, a P-type dopant for forming the floating region 84 is implanted prior to the formation of the cathode region 82. Thus, floating region 84 is formed at a constant depth position. That is, the floating region 84 can be easily formed at a predetermined depth position. For example, when the floating region 84 is formed to the drift region 18 having a relatively low doping concentration, the P-type inversion region is likely to spread, and it may be difficult to control the depth position of the floating region 84 . According to this example, the entire floating region 84 can be easily formed in the FS region 20 having a relatively high doping concentration, so that the position of the floating region 84 can be easily controlled.

  FIG. 27A is a flowchart showing another example of the method of manufacturing the semiconductor device according to the fourth embodiment. Steps S610 and S620-S680 in this example are identical to steps S610 and S620-S680 in FIG. In addition, in the manufacturing method of this example, the order of the injecting step for the cathode region and the injecting step for the collector region and the inter-cathode region are reversed with respect to the manufacturing method shown in FIGS.

  In this example, a cathode region injection step S636 is performed after step S610. In step S636, an N-type dopant is selectively implanted into the region where the cathode region 82 is to be formed, using the mask 68-1 as shown in step S632 and the like of FIG. The mask 68-1 is provided to cover the entire lower surface of the IGBT region 70 and the region where the inter-cathode region 81 is to be formed in the FWD region 80.

  Next, in step S620, a P-type dopant is implanted from the lower surface 64 of the semiconductor substrate 10 to form the collector region 22 and the inter-cathode region 81. In step S620, the P-type dopant may be implanted into the entire lower surface 64 of the semiconductor substrate 10. That is, the P-type dopant may be implanted also into the cathode region 82 implanted with the N-type dopant in step S636. In this case, even if the P-type dopant is implanted in step S620, the N-type dopant is implanted in step S636 at a concentration that allows the cathode region 82 to maintain the N + -type.

  After step S620, the floating region 84 is formed. Also in this example, as in the examples of FIGS. 23 and 24, the floating region 84 having the shape described in FIG. 22 can be formed. In addition, since the cathode region 82 is formed before the formation of the floating region 84, the possibility of the generation and adhesion of the particles 86 described in FIG. 4B can be reduced. For this reason, it is possible to suppress the influence on junction leak, breakdown voltage failure, switching characteristics and the like.

  FIG. 27B is a flowchart showing another example of the method of manufacturing the semiconductor device according to the fourth embodiment. The manufacturing method of this example is different from the manufacturing method described in FIG. 27A in that the order of step S620 and step S640 is switched. The other steps are identical to the example of FIG. 27A.

  In this example, the floating region injection step S640 is performed after the step S636. In step S640, as shown in FIG. 24 and the like, the mask 68-2 may be used to implant a P-type dopant. After step S640, in step S620, a P-type dopant is implanted from the lower surface 64 of the semiconductor substrate 10 to form the collector region 22 and the inter-cathode region 81. Step S620 is similar to step S620 in FIG. 27A. Also in this example, since the floating region 84 is formed after the cathode region 82 is selectively formed, the floating region 84 having the shape described in FIG. 22 can be formed.

  FIG. 28A is a flowchart showing another example of the manufacturing method of the semiconductor device according to the fourth embodiment. Steps S610 and S620-S680 in this example are identical to steps S610 and S620-S680 in FIG. Further, in the manufacturing method of the present example, the order of the injection step for the floating region and the injection step for the cathode region, the collector region and the inter-cathode region is switched with respect to the manufacturing method shown in FIGS.

  In this example, after the step S610, the floating region injection step S644 is performed. In step S644, a P-type dopant is selectively implanted into the region where the floating region 84 is to be formed, using the mask 68-2 as shown in step S642 and the like of FIG.

  Next, in step S620, a P-type dopant is implanted from the lower surface 64 of the semiconductor substrate 10 to form the collector region 22 and the inter-cathode region 81. In step S620, the P-type dopant may be implanted into the entire lower surface 64 of the semiconductor substrate 10.

  Next, in step S632, N-type dopant is selectively counterdoped from the lower surface 64 of the semiconductor substrate 10 to the inter-cathode region 81 of the FWD region 80. Thereby, a part of the inter-cathode region 81 is inverted to the N + -type region to form the cathode region 82.

  Also in this example, as in the example of FIGS. 25 and 26, floating region 84 is formed at a constant depth position. That is, the floating region 84 can be easily formed at a predetermined depth position.

  FIG. 28B is a flowchart showing another example of the method of manufacturing the semiconductor device according to the fourth embodiment. The manufacturing method of this example is different from the manufacturing method described in FIG. 28A in that the order of step S620 and step S632 is interchanged. The other steps are identical to the example of FIG. 28A.

  In this example, steps S620 and S632 are performed after step S644. Steps S620 and S632 are similar to steps S620 and S636 of FIG. 27A.

  Also in this example, as in the example of FIGS. 25 and 26, floating region 84 is formed at a constant depth position. That is, the floating region 84 can be easily formed at a predetermined depth position.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It is apparent to those skilled in the art that various changes or modifications can be added to the above embodiment. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the present invention.

  The execution order of each process such as operations, procedures, steps, and steps in the apparatuses, systems, programs, and methods shown in the claims, the specification, and the drawings is particularly “before”, “preceding” It is to be noted that “it is not explicitly stated as“ etc. ”and can be realized in any order as long as the output of the previous process is not used in the later process. With regard to the flow of operations in the claims, the specification and the drawings, even if it is described using “first,” “next,” etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  10 semiconductor substrate 12 emitter region 14 base region 15 contact region 16 storage region 18 drift region 20 FS region 22 collector region 23 Upper end 24, Collector electrode 30, Dummy trench portion 32, Dummy trench 33, Dummy trench insulating film 34, Dummy trench conductive portion 38, Interlayer insulating film 40, Gate trench · · · · · · · · · · · · · · · · · · · · · · · · · · · · Gate trench, 43 · · · · gate insulating film The lower surface 68, the mask 69, the end portion 70, the IGBT region 72, the boundary 80, the FWD region 81, the inter-cathode region 82, the cathode region 82 3 · · Upper end, 84 · · Floating area, 86 · · · Particle, 88 · · · · · · · · · · · · · 30 30 · · · · · · · · · 30 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · semiconductor device 101: first area 102: second area 103: third area 104: fourth area 110: active area 112: pad area 114: gate pad · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Heat treatment furnace, 200, 220, 240, 300 · · · semiconductor devices

In a third aspect of the present invention, another method of manufacturing a semiconductor device is provided. The semiconductor device may have a transistor region and a diode region on one semiconductor substrate. Another method of manufacturing a semiconductor device may include an implant stage for the collector region, an implant stage for the floating region, and an implant stage for the cathode region. In the collector region implantation step, a dopant of the first conductivity type may be implanted into the lower surface of the semiconductor substrate to form a collector region in the transistor region. In the floating region implantation step, a dopant of the first conductivity type may be implanted into the lower surface of the semiconductor substrate to form a floating region of the first conductivity type provided in the diode region. Implantation step for the cathode region may be after the full injection stage for route area. In the cathode region implantation step, a dopant of the second conductivity type may be implanted into the lower surface of the semiconductor substrate to form a cathode region in the diode region.

The implantation step for the floating region may be performed after the implantation step for the collector region. Alternatively, after the floating region for implantation step, it has rows collector region for implantation step, and good I rows implantation step for the cathode region after the implantation step for the collector region. Alternatively, the collector region implant step may be performed after the cathode region implant step.

After the collector region implant step, the cathode region implant step and the floating region implant step, the upper end of the cathode region may be closer to the top surface of the semiconductor substrate than the upper end of the collector region. The implantation step for the cathode region is a part of the lower surface of the semiconductor substrate to form a cathode region and an inter-cathode region of the first conductivity type alternately arranged in the predetermined direction with the cathode region in the diode region. A dopant of the second conductivity type may be implanted into the region of.

In addition, the peak of the P-type dopant concentration distribution of floating region 84 may be present at a position closer to FS region 20 than half the depth position of cathode region 82. In the third modification, floating region 84 is provided closer to FS region 20 than to lower surface 64. Thus, the risk of the floating region 84 being exposed to the lower surface 64 of the semiconductor device 160 can be reduced while the floating region 84 is provided in the cathode region 82. The third variation of FIG. 8 may be combined with the first variation of FIGS. 5A and 5B and the second variation of FIGS. 6A and 6B.

FIG. 9 is a diagram showing a stage of a method of manufacturing the semiconductor device 180 in the fourth modified example of the first embodiment. Step S240 of (a) of FIG. 9 corresponds to step S40 of (d) of FIG. 4B, and step S280 of (b) of FIG. 9 corresponds to step S80 of (h) of FIG. 4B. The description of the same steps as in the first embodiment will be omitted. The fourth modification is different from the first embodiment in that the lower end of the floating region 84 is formed above the cathode region 82. In (b) of FIG. 9, it indicates the distance between the upper end of the lower end and the cathode region 82 of the floating region 84 as L _2. In the fourth modification, in the FS region 20 between the lower end of the floating region 84 and the upper end of the cathode region 82, a tail region of the P-type dopant concentration distribution used to form the floating region 84 may be present. Further, as in the third modification of the first embodiment, a tail region of the P-type dopant concentration distribution used to form floating region 84 exists between the upper end of floating region 84 and the upper end of FS region 20. You may The fourth modification of FIG. 9 may be combined with the first modification of FIGS. 5A and 5B and the second modification of FIGS. 6A and 6B.

In the first modification, since the cathode region 82 is thicker than the collector region 22, the upper end 83 of the cathode region 82 is closer to the upper surface 62 than the upper end 23 of the collector region 22. Further, the lower end 94 of the floating region 84 is closer to the upper surface 62 than the upper end 23 of the collector region 22. Thereby, short circuit between floating region 84 and collector region 22 can be reliably prevented. Therefore, the characteristics of the semiconductor device 300 can be made close to the designed characteristics. Further, not only in the third embodiment in which the position of the boundary 72 coincides with the end 91 of the floating region 84, but also in the first and second embodiments, the cathode region 82 is thicker than the collector region 22. In this way, it is easier to manufacture the intended structure, and the reliability can be further improved. The cathode region 82 being thicker than the collector region 22 is not limited to the case where the cathode region 82 is thicker than the collector region 22 due to a slight difference, and the cathode region 82 is clearer than the collector region 22. A thick case may be intended. Specifically, the cathode region 82 may be about 1.2 times thicker than the collector region 22, and preferably the cathode region 82 may be about 1.4 times thicker than the collector region 22, more preferably The cathode region 82 may be about 1.6 times thicker than the collector region 22.

Thus, by arranging the floating region 84 and the cathode region 82 and the inter-cathode region 81 in an overlapping manner, the first region 101 and the second region 102 for adjusting the injection of carriers (electrons and holes), A third region 103 and a fourth region 104 can be provided. By adjusting the area ratio of these regions, the total injection amount of carriers (electrons and holes) in the FWD region 80 can be accurately adjusted. Further, in the Y-axis direction, provided the floating region 84 for each cathode de area 82, and the width of the floating region 84 is made larger than the width of the cathode de area 82, the cathode region 82 and cathode region 81 The first area 101 can be arranged at each boundary of

As an example, the area of floating region 84 in top view may be larger than the area of cathode region 82. The area of the floating region 84 is larger than the area of the first region 101. In addition, the area of the floating region 84 is larger than the area of the third region 103. The area of floating region 84 may be 90% or less of the sum of the areas of cathode region 82 and inter-cathode region 81. In addition, the area of the inter-cathode region 81 in top view may be larger than the area of the cathode region 82. The area of each region indicates the total area of each region in FWD region 80.

Claims (24)

A semiconductor device in which a diode region is provided on a semiconductor substrate,
The diode region is
A base region of a first conductivity type provided exposed on the upper surface of the semiconductor substrate;
A cathode region of a second conductivity type exposed on the lower surface of the semiconductor substrate;
An inter-cathode region of a first conductivity type provided on the lower surface of the semiconductor substrate and disposed alternately with the cathode region in a predetermined direction;
A semiconductor device comprising: a floating region of a second conductivity type provided above the cathode region and above the inter-cathode region. The semiconductor device according to claim 1, further comprising: a transistor region provided on the semiconductor substrate and arranged side by side with the diode region in a top view of the semiconductor substrate. The semiconductor device according to claim 1, wherein the inter-cathode region and the floating region are disposed apart in the depth direction of the semiconductor substrate. The diode region further includes a dummy trench portion extended in the extending direction on the upper surface of the semiconductor substrate,
The semiconductor device according to any one of claims 1 to 3, wherein the cathode region and the inter-cathode region are alternately arranged in the extending direction. The semiconductor device according to any one of claims 1 to 4, wherein in the diode region, the cathode region is provided deeper than the inter-cathode region with reference to the lower surface of the semiconductor substrate. The distance between the upper end of the cathode region and the lower end of the floating region in the depth direction of the semiconductor substrate is smaller than the distance between the upper end of the inter-cathode region and the lower end of the floating region. The semiconductor device according to claim 1. The semiconductor device according to any one of claims 1 to 6, wherein in a top view of the semiconductor substrate, an area of the floating region provided in the diode region is larger than an area of the cathode region. The semiconductor device according to any one of claims 1 to 7, wherein an area of the inter-cathode region provided in the diode region is larger than an area of the cathode region in a top view of the semiconductor substrate. A method of manufacturing a semiconductor device having a transistor region and a diode region on one semiconductor substrate,
Injecting a dopant for the first conductivity type into the lower surface of the semiconductor substrate to form a collector region in the transistor region;
Injecting the second conductivity type dopant into the lower surface of the semiconductor substrate to form a cathode region in the diode region;
After the implanting step for the cathode region, the implanting step for implanting the floating region of the first conductivity type to the lower surface of the semiconductor substrate to form the floating region of the first conductivity type provided in the diode region, A manufacturing method of a semiconductor device provided. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the implantation step for the cathode region is performed after the implantation step for the collector region. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the implantation step for the collector region is performed after the implantation step for the cathode region, and the implantation step for the floating region is performed after the implantation step for the collector region. 10. The method according to claim 9, wherein the step of implanting the collector region is performed after the step of implanting the floating region. A method of manufacturing a semiconductor device having a transistor region and a diode region on one semiconductor substrate,
Injecting a dopant for the first conductivity type into the lower surface of the semiconductor substrate to form a collector region in the transistor region;
Implanting a floating region for implanting a dopant of the first conductivity type into the lower surface of the semiconductor substrate to form a floating region of the first conductivity type provided in the diode region;
A cathode region implantation step of implanting a dopant of a second conductivity type on the lower surface of the semiconductor substrate to form a cathode region in the diode region after the floating region implantation step; 14. The method of claim 13, wherein the step of implanting the floating region is performed after the step of implanting the collector region. The method for manufacturing a semiconductor device according to claim 13, wherein the implantation step for the collector region is performed after the implantation step for the floating region, and the implantation step for the cathode region is performed after the implantation step for the collector region. The method for manufacturing a semiconductor device according to claim 13, wherein the implantation step for the collector region is performed after the implantation step for the cathode region. After the implantation step for the collector region, the implantation step for the cathode region and the implantation step for the floating region,
The end of the floating region closest to the boundary between the collector region and the cathode region reaches the boundary in a direction parallel to the arrangement direction of the cathode region and the collector region from the cathode region to the collector region. Well,
The method for manufacturing a semiconductor device according to any one of claims 9 to 16, wherein the floating region is located in the diode region. After the implantation step for the collector region, the implantation step for the cathode region and the implantation step for the floating region,
The end of the floating region closest to the boundary between the collector region and the cathode region is located at the boundary in the direction parallel to the arrangement direction of the cathode region and the collector region from the cathode region to the collector region. A method of manufacturing a semiconductor device according to any one of claims 9 to 16. The method of manufacturing a semiconductor device according to any one of claims 9 to 18, wherein a lower end of the floating region is closer to the upper surface of the semiconductor substrate than an upper end of the collector region. After the implantation step for the collector region, the implantation step for the cathode region and the implantation step for the floating region,
The method of manufacturing a semiconductor device according to claim 19, wherein at least a part of the floating region is located in the cathode region. The cathode region has at least two peaks of electron concentration at different positions in a depth direction from the lower surface to the upper surface,
21. The method of manufacturing a semiconductor device according to claim 20, wherein the peak position of the hole concentration in the floating region is located between two peaks of at least two electron concentration peaks in the cathode region in the depth direction. . 20. The method of manufacturing a semiconductor device according to claim 9, wherein a lower end of the floating region is separated from an upper end of the cathode region. After the implantation step for the collector region, the implantation step for the cathode region and the implantation step for the floating region,
The upper end of the cathode region is closer to the upper surface of the semiconductor substrate than the upper end of the collector region.
A method of manufacturing a semiconductor device according to any one of claims 9 to 22. In the cathode region injection step, the semiconductor substrate is formed in the diode region to form the cathode region and an inter-cathode region of a first conductivity type alternately arranged with the cathode region in a predetermined direction. The method for manufacturing a semiconductor device according to any one of claims 9 to 23, wherein a dopant of the second conductivity type is implanted into a partial region of the lower surface of the semiconductor device.

Images