JP2019037079A - Overcurrent protection circuit - Google Patents

Abstract

To make overcurrent protection according to a load compatible with securing of instantaneous current.SOLUTION: An overcurrent protection circuit has a threshold value generating section for changing over the overcurrent detection threshold Iocp between a first setting value IocpH and a second setting value IocpL(<IocpH) according to a threshold control signal, and threshold value control section generating the threshold control signal so as to change over the overcurrent detection threshold Iocp to the second setting value IocpL at a moment in time when a mask period Tmask elapses with the monitoring object current Io remaining above the second setting value IocpL when the overcurrent detection threshold Iocp is the first setting value IocpH. The threshold value generating section includes a function for gradually lowering the overcurrent detection threshold Iocp over a prescribed transition time Ttrans, when changing over the overcurrent detection threshold Iocp from the first setting value IocpH to the second setting value IocpL.SELECTED DRAWING: Figure 29

Description

  The present invention relates to an overcurrent protection circuit.

  Conventionally, many semiconductor integrated circuit devices include an overcurrent protection circuit as one of the abnormality protection circuits. For example, in an in-vehicle IPD [intelligent power device], an output current flowing through a power transistor is limited to an overcurrent detection threshold value or less so that the device is not destroyed even when a load connected to the power transistor is short-circuited. A current protection circuit is provided. In recent years, an overcurrent protection circuit that can arbitrarily adjust an overcurrent detection threshold using an external resistor has been proposed.

  In addition, Patent Document 1 and Patent Document 2 can be cited as examples of related art related to the above.

JP 2015-46954 A JP 2012- 211805 A

  However, some loads (such as capacitive loads) that require a large output current to flow instantaneously as their normal operation are present in the loads connected to the power transistors. When such an output current is to be monitored, it is difficult for a conventional overcurrent protection circuit having a single overcurrent detection threshold to achieve both instantaneous current securing and overcurrent protection according to the load. It was.

  In particular, in recent years, in-vehicle ICs are required to comply with ISO 26262 (international standard for functional safety related to automobile electrical / electronics), and higher reliability design is important for in-vehicle IPDs. It has become.

  In view of the above-mentioned problems found by the inventors of the present application, the invention disclosed in the present specification is an overcurrent protection capable of both ensuring an instantaneous current and overcurrent protection according to a load. An object is to provide a circuit.

  Therefore, whether the overcurrent protection circuit disclosed in this specification sets the overcurrent detection threshold value to the first set value or the second set value lower than the first set value according to the threshold control signal. A threshold generation unit for switching the overcurrent detection threshold, and when the overcurrent detection threshold is the first set value, the overcurrent detection threshold is set when the mask period elapses while the monitoring target current exceeds the second set value. A threshold control unit that generates the threshold control signal so as to switch to the second setting value, and the threshold generation unit switches the overcurrent detection threshold from the first setting value to the second setting value. The overcurrent detection threshold value is gradually lowered over a predetermined transition time (first configuration).

  In the overcurrent protection circuit having the first configuration, the threshold generation unit includes a variable current source that gradually decreases the variable current from the first current value to the second current value according to the threshold control signal. In addition, a configuration (second configuration) may be employed in which the overcurrent detection threshold is set using the variable current.

  In the overcurrent protection circuit having the second configuration, the variable current source includes an upper current generation unit that generates an upper current fixed to the first current value, and a lower side according to the threshold control signal. A lower current generator that gradually increases a current from a zero value to a difference value between the first current value and the second current value, and a differential current obtained by subtracting the lower current from the upper current A configuration for outputting the variable current (third configuration) is preferable.

  Further, in the overcurrent protection circuit having the third configuration, the lower-side current generating unit subtracts the second current of the second current value from the first current of the capacitor and the first current value. A charging current generating unit that generates a charging current of the capacitor, a charging control unit that starts charging the capacitor in response to the threshold control signal, and a voltage / current converting unit that converts the charging voltage of the capacitor into the lower current; , (4th configuration).

  Whether the overcurrent protection circuit disclosed in this specification sets the overcurrent detection threshold value to the first set value or the second set value lower than the first set value according to the threshold control signal. A threshold generation unit that switches between, an overcurrent detection unit that compares the current to be monitored and the overcurrent detection threshold to generate an overcurrent protection signal, and the overcurrent detection threshold is the first set value. A threshold control unit that generates the threshold control signal so that the overcurrent detection threshold is switched to the second set value when the mask period elapses while the current to be monitored exceeds the second set value. The overcurrent detection unit has a configuration (fifth configuration) including a first overcurrent detection unit and a second overcurrent detection unit that are selectively used according to the overcurrent detection threshold.

  In the overcurrent protection circuit having the fifth configuration, the threshold value generating unit takes a predetermined transition time when switching the overcurrent detection threshold value from the first set value to the second set value. A configuration in which the overcurrent detection threshold value is gradually lowered (sixth configuration) is preferable.

  The overcurrent protection circuit having the sixth configuration compares the overcurrent detection threshold with an intermediate set value that is lower than the first set value and higher than the second set value. It is preferable to have a configuration (seventh configuration) further including a switching control unit that generates the switching control signal.

  Further, in the overcurrent protection circuit having the seventh configuration, the threshold value generating unit gradually decreases the first variable current from the first current value to the intermediate current value according to the threshold control signal. And a second variable current source that gradually decreases the second variable current from the intermediate current value to the second current value in response to the switching control signal, the first variable current and the second variable current source. A configuration (eighth configuration) may be employed in which the overcurrent detection threshold is set using both variable currents.

  In the overcurrent protection circuit having the eighth configuration, the first variable current source includes a first element current generator that generates a first element current fixed to the intermediate current value, and the threshold control signal. A second element current generator that gradually reduces the second element current from the intermediate current value to the zero value according to the sum, and the summed current obtained by adding the first element current and the second element current Is preferably output as the first variable current (a ninth configuration).

  In the overcurrent protection circuit having the ninth configuration, the second element current generation unit includes a capacitor, a charging current generation unit that generates a charging current having the intermediate current value, and a discharging current having the intermediate current value. A discharge current generation unit that generates a voltage, a charge / discharge control unit that switches a charge state and a discharge state of the capacitor according to the threshold control signal, and a voltage / current conversion that converts a charge voltage of the capacitor into the second element current And a configuration (tenth configuration).

  In the overcurrent protection circuit having the ninth or tenth configuration, the second variable current source includes a third element current generation unit that generates a third element current fixed to the intermediate current value, A fourth element current generator that gradually increases a fourth element current from a zero value to a difference value between the intermediate current value and the second current value in response to a switching control signal, and the third element current It is preferable that the differential current obtained by subtracting the fourth element current from is output as the second variable current (eleventh configuration).

  Further, in the overcurrent protection circuit having the eleventh configuration, the fourth element current generation unit subtracts the lower current of the second current value from the upper current of the capacitor and the intermediate current value. A charging current generating unit that generates a charging current; a charging control unit that starts charging the capacitor in response to the switching control signal; and a voltage / current converting unit that converts a charging voltage of the capacitor into the fourth element current. It is good to set it as the structure (12th structure) containing these.

  In the overcurrent protection circuit having any one of the first to twelfth configurations, the first set value is a fixed value and the second set value is a variable value (a thirteenth configuration). Good.

  Further, a semiconductor integrated circuit device disclosed in the present specification includes a power transistor that conducts / cuts off a current path through which an output current flows, and the first to the above first to generate an overcurrent protection signal by monitoring the output current. An overcurrent protection circuit having any one of the thirteenth configurations and a gate control unit that controls the power transistor in accordance with the overcurrent protection signal are integrated (fourteenth configuration).

  An electronic device disclosed in the present specification has a semiconductor integrated circuit device having the fourteenth configuration and a load connected to the semiconductor integrated circuit device (fifteenth configuration). ing.

  In the electronic apparatus having the fifteenth configuration, the load may be a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor (a sixteenth configuration).

  Further, the vehicle disclosed in the present specification has a configuration (a seventeenth configuration) including the electronic device having the fifteenth or sixteenth configuration.

  According to the invention disclosed in the present specification, it is possible to provide an overcurrent protection circuit capable of ensuring both an instantaneous current and an overcurrent protection according to a load.

1 is a block diagram showing a first embodiment of a semiconductor integrated circuit device Block diagram showing one configuration example of signal output unit Block diagram showing one configuration example of the gate control unit Block diagram showing one configuration example of overcurrent protection circuit Circuit diagram showing one configuration example of the first current generator Circuit diagram showing one configuration example of the second current generator The circuit diagram which shows one structural example of a threshold voltage generation part and an overcurrent detection part Schematic diagram showing an example of overcurrent detection threshold Circuit diagram showing a configuration example of the reference voltage generation unit and the comparison unit Circuit diagram showing one configuration example of threshold control unit Timing chart showing an example of overcurrent protection operation Flow chart showing an example of threshold switching operation Schematic diagram showing a first usage example of an overcurrent protection circuit Schematic diagram showing a second usage example of the overcurrent protection circuit Block diagram showing a second embodiment of a semiconductor integrated circuit device Block diagram showing an example of the configuration of a two-channel overcurrent protection circuit Block diagram showing a first embodiment of the threshold control unit Timing chart showing threshold value switching operation of the first embodiment Timing chart showing problems of the first embodiment Block diagram showing a second embodiment of the threshold control unit Block diagram showing a configuration example of a discharge control unit Timing chart showing threshold value switching operation of the second embodiment Timing chart showing problems of the second embodiment Block diagram showing a third embodiment of the threshold control unit Timing chart showing threshold value switching operation of the third embodiment Flow chart showing an example of threshold switching operation Block diagram showing an example of introducing a multiplexer The figure which shows a mode that the undershoot of an overcurrent detection threshold occurs The figure which shows a mode that the undershoot of an overcurrent detection threshold is suppressed The figure which shows one structural example of the threshold voltage generation part provided with the soft switching function The figure which shows one structural example of a variable current source Diagram showing behavior of upper current, lower current, and differential current Diagram for explaining the operating point of the comparator The figure which shows the modification of a threshold voltage generation part and an overcurrent detection part The figure which shows the example of 1 structure of a current generation circuit Diagram showing overcurrent detection threshold switching operation Flow chart showing an example of threshold switching operation External view showing a configuration example of a vehicle

<Semiconductor integrated circuit device (first embodiment)>
FIG. 1 is a block diagram showing a first embodiment of a semiconductor integrated circuit device. The semiconductor integrated circuit device 1 according to this embodiment includes a vehicle-mounted high-side switch IC (= vehicle-mounted) that conducts / cuts off between the application terminal of the power supply voltage VBB and the load 3 in accordance with an instruction from an ECU [electronic control unit] 2. A kind of IPD).

  The semiconductor integrated circuit device 1 includes external terminals T1 to T4 as means for establishing electrical connection with the outside of the device. The external terminal T1 is a power supply terminal (VBB pin) for receiving supply of a power supply voltage VBB (for example, 12V) from a battery (not shown). The external terminal T2 is a load connection terminal (OUT pin) for externally connecting the load 3 (bulb lamp, relay coil, solenoid, light emitting diode, motor, or the like). The external terminal T3 is a signal input terminal (IN pin) for receiving an external input of the external control signal Si from the ECU 2. The external terminal T4 is a signal output terminal (SENSE pin) for externally outputting the state notification signal So to the ECU 2. An external sense resistor 4 is externally connected between the external terminal T4 and the ground terminal.

  In addition, the semiconductor integrated circuit device 1 includes an NMOSFET 10, an output current monitoring unit 20, a gate control unit 30, a control logic unit 40, a signal input unit 50, an internal power supply unit 60, an abnormality protection unit 70, and an output. The current detector 80 and the signal output unit 90 are integrated.

  The NMOSFET 10 is a high breakdown voltage (for example, 42V breakdown voltage) power transistor having a drain connected to the external terminal T1 and a source connected to the external terminal T2. The NMOSFET 10 connected in this way functions as a switch element (high side switch) for conducting / cutting off a current path from the application end of the power supply voltage VBB to the ground end via the load 3. The NMOSFET 10 is turned on when the gate drive signal G1 is at a high level, and turned off when the gate drive signal G1 is at a low level.

  The NMOSFET 10 may be designed so that the on-resistance value is several tens of mΩ. However, the lower the on-resistance value of the NMOSFET 10, the more easily an overcurrent flows when the external terminal T 2 is grounded (= a short-circuit to the ground terminal or a low-potential terminal corresponding thereto), and abnormal heat generation is likely to occur. Therefore, as the on-resistance value of the NMOSFET 10 is lowered, the importance of an overcurrent protection circuit 71 and a temperature protection circuit 73 described later becomes higher.

  The output current monitoring unit 20 includes NMOSFETs 21 and 21 ′ and a sense resistor 22, and generates a sense voltage Vs (= corresponding to a sense signal) corresponding to the output current Io flowing through the NMOSFET 10.

  The NMOSFETs 21 and 21 ′ are mirror transistors connected in parallel to the NMOSFET 10, and generate sense currents Is and Is ′ corresponding to the output current Io. The size ratio between the NMOSFET 10 and the NMOSFETs 21 and 21 'is m: 1 (where m> 1). Therefore, the sense currents Is and Is ′ have a magnitude obtained by reducing the output current Io to 1 / m. The NMOSFETs 21 and 21 'are turned on when the gate drive signal G1 is at a high level and turned off when the gate voltage G2 is at a low level, as in the NMOSFET 10.

  The sense resistor 22 (resistance value: Rs) is connected between the source of the NMOSFET 21 and the external terminal T2, and the sense voltage Vs (= Is × Rs + Vo) corresponding to the sense current Is, where Vo is connected to the external terminal T2. This is a current / voltage conversion element that generates an output voltage that appears.

  The gate control unit 30 performs on / off control of the NMOSFETs 10 and 21 by generating a gate drive signal G1 with an increased current capability of the gate control signal S1 and outputting it to the gates of the NMOSFETs 10 and 21, respectively. Note that the gate control unit 30 has a function of forcibly turning off the NMOSFETs 10 and 21 without depending on the gate control signal S1 when the overcurrent protection signal S71 is at the logic level at the time of abnormality detection.

  The control logic unit 40 receives the supply of the internal power supply voltage Vreg and generates the gate control signal S1. For example, when the external control signal Si is at a high level (= the logic level when the NMOSFET 10 is turned on), the internal power supply voltage Vreg is supplied from the internal power supply section 60, so that the control logic section 40 is in an operating state and gate control is performed. The signal S1 becomes high level (= Vreg). On the other hand, when the external control signal Si is at a low level (= a logic level when the NMOSFET 10 is turned off), the internal power supply voltage Vreg is not supplied from the internal power supply section 60, so that the control logic section 40 is in an inoperative state and gate control is performed. The signal S1 becomes low level (= GND). In addition, the control logic unit 40 monitors various abnormality protection signals (overcurrent protection signal S71, open protection signal S72, temperature protection signal S73, and reduced voltage protection signal S74). The control logic unit 40 also has a function of generating the output switching signal S2 according to the monitoring results of the overcurrent protection signal S71, the open protection signal S72, and the temperature protection signal S73 among the abnormality protection signals described above. Yes.

  The signal input unit 50 is a Schmitt trigger that receives an input of the external control signal Si from the external terminal T3 and transmits the input to the control logic unit 40 and the internal power supply unit 60. Note that the external control signal Si is, for example, at a high level when the NMOSFET 10 is turned on and at a low level when the NMOSFET 10 is turned off.

  The internal power supply unit 60 generates a predetermined internal power supply voltage Vreg from the power supply voltage VBB and supplies it to each unit of the semiconductor integrated circuit device 1. Note that whether or not the internal power supply unit 60 is operable is controlled according to the external control signal Si. More specifically, the internal power supply unit 60 is in an operating state when the external control signal Si is at a high level, and is in a non-operating state when the external control signal Si is at a low level.

  The abnormality protection unit 70 is a circuit block that detects various abnormalities of the semiconductor integrated circuit device 1, and includes an overcurrent protection circuit 71, an open protection circuit 72, a temperature protection circuit 73, and a voltage drop protection circuit 74. .

  The overcurrent protection circuit 71 generates an overcurrent protection signal S71 corresponding to the monitoring result of the sense voltage Vs (= whether or not an overcurrent abnormality of the output current Io has occurred). The overcurrent protection signal S71 is, for example, a low level when no abnormality is detected, and a high level when an abnormality is detected.

  The open protection circuit 72 generates an open protection signal S72 according to the monitoring result of the output voltage Vo (= whether or not an open abnormality of the load 3 has occurred). The open protection signal S72 is, for example, a low level when no abnormality is detected, and a high level when an abnormality is detected.

  The temperature protection circuit 73 includes a temperature detection element (not shown) that detects abnormal heat generation of the semiconductor integrated circuit device 1 (particularly around the NMOSFET 10), and a temperature corresponding to the detection result (= whether abnormal heat generation has occurred). A protection signal S73 is generated. The temperature protection signal S73 is, for example, a low level when no abnormality is detected, and a high level when an abnormality is detected.

  The voltage drop protection circuit 74 generates a voltage drop protection signal S74 according to the monitoring result of the power supply voltage VBB or the internal power supply voltage Vreg (= whether or not a voltage drop abnormality has occurred). The reduced voltage protection signal S74 is, for example, a low level when no abnormality is detected, and a high level when an abnormality is detected.

  The output current detector 80 generates a sense current Is ′ (= Io / m) corresponding to the output current Io by matching the source voltage of the NMOSFET 21 ′ with the output voltage Vo using a bias unit (not shown). To the signal output unit 90.

  Based on the output selection signal S2, the signal output unit 90 outputs one of the sense current Is ′ (= corresponding to the detection result of the output current Io) and the fixed voltage V90 (= corresponding to an abnormality flag, not shown in the drawing). Select output to terminal T4. When the sense current Is ′ is selectively output, the output detection voltage V80 (= Is ′) obtained by converting the sense current Is ′ to current / voltage by the external sense resistor 4 (resistance value: R4) as the state notification signal So. XR4) is transmitted to the ECU 2. The output detection voltage V80 increases as the output current Io increases, and decreases as the output current Io decreases. On the other hand, when the fixed voltage V90 is selected and output, the fixed voltage V90 is transmitted to the ECU 2 as the state notification signal So.

<Signal output section>
FIG. 2 is a block diagram illustrating a configuration example of the signal output unit 90. The signal output unit 90 of this configuration example includes a selector 91. The selector 91 selectively outputs the sense current Is ′ to the external terminal T4 when the output selection signal S2 is at the logic level when no abnormality is detected (for example, low level), and the output selection signal S2 is at the logic level when the abnormality is detected. When it is (for example, high level), the fixed voltage V90 is selectively output to the external terminal T4. The fixed voltage V90 is set to a voltage value higher than the upper limit value of the output detection voltage V80 described above.

  According to such a signal output unit 90, both the detection result of the output current Io and the abnormality flag can be transmitted to the ECU 2 using a single state notification signal So, which contributes to the reduction of the number of external terminals. It becomes possible. Note that when the current value of the output current Io is read from the state notification signal So, the state notification signal So may be A / D [analog-to-digital] converted. On the other hand, when the abnormality flag is read from the state notification signal So, the logic level of the state notification signal So may be determined using a threshold value slightly lower than the fixed voltage V90.

<Gate control unit>
FIG. 3 is a block diagram illustrating a configuration example of the gate control unit 30. The gate control unit 30 in this configuration example includes a gate driver 31, an oscillator 32, a charge pump 33, a clamper 34, and an NMOSFET 35.

  The gate driver 31 is connected between the output terminal of the charge pump 33 (= applied terminal of the boosted voltage VG) and the external terminal T2 (= applied terminal of the output voltage Vo), and has the current capability of the gate control signal S1. An increased gate drive signal G1 is generated. The gate drive signal G1 is at a high level (= VG) when the gate control signal S1 is at a high level, and is at a low level (= Vo) when the gate control signal S1 is at a low level.

  The oscillator 32 generates a clock signal CLK having a predetermined frequency and outputs it to the charge pump 33. Whether or not the oscillator 32 can operate is controlled according to an enable signal Sa from the control logic unit 40.

  The charge pump 33 generates a boosted voltage VG higher than the power supply voltage VBB by driving the flying capacitor using the clock signal CLK. Whether or not the charge pump 33 can operate is controlled according to the enable signal Sb from the control logic unit 40.

  The clamper 34 is connected between the external terminal T1 (= applied end of the power supply voltage VBB) and the gate of the NMOSFET 10. In an application in which the inductive load 3 is connected to the external terminal T2, when the NMOSFET 10 is switched from on to off, the output voltage Vo becomes a negative voltage (<GND) due to the back electromotive force of the load 3. Therefore, a clamper 34 (so-called active clamp circuit) is provided for energy absorption.

  The drain of the NMOSFET 35 is connected to the gate of the NMOSFET 10. The source of the NMOSFET 35 is connected to the external terminal T2. The gate of the NMOSFET 35 is connected to the application terminal of the overcurrent protection signal S71.

  In the gate control unit 30 of this configuration example, when the overcurrent protection signal S71 is at a low level (= logic level when no abnormality is detected), the NMOSFET 35 is turned off, so that the gate drive signal G1 is supplied to the NMOSFET 10 as usual. Applied. On the other hand, when the overcurrent protection signal S71 is at the high level (= the logic level at the time of abnormality detection), the NMOSFET 35 is turned on, so that the gate and the source of the NMOSFET 10 are short-circuited.

  As described above, the gate control unit 30 of this configuration example outputs the gate drive signal G1 so as to forcibly turn off the NMOSFET 10 when the overcurrent protection signal S71 is at the high level (= the logic level at the time of abnormality detection). It has a function to control.

<Overcurrent protection circuit>
FIG. 4 is a block diagram illustrating a configuration example of the overcurrent protection circuit 71. The overcurrent protection circuit 71 of this configuration example includes a first current generation unit 110, a second current generation unit 120, a threshold voltage generation unit 130, an overcurrent detection unit 140, a reference voltage generation unit 150, and a comparison unit. 160 and a threshold control unit 170.

  The first current generator 110 generates the first current Iref and outputs it to the threshold voltage generator 130. The current value of the first current Iref is fixed inside the semiconductor integrated circuit device 1.

  The second current generator 120 generates a second current Iset and outputs the second current Iset to the threshold voltage generator 130. The current value of the second current Iset can be arbitrarily adjusted from the outside of the semiconductor integrated circuit device 1.

  The threshold voltage generation unit 130 switches the threshold voltage Vth (= corresponding to the overcurrent detection threshold) between the internal setting value VthH and the external setting value VthL (where VthH> VthL) in accordance with the threshold control signal S170. The internal set value VthH is a fixed value (corresponding to the first set value) set in accordance with the first current Iref. On the other hand, the external set value VthL is a variable value (corresponding to the second set value) set according to the second current Iset.

  The overcurrent detection unit 140 compares the sense voltage Vs with the threshold voltage Vth and generates an overcurrent protection signal S71.

  The reference voltage generation unit 150 generates a reference voltage VIset (= corresponding to a reference value) corresponding to the second current Iset.

  The comparison unit 160 compares the sense voltage Vs with the reference voltage VIset and generates a comparison signal VCMP.

  The threshold control unit 170 monitors the comparison signal VCMP and generates a threshold control signal S170. The threshold control signal S170 is, for example, a low level when the internal set value VthH is to be selected as the threshold voltage Vth, and a high level when the external set value VthL is to be selected as the threshold voltage Vth.

<First current generator>
FIG. 5 is a circuit diagram illustrating a configuration example of the first current generation unit 110. The first current generation unit 110 of this configuration example includes an operational amplifier 111, an NMOSFET 112, and a resistor 113 (resistance value: R113).

  The power supply terminal of the operational amplifier 111 is connected to the application terminal of the internal power supply voltage Vreg. The reference potential terminal of the operational amplifier 111 is connected to the ground terminal GND. The non-inverting input terminal (+) of the operational amplifier 111 is connected to an application terminal for a reference voltage Vref (for example, a bandgap reference voltage that is not easily affected by power supply fluctuations, temperature fluctuations, etc.). The inverting input terminal (−) of the operational amplifier 111 and the source of the NMOSFET 112 are connected to the first terminal of the resistor 113. A second end of the resistor 113 is connected to the ground end GND. The output terminal of the operational amplifier 111 is connected to the gate of the NMOSFET 112. The drain of the NMOSFET 112 is connected to the output terminal of the first current Iref.

  The operational amplifier 111 connected as described above controls the gate of the transistor 112 so that the non-inverting input terminal (+) and the inverting input terminal (−) are imaginarily short-circuited. As a result, a first current Iref (= Vref × R113) having a fixed value flows through the resistor 113.

<Second current generator>
FIG. 6 is a circuit diagram illustrating a configuration example of the second current generator 120. The second current generation unit 120 of this configuration example includes an operational amplifier 121, an NMOSFET 122, a resistor 123 (resistance value: R123), and an external terminal SET.

  The power supply terminal of the operational amplifier 121 is connected to the application terminal of the internal power supply voltage Vreg. The reference potential terminal of the operational amplifier 121 is connected to the ground terminal GND. The non-inverting input terminal (+) of the operational amplifier 121 is connected to the application terminal for the reference voltage Vref. The inverting input terminal (−) of the operational amplifier 121 and the source of the NMOSFET 122 are connected to the external terminal SET. The output terminal of the operational amplifier 121 is connected to the gate of the NMOSFET 122. The drain of the NMOSFET 122 is connected to the output terminal of the second current Iset. The resistor 123 is connected between the external terminal SET and the ground terminal GND outside the semiconductor integrated circuit device 1.

  The operational amplifier 121 connected as described above controls the gate of the transistor 122 so that the non-inverting input terminal (+) and the inverting input terminal (−) are imaginarily short-circuited. As a result, a second current Iset (= Vref × R123) corresponding to its own resistance value R123 flows through the resistor 123. That is, the second current Iset increases as the resistance value R123 increases, and conversely decreases as the resistance value R123 decreases. Therefore, the second current Iset can be arbitrarily adjusted using the external resistor 123. If the differential stage in the operational amplifier 121 is a cascode circuit, the setting accuracy of the second current Iset can be increased.

<Threshold voltage generator / overcurrent detector>
FIG. 7 is a circuit diagram illustrating a configuration example of the threshold voltage generation unit 130 and the overcurrent detection unit 140. The threshold voltage generation unit 130 includes a current source 131, a resistor 132, and a current mirror 133. On the other hand, the overcurrent detection unit 140 includes a comparator 141.

  The current source 131 is connected between the current input terminal of the current mirror unit 133 and the application terminal of the constant voltage VBBM5, and selectively outputs one of the first current Iref and the second current Iset according to the threshold control signal S170. To do. More specifically, the current source 131 selectively outputs the first current Iref when the threshold control signal S170 is at a low level, and selectively outputs the second current Iset when the threshold control signal S170 is at a high level. To do.

  The resistor 132 is connected between the current output terminal of the current mirror unit 133 and the application terminal (= external terminal T2) of the output voltage Vo, and the resistance value thereof is the first resistance value according to the threshold control signal S170. It is switched to one of Rref1 and the second resistance value Rref2. More specifically, the resistance value of the resistor 132 becomes the first resistance value Rref1 when the threshold control signal S170 is at a low level, and becomes the second resistance value Rref2 when the threshold control signal S170 is at a high level. .

  The current mirror unit 133 operates by receiving the constant voltage VBB_REF and the boosted voltage VG, and mirrors the first current Iref or the second current Iset input from the current source 131 and outputs the mirrored current to the resistor 132. Accordingly, a threshold voltage Vth whose voltage value is switched according to the threshold control signal S170 is generated at the current output terminal of the current mirror unit 133 (= the high potential terminal of the resistor 132). More specifically, the threshold voltage Vth becomes the internal set value VthH (= Iref × Rref1) when the threshold control signal S170 is at a low level, and the external set value VthL when the threshold control signal S170 is at a high level. (= Iset × Rref2). The current mirror unit 133 also functions as a level shifter that transfers the first current Iref or the second current Iset from the first power supply system (VBB_REF-VBBM5 system) to the second power supply system (VG-Vo system).

  The constant voltage VBB_REF and the constant voltage VBBM5 are both reference voltages generated inside the semiconductor integrated circuit device 1. For example, VBB_REF≈VBB and VBBM5≈VBB-5V.

  The power supply terminal of the comparator 141 is connected to the application terminal of the boost voltage VG. The reference potential terminal of the comparator 141 is connected to the application terminal (external terminal T2) of the output voltage Vo. The non-inverting input terminal (+) of the comparator 141 is connected to the application terminal for the sense voltage Vs. The inverting input terminal (−) of the comparator 141 is connected to the application terminal of the threshold voltage Vth. The comparator 141 connected in this way compares the sense voltage Vs with the threshold voltage Vth and generates an overcurrent protection signal S71. The overcurrent protection signal S71 becomes low level (= logic level when no overcurrent is detected) when the sense voltage Vs is lower than the threshold voltage Vth, and high level (= when the sense voltage Vs is higher than the threshold voltage Vth). (Logic level when overcurrent is detected).

  FIG. 8 is a schematic diagram illustrating an example of an overcurrent detection threshold. As described above, the threshold voltage Vth compared with the sense voltage Vs is switched to one of the internal set value VthH and the external set value VthL according to the threshold control signal S170. This is equivalent to the overcurrent detection threshold value Iocp compared with the output current Io being switched to one of the internal set value IocpH and the external set value IocpL.

  The internal set value IocpH is a fixed value (for example, about 15 A) corresponding to the on-resistance value and the element breakdown voltage of the NMOSFET 10 so that the semiconductor integrated circuit device 1 is not destroyed even when a short circuit abnormality of the load 3 occurs. Is desirable. Thus, the internal set value IocpH is only for the purpose of protecting the semiconductor integrated circuit device 1 itself, and often deviates greatly from the steady value of the output current Io.

  On the other hand, in view of the fact that the abnormal value of the output current Io varies depending on the load 3, the external set value IocL is desirably a variable value (for example, 1A to 10A) corresponding to the load 3. For example, the output current Io when the bulb lamp is driven is generally larger than the output current Io when the solenoid is driven. In view of this, when the bulb lamp is driven, the external set value IocL may be set higher than when the solenoid is driven. Conversely, the output current Io when driving the light emitting diode is generally smaller than the output current Io when driving the solenoid. In view of this, when the light emitting diode is driven, the external set value IocL may be set lower than when the solenoid is driven.

  By the way, some loads 3 to be driven by the semiconductor integrated circuit device 1 need to flow a large output current Io instantaneously as a normal operation thereof. For example, when the bulb lamp is started, a larger inrush current flows instantaneously than during steady operation. Depending on the load 3, a difference of several tens of times may occur between the output current Io at the time of startup and the output current Io at the time of steady operation.

  Therefore, in order to achieve both the securing of the instantaneous current and the overcurrent protection according to the load 3, the overcurrent detection threshold Iocp compared with the output current Io (and thus the threshold voltage Vth compared with the sense voltage Vs). ) Must be switched at an appropriate time.

  Hereinafter, a detailed description will be given of means for realizing appropriate switching control of the threshold voltage Vth (the reference voltage generation unit 150, the comparison unit 160, and the threshold control unit 170).

<Reference voltage generator / comparator>
FIG. 9 is a circuit diagram illustrating a configuration example of the reference voltage generation unit 150 and the comparison unit 160. The reference voltage generation unit 150 includes a current source 151 and a resistor 152 (resistance value: R152). The comparison unit 160 includes a comparator 161.

  The current source 151 is connected between the application terminal of the boosted voltage VG and the resistor 152, and the second current Iset generated by the second current generator 120 (more precisely, equivalent to the second current Iset). Variable current).

  The resistor 152 is connected between the current source 151 and the application terminal (= external terminal T2) of the output voltage Vo, and generates a reference voltage VIset (= Iset × R152) corresponding to the second current Iset. It is a voltage conversion element.

  The power supply terminal of the comparator 161 is connected to the application terminal of the boost voltage VG. The reference potential terminal of the comparator 161 is connected to the application terminal (external terminal T2) of the output voltage Vo. The non-inverting input terminal (+) of the comparator 161 is connected to the application terminal for the sense voltage Vs. The inverting input terminal (−) of the comparator 161 is connected to the application terminal of the reference voltage VIset. The comparator 161 connected in this way compares the sense voltage Vs with the reference voltage VIset and generates a comparison signal VCMP. The comparison signal VCMP becomes a low level when the sense voltage Vs is lower than the reference voltage VIset, and becomes a high level when the sense voltage Vs is higher than the reference voltage VIset.

  The resistance value R152 of the resistor 152 is switched to one of the first resistance value Rdet1 and the second resistance value Rdet2 (where Rdet1> Rdet2) according to the comparison signal VCMP. More specifically, the resistance value R152 of the resistor 152 becomes the first resistance value Rdet1 when the comparison signal VCMP is at a low level, and becomes the second resistance value Rdet2 when the comparison signal VCMP is at a high level. Hysteresis characteristics can be imparted to the comparison unit 160 by such switching control of the resistance value R152.

<Threshold control unit>
FIG. 10 is a circuit diagram illustrating a configuration example of the threshold control unit 170. Threshold control unit 170 includes a comparator 171, a current source 172, a level shifter 173, an RS flip-flop 174, a discharge control unit 175, an NMOSFET 176, a capacitor 177, and an external terminal DLY.

  The power supply terminal of the comparator 171 is connected to the application terminal of the internal power supply voltage Vreg. The reference potential terminal of the comparator 171 is connected to the ground terminal GND. The non-inverting input terminal (+) of the comparator 171 is connected to the external terminal DLY (application terminal for the charging voltage Vd). The inverting input terminal (−) of the comparator 171 is connected to the application terminal of the mask period expiration voltage Vdref. The comparator 171 connected in this way compares the charging voltage Vd with the mask period expiration voltage Vdref and generates an internal signal Sx. The internal signal Sx becomes high level when the charging voltage Vd is higher than the mask period expiration voltage Vdref, and becomes low level when the charging voltage Vd is lower than the mask period expiration voltage Vdref.

  The current source 172 is connected between the application terminal of the internal power supply voltage Vreg and the external terminal DLY, and generates a predetermined charging current Id. Whether or not the current source 172 can operate is controlled in accordance with the internal signal Sy (= corresponding to the level-shifted comparison signal VCMP). More specifically, the current source 172 is in an operating state when the internal signal Sy is at a high level, and is in a non-operating state when the internal signal Sy is at a low level.

  The level shifter 173 generates an internal signal Sy that is pulse-driven between the internal power supply voltage Vreg and the ground voltage GND by level-shifting the comparison signal VCMP that is pulse-driven between the boosted voltage VG and the output voltage Vo. To do. Accordingly, when the comparison signal VCMP is at a high level (= VG), the internal signal Sy is also at a high level (= Vreg), and when the comparison signal VCMP is at a low level (= Vo), the internal signal Sy is also at a low level (= Vreg). GND).

  The RS flip-flop 174 outputs a threshold control signal S170 from the output terminal (Q) according to the internal signal Sx input to the set terminal (S) and the internal signal Sy input to the reset terminal (R). More specifically, the RS flip-flop 174 sets the threshold control signal S170 to a high level at the rising timing of the internal signal Sx, and resets the threshold control signal S170 to a low level at the falling timing of the internal signal Sy. .

  The discharge controller 175 generates an internal signal Sz in response to the internal signal Sx. More specifically, the discharge controller 175 sets the internal signal Sz to a high level over a predetermined discharge period Tdchg at the rising timing of the internal signal Sx.

  The NMOSFET 176 is a discharge switch element that conducts / cuts off between the external terminal DLY and the ground terminal GND (= between both ends of the capacitor 177) according to the internal signal Sz. The NMOSFET 176 is turned on when the internal signal Sz is at a high level, and turned off when the internal signal Sz is at a low level.

  The capacitor 177 is connected between the external terminal DLY and the ground terminal GND outside the semiconductor integrated circuit device 1. When the charging current Id is supplied from the current source 172 when the NMOSFET 176 is turned off, the charging voltage Vd of the capacitor 177 increases. On the other hand, when NMOSFET 176 is on, capacitor 177 is discharged through NMOSFET 176, so that charging voltage Vd decreases.

<Overcurrent protection operation>
FIG. 11 is a timing chart showing an example of the overcurrent protection operation. In order from the top, the external control signal Si, the first current Iref, the second current Iset, the sense voltage Vs, the comparison signal VCMP, the charge voltage Vd, and the internal signal Sx to Sz, a threshold control signal S170, a threshold voltage Vth, and a state notification signal So are depicted.

  When the external control signal Si is raised to a high level at time t11, the operation of generating the first current Iref is started without delay. However, at time t11, the shutdown of the semiconductor integrated circuit device 1 is not released, and the NMOSFET 10 remains off, so that the output current Io does not flow through the NMOSFET 10. Therefore, the sense voltage Vs is maintained at 0V.

  At time t12, when a predetermined activation delay period Tdly (for example, 5 μs) elapses from time t11, the shutdown of the semiconductor integrated circuit device 1 is released. As a result, the NMOSFET 10 is turned on and the output current Io starts to flow, so that the sense voltage Vs starts to rise. At time t12, the generation of the second current Iset and the reference voltage VIset corresponding to the second current Iset (VIset = VthL in this figure) is also started. At time t12, since the sense voltage Vs is lower than the reference voltage VIset, the comparison signal VCMP becomes low level. Therefore, since the threshold control signal S170 becomes low level, the internal set value VthH is selected as the threshold voltage Vth.

  When the sense voltage Vs exceeds the reference voltage VIset at time t13, the comparison signal VCMP becomes high level. As a result, the internal signal Sy goes high, and the charging voltage Vd begins to rise. At time t13, since the charging voltage Vd is lower than the mask period expiration voltage Vdref, the internal signal Sx remains at a low level. Therefore, since the threshold control signal S170 is maintained at the low level, the internal set value VthH remains selected as the threshold voltage Vth. Therefore, even if the sense voltage Vs exceeds the external set value VthL (= VIset), overcurrent protection is not applied.

  When the charging voltage Vd exceeds the mask period expiration voltage Vdref at time t14, the internal signal Sx becomes high level. Therefore, since the threshold control signal S170 is set to a high level, the threshold voltage Vth is switched to the external set value VthL. As a result, after time t14, overcurrent protection is applied so that the sense voltage Vs does not exceed the external set value VthL. When the internal signal Sx rises to a high level, the internal signal Sz also becomes a high level over a predetermined discharge period Tdchg, so that the charging voltage Vd is discharged to 0V. The discharge period Tdchg is desirably shorter (for example, 3 μs) than the above-described start delay period Tdly.

  Thus, when the threshold voltage Vth is the internal set value VthH, the threshold voltage is reached when a predetermined mask period Tmask (= time t13 to t14) elapses while the sense voltage Vs exceeds the reference voltage VIset. Vth is switched to the external set value VthL. Therefore, overcurrent protection according to the load 3 can be realized.

  On the other hand, although not explicitly shown in this figure, even if the sense voltage Vs instantaneously exceeds the reference voltage VIset, if the reference voltage VIset falls again before the mask period Tmask expires, the threshold voltage Vth becomes the internal set value VthH. Will remain maintained. Accordingly, since unintended overcurrent protection is not applied, it is possible to secure an instantaneous current at the time of startup.

  As a matter of course, when the threshold voltage Vth is set to the internal set value VthH, if the sense voltage Vs exceeds the internal set value VthH, overcurrent protection is applied without delay at that time. Therefore, when a short circuit abnormality of the load 3 or the like occurs, the NMOSFET 10 can be forcibly turned off quickly, so that the semiconductor integrated circuit device 1 itself can be prevented from being destroyed.

  The mask period Tmask is a variable value that can be arbitrarily adjusted using the external capacitor 177. More specifically, the mask period Tmask increases as the capacitance value of the capacitor 177 increases, and decreases as the capacitance value of the capacitor 177 decreases. However, the longer the mask period Tmask, the later the start timing of overcurrent protection using the external set value VthL. Therefore, it is desirable to set the mask period Tmask to the minimum necessary length in consideration of the duration of the instantaneous current at the time of startup.

  Further, depending on the application of the semiconductor integrated circuit device 1 (the type of the load 3), it is possible to arbitrarily use whether or not to provide the mask period Tmask. For example, if the external terminal DLY is left open, the mask period Tmask is substantially zero, which is equivalent to the case where only the external set value VthL is provided. For example, if the external terminal DLY is short-circuited to the ground terminal GND, the mask period Tmask becomes infinite, which is equivalent to the case where only the internal set value VthH is provided.

  When the sense voltage Vs falls below the reference voltage VIset at time t15, the comparison signal VCMP becomes low level, and the internal signal Sy becomes low level. As a result, the threshold control signal S170 is reset to a low level, and the threshold voltage Vth is switched to the internal set value VthH.

  Thus, when the threshold voltage Vth is the external set value VthL, the threshold voltage Vth is switched to the internal set value VthH when the sense voltage Vs falls below the reference voltage VIset. That is, when the overcurrent protection operation using the external set value VthL is canceled, the overcurrent protection circuit 71 is returned to the initial state at the time of startup.

  When the external control signal Si rises to a low level at time t16, the semiconductor integrated circuit device 1 is shut down and the above series of operations ends.

  Focusing on the state notification signal So, the output detection voltage V80 (see also the broken line in the figure) corresponding to the detection result of the output current Io is selectively output in the overcurrent non-detection period (other than times t14 to t15). ing. On the other hand, in the overcurrent detection period (time t14 to t15), instead of the output detection voltage V80, the constant voltage V90 corresponding to the abnormality flag is selectively output.

  FIG. 12 is a flowchart illustrating an example of the threshold value switching operation. When the flow starts, first, in step S101, the threshold voltage Vth is set to the internal set value VthH (= Iref × Rref1) (corresponding to time t12 in FIG. 11).

  Next, in step S102, it is determined whether or not the sense voltage Vs is higher than the reference voltage VIset. If the determination is yes, the flow proceeds to step S103. On the other hand, if a negative determination is made, the flow is returned to step S102, and the determination in this step is repeated (corresponding to times t12 to t13 in FIG. 11).

  In step S103, in response to a YES determination in step S102, charging of the capacitor 177 is started (corresponding to time t13 in FIG. 11).

  Next, in step S104, it is determined whether or not the charging voltage Vd is higher than the mask period expiration voltage Vdref. If the determination is yes, the flow proceeds to step S105. On the other hand, if a negative determination is made, the flow is returned to step S104, and the determination in this step is repeated (corresponding to times t13 to t14 in FIG. 11).

  In step S105, the capacitor 177 is discharged in response to a yes determination in step S104. In step S106, the threshold voltage Vth is switched to the external set value VthL (= Iset × Rref2). These steps S105 and S106 correspond to time t14 in FIG.

  Next, in step S107, it is determined whether or not the sense voltage Vs is lower than the reference voltage VIset. If the determination is yes, the flow returns to step S101, and the threshold voltage Vth is switched again to the internal set value VthH (= Iref × Rref1) (corresponding to time t15 in FIG. 11). On the other hand, if a negative determination is made, the flow is returned to step S107, and the determination in this step is repeated (corresponding to times t14 to t15 in FIG. 11).

<Usage example>
FIG. 13 is a schematic diagram illustrating a first usage example of the overcurrent protection circuit 71. For example, when the load 3 is a bulb lamp, as shown by the solid line in the figure, an instantaneous current larger than that during steady operation flows as the output current Io at the time of startup. However, if the above-described mask period Tmask is appropriately set, the instantaneous current can be excluded from the detection target, so that unintended overcurrent protection is not applied. That is, the output current Io and the internal set value IocpH are compared at the time of startup when an excessive instantaneous current flows, and the output current Io and the external set value IocpL are compared at the time of steady operation. Therefore, the drive area of the output current Io can be expressed as a hatched area in the drawing.

  FIG. 14 is a schematic diagram illustrating a second usage example of the overcurrent protection circuit 71. For example, when the load 3 is a motor, as indicated by a solid line in the figure, an instantaneous current larger than that during steady operation flows as the output current Io at the time of locking. However, if the above-described mask period Tmask is appropriately set, the instantaneous current can be excluded from the detection target, so that unintended overcurrent protection is not applied. That is, the output current Io and the internal set value IocpH are compared when the excessive instantaneous current flows, and the output current Io and the external set value IocpL are compared during steady operation. Therefore, the drive area of the output current Io can be expressed as a hatched area in the drawing.

<Action and effect>
As described above, in the overcurrent protection circuit 71, the two-stage internal set value IocpH and the external set value IocL are prepared as the overcurrent detection threshold Iocp to be compared with the output current Io, and A predetermined mask period Tmask is provided as a grace period until the internal set value IocpH is switched to the external set value IocL.

  By adopting such a configuration, it is possible to achieve both securing of instantaneous current and overcurrent protection according to the load 3. In particular, during the steady operation of the load 3, the external set value IocpL that is sufficiently lower than the internal set value IocpH is compared with the output current Io, so that a large current far from the drive current of the load 3 continues to flow as the output current Io. There is nothing. Therefore, it is possible to make the harness connected to the load 3 thinner than before.

  Further, the overcurrent protection circuit 71 eliminates the need for the ECU 2 to perform overcurrent protection in accordance with the load 3, thereby reducing the burden on the ECU 2 (= continuous monitoring of the output current Io, etc.). As a result, the ECU 2 can be made microcomputer-less.

<Semiconductor Integrated Circuit Device (Second Embodiment)>
FIG. 15 is a block diagram showing a second embodiment of the semiconductor integrated circuit device 1. The semiconductor integrated circuit device 1 of the present embodiment has been described so far so that the two-channel loads 3X and 3Y can be individually driven while being based on the first embodiment (FIG. 1). Elements (functional blocks 10 to 90, external terminals T1 to T4, and various voltages, currents, signals, etc.) are provided for each channel.

  Note that components related to driving of the load 3X are suffixed with “X”, and components related to driving of the load 3Y are suffixed with “Y”. Each operation and function is basically the same as the above-described components not suffixed with “X” and “Y”. For example, the operations and functions of the NMOSFETs 10X and 10Y are basically the same as those of the NMOSFET 10 described above. The same applies to other components. Therefore, unless there is a matter to be noted, the description of the operation and function of each component is omitted. Moreover, in this figure, although the output current detection part 80 and the signal output part 90 are not shown clearly, these functional blocks are separately mentioned later.

  In the semiconductor integrated circuit device 1 of the present embodiment, since the two-channel loads 3X and 3Y can be individually driven, the activation timing for each channel may be different. Therefore, in order to achieve both instantaneous current securing and overcurrent protection according to the load in each channel, the above-described mask period Tmask must be set correctly for each channel without depending on the difference in the start timing.

  The simplest configuration for realizing this is to prepare the above-described overcurrent protection circuit 71 (see FIG. 4) for two channels, and each of them as overcurrent protection circuits 71X and 71Y for each channel in parallel. Is to provide. However, in such a configuration, two external terminals DLY for setting the mask period Tmask are required, which may lead to a package change or an increase in cost of the semiconductor integrated circuit device 1.

  Therefore, in the following, an overcurrent protection circuit 71 is proposed in which the mask period Tmask can be set correctly for each channel without requiring the addition of the external terminal DLY.

  FIG. 16 is a block diagram showing an example of the configuration of the two-channel overcurrent protection circuit 71. The overcurrent protection circuit 71 of this configuration example includes a first current generation unit 110, a second current generation unit 120, threshold voltage generation units 130X and 130Y, overcurrent detection units 140X and 140Y, and a reference voltage generation unit 150X. And 150Y, comparison units 160X and 160Y, and a threshold control unit 170.

  Among the above components, the first current generation unit 110, the second current generation unit 120, the threshold voltage generation unit 130X, the overcurrent detection unit 140X, the reference voltage generation unit 150X, the comparison unit 160X, and the threshold control unit 170 are: It functions as an overcurrent detection circuit 71X for the first channel.

  Meanwhile, among the above components, the first current generation unit 110, the second current generation unit 120, the threshold voltage generation unit 130Y, the overcurrent detection unit 140Y, the reference voltage generation unit 150Y, the comparison unit 160Y, and the threshold control unit 170. Functions as an overcurrent detection circuit 71Y for the second channel.

  As described above, in the overcurrent protection circuit 71 of this configuration example, the first current generation unit 110, the second current generation unit 120, and the threshold control unit 170 are shared by the first channel and the second channel.

  The first current generator 110 generates the first current Iref and outputs it to the threshold voltage generators 130X and 130Y. The current value of the first current Iref is fixed inside the semiconductor integrated circuit device 1. The configuration of the first current generator 110 is basically the same as that shown in FIG. As means for outputting the first current Iref to both the threshold voltage generators 130X and 130Y, for example, a current mirror having two systems of current output terminals may be used.

  The second current generator 120 generates a second current Iset and outputs the second current Iset to the threshold voltage generators 130X and 130Y. The current value of the second current Iset can be arbitrarily adjusted from the outside of the semiconductor integrated circuit device 1. The configuration of the second current generator 120 is basically the same as that shown in FIG. As means for outputting the second current Iset to both the threshold voltage generators 130X and 130Y, for example, a current mirror having two systems of current output terminals may be used.

  The threshold voltage generation unit 130X switches whether the threshold voltage VthX is set to the internal setting value VthXH or the external setting value VthXL (where VthXH> VthXL) according to the threshold control signal S170X. The internal set value VthXH is a fixed value (= corresponding to the first set value) set in accordance with the first current Iref. On the other hand, the external set value VthXL is a variable value (= corresponding to the second set value) set according to the second current Iset.

  The threshold voltage generation unit 130Y switches whether the threshold voltage VthY is set to the internal setting value VthYH or the external setting value VthYL (where VthYH> VthYL) according to the threshold control signal S170Y. The internal set value VthYH is a fixed value (corresponding to the third set value) set according to the first current Iref. On the other hand, the external set value VthYL is a variable value (= corresponding to the fourth set value) set according to the second current Iset.

  The overcurrent detection unit 140X compares the sense voltage VsX corresponding to the output current IoX and the threshold voltage VthX to generate an overcurrent protection signal S71X.

  The overcurrent detection unit 140Y compares the sense voltage VsY corresponding to the output current IoY and the threshold voltage VthY to generate an overcurrent protection signal S71Y.

  The reference voltage generation unit 150X generates a reference voltage VIsetX (= corresponding to the first reference value) according to the second current Iset.

  The reference voltage generation unit 150Y generates a reference voltage VIsetY (= corresponding to a second reference value) corresponding to the second current Iset.

  The comparison unit 160X compares the sense voltage VsX with the reference voltage VIsetX to generate a comparison signal VCMPX.

  The comparison unit 160Y compares the sense voltage VsY and the reference voltage VIsetY to generate a comparison signal VCMPY.

  The threshold control unit 170 monitors both the comparison signals VCMPX and VCMPY to generate threshold control signals S170X and S170Y.

  The threshold control signal S170X is, for example, a low level when the internal set value VthXH should be selected as the threshold voltage VthX, and a high level when the external set value VthXL should be selected as the threshold voltage VthX.

  On the other hand, the threshold control signal S170Y is at a low level when, for example, the internal set value VthYH is to be selected as the threshold voltage VthY, and is at a high level when the external set value VthYL is to be selected as the threshold voltage VthY.

<Threshold control unit (first embodiment)>
FIG. 17 is a block diagram illustrating a first embodiment of the threshold control unit 170. The threshold control unit 170 of the present embodiment is based on the previous FIG. 10, and as means for realizing the two-channel, the comparator 171, the current source 172, the level shifters 173X and 173Y, the RS flip-flops 174X and 174Y, Discharge controller 175, NMOSFET 176, capacitor 177, charge controller 178, and external terminal DLY.

  The comparator 171 generates a charging voltage Vd (= charging voltage of the capacitor 177 appearing at the external terminal DLY) input to the non-inverting input terminal (+) and a mask period expiration voltage Vdref input to the inverting input terminal (−). The internal signal Sx is generated by comparison. The internal signal Sx becomes high level when the charging voltage Vd is higher than the mask period expiration voltage Vdref, and becomes low level when the charging voltage Vd is lower than the mask period expiration voltage Vdref. This is the same as FIG. 10 above.

  The current source 172 generates a charging current Id according to the charging control signal S178. Specifically, the current source 172 outputs the charging current Id when the current control signal S178 is at a high level, and stops the charging current Id when the charging control signal S178 is at a low level.

  The level shifter 173X shifts the level of the comparison signal VCMPX to generate the internal signal SyX.

  The level shifter 173Y generates the internal signal SyY by shifting the level of the comparison signal VCMPY.

  The RS flip-flop 174X outputs a threshold control signal S170X from the output terminal (Q) according to the internal signal Sx input to the set terminal (S) and the internal signal SyX input to the reset terminal (R). More specifically, the RS flip-flop 174X sets the threshold control signal S170X to a high level at the rising timing of the internal signal Sx, and resets the threshold control signal S170X to a low level at the falling timing of the internal signal SyX. .

  The RS flip-flop 174Y outputs a threshold control signal S170Y from the output terminal (Q) according to the internal signal Sx input to the set terminal (S) and the internal signal SyY input to the reset terminal (R). More specifically, the RS flip-flop 174Y sets the threshold control signal S170Y to a high level at the rising timing of the internal signal Sx, and resets the threshold control signal S170Y to a low level at the falling timing of the internal signal SyY. .

  The discharge controller 175 generates an internal signal Sz in response to the internal signal Sx. More specifically, the discharge controller 175 sets the internal signal Sz to a high level over a predetermined discharge period Tdchg at the rising timing of the internal signal Sx. This is the same as FIG. 10 above.

  The NMOSFET 176 is a discharge switch element that conducts / cuts off between the external terminal DLY and the ground terminal GND (= between both ends of the capacitor 177) according to the internal signal Sz. The NMOSFET 176 is turned on when the internal signal Sz is at a high level, and turned off when the internal signal Sz is at a low level. This is also the same as in FIG.

  The capacitor 177 is connected between the external terminal DLY and the ground terminal GND outside the semiconductor integrated circuit device 1. When the charging current Id is supplied from the current source 172 when the NMOSFET 176 is turned off, the charging voltage Vd of the capacitor 177 increases. On the other hand, when NMOSFET 176 is on, capacitor 177 is discharged through NMOSFET 176, so that charging voltage Vd decreases. This is also the same as in FIG.

  The charge control unit 178 generates a charge control signal S178 according to both the internal signals SyX and SyY (and thus the comparison signals VCMPX and VCMPY). Note that the charging control signal S178 basically becomes a high level (= logical level during charging) at the rising timing of the internal signal SyX or SyY.

  FIG. 18 is a timing chart showing the threshold value switching operation of the first embodiment. From the top, the sense voltages VsX and VsY, the comparison signals VCMPX and VCMPY (equivalent to the internal signals SyX and SyY), the charging voltage Vd, and the internal signal Sx and Sz, threshold control signals S170X and S170Y, and threshold voltages VthX and VthY are depicted, respectively.

  When the NMOSFET 10X is turned on at time t21, the sense voltage VsX starts to increase. However, since the sense voltage VsX is lower than the reference voltage VIsetX at time t21, the comparison signal VCMPX (= internal signal SyX) becomes low level. Therefore, since the threshold control signal S170X becomes low level, the internal set value VthXH is selected as the threshold voltage VthX. At time t21, the NMOSFET 10Y remains off and the sense voltage VsY is maintained at 0V.

  When the sense voltage VsX exceeds the reference voltage VIsetX at time t22, the comparison signal VCMPX (= internal signal SyX) becomes a high level, and the charging voltage Vd starts to rise. However, at time t22, since the charging voltage Vd is lower than the mask period expiration voltage Vdref, the internal signal Sx remains at a low level. Therefore, the threshold control signal S170X is maintained at a low level, and the internal set value VthXH remains selected as the threshold voltage VthX. Therefore, even if the sense voltage VsX exceeds the external set value VthXL (= VIsetX), overcurrent protection is not applied. At time t22, the NMOSFET 10Y remains off and the sense voltage VsY is maintained at 0V.

  At time t23, the NMOSFET 10Y is turned on and the sense voltage VsY starts to rise. At time t23, since the sense voltage VsY is lower than the reference voltage VIsetY, the comparison signal VCMPY (= internal signal SyY) is at a low level. Therefore, since the threshold control signal S170Y is at a low level, the internal set value VthYH is selected as the threshold voltage VthY.

  When the charging voltage Vd exceeds the mask period expiration voltage Vdref at time t24, the internal signal Sx becomes high level. At time t24, the comparison signal VCMPX (= internal signal SyX) is already at the high level (= the logic level when the reset is released). Accordingly, the threshold control signal S170X is set to a high level, and the threshold voltage VthX is switched to the external set value VthXL. As a result, after time t24, overcurrent protection is applied so that the sense voltage VsX does not exceed the external set value VthXL. When the internal signal Sx becomes high level, the internal signal Sz also becomes high level for a predetermined discharge period Tdchg, so that the charging voltage Vd is discharged to 0V.

  That is, when focusing on the threshold voltage VthX, when the threshold voltage VthX is set to the internal set value VthXH, the predetermined mask period Tmask (= time t22 to t24) has elapsed while the sense voltage VsX exceeds the reference voltage VIsetX. At the time, the threshold voltage VthX is switched to the external set value VthXL. Therefore, overcurrent protection according to the load 3X can be realized.

  On the other hand, at time t24, the comparison signal VCMPY (= internal signal SyY) is maintained at a low level (= logic level at reset). Therefore, even if the internal signal Sx rises to the high level, the threshold control signal S170Y is maintained at the low level, so that the internal set value VthYH remains selected as the threshold voltage VthY.

  At time t25, when the sense voltage VsY exceeds the reference voltage VIsetY, the comparison signal VCMPY (= internal signal SyY) becomes high level, so that the charging voltage Vd starts to rise again. However, at time t25, since the charging voltage Vd is lower than the mask period expiration voltage Vdref, the internal signal Sx remains at a low level. Accordingly, the threshold control signal S170Y is maintained at a low level, and the internal set value VthYH remains selected as the threshold voltage VthY. Therefore, even if the sense voltage VsY exceeds the external set value VthYL (= VIsetY), overcurrent protection is not applied.

  In the following description, the difference between the rising timing of the comparison signal VCMPX and the rising timing of the comparison signal VCMPY (= the difference between the starting timing of the first channel and the starting timing of the second channel) is referred to as a shift period Tshift.

  When the sense voltage VsX falls below the reference voltage VIsetX at time t26, the comparison signal VCMPX (= internal signal SyX) becomes low level. As a result, the threshold control signal S170X is reset to a low level, so that the threshold voltage VthX is switched to the internal set value VthXH.

  That is, focusing on the threshold voltage VthX, when the threshold voltage VthX is set to the external set value VthXL, the threshold voltage VthX is switched to the internal set value VthXH when the sense voltage VsX falls below the reference voltage VsetX.

  When the charging voltage Vd exceeds the mask period expiration voltage Vdref at time t27, the internal signal Sx becomes high level. At time t27, the comparison signal VCMPY (= internal signal SyY) is already at the high level (= the logic level when the reset is released). Accordingly, the threshold control signal S170Y is set to a high level, and the threshold voltage VthY is switched to the external set value VthXL. As a result, after time t27, overcurrent protection is applied so that the sense voltage VsY does not exceed the external set value VthYL. When the internal signal Sx becomes high level, the internal signal Sz also becomes high level for a predetermined discharge period Tdchg, so that the charging voltage Vd is discharged to 0V.

  In other words, focusing on the threshold voltage VthY, when the threshold voltage VthY is set to the internal set value VthYH, the predetermined mask period Tmask (= time t25 to t27) has elapsed while the sense voltage VsY remains higher than the reference voltage VIsetY. At the time, the threshold voltage VthY is switched to the external set value VthYL. Accordingly, overcurrent protection according to the load 3Y can be realized.

  At time t27, the comparison signal VCMPX (= internal signal SyX) has already fallen to a low level (= logic level at reset). Therefore, even if the internal signal Sx rises to the high level, the threshold control signal S170X is maintained at the low level, and thus the internal set value VthXH remains selected as the threshold voltage VthX.

  When the sense voltage VsY falls below the reference voltage VIsetY at time t28, the comparison signal VCMPY (= internal signal SyY) becomes low level. As a result, the threshold control signal S170Y is reset to a low level, so that the threshold voltage VthY is switched to the internal set value VthYH.

  That is, focusing on the threshold voltage VthY, when the threshold voltage VthY is set to the external set value VthYL, the threshold voltage VthY is switched to the internal set value VthYH when the sense voltage VsY falls below the reference voltage VsetY.

  As can be seen from the above-described series of threshold value switching operations, the threshold value control unit 170 according to the present embodiment does not require the addition of the external terminal DLY, and mask period Tmask (time t22 to t23 and time t25 to time) for each channel. It becomes possible to set t27) correctly.

  In this figure, the case where Tshift> Tmask has been described as an example. However, when Tshift ≦ Tmask, there is a risk that the above-described series of threshold value switching operations may fail. Below, the problem is explained in full detail.

  FIG. 19 is a timing chart showing the problems of the first embodiment. From the top, the comparison signals VCMPX and VCMPY, the internal signal Sx, and the threshold control signals S170X and S170Y are behaviors when Tshift <Tmask. Is depicted.

  In the example of this figure, since Tshift <Tmask, after the comparison signal VCMPX rises to the high level at time t31, the comparison signal VCMPY rises to the high level at time t32 before the mask period Tmaskk elapses. ing.

  Therefore, when the mask period Tmask elapses from time t31 and the internal signal Sx rises to high level at time t33, not only the comparison signal VCMPX but also the comparison signal VCMPY has already been at high level. Therefore, at time t33, the threshold control signals S170X and S170Y are simultaneously at the high level.

  In this case, there is no particular problem with the first channel that is activated first, but for the second channel that is activated later, the mask period Tmask is shortened by the shift period Tshift, which may hinder the securing of the instantaneous current. There is. Below, the 2nd Example of the threshold-value control part 170 which can eliminate this problem is proposed.

<Threshold control unit (second embodiment)>
FIG. 20 is a block diagram illustrating a second embodiment of the threshold control unit 170. The threshold value controller 170 of this embodiment is based on the first embodiment (FIG. 17), and in the discharge controller 175, not only the internal signal Sx but also the internal signals SyX and SyY (comparison signals VCMPX and VCMPY). Equivalent) and threshold control signals S170X and S170Y are also received. Therefore, hereinafter, the configuration and operation of the discharge control unit 175 will be mainly described.

  FIG. 21 is a block diagram illustrating a configuration example of the discharge control unit 175. The discharge control unit 175 of the figure includes a negative OR operator NOR1, an AND operator AND1 to AND3, an OR operator OR1, an inverter INV1 to INV3, a pulse generator PG1, a resistor R1, and a capacitor. And C1.

  The NOR circuit NOR1 generates a logic signal SA by performing a NOR operation on the threshold control signals S170X and S170Y. Accordingly, the logic signal SA is at a high level when both the threshold control signals S170X and S170Y are at a low level, and is at a low level when at least one of the threshold control signals S170X and S170Y is at a high level.

  The logical product operator AND1 generates a logical signal SB by a logical product operation of the internal signals SyX and SyY. Accordingly, the logic signal SB is at a high level when both the internal signals SyX and SyY are at a high level, and is at a low level when at least one of the internal signals SyX and SyY is at a low level.

  The logical product operator AND2 generates a logical signal SC by logical product operation of the logical signals SA and SB. Accordingly, the logic signal SC is at a high level when both of the logic signals SA and SB are at a high level, and is at a low level when at least one of the logic signals SA and SB is at a low level.

  The inverter INV1 inverts the logic signal SC to generate an inverted logic signal SCB.

  The resistor R1 and the capacitor C1 generate an integrated waveform logic signal SD obtained by blunting the inverted logic signal SCB with a predetermined time constant τ (= R × C).

  The inverters INV2 and INV3 compare the logic signal SD with a predetermined threshold value (= the logic inversion threshold value of the inverters INV2 and INV3) to generate a logic signal SE having a rectangular waveform.

  The AND operator AND3 generates a logic signal SF by the AND operation of the logic signals SC and SE. Therefore, the logic signal SF is at a high level when both the logic signals SC and SE are at a high level, and is at a low level when at least one of the logic signals SC and SE is at a low level.

  The pulse generator PG1 generates a one-shot pulse having a predetermined pulse width (= corresponding to the discharge period Tdchg) in the logic signal SG at the rising timing of the internal signal Sx.

  The logical sum operator OR1 generates an internal signal Sz by logical sum operation of the logical signals SF and SG. Therefore, the internal signal Sz becomes a low level when both of the logic signals SF and SG are at a low level, and becomes a high level when at least one of the logic signals SF and SG is at a high level.

  FIG. 22 is a timing chart showing the threshold value switching operation of the second embodiment. From the top, the comparison signals VCMPX and VCMPY (equivalent to the internal signals SyX and SyY), the logic signals SA to SG, the internal signal Sz, and the charging voltage are shown. For Vd, the internal signal Sx, and the threshold control signals S170X and S170Y, the behavior when Tshift <Tmask is depicted.

  In the example of this figure, after the comparison signal VCMPX rises to the high level at time t41, the comparison signal VCMPY rises to the high level at time t42 before the mask period Tmask elapses. That is, at time t42, the charging voltage Vd has not reached the mask period expiration voltage Vdref, and the internal signal Sx has not risen to a high level.

  Here, paying attention to the internal operation of the discharge control unit 175, at time t42, since the threshold control signals S170X and S170Y are both at the low level, the logic signal SA is at the high level. At time t42, the comparison signals CMPX and CMPY (and hence the internal signals SyX and SyY) are both at the high level, so that the logic signal SB rises to the high level. Therefore, the logic signal SC rises to a high level, and the logic signal SD starts to decrease with the time constant τ. However, since the logic signal SD is higher than the logic inversion threshold value of the inverter INV2 at the time t42, the logic signal SE is maintained at the high level.

  Therefore, at time t42, since both the logic signals SC and SE are at the high level, the logic signal SF rises to the high level, and the internal signal Sz rises to the high level. As a result, the charging voltage Vd is discharged.

  As described above, after one of the comparison signals CMPX and CMPY rises to a high level and the charging operation of the capacitor 177 is started, before the charging voltage Vd exceeds the mask period expiration voltage Vdref, the comparison signals CMPX and CMPY When the other rises to a high level, the capacitor 177 is discharged once, so that the timing operation of the mask period Tmask is reset.

  Thereafter, when the logic signal SD falls below the logic inversion threshold of the inverter INV2 at time t43, the logic signal SE falls to a low level. As a result, the logic signal SF falls to the low level, and eventually the internal signal Sz falls to the low level, so that the discharging operation is stopped and the charging voltage Vd starts to rise again.

  Note that the high level period (= time t42 to t43) of the logic signal SF corresponds to the discharging period Tdchg2 of the charging voltage Vd. The discharge period Tdchg2 can be arbitrarily set according to the time constant τ of the resistor R1 and the capacitor C1, and may be set to the same value (for example, 3 μs) as the above-described discharge period Tdchg.

  Thereafter, when the charging voltage Vd exceeds the mask period expiration voltage Vdref at time t44, the internal signal Sx rises to a high level. At this time, not only the comparison signal VCMPX but also the comparison signal VCMPY is already at the high level. Therefore, at time t44, the threshold control signals S170X and S170Y are simultaneously at the high level.

  With the above threshold value switching operation, the mask period of the threshold value control signal S170Y for the subsequent channel becomes the original set value (= Tmask). On the other hand, for the threshold control signal S170X of the advance channel, the mask period becomes a value (= Tmask + α) longer than the original set value.

  At time t44, when the internal signal Sx rises to a high level, a one-shot pulse having a predetermined pulse width (= Tdchg) is generated in the logic signal SG, so that the internal signal Sz becomes a high level and the charging voltage Vd Is discharged.

  At time t44, when the threshold control signals S170X and S170Y rise to a high level, the logic signal SA falls to a low level and the logic signal SC falls to a low level. As a result, the logic signal SD starts to rise with a time constant τ, and when the logic signal SD exceeds the logic inversion threshold of the inverter INV2, the logic signal SE rises to a high level. However, at this time, since the logic signal SC is already at the low level, the logic signal SF is maintained at the low level.

  As described above, with the threshold control unit 170 of the present embodiment, even if Tshift <Tmask, the masking period of the subsequent channel is not shortened, so that there is no possibility of hindering the securing of the instantaneous current.

  In this figure, the case where Tshift <Tmask has been described as an example. However, under the critical condition of Tshift = Tmask (or Tshift≈Tmask), even if the second embodiment is adopted, There is a risk of causing unintended problems. Below, the problem is explained in full detail.

  FIG. 23 is a timing chart showing the problems of the second embodiment. From the top, the comparison signals VCMPX and VCMPY (equivalent to the internal signals SyX and SyY), the charging voltage Vd, the internal signal Sx, and the threshold control signal are shown. For S170X and S170Y, the behavior when Tshift = Tmask is depicted.

  In the example of this figure, since Tshift = Tmask, after the comparison signal VCMPX rises to the high level at time t51, the comparison signal VCMPY rises to the high level at the same time as the mask period Tmask elapses at time t52. Yes.

  Here, when the above-described discharge operation (see time t42 in FIG. 22) is not in time and the charging voltage Vd exceeds the mask period expiration voltage Vdref and the internal signal Sx rises to the high level, the threshold control signals S170X and S170Y are At the same time, it becomes high level. As a result, the masking period of the subsequent channel becomes zero, so that an instantaneous current cannot be secured. Below, the 3rd Example of the threshold-value control part 170 which can eliminate this problem is proposed.

<Threshold control unit (third embodiment)>
FIG. 24 is a block diagram showing a third embodiment of the threshold control unit 170. The threshold control unit 170 of the present embodiment is characterized in that delay units 179X and 179Y are provided while being based on the second embodiment (FIG. 20). Therefore, the same components as those in the second embodiment are denoted by the same reference numerals as those in FIG. 20, and redundant descriptions are omitted. In the following, the delay units 179X and 179Y are mainly described.

  The delay unit 179X delays the internal signal SyX (equivalent to the comparison signal VCMPX) to generate a delay signal SyXd. Note that the delay unit 179X delays only the rising timing of the delay signal SyXd, and does not delay the falling timing of the delay signal SyXd. More specifically, the delay signal SyXd rises to a high level after a delay time td (eg, 3 μs) after the internal signal SyX rises to a high level, and at the same time the internal signal SyX falls to a low level. To fall.

  The delay unit 179Y delays the internal signal SyY (equivalent to the comparison signal VCMPY) to generate a delay signal SyYd. Note that the delay unit 179Y delays only the rising timing of the delay signal SyYd, and does not delay the falling timing of the delay signal SyYd. More specifically, the delay signal SyYd rises to a high level after a delay time td after the internal signal SyY rises to a high level, and falls to a low level at the same time that the internal signal SyY falls to a low level.

  With the addition of the delay units 179X and 179Y described above, the delay signals SyXd and SyYd are input to the RS flip-flops 174X and 174Y in place of the internal signals SyX and SyY, respectively.

  FIG. 25 is a timing chart showing the threshold value switching operation of the third embodiment. In order from the top, the comparison signal VCMPX (equivalent to the internal signal SyX), the delay signal SyXd, the comparison signal VCMPY (equivalent to the internal signal SyY), and the delay For signal SyYd, internal signal Sz, charging voltage Vd, internal signal Sx, and threshold control signals S170X and S170Y, the behavior when Tshift = Tmask is depicted.

  In the example of this figure, since Tshift = Tmask, after the comparison signal VCMPX (= SyX) rises to the high level at time t61, the comparison signal VCMPY (= SyY) coincides with the elapse of the mask period Tmask at time t62. ) Has risen to a high level. On the other hand, the delay signals SyXd and SyYd rise to a high level when a predetermined delay time td has elapsed from times t61 and t62, respectively.

  If the charging voltage Vd exceeds the mask period expiration voltage Vdref at time t62, the internal signal Sx becomes high level. At this time, the delay signal SyXd has already risen to the high level (= the logic level when the reset is released). Therefore, the threshold control signal S170X is set to a high level at time t62.

  On the other hand, at time t62, the delay signal SyYd is still maintained at the low level (= the logic level at the time of reset). Therefore, even if the internal signal Sx rises to a high level, the threshold control signal S170Y remains reset to a low level.

  Further, when the internal signal Sx rises to a high level, the internal signal Sz becomes a high level over a predetermined discharge period Tdchg, so that the charging voltage Vd is discharged to 0V. Thereafter, when the internal signal Sz falls to a low level at time t63, the discharging operation is stopped and the charging voltage Vd starts to rise again.

  When the charging voltage Vd exceeds the mask period expiration voltage Vdref at time t64, the internal signal Sx rises again to the high level. At this time, the delay signal SyYd has already risen to the high level (= the logic level when the reset is released). Therefore, the threshold control signal S170Y is set to a high level at time t64.

  Further, when the internal signal Sx rises to a high level, the internal signal Sz becomes a high level over a predetermined discharge period Tdchg, so that the charging voltage Vd is discharged to 0V. After that, when the internal signal Sz falls to the low level at time t65, the above discharge operation is stopped. Note that the charging operation for two channels is completed at this point, and therefore the charging voltage Vd does not start to rise again.

  Thereafter, when the comparison signal VCMPX (= internal signal SyX) falls to the low level at time t66, the delay signal SyXd also falls to the low level without delay. As a result, the threshold control signal S170X is reset to a low level.

  Similarly, when the comparison signal VCMPY (= internal signal SyY) falls to the low level at time t67, the delay signal SyYd also falls to the low level without delay. As a result, the threshold control signal S170Y is reset to a low level.

  As described above, the threshold control unit 170 according to the present embodiment generates the threshold control signals S170X and S170Y using the internal signal Sx and the delay signals SyXd and SyYd. Therefore, when Tshift ≦ Tmask, the charging voltage Vd is always discharged at the rising timing of the comparison signals VCMPX and VCMPY before the delay signals SyXd and SyYd rise to the high level.

  Therefore, even under a critical condition of Tshift = Tmask, the threshold control signals S170X and S170Y do not become high at the same time, so that the mask period Tmask can be set correctly for each channel.

<Flowchart>
FIG. 26 is a flowchart showing an example of the threshold switching operation with two channels. When the flow starts, first, in step S201, the threshold voltage Vth * of the activated channel is set to the internal set value Vth * H (where “*” is at least one of “X” and “Y”, and so on). (Corresponding to times t21 and t23 in FIG. 18).

  Next, in step S202, it is determined whether one of the comparison signals VCMPX and VCMPY is at a high level (that is, whether only one channel is activated). If the determination is yes, the flow proceeds to step S203 (corresponding to time t22 in FIG. 18). On the other hand, if a negative determination is made, the flow proceeds to step S208.

  In step S203, in response to a YES determination in step S202, charging of the capacitor 177 is started (corresponding to time t22 in FIG. 18).

  Next, in step S204, it is determined whether or not the charging voltage Vd is higher than the mask period expiration voltage Vdref. If the determination is yes, the flow proceeds to step S205 (corresponding to time t24 in FIG. 18). On the other hand, if a negative determination is made, the flow returns to step S204, and the determination at this step is repeated (corresponding to times t22 to t24 in FIG. 18).

  In step S205, the capacitor 177 is discharged in response to a yes determination in step S204. In step S206, the threshold voltage Vth * of the activated channel is switched to the external set value Vth * L. These steps S205 and S206 correspond to time t24 in FIG.

  Next, in step S207, it is determined whether the sense voltage Vs * of the activated channel is lower than the reference voltage VIset *. If the determination is yes, the flow returns to step S201, and the threshold voltage Vth * is switched to the internal set value Vth * H again (corresponding to time t26 in FIG. 18). On the other hand, if a negative determination is made, the flow is returned to step S207 and the determination in this step is repeated (corresponding to times t24 to t26 in FIG. 18).

  On the other hand, in step S208, it is determined whether or not both comparison signals VCMPX and VCMPY are at a high level in response to a negative determination in step S202 (that is, whether both channels are activated). A determination is made. If the determination is yes, the flow proceeds to step S209 (corresponding to time t23 in FIG. 18, time t42 in FIG. 22, or time t62 in FIG. 25). On the other hand, if no determination is made, since no channel is activated, the flow returns to step S201.

  In step S209, in response to a YES determination in step S208, whether or not one of the threshold control signals S170X and S170Y is at a high level (that is, the threshold voltage Vth * of the previous channel has already been switched to the external set value Vth * L). Is determined). If the determination is yes, the flow proceeds to step S203, and the threshold value switching operation for the subsequent channel is performed in steps S203 to S207 (corresponding to times t25 to t28 in FIG. 18). On the other hand, if a negative determination is made, the flow proceeds to step S210.

  In step S210, in response to the no determination in step S209, whether or not the threshold control signals S170X and S170Y are both at the low level (that is, the start timing of the subsequent channel is set before the mask period Tmask of the previous channel elapses). A determination is made as to whether or not it has arrived. If the determination is yes, the flow proceeds to step S211 (corresponding to time t42 in FIG. 22). On the other hand, if a negative determination is made, the flow proceeds to step S214.

  In step S211, in response to a YES determination in step S210, the capacitor 177 is once discharged, and then recharging is started (corresponding to times t42 to t43 in FIG. 22).

  Next, in step S212, it is determined whether or not the charging voltage Vd is higher than the mask period expiration voltage Vdref. If the determination is yes, the flow proceeds to step S213 (corresponding to time t44 in FIG. 22). On the other hand, when a negative determination is made, the flow is returned to step S212, and the determination at this step is repeated (corresponding to times t43 to t44 in FIG. 22).

  In step S213, the capacitor 177 is discharged in response to a yes determination in step S212. In step S214, the threshold voltages VthX and VthYL of both channels are simultaneously switched to the external setting values VthXL and VthYL. These steps S205 and S206 correspond to time t44 in FIG.

  Next, in step S215, it is determined whether or not the sense voltages VsX and VsY of both channels are lower than the reference voltages VIsetX and VIsetY. Here, if a yes determination is made, the flow returns to step S201 to enter a state of waiting for the next activation. On the other hand, if a negative determination is made, the flow is returned to step S215, and the determination in this step is repeated.

<Multiplexer>
FIG. 27 is a block diagram showing an example in which a multiplexer is introduced as the output stage of the status notification signal So in accordance with the two-channel semiconductor integrated circuit device 1 described so far. In the semiconductor integrated circuit device 1 of this configuration example, output current detection units 80X and 80Y, signal output units 90X and 90Y, a multiplexer 100, and an external terminal T5 are integrated.

  The output current detection unit 80X generates a sense current IsX ′ corresponding to the output current IoX and outputs it to the signal output unit 90X.

  The output current detection unit 80Y generates a sense current IsY ′ corresponding to the output current IoY and outputs it to the signal output unit 90Y.

  Based on the output selection signal S2X input from the control logic unit 40X, the signal output unit 90X is one of the sense current IsX ′ (= corresponding to the detection result of the output current IoX) and the fixed voltage V90 (= corresponding to the abnormality flag). Is included as a first state notification signal SoX. The selector 91X selectively outputs the sense current IsX ′ as the first state notification signal SoX when the output selection signal S2X is at the logic level (eg, low level) when no abnormality is detected, and the output selection signal S2X is abnormal. When it is at the logic level at the time of detection (for example, high level), the fixed voltage V90 is output as the first state notification signal SoX.

  Based on the output selection signal S2Y input from the control logic unit 40Y, the signal output unit 90Y is one of the sense current IsY ′ (= corresponding to the detection result of the output current IoY) and the fixed voltage V90 (= corresponding to the abnormality flag). Is included as a second state notification signal SoY. The selector 91Y selectively outputs the sense current IsY ′ as the second state notification signal SoY when the output selection signal S2Y is at the logic level (eg, low level) when no abnormality is detected, and the output selection signal S2Y is abnormal. When it is at the logic level at the time of detection (for example, high level), the fixed voltage V90 is output as the second state notification signal SoY.

  The multiplexer 100 determines whether the first state notification signal SoX (= sense current IsX ′ or fixed voltage V90) and the second state notification signal SoY (= sense current IsY ′ or One of the fixed voltages V90) is selectively output to the external terminal T4.

  When the sense current IsX ′ is selectively output to the external terminal T4, the output detection voltage V80X (= IsX ′ × R4) obtained by current / voltage conversion of the sense current IsX ′ with the external sense resistor 4 is used as the state notification signal So. It is transmitted to the ECU 2. The output detection voltage V80X increases as the output current IoX increases, and decreases as the output current IoX decreases.

  When the sense current IsY ′ is selectively output to the external terminal T4, the output detection voltage V80Y (= IsY ′ × R4) obtained by converting the sense current IsY ′ into current / voltage by the external sense resistor 4 as the state notification signal So. ) Is transmitted to the ECU 2. The output detection voltage V80Y increases as the output current IoY increases, and decreases as the output current IoY decreases.

  On the other hand, when the fixed voltage V90 is selectively output to the external terminal T4, the fixed voltage V90 is transmitted to the ECU 2 as the state notification signal So. Note that the fixed voltage V90 may be set to a voltage value higher than the upper limit values of the output detection voltages V80X and V80Y.

  By introducing such a multiplexer 100, it is possible to externally monitor both the detection results of the output currents IoX and IoY and the abnormality flag for any channel.

<Software switching function (undershoot suppression function)>
FIG. 28 is a diagram illustrating a state in which an undershoot of the overcurrent detection threshold Iocp occurs. As described above, in the overcurrent protection circuit 71, when the overcurrent detection threshold Iocp is set to the internal set value IocpH, the output current Io remains above the external set value IocpL (<IocpH). When the mask period Tmask (= see times t71 to t72) has elapsed, the overcurrent detection threshold Iocp is switched to the external set value IocL.

  At this time, if the difference between the internal set value IocpH and the external set value IocpL is large, the overcurrent detection threshold Iocp is likely to undershoot. When such an undershoot occurs, the output current Io is unnecessarily limited, which becomes a factor that hinders the stable operation of the load 3.

  Therefore, the overcurrent protection circuit 71 (particularly the threshold voltage generation unit 130) proposed below, as shown in FIG. 29, after the elapse of the mask period Tmask (= see times t81 to t82), the overcurrent detection threshold Iocp. When switching from the internal set value IocpH to the external set value IocL, a function for gradually decreasing the overcurrent detection threshold Iocp over a predetermined transition time Ttrans (= time t82 to t83) (hereinafter referred to as a software switching function) Called).

  By providing such a soft switching function, even if the difference between the internal set value IocpH and the external set value IocL is large, the undershoot of the overcurrent detection threshold value Iocp can be suppressed. Therefore, the output current Io is not unnecessarily limited, which can contribute to the stable operation of the load 3.

  FIG. 30 is a diagram illustrating a configuration example of the threshold voltage generation unit 130 having a soft switching function. The threshold voltage generation unit 130 of this configuration example includes a variable current source 134 and a resistor 135.

  The variable current source 134 is connected between the application terminal of the boost voltage VG and the output terminal of the threshold voltage Vth, and generates the variable current IREF. In particular, the variable current source 134 has a function of linearly controlling the current value of the variable current IREF in accordance with the threshold control signal S170. Specifically, the variable current source 134 fixes the variable current IREF to the first current Iref when the threshold control signal S170 is at a low level, while the threshold current control signal S170 rises to a predetermined level when the threshold control signal S170 rises to a high level. The variable current IREF is gradually reduced from the first current Iref to the second current Iset over time Ttrans.

  The resistor 135 is connected between the output terminal of the threshold voltage Vth and the application terminal (= external terminal T2) of the output voltage Vo, and generates the threshold voltage Vth (= IREF × R135) corresponding to the variable current IREF. .

  Therefore, with the linear control of the variable current IREF, the threshold voltage Vth gradually decreases from the internal set value VthH (= Iref × R135) to the external set value VthL (= Iset × R135). This is equivalent to the overcurrent detection threshold Iocp compared with the output current Io being gradually reduced from the internal set value IocpH to the external set value IocpL.

  FIG. 31 is a diagram illustrating a configuration example of the variable current source 134. The variable current source 134 of this configuration example includes an upper current generator 134H and a lower current generator 134L, and outputs a differential current (IH−IL) obtained by subtracting the lower current IL from the upper current IH as the variable current IREF. .

  Upper current generator 134H is a circuit block that generates upper current IH, and includes P-channel MOS field effect transistors P1 to P3. The sources and back gates of the transistors P1 to P3 are both connected to the application terminal of the internal power supply voltage Vreg. The gates of the transistors P1 to P3 are all connected to the drain of the transistor P1. Thus, the transistors P1 to P3 form a current mirror that mirrors the drain current of the transistor P1 as the drain currents of the transistors P2 and P3.

  Here, the first current Iref flows from the first current generation unit 110 to the drain of the transistor P1. Therefore, a mirror current equivalent to the first current Iref flows through the drains of the transistors P2 and P3. Note that the mirror current of the transistor P2 is supplied to the lower current generation unit 134L as the first current Iref itself. On the other hand, the mirror current of the transistor P3 is output from the upper current generator 134H as the upper current IH fixed to the same value as the first current Iref.

  The lower current generator 134L is a circuit block that generates a lower current IL, and includes P-channel MOS field effect transistors P4 to P7, N-channel MOS field effect transistors N1 to N7, an operational amplifier AMP, and a switch SW. And resistors R2 and R3 and a capacitor C2.

  The sources and back gates of the transistors P4 and P5 are both connected to the application terminal of the internal power supply voltage Vreg. The gates of the transistors P4 and P5 are both connected to the drain of the transistor P4. Thus, the transistors P4 and P5 form a current mirror that mirrors the drain current of the transistor P4 as the drain current of the transistor P5. Here, the second current Iset is supplied from the second current generator 120 to the drain of the transistor P4. Accordingly, a mirror current equivalent to the second current Iset flows through the drain of the transistor P5.

  The sources and back gates of the transistors N1 and N2 are both connected to the ground terminal. The gates of the transistors N1 and N2 are both connected to the drain of the transistor N1. Thus, the transistors N1 and N2 form a current mirror that mirrors the drain current of the transistor N1 as the drain current of the transistor N2. Here, the drain of the transistor N1 is connected to the drain of the transistor P5, and a mirror current equivalent to the second current Iset flows. Accordingly, a mirror current equivalent to the second current Iset also flows through the drain of the transistor N2.

  The sources and back gates of the transistors N3 and N4 are both connected to the ground terminal. The gates of the transistors N3 and N4 are both connected to the drain of the transistor N3. Thus, the transistors N3 and N4 form a current mirror that mirrors the drain current of the transistor N3 as the drain current of the transistor N4. Here, the drain of the transistor N3 is connected to the respective drains of the transistors P2 and N2, and a differential current (Iref−Iset) obtained by subtracting the second current Iset from the first current Iref is passed. Therefore, a mirror current equivalent to the differential current (Iref−Iset) flows through the drain of the transistor N4.

  The sources and back gates of the transistors P6 and P7 are both connected to the application terminal of the internal power supply voltage Vreg. The gates of the transistors P6 and P7 are both connected to the drain of the transistor P6. Thus, the transistors P6 and P7 form a current mirror that mirrors the drain current of the transistor P6 as the drain current of the transistor P7. Here, the drain of the transistor P6 is connected to the drain of the transistor N4, and the above-described differential current (Iref-Iset) flows therethrough. Therefore, a mirror current equivalent to the differential current (Iref−Iset) also flows through the drain of the transistor P7. This mirror current is used as a charging current for the capacitor C2.

  As described above, in the lower current generator 134L, the transistors P4 to P7 and N1 to N4 generate the charging current (= Iref−Iset) of the capacitor C2 by subtracting the second current Iset from the first current Iref. Functions as a charging current generator.

  The resistor R2 is connected between the drain of the transistor P7 and the ground terminal. The first end of the switch SW is connected to the drain of the transistor P7. The second end of the switch SW is connected to the first end of the capacitor C2. A second terminal of the capacitor C2 is connected to the ground terminal.

  The switch SW is turned off when the threshold control signal S170 is at a low level, and turned on when the threshold control signal S170 is at a high level. When the switch SW is on, the capacitor C2 is charged using the charging current (Iref-Iset) flowing through the drain of the transistor P7. In this manner, the switch SW functions as a charge control unit that starts charging the capacitor C2 in response to the rising of the threshold control signal S170. As the capacitor C2 is charged, the charging voltage VC of the capacitor C2 increases from a zero value to a predetermined upper limit value (= (Iref−Iset) × R2).

  The non-inverting input terminal (+) of the operational amplifier AMP is connected to the first terminal (= the output terminal of the charging voltage VC) of the capacitor C2. The inverting input terminal (−) of the operational amplifier AMP is connected to the source and back gate of the transistor N5. The output terminal of the operational amplifier AMP is connected to the gate of the transistor N5. The source and back gate of the transistor N5 are both connected to the first end of the resistor R3. A second end of the resistor R3 is connected to the ground end. The drain of the transistor N5 corresponds to the output terminal of the lower current generator 134L.

  The operational amplifier AMP controls the gate of the transistor N5 so that the non-inverting input terminal (+) and the inverting input terminal (−) are imaginarily short-circuited. Accordingly, since a voltage equivalent to the charging voltage VC is applied to the first end of the resistor R3, the lower current IL flowing through the drain of the transistor N5 is a variable voltage (= VC / R3) corresponding to the charging voltage VC. It becomes. More specifically, the lower current IL gradually increases from a zero value to a predetermined upper limit value (= (Iref−Iset) × R2 / R3) as the capacitor C2 is charged. Note that the upper limit value of the lower current IL can be set to (Iref−Iset) by setting the resistance values of the resistors R2 and R3 to the same value.

  As described above, in the lower current generation unit 134L, the operational amplifier AMP, the transistor N5, and the resistor R3 function as a voltage / current conversion unit that converts the charging voltage VC of the capacitor C2 into the lower current IL.

  The output terminal of the upper current generator 134H (= the drain of the transistor P3) and the output terminal of the lower current generator 134L (= the drain of the transistor N5) are both connected to the output terminal of the variable current IREF. Therefore, as the variable current IREF, a differential current (IH−IL) obtained by subtracting the lower current IL from the upper current IH is output.

  FIG. 32 is a diagram illustrating behaviors of the upper current IH, the lower current IL, and the variable current IREF (= IH−IL). As described above, the upper current IH (solid line) is a fixed value set to the same value as the first current Iref. On the other hand, the lower current IL (broken line) is a variable value that gradually increases from a zero value to a predetermined upper limit value (Iref-Iset) as the capacitor C2 is charged. Therefore, the variable current IREF (one-dot chain line) takes a predetermined transition time Ttrans (= see times t91 to t92) and the first current Iref (= Iref-0) to the second current Iset (= Iref− (Iref). -Iset)) gradually decreases.

<Operation range improvement>
In the semiconductor integrated circuit device 1 used as the in-vehicle high-side switch IC, it is necessary to allow a large current of several tens of A level as the on-resistance value of the NMOSFET 10 becomes smaller. Therefore, the overcurrent detection threshold Iocp (= internal setting) The value IocpH) increases. For example, when the on-resistance value of the NMOSFET 10 is 45 mΩ, the internal set value IocpH is set to type 30A (max 40A). On the other hand, the external set value IocL corresponding to the load 3 is set to less than 10A (min1 to 2A). That is, there is a difference of 40 times between the internal set value IocpH and the external set value IocL.

  Thus, when the internal set value IocpH increases and the current difference from the external set value IocpL increases, the operating range of the sense voltage Vs increases, making it difficult to achieve appropriate overcurrent protection. This problem will be described in detail with reference to the drawings.

  FIG. 33 is a diagram for explaining the operating point of the comparator 141. The comparator 141 in this figure includes a pair of N-channel MOS field effect transistors N6 and N7, and is configured as a so-called current mirror type comparator.

  The gates of the transistors N6 and N7 are both connected to the drain of the transistor N6. The drain of the transistor N6 is connected to the first output terminal of the current mirror 133, and the first current Iref or the second current Iset flows. The sources of the transistors N6 are all connected to the first end of the resistor 132 (= corresponding to the application end of the threshold voltage Vth). The second end of the resistor 132 is connected to the application end (= external terminal T2) of the output voltage Vo. The drain of the transistor N7 is connected to the second output terminal of the current mirror 133, and the first current Iref or the second current Iset flows therethrough. The drain of the transistor N7 is also connected to the output terminal of the overcurrent protection signal S71. The source of the transistor N7 is connected to the source of the NMOSFET 21 and the first end of the sense resistor 22 (= applied end of the sense voltage Vs). The second end of the sense resistor 22 is connected to the application end (= external terminal T2) of the output voltage Vo. The drain of the NMOSFET 21 is connected to the application terminal (= external terminal T1) of the power supply voltage VBB.

  The comparator 141 of this configuration example operates using the output voltage Vo as a reference potential, the threshold voltage Vth (= Iref (or Iset) × R132 + Vo) applied to the source of the transistor N6, and the sense applied to the source of the transistor N7. The overcurrent protection signal S71 is generated by comparing the voltage Vs (= Is × Rs + Vo).

  Here, for the power supply voltage VBB, the output voltage Vo, the sense voltage Vs, and the forward drop voltage Vf of the body diode associated between the source and drain of the NMOSFET 21, the following equation (1) is established.

  Vout <Vs <VBB + Vf (VBB≈OUT) (1)

  From the above equation (1), it can be seen that the operating point of the sense voltage Vs is at the Vout + Vf level. Therefore, considering that Vf=0.2V@150° C., for example, each of the sense resistor 22 and the resistor 132 is set so that the sense voltage Vs corresponding to the internal set value IocpH (for example, 40 A) is about 0.2V. When the resistance value is adjusted, the sense voltage Vs corresponding to the external set value IocpL (for example, 1 A) becomes a very low value of 5 mV.

  As described above, if the single comparator 141 is used to cope with both the internal set value IocpH and the external set value IocL, the operating point of the sense voltage Vs becomes very strict, so that it is easily affected by noise. There is a risk of deteriorating detection accuracy.

  FIG. 34 is a diagram showing a modification of the threshold voltage generation unit 130 and the overcurrent detection unit 140 (and their peripheral circuits) devised to solve the above problems. In the semiconductor integrated circuit device 1 of this modification, the overcurrent protection circuit 71 includes two threshold voltage generation units 130 and two overcurrent detection units 140. In the following description, the threshold voltage generation units 130a and 130b and the overcurrent detection units 140a and 140b will be described with individual reference numerals.

  Along with the above circuit change, the overcurrent protection circuit 71 is provided with a switching control unit 180 that performs switching control of the overcurrent detection units 140a and 140b, as well as the output current monitoring unit 20 and the gate control unit 30. In addition, various changes have been made. Hereinafter, the configuration of each part of the semiconductor integrated circuit device 1 will be specifically described in detail with reference to the drawing.

  The output current monitoring unit 20 includes NMOSFETs 21a to 21c and sense resistors 22a to 22c. Each of the NMOSFETs 21a to 21c is a mirror transistor connected in parallel to the NMOSFET 10, and generates a sense current Is corresponding to the output current Io. The size ratio between the NMOSFET 10 and the NMOSFETs 21a to 21c is m: 1 (where m> 1). Therefore, the sense current Is has a magnitude obtained by reducing the output current Io to 1 / m. Similar to the NMOSFET 10, the NMOSFETs 21a to 21c are turned on when the gate drive signal G1 is at a high level, and turned off when the gate voltage G2 is at a low level.

  The sense resistors 22a to 22c (resistance values: Rsa to Rsc) are connected between the sources of the NMOSFETs 21a to 21c and the external terminal T2, and generate currents / sense voltages Vsa to Vsc corresponding to the sense current Is. It is a voltage conversion element. The sense voltages Vsa and Vsb are used for comparison processing in the overcurrent detection units 140a and 140b, respectively. On the other hand, the sense voltage Vsc is used for comparison processing in the comparison unit 160.

  In the example of this figure, as a component of the comparison unit 160, a low-pass filter 162 and a delay unit 163 are provided in the subsequent stage of the comparator 161.

  The threshold voltage generators 130a and 130b include variable current sources 134a and 134b and resistors 135a and 135b (resistance values: Rrefa and Rrefb), respectively.

  The variable current source 134a is connected between the application terminal of the boost voltage VG and the output terminal of the threshold voltage Vtha, and generates the variable current Ia. In particular, the variable current source 134a has a function of linearly controlling the current value of the variable current Ia in accordance with the threshold control signal S170. Specifically, the variable current source 134a fixes the variable current Ia to the first current Iref when the threshold control signal S170 is at a low level, while the predetermined current transition occurs when the threshold control signal S170 rises to a high level. The variable current Ia is gradually reduced from the first current Iref to the intermediate current Im (however, Iset <Im <Iref) over time Ttrans1.

  The resistor 135a is connected between the output terminal of the threshold voltage Vtha and the external terminal T2, and generates a threshold voltage Vtha (= Ia × Rrefa) corresponding to the variable current Ia.

  The variable current source 134b is connected between the application terminal of the boost voltage VG and the output terminal of the threshold voltage Vthb, and generates the variable current Ib. In particular, the variable current source 134b has a function of linearly controlling the current value of the variable current Ib in accordance with the switching control signal S180. Specifically, the variable current source 134b fixes the variable current Ib to the intermediate current Im when the switching control signal S180 is at a high level, while the predetermined current transition occurs when the switching control signal S180 falls to a low level. The variable current Ib is gradually reduced from the intermediate current Im to the second current Iset over time Ttrans2.

  The resistor 135b is connected between the output terminal of the threshold voltage Vthb and the external terminal T2, and generates a threshold voltage Vthb (= Ib × Rrefb) corresponding to the variable current Ib.

  As described above, the threshold voltage generators 130a and 130b set the threshold voltages Vtha and Vthb (and thus the overcurrent detection threshold Iocp) using both the variable currents Ia and Ib.

  The overcurrent detection units 140a and 140b include comparators 141a and 141b, respectively, and compare the sense voltages Vsa and Vsb with the threshold voltages Vtha and Vthb, respectively, to generate overcurrent protection signals S71a and S71b.

  The non-inverting input terminal (+) of the comparator 141a is connected to the application terminal of the sense voltage Vsa. The inverting input terminal (−) of the comparator 141a is connected to the application terminal for the threshold voltage Vtha. The comparator 141a connected in this way compares the sense voltage Vsa and the threshold voltage Vtha to generate the overcurrent protection signal S71a. The overcurrent protection signal S71a is at a low level when the sense voltage Vsa is lower than the threshold voltage Vtha (= a logic level when no overcurrent is detected), and is at a high level when the sense voltage Vsa is higher than the threshold voltage Vtha (= (Logic level when overcurrent is detected).

  The non-inverting input terminal (+) of the comparator 141b is connected to the application terminal of the sense voltage Vsb. The inverting input terminal (−) of the comparator 141b is connected to the application terminal of the threshold voltage Vthb. The comparator 141b connected in this way compares the sense voltage Vsb and the threshold voltage Vthb to generate the overcurrent protection signal S71b. The overcurrent protection signal S71b is at a low level (= logic level when no overcurrent is detected) when the sense voltage Vsb is lower than the threshold voltage Vthb, and is at a high level (= when the sense voltage Vsb is higher than the threshold voltage Vthb). (Logic level when overcurrent is detected).

  As the gate control unit 30, two gate control units 30a and 30b are provided corresponding to the overcurrent detection units 140a and 140b, respectively. Gate control units 30a and 30b include NMOSFETs 35a and 35b, resistors 36a and 36b, and capacitors 37a and 37b, respectively. The gate control unit 30b further includes an NMOSFET 38.

  The drain of the NMOSFET 35 a is connected to the gate of the NMOSFET 10. The source of the NMOSFET 35a is connected to the external terminal T2. The overcurrent protection signal S71a is applied from the comparator 71a to the gate of the NMOSFET 35a. A resistor 36a and a capacitor 37a are connected in series between the drain and gate of the NMOSFET 35a.

  The NMOSFET 35a is turned off when the overcurrent protection signal S71a is at a low level, and turned on when the overcurrent protection signal S71a is at a high level. Accordingly, when the overcurrent protection signal S71a is raised to the high level, the gate drive signal G1 is lowered from the high level (= VG) at the steady state with a predetermined time constant τ (= R36a × C37a). As a result, the continuity of the NMOSFET 10 gradually decreases, so that the output current Io is limited. On the other hand, when the overcurrent protection signal S71a falls to the low level, the gate drive signal G1 is pulled up with a predetermined time constant τ. As a result, the conductivity of the NMOSFET 10 gradually increases, so that the restriction on the output current Io is released.

  The drain of the NMOSFET 35 b is connected to the gate of the NMOSFET 10. The source of the NMOSFET 35b is connected to the external terminal T2. The overcurrent protection signal S71b is applied from the comparator 71b to the gate of the NMOSFET 35b. A resistor 36b and a capacitor 37b are connected in series between the drain and gate of the NMOSFET 35b.

  The NMOSFET 35b is turned off when the overcurrent protection signal S71b is at a low level, and turned on when the overcurrent protection signal S71b is at a high level. Therefore, when the overcurrent protection signal S71b is raised to the high level, the gate drive signal G1 is lowered from the high level (= VG) at the steady state with a predetermined time constant τ (= R36b × C37b). As a result, the continuity of the NMOSFET 10 gradually decreases, so that the output current Io is limited. On the other hand, when the overcurrent protection signal S71b falls to the low level, the gate drive signal G1 is raised with a predetermined time constant τ. As a result, the conductivity of the NMOSFET 10 gradually increases, so that the restriction on the output current Io is released.

  An NMOSFET 38 that is turned on / off in response to the switching control signal S180 is connected between the gate of the NMOSFET 35b and the external terminal T2. Therefore, when the switching control signal S180 is at the high level, the NMOSFET 38 is turned on, and the overcurrent protection signal S71b is forcibly lowered to the low level, so that the NMOSFET 35b is turned off. Such an operation state corresponds to a state in which the overcurrent detection unit 140b is disabled (= a state in which overcurrent detection is performed using the overcurrent detection unit 140b).

  On the other hand, when the switching control signal S180 is at the low level, the NMOSFET 38 is turned off, so that the gate drive of the NMOSFET 35b is performed by the overcurrent protection signal S71b as described above. Such an operating state corresponds to a state in which the overcurrent detection unit 140b is enabled (= a state in which overcurrent detection is performed using the overcurrent detection unit 140b).

  As described above, the overcurrent detection units 140a and 140b are selectively used according to the switching control signal S180 (and overcurrent detection threshold Iocp).

  The switching control unit 180 includes a current source 181, a resistor 182, a comparator 183, and a NAND operator 184.

  The current source 181 is connected between the application terminal of the boost voltage VG and the output terminal of the threshold voltage VthM, and generates a predetermined intermediate current Im.

  The resistor 182 is connected between the output terminal of the threshold voltage VthM and the external terminal T2, and generates a threshold voltage VthM (= Im × R182) corresponding to the intermediate current Im. When replaced with the overcurrent detection threshold value Iocp, the threshold voltage VthM corresponds to an intermediate set value IocM that is lower than the internal set value IocpH and higher than the external set value IocpL.

  The inverting input terminal (−) of the comparator 183 is connected to the application terminal for the threshold voltage Vtha. The non-inverting input terminal (+) of the comparator 183 is connected to the application terminal for the threshold voltage VthM. The comparator 183 connected in this way compares the threshold voltage Vtha and the threshold voltage VthM to generate the comparison signal Scmp. The comparison signal Scmp is at a high level when the threshold voltage Vtha is higher than the threshold voltage VthM, and is at a low level when the threshold voltage Vtha is lower than the threshold voltage VthM. Such a comparison operation is nothing but an operation for detecting whether or not the overcurrent detection threshold value Iocp has decreased from the internal set value IocpH to the intermediate set value IocM.

  The NAND operator 184 generates the switching control signal S180 by performing a NAND operation on the comparison signal Scmp and the threshold control signal S170. Accordingly, the switching control signal S180 is at a low level when both the comparison signal Scmp and the threshold control signal S170 are at a high level, and is at a high level when at least one of the comparison signal Scmp and the threshold control signal S170 is at a low level. Become.

  FIG. 35 is a diagram illustrating a configuration example of the current generation circuit 190 included in the current source 181 and the variable current sources 134a and 134b. The current generation circuit 190 of this configuration example includes P-channel MOS field effect transistors P11 to P23, N-channel MOS field effect transistors N11 to N28, resistors R11 to R14, capacitors C11 and C12, and operational amplifiers AMP1 and AMP2. And switches SW1 and SW2 and an inverter INV.

  First, the connection relationship and operation will be described focusing on the parts (transistors P11 and P15 and transistors N15 and N16) that function as components of the current source 181.

  The sources and back gates of the transistors P11 to P15 are all connected to the application terminal of the internal power supply voltage Vreg. The gates of the transistors P11 to P15 are all connected to the drain of the transistor P11. Thus, the transistors P11 to P15 form a current mirror that mirrors the drain current of the transistor P11 as the drain currents of the transistors P12 to P15.

  Here, the intermediate current Im flows from the first current generator 110 to the drain of the transistor P11. As described above, the first current generator 110 is configured to generate the intermediate current Im instead of the first current Iref. Accordingly, a mirror current equivalent to the intermediate current Im flows through the drains of the transistors P12 to P15.

  The sources and back gates of the transistors N15 and N16 are both connected to the ground terminal. The gates of the transistors N15 and N16 are both connected to the drain of the transistor N15. Thus, the transistors N15 and N16 form a current mirror that mirrors the drain current of the transistor N15 as the drain current of the transistor N16. Here, the drain of the transistor N15 is connected to the drain of the transistor P15, and a mirror current equivalent to the intermediate current Im flows. Therefore, a mirror current equivalent to the intermediate current Im also flows through the drain of the transistor N16.

  The current source 181 receives a mirror current flowing through the drain of the transistor N16 as an input, and outputs an intermediate current Im equivalent thereto. Thus, the transistors P11 and P15 and the transistors N15 and N16 function as components of the current source 181.

  Next, attention is paid to portions (transistors P11 and P13 to P15, transistors N11 to N15 and N17, switch SW1, resistors R11 and R12, capacitor C11, inverter INV, and operational amplifier AMP1) that function as components of the variable current source 134a. To explain.

  The sources and back gates of the transistors N15 and N17 are both connected to the ground terminal. The gates of the transistors N15 and N17 are both connected to the drain of the transistor N15. Thus, the transistors N15 and N17 form a current mirror that mirrors the drain current of the transistor N15 as the drain current of the transistor N17. Here, as described above, a mirror current equivalent to the intermediate current Im flows through the drain of the transistor N15. Therefore, a mirror current equivalent to the intermediate current Im also flows through the drain of the transistor N17.

  The drain current of the transistor N17 is used as an element current i1 that is fixed to the same value as the intermediate current Im. Thus, the transistors P11 and P15 and the transistors N15 and N17 function as a first element current generation unit.

  The first ends of the resistor R11 and the switch SW1 are both connected to the drain of the transistor P13. The second end of the switch SW1 is connected to the first end of the capacitor C11. The second ends of the resistor R11 and the capacitor C11 are both connected to the ground end. When the switch SW1 is on, the capacitor C11 is charged using the drain current (= intermediate current Im) of the transistor P13. Thus, the transistors P11 and P13 function as a charging current generation unit that generates a charging current having the same value as the intermediate current Im.

  The sources and back gates of the transistors N12 and N13 are both connected to the ground terminal. The gates of the transistors N12 and N13 are connected to the drain of the transistor N12. Thus, the transistors N12 and N13 form a current mirror that mirrors the drain current of the transistor N12 as the drain current of the transistor N13. Here, the drain of the transistor N12 is connected to the drain of the transistor P14, and a mirror current equivalent to the intermediate current Im flows. Therefore, a mirror current equivalent to the intermediate current Im also flows through the drain of the transistor N13. The drain of the transistor N13 is connected to the first end of the capacitor C11. Therefore, when the current mirror is valid (= when the transistor N11 is turned off), the capacitor C11 is discharged using the drain current (= intermediate current Im) of the transistor N13. Thus, the transistors P11 and P14 and the transistors N12 and N13 function as a discharge current generation unit that generates a discharge current having the same value as the intermediate current Im.

  The input terminal of the inverter INV is connected to the application terminal of the threshold control signal S170. The output terminal of the inverter INV is connected to the control terminal of the switch SW1 and the gate of the transistor N11. The drain of the transistor N11 is connected to the drain of the transistor N12. The source and back gate of the transistor N11 are both connected to the ground terminal.

  When the threshold control signal S170 is at a low level, both the switch SW1 and the transistor N11 are turned on. As a result, the capacitor C11 is charged, and the charging voltage VC11 is charged to the upper limit value (= Im × R11). On the other hand, when the threshold control signal S170 is at a high level, both the switch SW1 and the transistor N11 are turned off. As a result, the capacitor C11 is discharged, and the charge voltage VC11 is discharged to a zero value. As described above, the inverter INV, the switch SW1, and the transistor N11 function as a charge / discharge control unit that switches the charge state and the discharge state of the capacitor C11 according to the threshold control signal S170.

  The non-inverting input terminal (+) of the operational amplifier AMP1 is connected to the first terminal (= the output terminal of the charging voltage VC11) of the capacitor C11. The inverting input terminal (−) of the operational amplifier AMP1 is connected to the source and back gate of the transistor N14. The output terminal of the operational amplifier AMP1 is connected to the gate of the transistor N14. The source and back gate of the transistor N14 are both connected to the first end of the resistor R12. A second end of the resistor R12 is connected to the ground end.

  The operational amplifier AMP1 controls the gate of the transistor N14 so that the non-inverting input terminal (+) and the inverting input terminal (−) are imaginarily short-circuited. Accordingly, since a voltage equivalent to the charging voltage VC11 is applied to the first end of the resistor R12, the element current i2 flowing through the drain of the transistor N14 is a variable voltage (= VC11 / R12) corresponding to the charging voltage VC11. Become. More specifically, the element current i2 gradually decreases from a predetermined upper limit value (= Im × R11 / R12) to a zero value as the capacitor C11 is discharged. Note that, by setting the resistance values of the resistors R11 and R12 to the same value, the upper limit value of the element current i2 can be set to the same value as the intermediate current Im.

  As described above, the operational amplifier AMP1, the transistor N14, and the resistor R12 function as a voltage / current conversion unit that converts the charging voltage VC11 of the capacitor C11 into the element current i2. And said capacitor C11, charging current generation part (P11, P13), discharge current generation part (P11, P14, N12, N13), charging / discharging control part (INV, SW1, N11), and voltage / current conversion part (AMP1, N14, R12) form a second element current generator that gradually decreases the element current i2 from a predetermined upper limit value (= Im) to a zero value in accordance with the threshold control signal S170.

  Note that the drain of the transistor N17 (= the output terminal of the element current i1) and the drain of the transistor N14 (= the output terminal of the element current i2) are connected to each other. An added current (i1 + i2) obtained by adding i2 flows.

  As described above, the element current i1 is a fixed value having the same value as the intermediate current Im, and the element current i2 is a variable value that decreases from a predetermined upper limit value (= Im) to a zero value. Therefore, the addition current (i1 + i2) changes from 2Im (= Im + Im) to Im (= Im + 0).

  The variable current source 134a receives the added current (i1 + i2) as an input and generates a variable current Ia equivalent to this. Specifically, the variable current source 134a fixes the variable current Ia to the first current Iref (= 2Im) when the threshold control signal S170 is at a low level, while the threshold control signal S170 rises to a high level. The variable current Ia is gradually reduced from the first current Iref to the intermediate current Im over a predetermined transition time Ttrans1.

  Next, attention is focused on the parts (transistors P11 and P12, transistors P15 to P23, transistors N15 and N18 to N28, switch SW2, resistors R13 and R14, capacitor C12, and operational amplifier AMP2) that function as components of the variable current source 134b. To explain.

  The sources and back gates of the transistors N15 and N18 are both connected to the ground terminal. The gates of the transistors N15 and N18 are both connected to the drain of the transistor N15. Thus, the transistors N15 and N18 form a current mirror that mirrors the drain current of the transistor N15 as the drain current of the transistor N18. Here, as described above, a mirror current equivalent to the intermediate current Im flows through the drain of the transistor N15. Therefore, a mirror current equivalent to the intermediate current Im also flows through the drain of the transistor N18.

  The sources and back gates of the transistors P16 and P17 are both connected to the application terminal of the internal power supply voltage Vreg. The gates of the transistors P16 and P17 are both connected to the drain of the transistor P16. Thus, the transistors P16 and P17 form a current mirror that mirrors the drain current of the transistor P16 as the drain current of the transistor P17. Here, the drain of the transistor P16 is connected to the drain of the transistor N18, and a mirror current equivalent to the intermediate current Im flows. Therefore, a mirror current equivalent to the intermediate current Im also flows through the drain of the transistor P17.

  The drain current of the transistor P17 is used as an element current i3 that is fixed to the same value as the intermediate current Im. Thus, the transistors P11 and P15 to P17 and the transistors N15 and N18 function as a third element current generation unit.

  The sources and back gates of the transistors P18 and P19 are both connected to the application terminal of the internal power supply voltage Vreg. The gates of the transistors P18 and P19 are both connected to the drain of the transistor P18. Thus, the transistors P18 and P19 form a current mirror that mirrors the drain current of the transistor P18 as the drain current of the transistor P19. Here, since the second current Iset flows from the second current generator 120 to the drain of the transistor P18, a mirror current equivalent to the second current Iset flows to the drain of the transistor P19.

  The sources and back gates of the transistors N21 and N22 are both connected to the ground terminal. The gates of the transistors N21 and N22 are both connected to the drain of the transistor N21. Thus, the transistors N21 and N22 form a current mirror that mirrors the drain current of the transistor N21 as the drain current of the transistor N22. Here, the drain of the transistor N21 is connected to the drain of the transistor P19, and a mirror current equivalent to the second current Iset is passed. Accordingly, a mirror current equivalent to the second current Iset also flows through the drain of the transistor N22.

  The sources and back gates of the transistors N23 and N24 are both connected to the ground terminal. The gates of the transistors N23 and N24 are both connected to the drain of the transistor N23. Thus, the transistors N23 and N24 form a current mirror that mirrors the drain current of the transistor N23 as the drain current of the transistor N24. Here, the drain of the transistor N23 is connected to the respective drains of the transistors P12 and N22, and a differential current (Im-Iset) obtained by subtracting the second current Iset from the intermediate current Im flows. Therefore, a mirror current equivalent to the differential current (Im-Iset) flows also to the drain of the transistor N24.

  The sources and back gates of the transistors P20 and P21 are both connected to the application terminal of the internal power supply voltage Vreg. The gates of the transistors P20 and P21 are both connected to the drain of the transistor P20. Thus, the transistors P20 and P21 form a current mirror that mirrors the drain current of the transistor P20 as the drain current of the transistor P21. Here, the drain of the transistor P20 is connected to the drain of the transistor N24, and the above-described differential current (Im-Iset) flows therethrough. Therefore, a mirror current equivalent to the differential current (Im−Iset) also flows through the drain of the transistor P21. This mirror current is used as a charging current for the capacitor C12.

  As described above, the transistors P4 to P7 and N1 to N4 function as a charging current generator that generates the charging current (= Im−Iset) of the capacitor C12 by subtracting the second current Iset from the intermediate current Im.

  The resistor R13 is connected between the drain of the transistor P21 and the ground terminal. The first end of the switch SW2 is connected to the drain of the transistor P21. The second end of the switch SW2 is connected to the first end of the capacitor C12. The second end of the capacitor C12 is connected to the ground end.

  The switch SW2 is turned off when the switching control signal S180 is at a high level, and is turned on when the switching control signal S180 is at a low level. When the switch SW2 is on, the capacitor C12 is charged using the charging current (Im-Iset) flowing through the drain of the transistor P21. Thus, the switch SW2 functions as a charge control unit that starts charging the capacitor C12 in response to the rise of the switching control signal S180. As the capacitor C12 is charged, the charging voltage VC12 of the capacitor C12 increases from a zero value to a predetermined upper limit value (= (Im−Iset) × R13).

  The non-inverting input terminal (+) of the operational amplifier AMP2 is connected to the first terminal (= the output terminal of the charging voltage VC12) of the capacitor C12. The inverting input terminal (−) of the operational amplifier AMP2 is connected to the source and back gate of the transistor N25. The output terminal of the operational amplifier AMP2 is connected to the gate of the transistor N25. The source and back gate of the transistor N25 are both connected to the first end of the resistor R14. A second end of the resistor R14 is connected to the ground end.

  The operational amplifier AMP2 controls the gate of the transistor N25 so that the non-inverting input terminal (+) and the inverting input terminal (−) are imaginarily short-circuited. Therefore, since a voltage equivalent to the charging voltage VC12 is applied to the first end of the resistor R14, the element current i4 flowing through the drain of the transistor N25 is a variable voltage (= VC12 / R14) corresponding to the charging voltage VC12. Become. More specifically, the element current i4 gradually increases from a zero value to a predetermined upper limit value (= (Im−Iset) × R13 / R14) as the capacitor C12 is charged. The upper limit value of the element current i4 can be set to (Im−Iset) by setting the resistance values of the resistors R13 and R14 to the same value.

  The sources and back gates of the transistors P22 and P23 are both connected to the application terminal of the internal power supply voltage Vreg. The gates of the transistors P22 and P23 are both connected to the drain of the transistor P22. Thus, the transistors P22 and P23 form a current mirror that mirrors the drain current of the transistor P22 as the drain current of the transistor P23. Here, the drain of the transistor P22 is connected to the drain of the transistor N25, and the previous element current i4 flows therethrough. Therefore, a mirror current equivalent to the element current i4 also flows through the drain of the transistor P23.

  The sources and back gates of the transistors N27 and N28 are both connected to the ground terminal. The gates of the transistors N27 and N28 are connected to the drain of the transistor N27. Thus, the transistors N27 and N28 form a current mirror that mirrors the drain current of the transistor N27 as the drain current of the transistor N28. Here, the drain of the transistor N27 is connected to the drain of the transistor P23, and the above-described element current i4 flows. Therefore, a mirror current equivalent to the element current i4 also flows through the drain of the transistor N28.

  The drain of the transistor N26 is connected to the drain of the transistor N27. The source and back gate of the transistor N26 are connected to the ground terminal. The gate of the transistor N26 is connected to the application terminal of the switching control signal S180.

  When the switching control signal S180 is at a high level, the transistor N26 is turned on. As a result, the current mirror composed of the transistors N27 and N28 is disabled, and the output of the element current i4 is prohibited. On the other hand, when the switching control signal S180 is at a low level, the transistor N26 is turned off. As a result, the current mirror composed of the transistors N27 and N28 becomes effective, and the output of the element current i4 is permitted.

  As described above, the operational amplifier AMP2, the transistor N25, and the resistor R14 (and the subsequent transistors P22 and P23, and the transistors N27 and N28) include a voltage / current conversion unit that converts the charging voltage VC12 of the capacitor C12 into the element current i4. Function as. The capacitor C12, the charging current generator (P11, P12, P18 to P21, N21 to N24), the charging controller (SW2), and the voltage / current converter (AMP2, N25, R14) are switched. A fourth element current generator is formed that gradually increases the element current i4 from a zero value to a predetermined upper limit value (= Im−Iset) in response to the signal S180.

  The sources and back gates of the transistors N19 and N20 are both connected to the ground terminal. The gates of the transistors N19 and N20 are both connected to the drain of the transistor N19. Thus, the transistors N19 and N20 form a current mirror that mirrors the drain current of the transistor N19 as the drain current of the transistor N20. Here, the drain of the transistor N19 is connected to the drains of the transistors P17 and N28, and a differential current (i3-i4) obtained by subtracting the element current i4 from the element current i3 is passed. Therefore, a mirror current equivalent to the differential current (i3-i4) flows also to the drain of the transistor N20.

  As described above, the element current i3 is a fixed value that is the same value as the intermediate current Im, and the element current i4 is a variable value that increases from a zero value to a predetermined upper limit value (= Im−Iset). . Therefore, the differential current (i3-i4) changes from Im (= Im-0) to Iset (= Im- (Im-Iset)).

  The variable current source 134b receives the differential current (i3-i4) as an input and generates a variable current Ib equivalent to this. Specifically, the variable current source 134b fixes the variable current Ib to the intermediate current Im when the switching control signal S180 is at a high level, while the predetermined current transition occurs when the switching control signal S180 falls to a low level. The variable current Ib is gradually reduced from the intermediate current Im to the second current Iset over time Ttrans2.

  In the above description, the case where Im = Iref / 2 is taken as an example. However, the current value of the intermediate current Im is not limited to this, and the operation points of the sense voltages Vsa and Vsb are hindered. It is possible to set an arbitrary current value within a range where no occurs.

  FIG. 36 is a diagram illustrating the switching operation of the overcurrent detection threshold value Iocp. As shown in the figure, when the threshold control signal S170 rises to a high level after the mask period Tmask (= refer to times t101 to t102), a transition time Ttrans1 (= refer to times t102 to t103) is applied. The overcurrent detection threshold Iocp is lowered from the internal set value IocpH to the intermediate set value IocpM. Note that the overcurrent detection operation (IocpM <Iocp <IocpH) before time t103 is mainly performed by the overcurrent detection unit 140a.

  After that, when the overcurrent detection threshold Iocp decreases to the intermediate set value IocpM and the switching control signal S180 falls to the low level, the transition time Ttrans2 (= see time t103 to t104) is applied and the overcurrent detection threshold Iocp is The value is further lowered from the intermediate set value IocpM to the external set value IocpL. The overcurrent detection operation after time t103 (IocpL <Iocp <IocM) is performed mainly by the overcurrent detection unit 140b.

  In this way, if the two overcurrent detection units 140a and 140b are prepared separately and both are used according to the overcurrent detection threshold Iocp, the difference between the internal set value IocpH and the external set value IocL is Even if it is large, the operating points of the sense voltages Vsa and Vsb can be adjusted individually, so that appropriate overcurrent protection can be realized.

  As described above, as the difference between the internal set value IocpH and the external set value IocpL increases, an undershoot is more likely to occur when the overcurrent detection threshold Iocp is switched. Therefore, when switching overcurrent detection threshold value Iocp, it can be said that it is desirable to introduce a soft switching function that gradually reduces overcurrent detection threshold value Iocp over a predetermined transition time Ttrans (= Ttrans1 + Ttrans2).

  However, the undershoot suppression technology for the overcurrent detection threshold Iocp and the operating point improvement technology for the sense voltages Vsa and Vsb can be implemented independently. For example, if it is not necessary to suppress the undershoot of the overcurrent detection threshold value Iocp, it is optional to set one or both of the transition times Ttrans1 and Ttrans2 to zero values.

  FIG. 37 is a flowchart showing an example of the threshold value switching operation in the present modification. When the flow starts, first, in step S300, the overcurrent protection circuit 71 is activated, and the first current Iref (and the intermediate current Im serving as the reference) and the second current Iset are generated.

  Next, in step S301, the overcurrent detection threshold Iocp is initially set to the internal set value IocpH (∝Iref).

  Next, in step S302, it is determined whether or not the comparison signal VCMP is at a high level (Vsc> Vset). Here, if the determination is yes, the flow proceeds to step S303. On the other hand, if a negative determination is made, the flow returns to step S302 and the determination in this step is repeated.

  In step S303, in response to a YES determination in step S302, charging of the capacitor 177 is started.

  Subsequently, in step S304, it is determined whether or not the threshold control signal S170 is at a high level (Vd> Vdref). If the determination is yes, the flow proceeds to step S305. On the other hand, if a negative determination is made, the flow returns to step S304 and the determination in this step is repeated.

  In step S305, the capacitor 177 is discharged in response to a yes determination in step S304.

  In step S306, overcurrent detection threshold Iocp is lowered from internal set value IocpH (∝Iref) to intermediate set value IocM (∝Im) over a predetermined transition time Ttrans1.

  Next, in step S307, it is determined whether or not the switching control signal S180 is at a low level (S170 = H and Vtha <VthM). If the determination is yes, the flow proceeds to step S308. On the other hand, if a negative determination is made, the flow returns to step S307 and the determination in this step is repeated.

  Note that, prior to the YES determination in step S307, the overcurrent detection unit 140b is invalidated, and thus an overcurrent detection operation mainly including the overcurrent detection unit 140a is performed. On the other hand, since the overcurrent detection unit 140b is enabled after the determination of YES in step S307, an overcurrent detection operation mainly including the overcurrent detection unit 140b is performed.

  In step S308, the overcurrent detection threshold Iocp is lowered from the intermediate set value IocM to the second set value IocL over the predetermined transition time Ttrans2.

  Next, in step S309, it is determined whether or not the comparison signal VCMP is at a low level (Vsc <VIset). If the determination is yes, the flow returns to step S301, and the overcurrent detection threshold Iocp is switched again to the internal set value IocpH. On the other hand, if a negative determination is made, the flow is returned to step S309 and the determination in this step is repeated.

<Application to vehicles>
FIG. 38 is an external view showing a configuration example of a vehicle. The vehicle X of this configuration example includes a battery (not shown in the figure) and various electronic devices X11 to X18 that operate by receiving power supply from the battery. In addition, about the mounting position of the electronic devices X11-X18 in this figure, it may differ from the actual for convenience of illustration.

  The electronic device X11 is an engine control unit that performs control related to the engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, and the like).

  The electronic device X12 is a lamp control unit that performs on / off control such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

  The electronic device X13 is a transmission control unit that performs control related to the transmission.

  The electronic device X14 is a body control unit that performs control (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.) related to the motion of the vehicle X.

  The electronic device X15 is a security control unit that performs drive control such as a door lock and a security alarm.

  The electronic device X16 is an electronic device that is built into the vehicle X at the factory shipment stage as a standard equipment item or manufacturer's option product, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat. It is.

  The electronic device X17 is an electronic device that is optionally mounted on the vehicle X as a user option product such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].

  The electronic device X18 is an electronic device that includes a high-voltage motor such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

  The semiconductor integrated circuit device 1, the ECU 2, and the load 3 described above can be incorporated in any of the electronic devices X11 to X18.

<Other variations>
Further, in the above embodiment, the description has been given by taking the in-vehicle high-side switch IC as an example, but the application target of the invention disclosed in the present specification is not limited to this, for example, In addition to other in-vehicle IPDs (such as in-vehicle low-side switch ICs and in-vehicle power supply ICs), the present invention can be widely applied to semiconductor integrated circuit devices other than in-vehicle applications.

  Various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. That is, the above-described embodiment is to be considered in all respects as illustrative and not restrictive, and the technical scope of the present invention is indicated not by the description of the above-described embodiment but by the scope of the claims. It should be understood that all modifications that fall within the meaning and range equivalent to the terms of the claims are included.

  The invention disclosed in this specification can be used for in-vehicle IPD and the like.

1 Semiconductor integrated circuit device 2 ECU
3, 3X, 3Y Load 4 External sense resistor 10, 10X, 10Y NMOSFET
20, 20X, 20Y Output current monitoring unit 21, 21 ', 21a, 21b, 21c NMOSFET
22, 22a, 22b, 22c Sense resistor 30, 30X, 30Y, 30a, 30b Gate control unit 31 Gate driver 32 Oscillator 33 Charge pump 34 Clamper 35, 35a, 35b NMOSFET
36a, 36b Resistor 37a, 37b Capacitor 38 NMOSFET
40, 40X, 40Y Control logic unit 50, 50X, 50Y Signal input unit 60, 60X, 60Y Internal power supply unit 70, 70X, 70Y Abnormal protection unit 71, 71X, 71Y Overcurrent protection circuit 72 Open protection circuit 73 Temperature protection circuit 74 Voltage drop protection circuit 80, 80X, 80Y Output current detector 90, 90X, 90Y Signal output unit 91, 91X, 91Y Selector 100 Multiplexer 110 First current generator 111 Operational amplifier 112 NMOSFET
113 Resistor 120 Second Current Generating Unit 121 Operational Amplifier 122 NMOSFET
123 Resistance 130, 130X, 130Y, 130a, 130b Threshold voltage generator 131 Current source 132 Resistor 133 Current mirror 134, 134a, 134b Variable current source 134H Upper current generator 134L Lower current generator 135, 135a, 135b Resistor 140, 140X, 140Y, 140a, 140b Overcurrent detection unit 141, 141a, 141b Comparator 150, 150X, 150Y Reference voltage generation unit 151 Current source 152 Resistor 160, 160X, 160Y Comparison unit 161 Comparator 162 Low-pass filter 163 Delay unit 170 Threshold control unit 171 Comparator 172 Current source 173, 173X, 173Y Level shifter 174, 174X, 174Y RS flip-flop 175 Discharge controller 176 NMOSFET
177 Capacitor 178 Charge control unit 179X, 179Y Delay unit 180 Switching control unit 181 Current source 182 Resistor 183 Comparator 184 Negated logical product operator 190 Current generation circuit NOR1 Negated logical sum operator AND1-AND3 Logical product operator OR1 Logical sum operator INV1 to INV3, INV Inverter PG1 Pulse generator R1 to R3, R11 to R14 Resistors C1, C2, C11, C12 Capacitors T1 to T5, SET, DLY External terminals P1 to P7, P11 to P23 P channel type MOS field effect transistor N1 N7, N11 to N28 N-channel MOS field effect transistor AMP, AMP1, AMP2 Operational amplifier SW, SW1, SW2 Switch X Vehicle X11 to X18 Electronic equipment

Claims (17)

A threshold value generation unit that switches between an overcurrent detection threshold value as a first setting value or a second setting value lower than the first setting value in accordance with a threshold control signal;
When the overcurrent detection threshold is set to the first set value, the overcurrent detection threshold is switched to the second set value when the mask period elapses while the monitoring target current exceeds the second set value. A threshold control unit for generating the threshold control signal,
Have
The threshold generation unit gradually lowers the overcurrent detection threshold over a predetermined transition time when switching the overcurrent detection threshold from the first set value to the second set value. Overcurrent protection circuit.   The threshold generation unit includes a variable current source that gradually decreases a variable current from a first current value to a second current value according to the threshold control signal, and sets the overcurrent detection threshold using the variable current. The overcurrent protection circuit according to claim 1. The variable current source is:
An upper current generator for generating an upper current fixed at the first current value;
A lower current generator that gradually increases a lower current from a zero value to a difference value between the first current value and the second current value according to the threshold control signal;
Including
The overcurrent protection circuit according to claim 2, wherein a differential current obtained by subtracting the lower current from the upper current is output as the variable current. The lower current generator is
A capacitor;
A charging current generator that subtracts a second current of the second current value from a first current of the first current value to generate a charging current of the capacitor;
A charge control unit that starts charging the capacitor in response to the threshold control signal;
A voltage / current converter that converts the charging voltage of the capacitor into the lower current;
The overcurrent protection circuit according to claim 3, further comprising: A threshold value generation unit that switches between an overcurrent detection threshold value as a first setting value or a second setting value lower than the first setting value in accordance with a threshold control signal;
An overcurrent detection unit that generates an overcurrent protection signal by comparing the monitoring target current and the overcurrent detection threshold;
When the overcurrent detection threshold is set to the first set value, the overcurrent detection threshold is switched to the second set value when the mask period elapses while the monitoring target current exceeds the second set value. A threshold control unit for generating the threshold control signal,
Have
The overcurrent detection circuit, wherein the overcurrent detection unit includes a first overcurrent detection unit and a second overcurrent detection unit that are selectively used according to the overcurrent detection threshold.   The threshold generation unit gradually lowers the overcurrent detection threshold over a predetermined transition time when switching the overcurrent detection threshold from the first set value to the second set value. The overcurrent protection circuit according to claim 5.   A switching control unit that generates a switching control signal for the overcurrent detection unit by comparing the overcurrent detection threshold with an intermediate setting value that is lower than the first setting value and higher than the second setting value; The overcurrent protection circuit according to claim 6. The threshold generation unit
A first variable current source that gradually decreases a first variable current from a first current value to an intermediate current value in response to the threshold control signal;
A second variable current source that gradually decreases the second variable current from the intermediate current value to the second current value in response to the switching control signal;
Including
The overcurrent protection circuit according to claim 7, wherein the overcurrent detection threshold is set using both the first variable current and the second variable current. The first variable current source includes:
A first element current generator for generating a first element current fixed at the intermediate current value;
A second element current generator that gradually decreases the second element current from the intermediate current value to a zero value in response to the threshold control signal;
Including
9. The overcurrent protection circuit according to claim 8, wherein an addition current obtained by adding the first element current and the second element current is output as the first variable current. The second element current generator is
A capacitor;
A charging current generator for generating a charging current of the intermediate current value;
A discharge current generator for generating a discharge current of the intermediate current value;
A charge / discharge control unit that switches a charge state and a discharge state of the capacitor according to the threshold control signal;
A voltage / current converter for converting a charging voltage of the capacitor into the second element current;
The overcurrent protection circuit according to claim 9, comprising: The second variable current source includes:
A third current generator for generating a third element current fixed at the intermediate current value;
A fourth current generator that gradually increases a fourth element current from a zero value to a difference value between the intermediate current value and the second current value in response to the switching control signal;
Including
The overcurrent protection circuit according to claim 9 or 10, wherein a differential current obtained by subtracting the fourth element current from the third element current is output as the second variable current. The fourth element current generator is
A capacitor;
A charging current generator that subtracts a lower current of the second current value from an upper current of the intermediate current value to generate a charging current of the capacitor;
A charge control unit that starts charging the capacitor in response to the switching control signal;
A voltage / current converter for converting the charging voltage of the capacitor into the fourth element current;
The overcurrent protection circuit according to claim 11, comprising:   The overcurrent protection circuit according to any one of claims 1 to 12, wherein the first set value is a fixed value, and the second set value is a variable value. A power transistor that conducts / cuts off a current path through which an output current flows; and
The overcurrent protection circuit according to any one of claims 1 to 13, wherein the overcurrent protection signal is generated by monitoring the output current;
A gate controller for controlling the power transistor in response to the overcurrent protection signal;
A semiconductor integrated circuit device characterized by being integrated. A semiconductor integrated circuit device according to claim 14,
A load connected to the semiconductor integrated circuit device;
An electronic device comprising:   The electronic device according to claim 15, wherein the load is a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor.   A vehicle comprising the electronic device according to claim 15 or 16.

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