JP2019033233A - Semiconductor device, and electronic equipment - Google Patents

Abstract

To provide a novel semiconductor device capable of arithmetic processing of AI (artificial intelligence).SOLUTION: A semiconductor device has a first processor chip, a memory, and a data bus. The first processor chip and the memory are electrically connected with the data bus, respectively. The first processor chip has an arithmetic circuit array performing calculation of AI, and the arithmetic circuit array has multiple arithmetic circuits. Each of multiple arithmetic circuits has a first transistor, a second transistor, a capacitive element, and a holding node. The first transistor has a function for controlling the writing of data in the holding node, and the channel formation region thereof has a metal oxide. The gate of the second transistor is electrically connected with the holding node, and the capacitive element is electrically connected with the holding node. Furthermore, the semiconductor device may have a second processor chip having an FPGA.SELECTED DRAWING: Figure 1

Description

For example, one embodiment of the present invention relates to a semiconductor device and an electronic device including the semiconductor device.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, or the like is one embodiment of a semiconductor device. In addition, a display device, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell and an organic thin film solar cell), and an electronic device may include a semiconductor device.

A transistor having a metal oxide in a channel formation region (hereinafter may be referred to as a “metal oxide transistor”, an “oxide semiconductor transistor”, or an “ox transistor”) is known. The ox transistor has an extremely small off-state current. By configuring the write transistor of the memory cell with an ox transistor, it is possible to provide a memory cell with excellent retention characteristics. For example, Non-Patent Document 1 discloses a multi-value NOSRAM (registered trademark) using an ox transistor.

Note that in this specification, NOSRAM refers to a memory device in which a memory cell is a two-transistor (2T) or three-transistor (3T) gain cell, and a write transistor of the memory cell is an ox transistor. Note that “NOSRAM” is an abbreviation for [Nonvolatile Oxide Semiconductor RAM].

In recent years, technological development in the field of artificial intelligence (AI) has been remarkable. Patent Document 1 describes a semiconductor device that uses an ox transistor and can constitute a neural network.

JP 2016-219011 A

T.A. Matsuzaki et al. "A 128 kb 4 bit / Cell Nonvolatile Memory with Crystalline In-Ga-Zn Oxide FET Using Vt Cancel Write Method," ISSCC Dig. Tech. Papers, 2015, pp. 306-307.

For example, an object of one embodiment of the present invention is to provide a novel semiconductor device having an ox transistor, or to provide a low power consumption semiconductor device capable of calculating AI.

One embodiment of the present invention need not solve all of the problems illustrated. The description of a plurality of tasks does not disturb the existence of each other's tasks. Problems other than those illustrated will be apparent from the description of this specification and the like, and these problems may also be a problem of one embodiment of the present invention.

The illustration of a plurality of issues does not preclude the existence of each other's issues. One embodiment of the present invention need not solve all of the problems illustrated. In addition, problems other than those listed will become apparent from the description of the present specification and the like, and such problems may also be a problem of one embodiment of the present invention.

(1) One embodiment of the present invention is a semiconductor device including a first processor chip, a memory unit, and a data bus, and the first processor chip and the memory unit are electrically connected to the data bus, respectively. The first processor chip includes an arithmetic circuit array that performs artificial intelligence operations, the arithmetic circuit array includes a plurality of arithmetic circuits, the arithmetic circuit includes a plurality of memory circuits, and the plurality of memory circuits include Each of the plurality of memory cells includes a holding node and a transistor that controls writing of data to the holding node, and a channel formation region of the transistor includes a metal oxide.

(2) In the above form (1), analog data is written in the holding node.

(3) One embodiment of the present invention is a semiconductor device including a first processor chip, a memory unit, and a data bus, and the first processor chip and the memory unit are electrically connected to the data bus, respectively. The first processor chip includes an arithmetic circuit array that performs artificial intelligence operations, the arithmetic circuit array includes a plurality of arithmetic circuits, the arithmetic circuit includes a plurality of memory circuits, and the plurality of memory circuits include , Each having a plurality of memory cells, each of the plurality of memory cells including a holding node and a transistor for controlling data writing to the holding node, and a channel formation region of the transistor including a metal oxide A semiconductor device characterized by the above.

(4) In the above form (3), digital data is written in the holding node.

(5) The semiconductor device according to any one of the above aspects (1) to (4) further includes a second processor chip.

In this specification and the like, ordinal numbers such as “first”, “second”, and “third” may be used to indicate order. Or it may be used to avoid confusion between components. In these cases, the use of ordinal numbers does not limit the number of components. For example, one form of the present invention can be described by replacing “first” with “second” or “third”.

In this specification and the like, when it is described that X and Y are connected, X and Y are electrically connected and X and Y are functionally connected The case and the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text. X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

The transistor has three terminals called gate, source, and drain. The gate is a control terminal that controls the conduction state of the transistor. Two terminals functioning as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals is a source and the other is a drain depending on the conductivity type (n-channel type, p-channel type) of the transistor and the potential applied to the three terminals of the transistor. Therefore, in this specification and the like, the terms source and drain can be used interchangeably. In this specification and the like, the two input / output terminals other than the gate may be referred to as a first terminal, a second terminal, and the like.

A node can be restated as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like depending on a circuit configuration, a device structure, or the like. Further, a terminal, a wiring, or the like can be referred to as a node.

In many cases, the voltage indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Thus, a voltage can be rephrased as a potential. Note that the potential is relative. Therefore, even if it is described as GND, it may not necessarily mean 0V.

In this specification, terms and phrases such as “above” and “below” may be used for convenience in describing the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

In this specification and the like, the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, it may be possible to change the term “conductive layer” to the term “conductive film”. For example, it may be possible to change the term “insulating film” to the term “insulating layer”.

According to one embodiment of the present invention, a novel semiconductor device including an ox transistor can be provided.

The description of a plurality of effects does not disturb the existence of other effects. Further, one embodiment of the present invention does not necessarily have all of the exemplified effects. Further, problems, effects, and novel features of the embodiment of the present invention other than those described above will be apparent from the description of the present specification and the drawings.

FIG. 11 is a functional block diagram illustrating a configuration example of a semiconductor device. A circuit diagram showing a configuration example of an AC: ox memory circuit. The schematic diagram which shows the structural example of the circuit part of an oxAI chip. A, B: The perspective schematic diagram which shows the structural example of an evaluation board. The figure which shows the structure of the fully connected neural network comprised by oxAI chip. The functional block diagram which shows the structural example of an oxAI chip. The circuit diagram which shows the structural example of a MAC array. The functional block diagram which shows the structural example of an oxAI chip. The block diagram which shows the structural example of a calculation array. The circuit diagram which shows the structural example of an arithmetic circuit. A: A circuit diagram showing a configuration example of a memory circuit. B: A circuit diagram showing a configuration example of a memory cell. FIG. 3 is a circuit diagram illustrating a configuration example of a memory circuit. A and B: Circuit diagrams showing a configuration example of a switch circuit. 2 shows the structure of a convolutional neural network composed of oxAI chips. A and B: schematic perspective views of a computer in which a semiconductor device is incorporated. A: A schematic perspective view of a supercomputer. B: A schematic perspective view showing an example of the internal structure of a computer. FIG. 9 illustrates an electronic device.

Hereinafter, embodiments of the present invention will be described. However, one form of the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, one embodiment of the present invention is not construed as being limited to the description of the embodiment modes to be given below.

A plurality of embodiments shown below can be appropriately combined. Further, in the case where a plurality of structure examples (including a manufacturing method example, an operation method example, a usage method example, and the like) are given in one embodiment, appropriate combinations of the structure examples with each other and other implementations It is also possible to appropriately combine with one or a plurality of configuration examples described in the embodiment.

In the drawings, the size, layer thickness, or region may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

[Embodiment 1]
In this embodiment, a semiconductor device having an arithmetic function for artificial intelligence, an electronic device in which the semiconductor device is mounted, and the like will be described. The arithmetic processing of artificial intelligence is arithmetic processing based on a mathematical model related to AI such as machine learning and neural network.

FIG. 1 is a functional block diagram illustrating a configuration example of a semiconductor device. A semiconductor device 100 illustrated in FIG. 1 includes a data bus 110, an input / output (I / O) interface 112, a memory unit 114, an FPGA chip 115, and an oxAI chip 120. The I / O interface 112, the memory unit 114, the FPGA chip 115, and the oxAI chip 120 exchange data via the data bus 110.

The I / O interface 112 preferably includes a plurality of types of interfaces for connecting various peripheral devices 150. For example, a USB connector, HDMI, (registered trademark) connector, eDP connector, ePCIe, LAN connector, and the like are provided.

“USB” is an abbreviation for Universal Serial Bus. “HDMI / eDP” is an abbreviation for High-Definition Multimedia Interface /. That is. eDP is an abbreviation for embedded DisplayPort. “EPCIe” is an abbreviation for Peripheral Component Interconnect Express. “LAN” is an abbreviation for Local Area Network.

The memory unit 114 has one or more memory chips. For example, a plurality of types of memory chips are provided in the memory unit 114, and the memory unit 114 is hierarchized. For example, an SRAM chip, a DRAM chip, and a flash memory chip are provided in the memory unit 114. A NOSRAM chip or a DOSRAM chip may be provided in place of the DRAM chip. A NOSRAM chip or a DOSRAM chip may be provided instead of the flash memory chip.

“DOSRAM (registered trademark)” is an abbreviation of “Dynamic Oxide Semiconductor RAM” and refers to a RAM having a one-transistor one-capacitance type memory cell composed of an ox transistor and a capacitor. Both NOSRAM and DOSRAM can be used as nonvolatile memories because the write transistor of the memory cell is an ox transistor.

Since the FPGA chip 115 is mounted on the semiconductor device 100, the semiconductor device 100 has high expandability. A memory device is incorporated in the FPGA chip 115.

Depending on the application of the semiconductor device 100 and the like, the types of IC chips incorporated in the semiconductor device 100 are discarded. It is preferable to incorporate at least a processor chip that executes an AI operation in the semiconductor device 100.

A user can develop software that operates on the semiconductor device 100 by connecting a host device 155 (for example, a personal computer (PC)) to the semiconductor device 100. The semiconductor device 100 can function as an accelerator for the host device 155.

<OxAI chip 120>
The oxAI chip 120 is an IC chip that can perform AI arithmetic processing using ox transistors. Data used by the oxAI chip 120 includes weight coefficient data (data that can be learned), image data, teacher data, and the like. The calculation result of the oxAI chip 120 is output as inference data, for example.

A feature of the oxAI chip 120 is that a memory circuit that stores data (typically, weight coefficient data) used for calculation is provided close to the calculation circuit. An ox transistor is used in this memory circuit. In this specification, a memory circuit including an ox transistor may be referred to as an “ox memory circuit”. 2A to 2C show circuit configuration examples of the ox memory circuit.

The ox memory circuit 11 shown in FIG. 2A has the same circuit configuration as the 2T gain cell, and includes a write transistor MW1, a read transistor MR1, and a capacitor element CS1. The gate of the read transistor MR1 is the holding node SN. Each of the write transistor MW1 and the read transistor MR1 is an ox transistor.

Since the band gap of metal oxide is 2.5 eV or more, the ox transistor has a minimum off-state current. As an example, the off-current per channel width of 1 μm is less than 1 × 10 ⁻²⁰ A, less than 1 × 10 ⁻²² A, or 1 × 10 at a source-drain voltage of 3.5 V and room temperature (25 ° C.). It can be less than ⁻²⁴ A. That is, the on / off current ratio of the drain current can be 20 digits or more and 150 digits or less. The semiconductor layers of the write transistor MW and the read transistor MR will be described later.

The node SN of the ox memory circuit 11 is charged with charge through the write transistor MW1. Since the ox transistor has a minimum off-state current, the write transistor MW1 hardly leaks the charge of the node SN. Therefore, the ox memory circuit 11 can function as a nonvolatile memory circuit and can be easily multi-valued. Therefore, the ox memory circuit 11 can be provided in the oxAI chip 120 as a nonvolatile analog memory circuit.

Metal oxides applied to ox transistors are Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). In addition, oxides containing indium and zinc include aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten , Or one or more selected from magnesium or the like may be included.

In order to improve the reliability and electrical characteristics of the ox transistor, the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystal part such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline metal oxide semiconductor. CAC-OS is an abbreviation for Cloud-Aligned Composite metal oxide semiconductor. nc-OS is an abbreviation for nanocrystalline metal oxide semiconductor.

The CAAC-OS has a c-axis orientation and has a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction to have a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement is changed between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

The CAC-OS has a function of flowing electrons (or holes) serving as carriers and a function of not flowing electrons serving as carriers. By separating the function of flowing electrons from the function of not flowing electrons, both functions can be maximized. That is, by using the CAC-OS for the channel formation region of the ox transistor, both a high on-state current and an extremely low off-state current can be realized.

By changing the back gate voltage of the write transistor MW1, the threshold voltage of the write transistor MW1 can be changed. The write transistor MW1 may be an ox transistor without a back gate. The same applies to the read transistor MR1.

Metal oxides have a large energy gap, electrons are difficult to be excited, and the effective mass of holes is large. Therefore, ox transistors are less likely to cause avalanche collapse or the like than general Si transistors. . Therefore, for example, hot carrier deterioration due to avalanche collapse may be suppressed. By suppressing the hot carrier deterioration, the ox transistor can be driven with a high drain voltage. Therefore, since the write transistor MW is an OS transistor, a high voltage can be applied to the node SN, so that the ox memory circuit 11 can be easily multi-valued.

The ox transistor is a storage type transistor having electrons as majority carriers. Therefore, the influence of DIBL (Drain-Induced Barrier Lowering), which is one of the short channel effects, is smaller than that of an inverting transistor having a pn junction (typically, a Si transistor). In other words, the ox transistor has higher resistance to the short channel effect than the Si transistor.

Since the ox transistor has high resistance to the short channel effect, the channel length can be reduced without deteriorating the reliability of the ox transistor. Therefore, by using the ox transistor, the degree of circuit integration can be increased. As the channel length becomes finer, the drain electric field becomes stronger. However, as described above, the ox transistor is less prone to avalanche collapse than the Si transistor.

In addition, since the ox transistor has high resistance to the short channel effect, the gate insulator can be made thicker than a transistor such as Si silicon. For example, even in a minute transistor with a channel length and a channel width of 50 nm or less, a thick gate insulator of about 10 nm may be provided. Since the parasitic capacitance can be reduced by increasing the thickness of the gate insulator, the operation speed of the circuit can be improved. Moreover, since the leakage current is reduced by increasing the thickness of the gate insulator, static current consumption is reduced.

An ox memory circuit 12 shown in FIG. 2B is a modification of the ox memory circuit 11, and the read transistor MW2 is an n-channel Si transistor. The read transistor MW2 may be a p-channel Si transistor.

The ox memory circuit 13 illustrated in FIG. 2C is a three-transistor gain cell, and includes a write transistor MW3, a read transistor MR3, a selection transistor MS3, and a capacitor element CS3. The transistors MW3, MR3, and MS3 are ox transistors each having a back gate. Some or all of these transistors may be ox transistors without a back gate.

An ox memory circuit 14 illustrated in FIG. 2D is a modification of the ox memory circuit 13. The read transistor MR4 and the select transistor MS4 are n-channel Si transistors. One or both of the transistors MR4 and MS4 may be p-channel Si transistors.

In order to rewrite data by charging / discharging the capacitive element CS1, the ox memory circuit 11 has no restriction on the number of rewrites in principle, can write and read data with low energy, and does not consume power to hold data. . Therefore, by incorporating the ox memory circuit 11 into the oxAI chip 120, an AI chip with low power consumption can be provided. The ox memory circuits 12 to 14 have the same features as the ox memory circuit 11.

FIG. 3A schematically shows a stacked structure of the circuit unit 121A of the oxAI chip 120. FIG. The circuit portion 121A has a stacked structure and is roughly divided into a Si transistor layer 1011, a wiring layer 1012, and an ox transistor layer 1013. Since the ox transistor layer 1013 can be stacked over the Si transistor layer 1011, the area of the oxAI chip 120 can be reduced.

A plurality of ox transistor layers 1013 may be provided as in the circuit portion 121B (see FIG. 3B) and the circuit portion 121C (see FIG. 3C). Unlike the circuit portions 121A and 121B, the circuit portion 121C is not provided with the Si transistor layer 1011. The number of ox transistor layers 1013 in the circuit portion 121C may be one layer.

A more specific circuit configuration of the oxAI chip 120 will be described in a second embodiment. As will be described later, the arithmetic unit of the oxAI chip 120 can be configured with a small number of elements and wires, which is advantageous for integration. Since the number of parallel processes can be increased by integrating the arithmetic circuit, the oxAI chip 120 has a possibility of realizing an arithmetic performance equal to or higher than that of a commercially available GPU chip.

For example, if 3GHz the operating frequency of the commercial GPU chip, the number of parallel processes of multiplying 10 ^3, operation performance of the GPU chip is ^{3 × 10 12 OPS (Operations Per} Second) = 3Tera OPS (TOPS). For example, the oxAI chip 120 can be provided with about 10 ^{6 to} 10 ⁸ arithmetic circuits, and the number of parallel processing of multiplication can be 10 ^{6 to} 10 ⁸ . In this case, even if the operating frequency of oxAI is reduced to 3 MHz or 30 MHz, the computing performance of the oxAI chip 120 is comparable to that of the GPU. Reducing the operating frequency is very effective for reducing the dynamic power consumption of the IC chip.

In addition, the GPU chip is driven at a high frequency in order to perform large-scale calculation processing such as AI calculation. Therefore, large power is consumed and the temperature becomes high. Since the oxAI chip 120 can reduce the operating frequency, heat generation of the oxAI chip 120 can be suppressed. Therefore, in the semiconductor device 100, the heat dissipation mechanism of the oxAI chip 120 can be made simpler than that of the GPU chip.

As described above, the GPU chip has a trade-off relationship between the improvement of calculation performance, power saving, and heat generation suppression. On the other hand, the oxAI chip 120 can reduce the deterioration of the calculation performance even if the operating frequency is reduced. Therefore, the oxAI chip 120 can execute large-scale arithmetic processing with high efficiency with respect to time and power.

<< Evaluation Board >>
For example, the semiconductor device 100 can be used as an evaluation board. 4A and 4B are schematic perspective views of configuration examples of the evaluation board.

As shown in FIG. 4A, various electronic components are incorporated in the board 210 of the evaluation board 200. 4A includes an oxAI chip 220, memory chips 231, 232, FPGA chips 235, 236, a PCIe connector 240, a USB connector 242, an HDMI input (RX) connector 244, and an HDMI output (TX) connector 245.

The FPGA chip 236 includes a memory device. Instead of the HDMI input connector 244 and the HDMI output connector 245, an eDP input connector and an eDP output connector may be provided.

The oxAI chip 220 is detachable from the board 210 using a connector (not shown). For example, the oxAI chip 222 or the GPU chip 225 of another architecture can be replaced. Using the evaluation board 200, it is possible to check the performance and functions of a plurality of types of chips having an AI processing function.

In the evaluation board 202 shown in FIG. 4B, the oxAI chip is mounted on a dedicated board 212. The board 210 is provided with connectors 250A and 250B, and the board 212 is provided with connectors 252A and 252B. Connectors 250A and 250B are connected to connectors 250A and 250B, respectively.

<< Electronic equipment >>
Here, an electronic device incorporating an oxAI chip will be described.

15A and 15B show an example of the computer 7000. As illustrated in FIG. 15A, the computer 7000 includes a housing 7010, a monitor unit 7012, a keyboard 7013, and a port 7015. A keyboard 7013 and a port 7015 are provided in the housing 7010. Examples of the port 7015 include a USB port, a LAN port, and an HDMI port.

The monitor portion 7012 is attached to the housing 7010 so that it can be opened and closed. FIG. 15A shows a state where the monitor unit 7012 is open, and FIG. 15B shows a state where the monitor unit 7012 is closed. For example, the maximum opening angle of the monitor unit 7012 is about 135 °.

As shown in FIG. 15B, the housing 7010 is provided with a cover 7011 that can be opened and closed. A plurality of semiconductor devices 100 are detachably incorporated in the housing 7010. A device for cooling the semiconductor device 100 or a device for radiating heat may be provided in the housing 7010. Since the cover 7011 can be opened and the semiconductor device 100 can be replaced, the expandability of the computer 7000 is high. By incorporating a plurality of oxAI chips into the computer 7000, various AI processes can be performed at high speed.

A large number of semiconductor devices 100 can be used to construct a computing system that performs large-scale parallel operations such as a large parallel computer, a supercomputer, and a server. FIG. 16A shows an example of a supercomputer 7200. The super computer 720 has a plurality of racks 7210. A plurality of rack mount computers 7220 are stored in each of the plurality of racks 7210. As shown in FIG. 16B, the computer 7220 includes a motherboard 7224 and a PC card 7225. The semiconductor device 100 is applied to the PC card 7225. Thereby, the supercomputer 720 with low power consumption can be provided. Since the heat generation of the computer 7220 is suppressed, the power of the cooling facility of the supercomputer 7200 can be reduced.

As shown in FIG. 17, the semiconductor device 100 can be incorporated into various electronic devices (for example, a PC 7500, game machines 7520 and 7530, a navigation system 7540, and a TV (television receiver) device 7550).

The PC 7500 is a stationary type. A keyboard 7502 and a monitor device 7503 are connected to the PC 7500 wirelessly or by wire. The semiconductor device 100 can also be incorporated into a computer such as a notebook PC or a tablet terminal.

Game machine 7520 is an example of a stationary game machine. A controller 7522 is connected to the game machine 7520 wirelessly or by wire. The game machine 7530 is an example of a portable game machine. Since the semiconductor device 100 is incorporated in the game machine 7520, for example, the game machine 7520 can develop a game so as to entertain the user by using AI. The same applies to the game machine 7530. The controller 7522 can be connected to the PC 7500 so that the PC 7500 can be used as a gaming PC.

FIG. 17 shows an example in which a navigation system 7540 is incorporated in a control panel of an automobile. Since the semiconductor device 100 is incorporated, in the navigation system 7540, it is possible to predict a traffic jam by AI and set a route to be guided, and to perform voice conversation by AI.

For example, the semiconductor device 100 incorporated in the TV device 7550 can function as an image engine using an AI algorithm. The semiconductor device 100 performs image processing such as noise removal and resolution up-conversion.

[Embodiment 2]
In this embodiment, a specific configuration example of the oxAI chip will be described.

<< Analog oxAI chip >>
Here, the oxAI chip 400 capable of massively parallel computing using analog operations will be described. The oxAI chip 400 is very advantageous for a fully connected neural network (FCNN). In order to facilitate understanding of the configuration example and the operation method example of the oxAI chip 400, it is assumed that the FCNN shown in FIG. The FCNN shown in FIG. 5 has one hidden layer. The numbers of units in the input layer, hidden layer, and output layer are 1024, 128, and 32, respectively. ReLU (Rectified Liner Unit) is used for the activation function. The FCNN of the oxAI chip 400 is applied to handwritten character recognition and general-purpose AI, for example.

FIG. 6 is a functional block diagram illustrating a configuration example of the oxAI chip 400. The oxAI chip 400 shown in FIG. 6 includes a receiver (RX) 401, digital-analog converters (DAC) 403 and 404, product-sum operation circuit (MAC) arrays 405 and 406, a gate driver 407, and a digital-analog converter (DAC) 408. , A transmitter (TX) 409.

The data transmission method of the oxAI chip 400 is a differential transmission method. For example, an LVDS (Low Voltage Differential Signaling) receiver is used as the receiver 401, and an LVDS transmitter is used as the transmitter 409.

The reset signal rest_n resets the oxAI chip 400.

Data in_w [7: 0] is learned data. For example, an 8-bit digital signal representing a weighting factor. In accordance with the enable signal en_la_w and the clock signal dclk_w, the DAC 404 converts the data in_w [7: 0] into analog data. The gate driver 407 controls the writing of analog data to the MAC arrays 405 and 406. The gate driver 407 receives the clock signal gclk, the pulse width control signal gpwc, and the start pulse signal gsp.

Data processed by the oxAI chip 400 is 8-bit digital data, and is input by a differential transmission method. For example, a LVDS (Low Voltage Differential Signaling) receiver is used as the receiver 401. The receiver 401 converts the input data rx_dp [7: 0] and rx_dn [7: 0] into single-ended 8-bit data in accordance with the differential clock signals rx_clp and rx_cln. The DAC 403 converts this 8-bit data into analog data. Analog data output from the DAC 404 is sequentially written to the MAC array 405.

<MAC arrays 405 and 406>
A circuit configuration example of the MAC array 405 will be described with reference to FIG. The MAC array 405 is provided with multiplication circuits 40 in a matrix of 1024 rows and 144 columns. The multiplier circuit 40 has the same circuit configuration as the ox memory circuit 12 in FIG. 2B. That is, the multiplier circuit 40 has both functions of an arithmetic circuit and a nonvolatile local memory circuit that stores weighting coefficients. As a result, the oxAI chip 400 can realize a massively parallel operation with a very small number of transistors compared to the GPU. Reduction of the number of transistors leads to downsizing of the oxAI chip 400 and reduction of power consumption.

The MAC array 405 is provided with a gate line GL1 and data lines VX1, WD1, and RD1 in accordance with the arrangement of the multiplication circuits 40. The data line WD1 is a wiring for inputting weight coefficient data to the multiplication circuit 40. Analog data is input from the DAC 403 to the data line WD1. The gate line GL1 is a signal line for selecting the multiplication circuit 40 to which weight coefficient data is input. The gate line GL1 is driven by the gate driver 407.

By writing the weight coefficient data w0 into the multiplier circuit 40, the voltage of the holding node (the gate of the read transistor) of the multiplier circuit 40 becomes the voltage Vw0 corresponding to the weight coefficient data.

The data line VX1 is an input wiring for data processed by the CFNN. Analog data is input from the DAC 402 to the data line VX1. The operation result of the multiplication circuit 40 is read out to the data line RD1. A current source 42 and an offset circuit 43 are electrically connected to the data line RD1.

The current I0 flowing through the multiplier circuit 40 is proportional to the product of the voltage Vx0 of the holding node and the voltage Vx0 of the data line RD1. That is, the current I0 represents the product of the weight coefficient and the input data. Similarly, the current I1 is proportional to the product of the holding node voltage Vw1 and the voltage Vx1. That is, the multiplication circuit 40 can calculate the product of the weight coefficient data and the input data.

1024 multiplication circuits 40 are electrically connected per data line RD1. The current source 42 generates a reference current Iref. The current Iout input to the offset circuit 43 is the difference between the reference current Iref and the current Imac. The current Imac is the sum of the currents flowing through the 1024 multiplication circuits 40, and represents the product sum of the weighting coefficient and the input data. By taking the difference between the reference currents Iref and Imac, the noise component of the current Iout can be reduced.

The offset circuit 43 converts the current Iout into the voltage Vout, and takes the difference between the reference voltage Vref and the voltage Vout. Thereby, the noise component of the voltage Vout is reduced. The offset circuit 43 amplifies the differential voltage between Vref and Vout and outputs the amplified voltage to the activation function circuit 44. The activation function circuit 44 outputs the processed data to the MAC array 405.

Of the 144 columns of the MAC array 405, 16 columns do not contribute to the generation of the current Iout and hold reference data used for the product-sum operation.

The MAC array 406 has the same configuration as the MAC array 405. Multiplier circuits 40 are arranged in a matrix of 36 rows and 128 columns. In the MAC array 406, four of the 36 rows do not contribute to the generation of the current Iout and are used to hold reference data.

The enable signal en_cm shown in FIG. 6 is an enable signal for the current source 42 of the MAC arrays 405 and 406. The enable signal en_abs is an enable signal for the offset circuit 43 of the MAC arrays 405 and 406, the signals osp1, osn1, and en_res1 are control signals of the offset circuit 43 of the MAC array 405, and the signals osp2, osn2, and en_res2 are MAC arrays. This is a control signal for the offset circuit 43 at 406.

<ADC 408, TX 409>
The ADC 408 receives analog data from the MAC arrays 406 to 32 in parallel. The ADC 408 includes a register at the output stage in order to perform serial / parallel conversion. The ADC 408 outputs one channel of 8-bit digital data.

The signals clk_sar, res_sar, go, and stby_adc are a clock signal, a reset signal, an enable signal, and a standby signal for the ADC 408, respectively. The signals dclk_p2s, en_p2s_per, and en_p2s_ser are a register clock signal, a latch signal, and an output enable signal, respectively. The ADC 408 receives 32 analog data and outputs 8-bit digital data to the transmitter 409. The signal stby_tx is a standby signal for the transmitter 409.

The transmitter 409 converts the 8-bit digital data into differential format data tx_dp [7: 0] and tx_dn [7: 0] according to the signal dclk_p2s, outputs the data, and outputs the signal dclk_p2s to the differential format clock signals tx_clp and tx_cln. And output. The difference data tx_dp [7: 0] and tx_dn [7: 0] are 32 types of inference data acquired by the FCNN.

Since the input and output data of the MAC arrays 405 and 406 are analog data, the number of wires of the MAC arrays 405 and 406 can be greatly reduced as compared with the case where the input / output data is digital data. Since the multiplication circuit 40 has both a multiplication function and a weight coefficient data holding function, data is not read at the time of calculation. That is, the multiplication circuit 40 has substantially no data transmission time penalty and power penalty.

A GPU is known as a processor having a parallel processing architecture. Similarly to the CPU, data exchange between the calculation unit and the memory unit is a bottleneck of calculation efficiency in the GPU. On the other hand, the oxAI chip 400 does not have such a problem.

The multiplier circuit 40 has the same circuit configuration as the 2T gain cell, and can perform analog data multiplication with a small number of transistors. Therefore, by configuring the product-sum operation unit using a large number of multiplication circuits 40, it is possible to provide the oxAI chip 400 that can perform the massively parallel operation processing with low power consumption. For example, when the number of multiplication circuits 40 is about 10 ^{6 to} 10 ⁸ and the operation frequency is 3 MHz or 30 MHz, the calculation performance of the oxAI chip 400 is about 3 TOPS (Tele Operations Per Second) to 3 POPS (Peta OPS). is there.

<< Programmable oxAI chip >>
The oxAI chip 450 shown here can constitute a programmable NN. The data format calculated by the oxAI chip 450 is digital. The arithmetic circuit of the oxAI chip 450 has a dedicated non-volatile local memory circuit, and the non-volatile local memory is composed of an ox memory circuit. The NN of the oxAI chip 450 can be used as, for example, various image processing (for example, noise removal and high resolution), object recognition, and general-purpose AI.

FIG. 8 is a functional block diagram illustrating a configuration example of the oxAI chip 450. The oxAI chip 450 includes a controller 460, an I2C module 462, a receiver (RX) 463, a transmitter (TX) 464, a data driver 466, and a word driver 467. The controller 460 includes an arithmetic circuit array 470, an arithmetic unit 471, an SRAM 472, selectors 474 and 475, and a demultiplexer 476.

The input data of the oxAI chip 450 includes operation setting data, learned data, pipeline structure data, and data processed by the arithmetic circuit array 470. The learned data and pipeline structure data are input to the oxAI chip 450 as configuration data of the controller 460.

Data sda is operation setting data in a serial format, and is written in the I2C module 462. The I2C module 462 outputs the written operation setting data to the controller 460. Signals i2c_clk, i2c_resetb, and scl are an I2C controller clock signal, an I2C reset signal, and an I2C clock signal, respectively. The signals O_SAVE, O_LOAD, and OS_USE are used for backup control of operation setting data.

The data DATA0 is input to the data driver 466. Data DATA0 is configuration data. The data driver 466 outputs a signal nSTATUS. The signal nSTATUS is a signal indicating a configuration state.

As a data transmission method to the oxAI chip 450, a single end method and an LVDS method can be used. Data din [7: 0] is single-ended input data and is input to the selector 474. The receiver 463 has the same configuration as that of the receiver of the oxAI chip 400, and the differential input data rx_dp [7: 0] and rx_dn [7: 0] are converted into single-ended data rx_ds [according to the differential clock signals rx_clp and rx_cln. 7: 0] and output to the selector 474. Signals stby_rx and hpe_rx are standby signals for the receiver 463, respectively.

The signals nCONFIG and DCLK are input to the controller 460, and the controller 460 outputs the signal CONF_DONE. Signals nCONFIG and DCLK are a configuration start signal and a configuration clock signal, respectively. The signal CONF_DONE is a signal indicating that the configuration is completed.

Signals sys_clk, sys_resetb, user_resetb, context_ex [5: 0] are a system clock signal, a system reset signal, a user reset signal, and an external context signal. The signal data_en is a signal that sets a period for executing transmission of input data to the controller 460. These signals are input to the controller 460. The controller 460 outputs signals State [2: 0] and sabbstate [2: 0]. Signals State [2: 0] and sabbstate [2: 0] represent the internal state and sub-state of controller 460, respectively.

The output data of the selector 475 is input to the arithmetic circuit array 470. The arithmetic circuit array 470 outputs the processed data to the arithmetic unit 471. The output data of the calculation unit 471 is temporarily stored in the SRAM 472. Data read from the SRAM 472 is output to the selector 475 and the demultiplexer 476. The selector 475 outputs either the output data of the selector 474 or the output data of the SRAM 473 to the arithmetic circuit array 470.

The demultiplexer 476 has a function of selecting an output format of data. One output data of the demultiplexer 476 is output to the outside of the oxAI chip 450 as single-ended data dout [7: 0]. The other output data is processed by the transmitter 464, converted into differential data tx_dp [7: 0], tx_dn [7: 0], and output to the outside of the oxAI chip 450.

<Arithmetic circuit array 470>
The arithmetic circuit array 470 will be described with reference to FIGS. As shown in FIG. 9, the arithmetic circuit array 470 includes a plurality of arithmetic circuits 21 and a plurality of switch circuits 22 arranged in a matrix. The arithmetic circuit 21 and the switch circuit 22 are programmable circuits. The arithmetic circuit 21 is configured according to the processing contents of the arithmetic circuit array 470. By changing the circuit configuration of the switch circuit 22 in accordance with the processing contents of the arithmetic circuit array 470, the connection relationship of the arithmetic circuits 21 is changed.

Note that “U”, “D,“ L ”, and“ R ”in FIG. 9 are the names of the wirings of the switch circuit 22 and represent the connection directions (up, down, left, and right).

FIG. 10 shows a configuration example of the arithmetic circuit 21. The arithmetic circuit 21 includes an input register 51, a memory circuit 52, a multiplier circuit 53, an adder circuit 54, output registers 55A and 55B, selectors 56A to 56D, and memory circuits 57A to 57C. The memory circuits 52 and 57A to 57C are nonvolatile local memory circuits of the arithmetic circuit 21, and ox memory circuits are applied.

Data sin is input to the input register 51. The input register 51 holds data sin under the control of the latch signal slat. The input register 51 outputs the retained data as data sout to the selector 56A. In accordance with the output signal of the memory circuit 57A, the selector 56A selects either the data sin or the data sout, and outputs the selected data to the multiplication circuit 53. The data sout is output to the outside of the arithmetic circuit 21. By providing the input register 51, the data sin can be temporarily stored in the input register 51, so that the data sout obtained by shifting the data sin can be output.

  The memory circuit 52 is input with a context signal context_W [1: 0]. The context signal context_W [1: 0] is an internal signal generated by decoding the signal context_ex [5: 0]. The memory circuit 52 stores a plurality of weight coefficient data. The weight coefficient data is written in the memory circuit 52 as configuration data. Configuration data is transmitted from the data driver 446.

As illustrated in FIG. 11A, the memory circuit 52 includes a flip-flop 71, a decoder 72, memory cells 73_0 to 73_3, a transistor 77, and a latch circuit 78. The memory cells 73_0 to 73_3 have the same circuit configuration as the ox memory circuit 13 (see FIG. 2C) and are gain cells including three ox transistors.

Signals word 0 to word 3 are generated by the word driver 67. One memory cell is selected by signals word0 to word3, and configuration data is written to the selected memory cell.

The flip-flop 71 holds the context signal context_W [1: 0]. The decoder 72 decodes the context signal context_W [1: 0] to generate and output the switching signals context_W0 to context_W3. It has a function. The switching signals context_W0 to context_W3 have a function of selecting a memory cell that outputs weight coefficient data. The weight data read from the selected memory cell is output to the multiplication circuit 53 as data cmout. The transistor 77 has a function of precharging a wiring from which data cmout is read to the voltage Vpre. In accordance with the signal prch, the transistor 77 precharges the wiring.

FIG. 11B shows another configuration example of the memory cell. A memory cell 74 illustrated in FIG. 11B is a modified example of the memory cell 73_0, and a latch circuit including two inverter circuits is provided at the gate of the read transistor. For example, these inverter circuits are CMOS circuits composed of an n-channel Si transistor and a p-channel Si transistor.

FIG. 12 shows a configuration example of the memory circuit 57A. The memory circuit 57A includes memory cells 91_0 and 91_1 and transistors 92_0, 92_1, and 93. Configuration data, switching signals context_A0 and context_A1, and signals wordA0, wordB0, wordA1 and wordB1 are input to the memory circuit 57A.

Each of the memory cells 91_0 and 91_1 includes two ox memory circuits 12 (FIG. 2B). When the configuration data “1” is written to the memory cell 91_0, the signal wordA0 is set to “H”, and the signals wordB0, wordA1, and wordB1 are set to “L”. When the configuration data “0” is written to the memory cell 91_1, the signal wordB0 is set to “H”, and the signals wordA0, wordA1, and wordB1 are set to “L”.

While the control signal is sent to the selector 56A, the transistor 93 is in the off state. One of the transistors 92_0 and 92_1 is turned on by the switching signals context_A0 and context_A1. For example, when the transistor 92_0 is turned on, a logic control signal corresponding to the data held in the memory cell 91_0 is output to the selector 56A.

The memory circuits 57B and 57C have the same circuit configuration as the memory circuit 57A.

The multiplication circuit 53 calculates the product of the data sdata and the data cmout, and generates data mout representing the calculation result. Data mout is output to addition circuit 54 and selector 56B.

Data ain is output data of another arithmetic circuit 21 or output data of the selector 475. The adder circuit 54 calculates the sum of the data ain and the data mout and generates data aout representing the calculation result. Data aout is output to selector 56B.

The output register 55A holds the output data of the selector 56B, and the output register 55B holds the output data of the selector 56C. By providing the output registers 55A and 55B, it is possible to prevent calculation errors due to signal delay. The signal res_rg is a reset signal for the output registers 55A and 55B.

The output register 55A outputs the retained data to the selector 56D. The output data of the selector 56D or the output register 55B is output from the arithmetic circuit 21 as data sout.

Since the arithmetic circuit array 470 has the arithmetic circuits 21 arranged in a matrix, the arithmetic circuit array can function as a product-sum arithmetic device.

Output data of the arithmetic circuit array 470 is input to the arithmetic unit 471. For example, the calculation unit 471 has an activation function function and / or a pooling layer function.

<Configuration of Switch Circuit 22>
The switch circuit 22 will be described with reference to FIGS. 13A and 13B. As shown in FIG. 13A, the switch circuit 22 is provided with eight switch circuits 25. The output wiring 26S for the data sout is electrically connected to any one of the wirings U, D, L, and R. The same applies to the output wiring 26A for the data acout.

As illustrated in FIG. 13B, the switch circuit 25 includes a flip-flop 80, a decoder 81, memory cells 83_0 and 83_1, and a wiring 87. The wiring 87 is any one of the wirings L, R, U, and D. FIG. 13B shows a switch circuit 25 for transmitting 4-bit data.

The flip-flop 80 holds the context signal context_C. The decoder 72 decodes the context signal context_C and generates switching signals context_C0 and context_C1. Signals context_C0 and word0 are input to the memory cell 83_0, and signals context_C0 and word1 are input to the memory cell 83_1.

The write transistor of the memory cell 83_0 is an ox transistor having a back gate. In the memory cell 83_0, the n-channel transistor having no back gate is a Si transistor. Note that all the transistors of the memory cell 83_0 may be ox transistors. The memory cell 83_1 is also imposing.

Configuration data is written to the memory cell 83_0 by turning on the writing transistor with the signal word0. When the memory cell 83_0 is selected by the switching signal context_C0, the connection state between the wiring 87 and the arithmetic circuit 21 is determined in accordance with the configuration data held in the memory cell 83_0.

Since the arithmetic circuit 21 and the switch circuit 22 incorporate a nonvolatile local memory circuit, the circuits 21 and 22 do not need to access a memory device outside the oxAI chip 450 during the operation. Therefore, similarly to the oxAI chip 400, the oxAI chip 450 does not cause a calculation efficiency bottleneck to exchange data between the arithmetic unit and the memory unit. Since data exchange and arithmetic processing are sequentially performed between the arithmetic circuits 21, arithmetic can be performed with high efficiency.

Since the arithmetic circuit 21 and the switch circuit 22 are multi-context programmable circuits, it is possible to efficiently execute massively parallel arithmetic processing with few hardware resources. Various NNs can be realized by the hardware of the oxAI chip 450. For example, the convolution NN as shown in FIG. 14 can be realized by a hard wafer of the oxAI chip 450. The numerical values in FIG. 14 represent the layer size and depth (number of channels). For example, the input layer width W, height H, and number of channels M are 38, 24, and 1, respectively. The size of the input layer filter W × H × M is 3 × 3 × 1.

11, 12, 13, 14: ox memory circuit,
100: Semiconductor device 110: Data bus 112: I / O (input / output) interface 114: Memory unit 115: FPGA chip 120: oxAI chip
121A, 121B, 121C: circuit unit, 150: peripheral device,
200, 202: Evaluation board, 202: Evaluation board, 210, 212: Board,
220, 222: oxAI chip, 225: GPU chip, 231, 232: Memory chip, 235, 236: FPGA chip, 240: PCIe connector, 242: USB connector, 244: HDMI input connector, 244: HDMI input connector, 245: HDMI output connector,
250A, 250B, 252A, 252B: Connector

Claims (7)

A first processor chip;
A memory section;
A data bus, and
Each of the first processor chip and the memory unit is electrically connected to the data bus;
The first processor chip has an arithmetic circuit array for performing artificial intelligence operations,
The arithmetic circuit array has a plurality of arithmetic circuits,
The arithmetic circuit has a first transistor, a second transistor, a capacitor, and a holding node,
The channel formation region of the first transistor has a metal oxide,
The first transistor has a function of controlling data writing to the holding node,
A gate of the second transistor is electrically connected to the holding node;
The semiconductor device is characterized in that the capacitor is electrically connected to the holding node. In claim 1,
The holding node is a semiconductor device to which analog data is written. A first processor chip;
A memory section;
A data bus, and
The first processor chip and the memory unit are each electrically connected to the data bus,
The first processor chip has an arithmetic circuit array for performing artificial intelligence operations,
The arithmetic circuit array has a plurality of arithmetic circuits,
The arithmetic circuit has a plurality of memory circuits,
Each of the plurality of memory circuits includes a plurality of memory cells;
Each of the plurality of memory cells includes a holding node and a transistor that controls writing of data to the holding node.
The channel formation region of the transistor includes a metal oxide. In claim 3,
The holding node is a semiconductor device to which digital data is written. In any one of Claims 1 thru | or 4,
Further, a two-processor chip having an FPGA is provided.   An evaluation board comprising the semiconductor device according to claim 1.   An electronic apparatus comprising the semiconductor device according to claim 1.

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