JP2019012231A - Image forming apparatus and control method - Google Patents

Abstract

To provide an image forming apparatus that can prevent the occurrence of overshoot of a grid voltage while reducing start-up time.SOLUTION: An ASIC 61 of a printer 1 executes processing of controlling a charge voltage generation circuit 70 on the basis of a grid current Ig detected by a grid current detection circuit 82 to adjust the current value of a line current Ir1 (grid current) to a target current value It1, and processing of controlling a grid voltage adjustment circuit 81 to adjust the voltage value of a divided voltage detection signal Sid (grid voltage) to target voltage values Vt1 to Vt3. After starting the operations of the charge voltage generation circuit 70 and grid voltage adjustment circuit 81, the ASIC 61 starts the processing of adjusting the current value of the grid current to the target current value It1 before starting the processing of adjusting the voltage value of the grid voltage to the target voltage values Vt1 to Vt3.SELECTED DRAWING: Figure 3

Description

  The technique disclosed in the present invention is a technique related to power supply to a charger that charges a photosensitive member included in an image forming apparatus.

  Conventionally, for example, there is an image forming apparatus including a plurality of chargers that charge each of a plurality of photosensitive members corresponding to each color (for example, Patent Document 1). Each charger is provided with a charging wire and a grid. By applying a voltage between the charging wire and the grid, a corona discharge is generated between the charging wire and the photosensitive member, and the surface of the photosensitive member is made uniform. Charge positively. The image forming apparatus disclosed in Patent Document 1 supplies a high charging voltage from one charging voltage generation circuit to charging wires of a plurality of chargers. The image forming apparatus controls the charging voltage supplied from the charging voltage generation circuit to each charging wire based on the current value of the grid current generated in the grid. The image forming apparatus also includes a grid voltage adjustment circuit that controls the grid voltage generated in each of the plurality of grids to a constant voltage value. The grid voltage adjustment circuit changes the voltage between the collector and the emitter of the transistor connected to the grid and controls the grid voltage to a constant value.

JP 2014-235229 A

  In the above-described image forming apparatus, for example, if the charging voltage generation circuit and the grid voltage adjustment circuit are activated at the same time in order to shorten the activation time, the grid voltage may increase excessively. More specifically, the charging voltage generation circuit changes the charging voltage so that the current value of the grid current becomes the target current value. On the other hand, the grid voltage adjustment circuit controls the base current of the transistor in order to increase the voltage value of the grid voltage to the target voltage value when the operation starts. Thereby, when the current value of the grid current referred to in the control of the charging voltage generation circuit is lower than the target current value, the charging voltage generation circuit increases the charging voltage in accordance with the reduction of the grid current. As a result, so-called overshoot may occur in which the grid voltage exceeds the target voltage value.

  The present application has been proposed in view of the above-described problems, and an object thereof is to provide an image forming apparatus and a control method capable of suppressing the occurrence of grid voltage overshoot while reducing the startup time.

  An image forming apparatus made to solve the above problems includes a photosensitive member, a charging wire and a grid, and a charger for charging the photosensitive member, and a voltage applied to the charging wire of the charging device connected to the charger. A charging voltage generation circuit that generates a charging voltage, a grid voltage adjustment circuit that adjusts a grid voltage that is applied to the grid, a grid current detection circuit that detects a grid current that is a current flowing through the grid, and a control The control device controls the charging voltage generation circuit based on the grid current detected by the grid current detection circuit and adjusts the current value of the grid current to the target current value, and controls the grid voltage adjustment circuit. And adjusting the voltage value of the grid voltage to the target voltage value, and starting the operation of the charging voltage generation circuit and the grid voltage adjustment circuit. To, after starting the process of adjusting the current value of the grid current to the target current value, starts the process of adjusting the voltage value of the grid voltage to the target voltage value.

  The present invention can be realized not only in the form of an image forming apparatus but also in the form of a control method for the image forming apparatus, for example.

  According to the image forming apparatus and the like described in the present application, the occurrence of grid voltage overshoot can be suppressed while shortening the startup time.

It is sectional drawing which shows schematic structure of the color laser printer of 1st embodiment. FIG. 2 is a schematic block diagram relating to a high-voltage power supply device for a printer. It is a timing chart of PWM signal Sp1 etc. at the time of the operation start in a first embodiment. It is a timing chart of PWM signal Sp1 etc. at the time of the operation start in a second embodiment. It is a timing chart of PWM signal Sp1 etc. at the time of the operation start in a third embodiment. It is a timing chart of PWM signal Sp1 at the time of the start of operation in a fourth embodiment. It is a timing chart of PWM signal Sp1 etc. at the time of the operation start in a fifth embodiment. It is a timing chart of PWM signal Sp1 at the time of the operation start in a comparative example.

(First embodiment)
Hereinafter, a first embodiment of the present application will be described with reference to the drawings. A laser printer 1 that is a first embodiment of the image forming apparatus according to the present invention shown in FIG. 1 is a color laser printer that forms a color image on a sheet P or the like by an electrophotographic method, and is a so-called tandem method using four color toners. This is a laser printer. In the following description, as shown in FIG. 1, the right side of the drawing is defined as the front side of the laser printer 1, and the left side of the drawing is defined as the rear side. Hereinafter, the laser printer 1 is simply referred to as the printer 1. 1 is defined as a left side when the front side of the printer 1 is viewed from the front side of the printer 1, and a rear side of the page is defined as a right side. 1 is defined as the upper side of the printer 1 and the lower side of the page is defined as the lower side.

  As shown in FIG. 1, the printer 1 has a substantially box-shaped main body housing 2, and a paper feeding unit 10, an image forming unit 20, and the like are housed inside the main body housing 2. A discharge tray 5 is provided on the upper surface of the main body housing 2 to store the sheets P on which images are formed in a stacked state. The paper feed unit 10 includes a paper feed tray 11 in which the paper P is accommodated and various rollers, and drives the various rollers to feed the paper P to the image forming unit 20. The paper feed tray 11 is configured to be detachable from the lower portion of the main body housing 2.

  The image forming unit 20 includes a transport unit 21, four process cartridges 30C, 30M, 30Y, and 30K, an exposure unit 35, and a fixing unit 50. The transport unit 21 is provided between the paper feed unit 10 and the process cartridge 30C in the vertical direction, and includes a transport belt 23, four transfer rollers 25, and the like. The conveying belt 23 is an endless belt configured by making the belt into an annular shape, and is wound around a driving roller 27 positioned below the rear end side of the image forming unit 20 and a driven roller 29 positioned below the front end side. The upper surface of the conveyor belt 23 extends substantially horizontally just below the process cartridge 30C and the like, and comes into contact with the back surface of the paper P supplied from the paper supply unit 10. The driving roller 27 rotates the transport belt 23 in a predetermined direction. Further, the transport belt 23 is negatively charged by applying a transfer bias to each transfer roller 25, and the sheet P is sucked to the upper surface by electrostatic force, while the sucked sheet P is discharged along the transport path R to the discharge tray. Convey toward 5

  Each of the process cartridges 30C, 30M, 30Y, and 30K corresponds to four colors of cyan (C), magenta (M), yellow (Y), and black (K). Each of the process cartridges 30C and the like accommodates toner of corresponding colors (C, M, Y, K). The four process cartridges 30C and the like are provided in the order of process cartridges 30K, 30Y, 30M, and 30C from the front to the rear of the printer 1.

  The process cartridge 30C includes a drum-shaped photoconductor 31, a charger 41, a toner cartridge 33, and the like. The other process cartridges 30M, 30Y, and 30K have different toner colors, but other configurations are the same as those of the process cartridge 30C. For this reason, in the following description, the process cartridge 30C will be described as a representative, and description of the other process cartridges 30M, 30Y, and 30K will be omitted as appropriate.

  The photoconductor 31 is positioned above the transfer roller 25 and sandwiches the transport belt 23 between the transfer roller 25 and the vertical direction. The charger 41 is, for example, a scorotron type charger in which a charging wire 42 and a grid 43 are accommodated in a shield case 45. The charging wire 42 is made of metal, for example, gold-plated tungsten or tungsten alone. The shield case 45 is formed in a substantially rectangular tube shape that is elongated along the left-right direction. An opening is formed in the portion of the shield case 45 facing the photoreceptor 31. The grid 43 is configured by stretching a conductive wire in a mesh shape at the opening of the shield case 45. Further, the charging wire 42 is stretched along the left-right direction in the shield case 45, and is arranged at an upper position on the rear side with respect to the photoconductor 31 with a gap. Therefore, the grid 43 is disposed between the photoreceptor 31 and the charging wire 42.

  The charger 41 uniformly positively charges the surface of the photoreceptor 31 during image formation. Specifically, when a voltage is applied to the charging wire 42 and the grid 43, an electric field is formed between the charging wire 42 and the photoreceptor 31, and corona discharge is generated. When an electric field is formed between the charging wire 42 and the grid 43, a voltage different from that of the charging wire 42 is applied to the grid 43, whereby the electric field strength is controlled and the charge amount of the photoreceptor 31 is increased. Be controlled.

  The exposure unit 35 is provided on the uppermost part inside the main body housing 2 and forms an electrostatic latent image based on image data on the surface of each charged photoconductor 31. The toner cartridge 33 supplies toner to the surface of the photoreceptor 31 by carrying the toner contained on the surface of the developing roller 47. The photoreceptor 31 is formed with a toner image by supplying toner to the electrostatic latent image formed on the surface. The transport unit 21 transfers the toner image developed on the surface of the photosensitive member 31 to the paper P by applying a transfer bias to the transfer roller 25 while transporting the paper P toward the fixing unit 50.

  The fixing unit 50 is provided on the downstream side of the transport path R compared to the transport unit 21. The fixing unit 50 includes a heating roller 51 and a pressure roller 52. The heating roller 51 is disposed on the image forming surface side of the paper P, rotates in synchronization with the transport belt 23 and the like, and transports the paper P while heating the toner transferred onto the paper P. The pressure roller 52 sandwiches the paper P between itself and the heating roller 51 and rotates following the paper P while pressing the paper P toward the heating roller 51. Accordingly, the fixing unit 50 conveys the sheet P along the conveyance path R while heating and melting the toner transferred to the sheet P to fix the toner P on the sheet P.

  Next, an electrical configuration related to the present application of the printer 1 will be described with reference to FIG. FIG. 2 shows a schematic block diagram of a high-voltage power supply device 60 mounted on a circuit board (not shown) built in the printer 1 and a connection configuration related to the high-voltage power supply device 60. In the following description, when each component is distinguished for each color, the reference numerals of each part are suffixed with Y (yellow), M (magenta), C (cyan), K (black), or “1”. -4 "(for example, grid voltages GRID1 to GRID4) are added, and if not distinguished, the subscripts are omitted (for example, indicated as grid voltage GRID).

  The high-voltage power supply device 60 includes an ASIC (application specific IC) 61, a high-voltage power supply circuit 62 connected to the ASIC 61, a ROM 63, and a RAM 64. The ASIC 61 (an example of a control device) controls the entire printer 1 in addition to controlling the high-voltage power supply circuit 62. The ROM 63 is a storage medium that stores various operation programs executed by the ASIC 61. The ROM 63 of the present embodiment stores a program PG for executing a control operation shown in FIG. The RAM 64 stores temporary data in various processes, image data used for printing processes, and the like.

  The high voltage power supply circuit 62 includes a grid voltage adjustment circuit 81 including a charging voltage generation circuit 70 and a grid current detection circuit 82. A power supply line PL is connected to the charging voltage generation circuit 70. Each charger 41 (41K to 41C) is connected in parallel to the power line PL. The charging voltage generation circuit 70 applies the charging voltage CHG to each charger 41 through the power line PL. The grid voltage adjustment circuits 81K to 81C and the grid current detection circuits 82K to 82C are provided corresponding to the chargers 41K to 41C.

  The charging voltage generation circuit 70 includes, for example, a PWM signal control circuit 71, a transformer drive circuit 72, a booster circuit 73, and an output voltage detection circuit 78. The charging voltage generation circuit 70 generates a charging voltage CHG to be applied to the charging wires 42K to 42C of the chargers 41K to 41C. The grid voltages GRID1 to GRID4 applied to the grid 43 are adjusted by the grid voltage adjustment circuits 81K to 81C. The charging voltage CHG is, for example, about 5.5 kV to 7 kV. The grid voltage GRID is about 700V, for example.

  The PWM signal control circuit 71 includes, for example, a resistor and a capacitor (not shown), smoothes a PWM (Pulse Width Modulation) signal Sp1 from the port PWM1 of the ASIC 61, and converts the smoothed PWM signal Sp1 into a transformer drive circuit. 72. For example, the transformer drive circuit 72 supplies the smoothed PWM signal Sp1 supplied from the PWM signal control circuit 71 to a drive transistor (not shown), and supplies an oscillation current to the booster circuit 73.

  The transformer 74 of the booster circuit 73 includes a primary winding 74a, a secondary winding 74b, and an auxiliary winding 74c. The transformer drive circuit 72 supplies an oscillating current from the drive transistor to the primary side winding 74 a of the transformer 74. The transformer 74 changes the voltage value of the output voltage (charging voltage CHG) output from the secondary winding 74b according to the duty ratio of the transmission current. For example, the transformer 74 generates the charging voltage CHG having a larger voltage value as the duty ratio of the PWM signal Sp1 increases. A rectifier diode 75, a smoothing capacitor 76, and an output resistor 77 are connected to the secondary winding 74b. As a result, the booster circuit 73 boosts and rectifies the voltage generated in the primary winding 74a of the transformer 74, and applies it as the charging voltage CHG to the charging wires 42K to 42C of the chargers 41K to 41C.

  The output voltage detection circuit 78 is connected between the auxiliary winding 74 c of the transformer 74 and the ASIC 61. The output voltage detection circuit 78 has, for example, a smoothing circuit and a voltage dividing resistor (not shown). The output voltage detection circuit 78 detects the output voltage v1 generated in the auxiliary winding 74c as the charging voltage CHG is generated. The output voltage detection circuit 78 smoothes and divides the output voltage v1 and supplies it to the port A / D1 of the ASIC 61 as the output voltage detection signal Sv1.

  Each of the grid voltage adjustment circuits 81 includes a voltage detection circuit 83 and an operational amplifier OP1. Since the circuit configurations of the grid voltage adjustment circuits 81K to 81C are the same, in the following description, the grid voltage adjustment circuit 81K corresponding to K (black) color will be described, and the other grid voltage adjustment circuits 81Y to 81Y will be described. A description of 81C will be omitted as appropriate. The voltage detection circuit 83K has two voltage dividing resistors R7 and R8 connected in series. A shunt current Id1 of the grid current Ig1 flowing through the grid 43K flows through the voltage dividing resistors R7 and R8. The voltage detection circuit 83K outputs a detection voltage Vgr1 corresponding to the grid voltage GRID1 applied to the grid 43K from the connection point of the two voltage dividing resistors R7 and R8. The voltage detection circuit 83K supplies the detection voltage Vgr1 to the port A / D2 of the ASIC 61 as the divided voltage detection signal Sid1. The capacitor C3 constitutes an RC filter by being connected in parallel with the voltage dividing resistor R8.

  The operational amplifier OP1 is connected to the port PWM2 of the ASIC 61 via the output resistor R9. The output resistor R9 is grounded to GND via the capacitor C4. The ASIC 61 supplies the PWM signal Spp1 from the port PWM2, and supplies the PWM signal Spp1 to the operational amplifier OP1 via the output resistor R9. Accordingly, the ASIC 61 is configured to be able to change the reference voltage and the like of the operational amplifier OP1. The operational amplifier OP1 may be configured to receive a fixed value PWM signal Spp1 (reference voltage value). In this case, the operational amplifier OP1 may be configured not to be connected to the ASIC 61.

  A smoothing circuit including a voltage dividing resistor R4 and a capacitor C2 is connected to the output terminal of the operational amplifier OP1. A connection point on the grid 43K side (opposite side of the output terminal of the operational amplifier OP1) of the voltage dividing resistor R4 is grounded to GND through a capacitor C2. Further, the base of the transistor Q1 for making the grid voltage GRID1 constant is connected to a connection point on the grid 43K side of the voltage dividing resistor R4. The transistor Q1 is connected to a voltage control line Ln1 connected to a connection point between the voltage dividing resistor R7 and the grid 43K. The transistor Q1 is, for example, an NPN transistor, and has a collector connected to a connection point (voltage control line Ln1) on the grid 43K side and an emitter connected to a grid current detection circuit 82K (resistor R3). The transistor Q1 is not limited to a bipolar transistor, and may be, for example, an FET (Field Effect Transistor).

  The base current of the transistor Q1 is controlled by the output of the operational amplifier OP1. The collector resistance of the transistor Q1 is changed depending on the magnitude of the base current, and functions as a variable resistance. The collector resistance here is a resistance value obtained by dividing the collector-emitter voltage by the collector current. For example, increasing the base current decreases the resistance value, and conversely decreasing the base current increases the resistance value. As a result, the collector-emitter voltage is changed.

  The ASIC 61 performs feedback control based on the detection voltage Vgr1 (divided voltage detection signal Sid1) detected by the voltage detection circuit 83K. The ASIC 61 changes the PWM voltage Spp1, changes the base voltage of the transistor Q1, and changes the grid voltage GRID1. Therefore, the ASIC 61 can change the voltage value of the grid voltage GRID1 to a predetermined target voltage value by changing the duty ratio of the PWM signal Spp1. A capacitor C1 that is charged with the grid voltage GRID is provided between the voltage control line Ln1 and the grid 43K.

  The voltage control line Ln1 is connected to a grid current detection circuit 82K that detects a line current Ir1 corresponding to the grid current Ig1 flowing through the grid 43K. The resistor R3 of the grid current detection circuit 82K is connected between the emitter of the transistor Q1 and GND. The grid current detection circuit 82K supplies the positive terminal voltage of the resistor R3 to the port A / D3 of the ASIC 61 as the line voltage detection signal Sir1.

  The ASIC 61 of the present embodiment controls the voltage value of the charging voltage CHG supplied from the charging voltage generation circuit 70 based on the current value of the grid current Ig. For example, the ASIC 61 controls the charging voltage CHG based on the grid current Ig having the smallest current value among the four grid currents Ig1 to Ig4. For example, the adhesion of toner to the charging wire 42 causes variations in the increase in the current values of the grid currents Ig1 to Ig4. Therefore, the charging voltage CHG is controlled based on the grid current Ig with the smallest increase in current value. As a result, when there are variations in the amount of change in the grid currents Ig1 to Ig4, the current values of all the grid currents Ig1 to Ig4 can be reliably increased by a magnitude greater than the target current value.

  For example, the case where the grid current Ig1 has a minimum current value (current to be controlled) will be described. For example, the ASIC 61 calculates the line current Ir1 (grid current Ig1) from the resistance value of the resistor R3 and the voltage value of the line voltage detection signal Sir1. The ASIC 61 controls the charging voltage generation circuit 70 based on the calculated current value of the grid current Ig1, and matches the current value of the grid current Ig1 with a desired target current value. The ASIC 61 changes the duty ratio of the PWM signal Sp1 output from the port PWM1 to make the current value of the grid current Ig1 coincide with a desired target current value. Thereby, the current values of all the grid currents Ig1 to Ig4 can be reliably increased by a magnitude equal to or larger than the target current value.

  Note that the ASIC 61 may not control the charging voltage generation circuit 70 (charging voltage CHG) based on the minimum grid current Ig. For example, the ASIC 61 may control the charging voltage CHG based on the grid current Ig having the largest current value (maximum value) among the four grid currents Ig1 to Ig4. Alternatively, the ASIC 61 may control the charging voltage CHG based on the average value of the current values of the two grid currents Ig.

(About control operation)
Next, the control operation in the printer 1 when starting the operation of the charging voltage generation circuit 70 and the four grid voltage adjustment circuits 81K to 81C having the above-described configuration will be described. For example, when the ASIC 61 receives a print instruction and activates the charging voltage generation circuit 70 or the like, the ASIC 61 performs a control operation described below. Alternatively, for example, the ASIC 61 performs a control operation described below when the printer 1 is powered on and performs a warm-up operation. In the following description, a case where the grid current Ig1 has a minimum current value (current to be controlled) will be described as in the above example.

  First, the control operation of the comparative example will be described with reference to FIG. FIG. 8 shows a timing chart of the PWM signal Sp1 and the like in the comparative example. The upper part of FIG. 8 shows the output timing of the PWM signals Sp1, Spp1 to Spp3 supplied from the ports PWM1 and PWM2. The rising edges of the waveforms of the PWM signals Sp1, Spp1 to Spp3 indicate the timing of starting supply. The rising height of the PWM signals Sp1, Spp1 to Spp3 indicates the height of the duty ratio. For example, the higher the rising height, the higher the duty ratio.

  Further, waveforms of the charging voltage CHG, the partial pressure detection signal Sid, and the line current Ir are shown below the PWM signals Sp1, Spp1 to Spp3. As described above, the partial pressure detection signal Sid has a correlation that increases and decreases according to the increase and decrease of the grid voltage GRID. When each divided voltage detection signal Sid is matched with the target voltage values Vt1 to Vt3, the grid voltage GRID matches the target voltage value (value corresponding to the target voltage values Vt1 to Vt3). For this reason, in the following description, matching the grid voltage GRID with the target voltage value may be described as matching the grid voltage GRID with the target voltage values Vt1 to Vt3 for convenience of explanation.

  Similarly, the line current Ir has a correlation that increases and decreases according to the increase and decrease of the grid current Ig. When the line current Ir is matched with the target current values It1 to It3, the grid current Ig matches the target current value (value corresponding to the target current values It1 to It3). Therefore, in the following description, matching the grid current Ig with the target current value may be described as matching the grid current Ig with the target current values It1 to It3 for convenience of explanation. 3 to 8 including FIG. 8, the grid voltage (divided voltage detection signal Sid4) and the grid current (line current Ir4) corresponding to the charger 41C are not shown in order to prevent the drawing from becoming complicated. doing.

  First, at time T0 shown in FIG. 8, the ASIC 61 accepts a print instruction. The ASIC 61 starts supplying the PWM signal Sp1 and the PWM signals Spp1 to Spp4 simultaneously in order to start the operation of the charging voltage generation circuit 70 and the four grid voltage adjustment circuits 81 in response to the reception of the print instruction (time T1). . The ASIC 61 controls the charging voltage generation circuit 70 based on the current value of the grid current Ig1 to be controlled, and starts control to make the current value of the grid current Ig1 coincide with the desired target current value It1. The ASIC 61 increases the duty ratio of the PWM signal Sp1 output from the port PWM1. The charging voltage generation circuit 70 increases the charging voltage CHG according to the PWM signal Sp1.

  On the other hand, the grid voltage adjustment circuit 81K increases the divided voltage detection signal Sid1 (detection voltage Vgr1) after a certain delay time T3 has elapsed from the time T1 when the supply of the PWM signal Spp1 is started. This delay time T3 is a delay time generated according to the circuit constants of the circuit elements included in the grid voltage adjustment circuit 81K. The delay time T3 of the present embodiment is, for example, a time from time T1 to time T4, and is set to a time necessary for increasing the line current Ir1 to the target current value It1. The ASIC 61 may change the delay time T3 by controlling the supply timing and duty ratio of the PWM signal Spp1. Similarly, the other grid voltage adjustment circuits 81Y, 81M and 81C increase the divided voltage detection signals Sid2 to Sid4 after a certain delay time T3 has elapsed from the time T1 when the supply of the PWM signals Spp2 to Spp4 is started. .

  During this delay time T3, the transistor Q1 of the grid voltage adjustment circuit 81K is supplied with the high-level base current as a base and is turned on. For this reason, almost all of the grid current Ig1 flowing through the grid 43K flows through the resistor R3 as the line current Ir1. Therefore, the charging voltage CHG increases as the line current Ir1 increases until the current value of the line current Ir1 (grid current Ig1) increases to the target current value It1. At time T4, the line current Ir1 becomes the target current value It1.

  Incidentally, the ASIC 61 of the present embodiment controls the charging voltage CHG based on the grid current Ig1 (line current Ir1) having the smallest increase in current value among the four grid currents Ig1 to Ig4 as described above. Therefore, at time T4, the line current Ir1 becomes the target current value It1, while the other non-control target line currents Ir2 to Ir4 (grid currents Ig2 to Ig4) are the target current values It2 and It3 (for example, The current value is larger than the target current value It1.

  At time T4, since the four grid voltage adjustment circuits 81 have passed the delay time T3 from the time when the supply of the PWM signals Spp1 to Spp4 is started (time T1), the transistor Q1 corresponds to the duty ratio of the PWM signals Spp1 to Spp4. Switching. For example, the ASIC 61 continuously turns off the transistor Q1 in order to increase the divided voltage detection signal Sid (grid voltage GRID). The resistance value of the collector resistance is increased by the off control of the transistor Q1, and the grid current Ig flowing through each grid 43 is likely to flow to the voltage detection circuit 83 side (as the shunt current Id). The shunt current Id flowing through the voltage detection circuit 83 (such as the voltage dividing resistor R7) increases. The divided voltage detection signal Sid (grid voltage GRID) increases as the divided current Id increases.

  On the other hand, since the operation of the four grid voltage adjustment circuits 81 is started simultaneously with the charging voltage generation circuit 70, the line current Ir of each grid voltage adjustment circuit 81 is reduced according to the off period of the transistor Q1, and the target current value It1 ~ 1. The current value is smaller than that of It3. The ASIC 61 increases the charging voltage CHG according to the reduction of the line current Ir1 that is the control target, and tries to increase the line current Ir1 to the target current value It1. As a result, for example, a so-called overshoot in which the divided voltage detection signal Sid exceeds the target voltage values Vt1 to Vt3 occurs near the time T5. That is, overshoot occurs in the grid voltage GRID. Incidentally, the time from time T0 to time T5 is, for example, about 100 ms.

(Control operation of the first embodiment)
On the other hand, in the ASIC 61 of the present embodiment, as shown in FIG. 3, the timing (time T8) for starting the supply of the PWM signals Spp1 to Spp4 is compared with the timing for starting the supply of the PWM signal Sp1 (time T7). Delay. That is, after starting the process of adjusting the current value of the grid current Ig (line current Ir1, etc.) to the target current value It1, the voltage value of the grid voltage GRID (divided voltage detection signal Sid1, etc.) is adjusted to the target voltage value Vt2. By starting the processing, occurrence of overshoot of the grid voltage GRID is suppressed. The ASIC 61 realizes the control operation shown in FIG. 3 by reading the program PG from the ROM 63 and executing it, for example. In the following description, parts similar to those in FIG. 8 described above (time T0 and the like) are denoted by the same reference numerals, and description thereof is omitted as appropriate.

  First, at time T7 shown in FIG. 3, the ASIC 61 starts supplying the PWM signal Sp1 in order to start the operation of only the charging voltage generation circuit 70 in response to acceptance of the print instruction. The ASIC 61 controls the charging voltage generation circuit 70 based on the current value of the grid current Ig1 to be controlled, and starts control to make the current value of the grid current Ig1 coincide with the desired target current value It1. The charging voltage generation circuit 70 increases the charging voltage CHG according to the PWM signal Sp1.

  The transistor Q1 of the grid voltage adjustment circuit 81K is supplied with a high level base current as a base and maintains the on state. Until the current value of the line current Ir1 (grid current Ig1) increases to the target current value It1, the charging voltage CHG increases as the line current Ir1 increases.

  At time T8, the ASIC 61 starts supplying the PWM signals Spp1 to Spp4 in order to start the operation of the grid voltage adjustment circuit 81. The time between the time T7 at which the supply of the PWM signal Sp1 is started and the time T8 at which the supply of the PWM signals Spp1 to Spp4 is started, that is, the delay time T11 for delaying the supply of the PWM signals Spp1 to Spp4 is over the grid voltage GRID. The time is sufficient to suppress the chute, and is determined and set by simulation, for example. At time T8, the line current Ir1 increases to a current value close to the target current value It1. At time T9, the line current Ir1 becomes the target current value It1.

  The grid voltage adjustment circuit 81 switches the transistor Q1 in accordance with the duty ratio of the PWM signals Spp1 to Spp4 at the time T10 when the delay time T3 has elapsed from the time T8 when the supply of the PWM signals Spp1 to Spp4 is started. Increase of the partial pressure detection signal Sid1 (detection voltage Vgr1) is started. The shunt current Id flowing through the voltage detection circuit 83 (such as the voltage dividing resistor R7) increases according to the off period of the transistor Q1. The divided voltage detection signal Sid (grid voltage GRID) increases as the divided current Id increases.

  As shown in FIG. 3, the charging voltage CHG is a constant voltage value and is stable from time T9 to T10. Therefore, the charging voltage generation circuit 70 can stabilize the voltage value and circuit operation of the charging voltage CHG before the grid voltage adjustment circuit 81 starts increasing the divided voltage detection signal Sid (grid voltage adjustment circuit 81). it can. Further, for example, a sufficient charge is accumulated in the capacitor C1 and the like of the grid voltage adjustment circuit 81. Thereby, the reduction of the line current Ir1 corresponding to the off period of the transistor Q1 can be suppressed, and the line current Ir1 can be maintained at the target current value It1. By suppressing the reduction of the line current Ir1, the charging voltage CHG varies in accordance with (follows) the amount of change in the grid voltage GRID (partial voltage detection signal Sid). As a result, overshoot of the grid voltage GRID can be suppressed. In addition, by setting the delay time T11 to the shortest time in which no overshoot occurs, the delay in supplying the PWM signals Spp1 to Spp4 is minimized, and the operation start time of the charging voltage generation circuit 70 and the grid voltage adjustment circuit 81 is shortened. That is, it is possible to shorten the startup time of the printer 1.

  In addition, as described above, after the line current Ir1 becomes the target current value It1 and the charging voltage CHG becomes a constant voltage value and is stabilized, the divided voltage detection signal Sid (grid voltage GRID) is increased, thereby overshooting. Can be suppressed. Therefore, the delay time T11 for delaying the supply of the PWM signals Spp1 to Spp4 can be set according to the timing (time T9) when the current value of the grid current Ig1 (line current Ir1) reaches the target current value It1. For example, the delay time T11 can be set so that the time T9 coincides with the timing at which 1/3 of the entire delay time T3 has elapsed. The ASIC 61 may not delay the timing for supplying the PWM signal Spp according to the delay time T11 preset in the program PG. For example, the ASIC 61 may start supplying the PWM signal Spp in response to detecting that the current value of the line current Ir1 has increased to a value close to the target current value It1.

  Incidentally, the printer 1 is an example of an image forming apparatus. The ASIC 61 is an example of a control device. The line current Ir1 is an example of a grid current. The partial pressure detection signal Sid (detection voltage Vgr1) is an example of a grid voltage.

According to the first embodiment described above, the following effects are provided.
(1) The printer 1 (image forming apparatus) according to the first embodiment includes a photoconductor 31, a charging wire 42 and a grid 43, and is connected to a charger 41 that charges the photoconductor 31, and the charger 41. A charging voltage generation circuit 70 that generates a charging voltage CHG that is a voltage applied to the charging wire 42 of the charger 41, a grid voltage adjustment circuit 81 that adjusts a grid voltage GRID that is a voltage applied to the grid 43, and the grid 43 A grid current detection circuit 82 that detects a grid current Ig (line current Ir1) that is a current flowing through the ASIC 61 and an ASIC 61 (control device). The ASIC 61 controls the charging voltage generation circuit 70 based on the grid current Ig detected by the grid current detection circuit 82 to adjust the current value of the grid current Ig1 (line current Ir1) to the target current value It1, and the grid voltage adjustment A process of controlling the circuit 81 and adjusting the voltage value of the grid voltage GRID (divided voltage detection signal Sid) to the target voltage values Vt1 to Vt3 is executed. When the ASIC 61 starts the operation of the charging voltage generation circuit 70 and the grid voltage adjustment circuit 81, the ASIC 61 starts the process of adjusting the current value of the grid current Ig1 to the target current value It1, and then sets the voltage value of the grid voltage GRID to the target value. The process of adjusting the voltage values Vt1 to Vt3 is started.

  According to this, the ASIC 61 (control device) starts the process of adjusting the voltage value of the grid voltage GRID after starting the process of adjusting the current value of the grid current Ig1. It is possible to start the operation of the grid voltage adjustment circuit 81 in a state where the grid current Ig1 is increased to the target current value It1 and the voltage value of the charging voltage CHG generated by the charging voltage generation circuit 70 is stabilized. Thereby, as the operation of the grid voltage adjustment circuit 81 starts, the current value of the grid current Ig1 (line current Ir1) referred to by the control of the charging voltage generation circuit 70, that is, the current detected by the grid current detection circuit 82K. It can suppress that a value reduces rather than target current value It1. As a result, it is possible to suppress the occurrence of overshoot of the grid voltage GRID while reducing the startup time by suppressing the decrease of the grid current Ig1 and suppressing the excessive increase of the charging voltage CHG.

(2) Further, the ASIC 61 (control device) determines the voltage value of the grid voltage GRID in accordance with the timing (time T9 in FIG. 3) when the current value of the grid current Ig1 (line current Ir1) reaches the target current value It1. The process of adjusting to the target voltage values Vt1 to Vt3 is started.

  As described above, the delay time T11 can be set according to the timing (time T9) at which the current value of the grid current Ig1 (line current Ir1) reaches the target current value It1. Then, the grid voltage adjustment circuit 81 operates (partial voltage detection signal) in a state where the grid current Ig1 is increased to the target current value It1 and the voltage value of the charging voltage CHG generated by the charging voltage generation circuit 70 is more reliably stabilized. Sid increase) can be started. As a result, the occurrence of overshoot of the grid voltage GRID can be more reliably suppressed.

(Second embodiment)
Next, the control operation of the second embodiment will be described with reference to FIG. In the ASIC 61 of the second embodiment, as shown in FIG. 4, the timing for starting the supply of the PWM signals Spp2 to Spp4 is delayed compared to the timing for starting the supply of the PWM signal Sp1 and the PWM signal Spp1 (time T13). Further, the supply of the PWM signals Spp2 to Spp4 is started in order at different times (T14, T15). That is, each of the plurality of grid voltage adjustment circuits 81 starts the process of adjusting the current value of the grid current Ig1 (line current Ir1) to the target current value It1, and then the grid voltage GRID (divided voltage detection signals Sid2 to Sid4). ) Is adjusted in order to target voltage values Vt2 to Vt3.

  Note that the timing for starting the supply of the PWM signal Spp1 may be delayed compared to the timing for starting the supply of the PWM signal Sp1 (time T13). That is, the timing for starting the supply of the PWM signals Spp1 to Spp4 may be different from the time after the start of the supply of the PWM signal Sp1. Moreover, in the following description, the same code | symbol is attached | subjected about the part (time T0 etc.) similar to above-described 1st embodiment, and the description is abbreviate | omitted suitably.

  First, as shown in FIG. 4, the ASIC 61 starts supplying the PWM signal Sp1 and the PWM signal Spp1 simultaneously in order to start the operation of the charging voltage generation circuit 70 and the grid voltage adjustment circuit 81K in response to the reception of the print instruction. (Time T13). The ASIC 61 controls the charging voltage generation circuit 70 based on the current value of the grid current Ig1 to be controlled, and starts control to make the current value of the grid current Ig1 coincide with the desired target current value It1. The charging voltage generation circuit 70 increases the charging voltage CHG according to the PWM signal Sp1.

  The transistor Q1 of the grid voltage adjustment circuit 81K is supplied with a high level base current as a base and maintains the on state. Until the current value of the line current Ir1 (grid current Ig1) increases to the target current value It1, the charging voltage CHG increases as the line current Ir1 increases. At the time (time T15) when the delay time T3 has elapsed since the time T13 when the supply of the PWM signal Spp1 was started (time T15), the current value of the line current Ir1 (grid current Ig1) becomes the target current value It1. The grid voltage adjustment circuit 81K increases the divided voltage detection signal Sid1 (detection voltage Vgr1) at time T15.

  On the other hand, the other grid voltage adjustment circuits 81Y, 81M, 81C are not supplied with the PWM signals Spp2 to Spp4 at time T13 and have not started operating. The line currents Ir2 to Ir4 (grid currents Ig2 to Ig4) do not increase.

  At time T14, the ASIC 61 starts supplying the PWM signal Spp2 in order to start the operation of the next grid voltage adjustment circuit 81Y. The time between the time T13 for starting the supply of the PWM signal Spp1 and the time T14 for starting the supply of the next PWM signal Spp2, that is, the delay time T18 for delaying the supply of the PWM signal Spp2 is an overshoot of the grid voltage GRID. This is a sufficient time to suppress the noise, and is determined and set by simulation, for example. At time T14, the line current Ir1 increases, for example, to a current value close to the target current value It1.

  Similarly, at time T15, the ASIC 61 starts supplying the PWM signal Spp3 in order to start the operation of the next grid voltage adjustment circuit 81M. At time T15, the line current Ir1 becomes the target current value It1. The partial pressure detection signal Sid1 (grid voltage GRID1) starts to increase. Further, at time T15, for example, the line current Ir2 is a non-control target current, and thus has a value exceeding the target current value It2. Although not shown, for example, at a time delayed by a delay time T18 from the time T15, the ASIC 61 starts supplying the PWM signal Spp4 in order to start the operation of the next grid voltage adjustment circuit 81C.

  In addition, the divided voltage detection signal Sid2 (grid voltage GRID2) starts increasing at a time T16 delayed by a delay time T3 from the time T14 at which the supply of the PWM signal Spp2 is started. Further, at time T17 delayed by delay time T3 from time T15 at which the supply of PWM signal Spp3 is started, the partial pressure detection signal Sid3 (grid voltage GRID3) starts to increase.

  In this embodiment, the timing of starting the operation of the grid voltage adjustment circuit 81, that is, the timing of increasing the grid voltage GRID is shifted in order to suppress the reduction of the line current Ir1 that is the control target, and the charging voltage CHG Rapid fluctuation (increase / decrease) can be suppressed. In particular, as shown in FIG. 4, the charging voltage CHG is suppressed from a rapid increase and increases with a small amount of change after time T15 when the partial pressure detection signal Sid1 is increased. Then, by suppressing the rapid fluctuation of the charging voltage CHG, it is possible to suppress the rapid increase of the grid voltage GRID (partial pressure detection signal Sid) and to suppress the occurrence of overshoot.

According to the second embodiment described above, the following effects are obtained.
(1) The printer 1 of the second embodiment includes a plurality of chargers 41 and a plurality of grid voltage adjustment circuits 81. The charging voltage generation circuit 70 is connected to a plurality of chargers 41. The ASIC 61 (control device) adjusts the voltage value of the grid voltage GRID (divided voltage detection signal Sid) by at least one grid voltage adjustment circuit 81 among the plurality of grid voltage adjustment circuits 81 to the target voltage values Vt1 to Vt3. The plurality of grid voltage adjustment circuits 81 are controlled so that the timing of starting the operation is different from the other grid voltage adjustment circuits 81.

  According to this, at least one grid voltage adjustment circuit 81 among the plurality of grid voltage adjustment circuits 81 performs a process of adjusting the grid voltage GRID to the target voltage values Vt1 to Vt3 at timings different from those of the other grid voltage adjustment circuits 81. Start with. Thereby, the ASIC 61 starts the process of adjusting the voltage value of the grid voltage GRID by at least one circuit after starting the process of adjusting the current value of the grid current Ig1. Then, by suppressing the decrease of the grid current Ig1 and suppressing the excessive increase of the charging voltage CHG, it is possible to suppress the occurrence of overshoot of the grid voltage GRID while shortening the startup time.

(2) Each of the plurality of grid voltage adjustment circuits 81 starts the process of adjusting the current value of the grid current Ig1 (line current Ir1) to the target current value It1, and then sets the voltage value of the grid voltage GRID to the target value. The process of adjusting the voltage values Vt1 to Vt3 may be started in order at different times.

  According to this, all the grid voltage adjustment circuits 81 start the process of adjusting the grid voltage GRID to the target voltage values Vt1 to Vt3 after the process of adjusting the grid current Ig1 to the target current value It1 is started. Further, the plurality of grid voltage adjustment circuits 81 start the adjustment process in order at different times. As a result, the reduction of the grid current Ig1 can be more reliably suppressed, and the occurrence of overshoot of the grid voltage GRID can be more reliably suppressed.

(Third embodiment)
Next, the control operation of the third embodiment will be described with reference to FIG. In the ASIC 61 of the third embodiment, as shown in FIG. 5, the supply of the PWM signal Sp1 and the PWM signals Spp1 to Spp4 starts simultaneously, and the target voltage value starts after the grid voltage GRID (partial voltage detection signal Sid) starts to increase. Vt1 to Vt3 are temporarily reduced. In the following description, the same reference numerals are given to the same parts as those of the above-described embodiments, and the description thereof is omitted as appropriate.

  First, at time T1 shown in FIG. 5, the ASIC 61 starts the operations of the charging voltage generation circuit 70 and the four grid voltage adjustment circuits 81 in response to the reception of the print instruction, so that the PWM signal Sp1 and the PWM signals Spp1 to Spp4. Start feeding at the same time. The charging voltage CHG increases as the line current Ir1 increases. At time T4, the line current Ir1 becomes the target current value It1.

  The four grid voltage adjustment circuits 81 start increasing the divided voltage detection signal Sid (detection voltage Vgr) at a time T4 after a delay time T3 has elapsed from the time T1 when the supply of the PWM signals Spp1 to Spp4 is started. Then, after the divided voltage detection signal Sid (grid voltage GRID) increases, the ASIC 61 reduces the target voltage values Vt1 to Vt3 of the four grid voltage adjustment circuits 81 at time T21. For example, the ASIC 61 reduces the duty ratio of the PWM signals Spp <b> 1 to Spp <b> 4 to suppress an increase in the partial pressure detection signal Sid. Thereby, the increase in the grid voltage GRID is suppressed.

  The ASIC 61 returns the target voltage values Vt1 to Vt3 of the four grid voltage adjustment circuits 81 to the original values (values during normal control) at time T22 after the time T23 has elapsed from time T21. The ASIC 61 increases the duty ratio of the PWM signals Spp1 to Spp4, for example. The above-described times T21 to T23 are determined according to the generation timing and period of the grid voltage GRID overshoot that occurred at time T5 shown in FIG. Thereby, the increase in the grid voltage GRID is temporarily suppressed according to the overshoot occurrence timing, and the occurrence of overshoot is suppressed. Then, by returning the target voltage values Vt1 to Vt3 to the original values, the grid current Ig and the grid voltage GRID are stabilized at predetermined target values.

  The ASIC 61 temporarily reduces all the four target voltage values Vt1 to Vt3, but may reduce at least one target voltage value Vt1 to Vt3. Moreover, the timing which reduces target voltage value Vt1-Vt3 is not restricted to time T21, For example, time T4 may be sufficient. That is, the target voltage values Vt1 to Vt3 may be reduced at the timing when the line current Ir1 becomes the target current value It1.

According to the third embodiment described above, the following effects can be obtained.
(1) The printer 1 according to the third embodiment includes a photoconductor 31, a charging wire 42 and a grid 43, and is connected to the charger 41 that charges the photoconductor 31, and the charger 41. A charging voltage generation circuit 70 that generates a charging voltage CHG that is a voltage applied to the wire 42, a grid voltage adjustment circuit 81 that adjusts a grid voltage GRID that is a voltage applied to the grid 43, and a current that flows through the grid 43. A grid current detection circuit 82 for detecting the grid current Ig and an ASIC 61 (control device) are provided. The ASIC 61 controls the charging voltage generation circuit 70 based on the grid current Ig1 detected by the grid current detection circuit 82 to adjust the current value of the grid current Ig1 to the target current value It1, and controls the grid voltage adjustment circuit 81. The process of adjusting the voltage value of the grid voltage GRID to the target voltage values Vt1 to Vt3 is executed. When the ASIC 61 starts the operation of the charging voltage generation circuit 70 and the grid voltage adjustment circuit 81, the ASIC 61 adjusts the current value of the grid current Ig1 to the target current value It1, and the grid voltage GRID (divided voltage detection signal Sid). The process of adjusting the voltage value to the target voltage values Vt1 to Vt3 is started at the same time, and the target voltage values Vt1 to Vt3 are temporarily reduced according to the timing when the increase of the grid voltage GRID starts.

  According to this, the ASIC 61 starts the adjustment processing of the grid current Ig and the grid voltage GRID at the same time, and temporarily decreases the target voltage values Vt1 to Vt3 as the grid voltage GRID increases thereafter. Thereby, the increase of the grid voltage GRID boosted by the grid voltage adjustment circuit 81 can be suppressed in accordance with the overshoot occurrence time. As a result, by suppressing an excessive increase in the charging voltage CHG, it is possible to suppress the occurrence of overshoot of the grid voltage GRID while shortening the startup time.

(2) Further, the period for temporarily reducing the target voltage values Vt1 to Vt3 is set in advance according to the period during which the voltage value of the grid voltage GRID may exceed the target voltage values Vt1 to Vt3 before the reduction. Period.

  According to this, the period in which the target voltage values Vt1 to Vt3 are temporarily reduced is set in advance according to the overshoot period of the grid voltage GRID. As a result, the occurrence of overshoot of the grid voltage GRID can be more reliably suppressed.

(Fourth embodiment)
Next, the control operation of the fourth embodiment will be described with reference to FIG. In the ASIC 61 of the fourth embodiment, as shown in FIG. 6, the supply of the PWM signal Sp1 and the PWM signals Spp1 to Spp4 is started at the same time and the target voltage values Vt1 to Vt3 are temporarily increased. The ASIC 61 restores the temporarily increased target voltage values Vt1 to Vt3 after the grid voltage GRID (the partial pressure detection signal Sid) starts to increase. In the following description, the same reference numerals are given to the same parts as those of the above-described embodiments, and the description thereof is omitted as appropriate.

  First, at time T25 shown in FIG. 6, the ASIC 61 starts the operation of the charging voltage generation circuit 70 and the four grid voltage adjustment circuits 81 in response to the reception of the print instruction, so that the PWM signal Sp1 and the PWM signals Spp1 to Spp4 are started. Start feeding at the same time. Further, at time T25, the ASIC 61 sets the target voltage values Vt1 to Vt3 of the four grid voltage adjustment circuits 81 to values increased as compared with the normal time. The ASIC 61, for example, increases the duty ratio of the PWM signals Spp1 to Spp4 as compared with the normal time. Accordingly, the grid voltage adjustment circuit 81 starts to operate in response to the target voltage values Vt1 to Vt3 set higher, that is, the PWM signals Spp1 to Spp4 having a high duty ratio. The charging voltage CHG increases as the line current Ir1 increases.

  At time T26, the line currents Ir1 to Ir4 have the same value as or exceed the target current values It1 to It3. Since the target current values It1 to It3 are not changed, the increase amounts of the line currents Ir1 to Ir4 are the same as those shown in FIG. 8 (comparative example). On the other hand, by increasing the target voltage values Vt1 to Vt3 and increasing the duty ratio of the PWM signals Spp1 to Spp4, the increase amount of the charging voltage CHG is increased as compared with the case shown in FIG. At time T26, the charging voltage CHG has a larger voltage value than that shown in FIG.

  The four grid voltage adjustment circuits 81 start increasing the divided voltage detection signal Sid (detection voltage Vgr) at a time T26 after a delay time T3 has elapsed from the time T25 when the supply of the PWM signals Spp1 to Spp4 is started. After the partial pressure detection signal Sid (grid voltage GRID) increases, the ASIC 61 returns the temporarily increased target voltage values Vt1 to Vt3 to the normal target voltage values Vt1 to Vt3 at time T27. For example, the ASIC 61 reduces the duty ratio of the PWM signals Spp1 to Spp4. For example, the time T27 is a time when the target voltage values Vt1 to Vt3 before the increase, that is, the normal target voltage values Vt1 to Vt3 coincide with the voltage value of the boosted divided voltage detection signal Sid.

  By reducing the target voltage values Vt1 to Vt3, the charging voltage CHG is reduced. The grid current Ig1 (line current Ir1) becomes the target current value It1 at time T28 after being temporarily reduced as the charging voltage CHG is reduced. The other grid currents Ig2 to Ig4 are also temporarily reduced. Further, since the charging voltage generation circuit 70 performs an operation of reducing the charging voltage CHG, an increase in the partial pressure detection signal Sid (grid voltage GRID) is suppressed. Thereby, the increase in the grid voltage GRID is suppressed, and the occurrence of overshoot is suppressed. Then, by returning the target voltage values Vt1 to Vt3 to the original values, the grid current Ig and the grid voltage GRID are stabilized at predetermined target values.

  The ASIC 61 temporarily increases all the four target voltage values Vt1 to Vt3, but may increase at least one target voltage value Vt1 to Vt3. The timing for increasing the target voltage values Vt1 to Vt3 is not limited to the time T25, and may be after a predetermined time has elapsed from the time T25, for example. That is, the target voltage values Vt1 to Vt3 may be increased with a slight delay from the timing at which the supply of the PWM signals Spp1 to Spp4 is started.

According to the fourth embodiment described above, the following effects can be obtained.
(1) The printer 1 according to the fourth embodiment includes a photoconductor 31, a charging wire 42, and a grid 43, and is connected to the charger 41 that charges the photoconductor 31, and the charger 41. A charging voltage generation circuit 70 that generates a charging voltage CHG that is a voltage applied to the wire 42, a grid voltage adjustment circuit 81 that adjusts a grid voltage GRID that is a voltage applied to the grid 43, and a current that flows through the grid 43. A grid current detection circuit 82 for detecting the grid current Ig and an ASIC 61 (control device) are provided. The ASIC 61 controls the charging voltage generation circuit 70 based on the grid current Ig1 detected by the grid current detection circuit 82 to adjust the current value of the grid current Ig1 to the target current value It1, and controls the grid voltage adjustment circuit 81. The process of adjusting the voltage value of the grid voltage GRID to the target voltage values Vt1 to Vt3 is executed. The ASIC 61 adjusts the current value of the grid current Ig1 to the target current value It1 when starting the operations of the charging voltage generation circuit 70 and the grid voltage adjustment circuit 81, and the voltage value of the grid voltage GRID as the target voltage value Vt1. The process of adjusting to ~ Vt3 is started at the same time, the target voltage values Vt1 to Vt3 are temporarily increased, and the temporarily increased target voltage values Vt1 to Vt3 are started to increase in the grid voltage GRID. After that, put it back.

  According to this, the ASIC 61 starts the adjustment process of the grid current Ig1 and the grid voltage GRID at the same time, and temporarily sets the target voltage values Vt1 to Vt3. The grid voltage adjustment circuit 81 performs a process of increasing the grid voltage GRID in accordance with the increased target voltage values Vt1 to Vt3. Further, the target voltage values Vt1 to Vt3 are restored after the start of the increase of the grid voltage GRID. The charging voltage CHG temporarily increases or decreases according to the increase or decrease of the target voltage values Vt1 to Vt3. By reducing the temporarily increased charging voltage CHG in accordance with the increase of the grid voltage GRID, it is possible to suppress the increase of the grid voltage GRID and suppress the occurrence of overshoot. As a result, it is possible to suppress the occurrence of overshoot of the grid voltage GRID while shortening the startup time.

(Fifth embodiment)
Next, the control operation of the fifth embodiment will be described with reference to FIG. In the ASIC 61 of the fifth embodiment, as shown in FIG. 7, the supply of the PWM signal Sp1 and the PWM signals Spp1 to Spp4 is started at the same time and the target current values It1 to It3 are temporarily increased. The ASIC 61 restores the temporarily increased target current values It1 to It3 after the grid voltage GRID (partial voltage detection signal Sid) starts to increase. In the following description, the same reference numerals are given to the same parts as those of the above-described embodiments, and the description thereof is omitted as appropriate.

  First, at time T30 shown in FIG. 7, the ASIC 61 starts the operations of the charging voltage generation circuit 70 and the four grid voltage adjustment circuits 81 in response to the reception of the print instruction, and therefore the PWM signal Sp1 and the PWM signals Spp1 to Spp4. Start feeding at the same time. Further, at time T30, the ASIC 61 sets the target current values It1 to It3 corresponding to the four grid currents Ig1 to Ig4 to increased values compared to the normal time. Since the ASIC 61 sets higher target current values It1 to It3 than in the case shown in FIG. 8, the duty ratio of the PWM signal Sp1 is made higher than in the case shown in FIG. 8, and the change amount of the charging voltage CHG is increased. The charging voltage CHG increases as the line current Ir1 increases.

  At time T31, the line currents Ir1 to Ir4 increase to current values corresponding to the increased target current values It1 to It3. Further, by increasing the target current values It1 to It3, the charging voltage generation circuit 70 further increases the charging voltage CHG and tries to make the line currents Ir1 to Ir4 coincide with the target current values It1 to It3. As a result, at time T31, the charging voltage CHG has a larger voltage value than that in the case of FIG.

  The four grid voltage adjustment circuits 81 start increasing the divided voltage detection signal Sid (detection voltage Vgr) at a time T31 after a delay time T3 has elapsed from the time T30 when the supply of the PWM signals Spp1 to Spp4 is started. For example, the ASIC 61 continuously turns off the transistor Q1 in order to increase the partial pressure detection signal Sid. Due to the off control of the transistor Q1, the grid current Ig flowing through each grid 43 can easily flow to the voltage detection circuit 83 side. The shunt current Id flowing through the voltage detection circuit 83 increases. The divided voltage detection signal Sid (grid voltage GRID) increases as the divided current Id increases.

  On the other hand, the line current Ir of each grid voltage adjustment circuit 81 decreases in accordance with the off period of the transistor Q1, and becomes a current value smaller than the temporarily increased target current values It1 to It3 (time T32). The ASIC 61 attempts to increase the charging voltage CHG in accordance with the reduction of the line current Ir1 that is the control target. However, at time T32, the ASIC 61 returns the temporarily increased target current values It1 to It3 to the normal target current values It1 to It3. For this reason, the ASIC 61 performs control for maintaining or reducing the voltage value of the charging voltage CHG without controlling the charging voltage generation circuit 70 to increase the charging voltage CHG. The time T32 is, for example, a time when the magnitude of the partial pressure detection signal Sid and the target voltage values Vt1 to Vt3 coincide.

  The grid current Ig1 (line current Ir1) becomes the target current value It1 after returning (normal time) at time T33 after being temporarily reduced. The other grid currents Ig2 to Ig4 are also temporarily reduced. In addition, since the charging voltage generation circuit 70 performs an operation for maintaining or reducing the charging voltage CHG, an increase in the partial pressure detection signal Sid (grid voltage GRID) is suppressed. Thereby, the increase in the grid voltage GRID is suppressed, and the occurrence of overshoot is suppressed. Then, by returning the target current values It1 to It3 to the original values, the grid current Ig and the grid voltage GRID are stabilized at predetermined target values.

  Note that the ASIC 61 temporarily increases all of the four target current values It1 to It3. However, for example, only the target current value It1 to be controlled may be increased. The timing for increasing the target current values It1 to It3 is not limited to the time T30, but may be after a predetermined time has elapsed from the time T30. That is, the target current values It1 to It3 may be increased with a slight delay from the timing at which the supply of the PWM signal Sp1 is started.

According to the fifth embodiment described above, the following effects are provided.
(1) The printer 1 of the fifth embodiment includes the photosensitive member 31, the charging wire 42 and the grid 43, and is connected to the charging device 41 that charges the photosensitive member 31 and the charging device 41. A charging voltage generation circuit 70 that generates a charging voltage CHG that is a voltage applied to the wire 42, a grid voltage adjustment circuit 81 that adjusts a grid voltage GRID that is a voltage applied to the grid 43, and a current that flows through the grid 43. A grid current detection circuit 82 for detecting the grid current Ig and an ASIC 61 (control device) are provided. The ASIC 61 executes processing for controlling the charging voltage generation circuit 70 based on the grid current Ig detected by the grid current detection circuit 82 and adjusting the current value of the grid current Ig1 to the target current value It1. When the ASIC 61 starts the operation of the charging voltage generation circuit 70, the ASIC 61 starts with the target current value It1 temporarily increased, and the grid voltage GRID starts increasing the target current value It1 that has been temporarily increased. After that, put it back.

  According to this, when the ASIC 61 starts the adjustment process of the grid current Ig1, the ASIC 61 temporarily sets the target current values It1 to It3. The charging voltage generation circuit 70 increases the charging voltage CHG in accordance with the increased target current values It1 to It3. Further, the target current values It1 to It3 are restored after the start of the increase of the grid voltage GRID. The charging voltage CHG temporarily increases or decreases according to the increase or decrease of the target current values It1 to It3. By reducing the temporarily increased charging voltage CHG in accordance with the increase of the grid voltage GRID, it is possible to suppress the increase of the grid voltage GRID and suppress the occurrence of overshoot. As a result, it is possible to suppress the occurrence of overshoot of the grid voltage GRID while shortening the startup time.

(2) Further, the ASIC 61 (control device) executes a process of controlling the grid voltage adjustment circuit 81 and adjusting the voltage value of the grid voltage GRID to the target voltage values Vt1 to Vt3. In addition, the ASIC 61 adjusts the current value of the grid current Ig1 to the target current value It1 when starting the operation of the charging voltage generation circuit 70 and the grid voltage adjustment circuit 81, and the voltage value of the grid voltage GRID as the target voltage. The process of adjusting the values Vt1 to Vt3 is started at the same time, and is started in a state where the target current value It1 is temporarily increased.

  According to this, the grid voltage adjustment circuit 81 can be controlled by the ASIC 61, and the voltage value of the grid voltage GRID can be controlled to an arbitrary value. As a result, the grid voltage GRID can be adjusted according to the printing status (image quality) and the deterioration of the grid 43 and the like. In such a configuration, by temporarily increasing the target current values It1 to It3, it is possible to suppress the occurrence of overshoot of the grid voltage GRID while shortening the startup time.

In addition, this application is not limited to said each embodiment, It cannot be overemphasized that various improvement and change are possible within the range which does not deviate from the meaning of this invention.
For example, in each of the embodiments described above, an example in which one charger 41 is associated with one photoreceptor 31 has been described, but the present invention is not limited to this. In the present application, a configuration in which a plurality of chargers 41 are made to correspond to one photoconductor 31, for example, a printer (image forming unit) that superimposes toner images of respective colors on one photoconductor 31 and then transfers them to a sheet P at a time. (Apparatus). In this case, the number of the photoreceptors 31 may be one.
The printer 1 may be a monochrome printer that includes only the photosensitive member 31K corresponding to black.
Further, the printer 1 may be configured to include only one charger 41.

Further, the ASIC 61 may execute a control operation that combines the controls of the above-described embodiments. For example, the ASIC 61 shifts the supply start timing of the PWM signal Sp1 and the PWM signals Spp1 to Spp4 (first and second embodiments) and temporarily reduces the target voltage values Vt1 to Vt3 (third embodiment). )
In each of the above embodiments, the drum-shaped photoconductor 31 is exemplified as the photoconductor. However, the photoconductor is not limited thereto, and may be, for example, a belt-shaped photoconductor.
In each of the above embodiments, the ASIC 61 is used as the control device. However, the control device in the present application is not limited to the case of being configured by dedicated hardware such as the ASIC 61. For example, the control device is configured by software operating on the CPU. May be.
In each of the above embodiments, the electrophotographic laser printer 1 is employed as the image forming apparatus of the present application, but the present invention is not limited thereto. The image forming apparatus of the present application may be a multifunction machine, a facsimile machine, a copier, or the like.

DESCRIPTION OF SYMBOLS 1 Laser printer (image forming apparatus), 31 Photoconductor, 41 Charger, 42 Charging wire, 43 grid, 61 ASIC (control apparatus), 70 Charging voltage generation circuit, 81 Grid voltage adjustment circuit, 82 Grid current detection circuit, CHG Charging voltage, GRID grid voltage, Ig grid current, Ir line current (grid current), It1 to It3 target current value, Vt1 to Vt3 target voltage value.

Claims (10)

A photoreceptor,
A charger having a charging wire and a grid, and charging the photoreceptor;
A charging voltage generating circuit that is connected to the charger and generates a charging voltage that is a voltage applied to the charging wire of the charger;
A grid voltage adjusting circuit for adjusting a grid voltage, which is a voltage applied to the grid;
A grid current detection circuit for detecting a grid current that is a current flowing through the grid;
A control device,
The control device includes:
Processing for controlling the charging voltage generation circuit based on the grid current detected by the grid current detection circuit and adjusting the current value of the grid current to a target current value;
Controlling the grid voltage adjustment circuit and adjusting the voltage value of the grid voltage to a target voltage value, and
When starting the operation of the charging voltage generation circuit and the grid voltage adjustment circuit, after starting the process of adjusting the current value of the grid current to the target current value, the voltage value of the grid voltage is changed to the target voltage value. An image forming apparatus that starts a process of adjusting the image. The control device includes:
The image forming apparatus according to claim 1, wherein processing for adjusting the voltage value of the grid voltage to the target voltage value is started in accordance with a timing at which the current value of the grid current reaches the target current value. A plurality of the chargers;
A plurality of the grid voltage adjustment circuits are provided,
The charging voltage generation circuit is connected to a plurality of the chargers,
The control device includes:
The timing at which the process of adjusting the voltage value of the grid voltage to the target voltage value by at least one grid voltage adjustment circuit among the plurality of grid voltage adjustment circuits is different from the other grid voltage adjustment circuits. The image forming apparatus according to claim 1, wherein the plurality of grid voltage adjustment circuits are controlled.   Each of the plurality of grid voltage adjustment circuits performs a process of adjusting the voltage value of the grid voltage to the target voltage value after the process of adjusting the current value of the grid current to the target current value is started. The image forming apparatus according to claim 3, wherein the image forming apparatuses start in order with a shift. A photoreceptor,
A charger having a charging wire and a grid, and charging the photoreceptor;
A charging voltage generating circuit that is connected to the charger and generates a charging voltage that is a voltage applied to the charging wire of the charger;
A grid voltage adjusting circuit for adjusting a grid voltage, which is a voltage applied to the grid;
A grid current detection circuit for detecting a grid current that is a current flowing through the grid;
A control device,
The control device includes:
Processing for controlling the charging voltage generation circuit based on the grid current detected by the grid current detection circuit and adjusting the current value of the grid current to a target current value;
Controlling the grid voltage adjustment circuit and adjusting the voltage value of the grid voltage to a target voltage value, and
When starting the operation of the charging voltage generation circuit and the grid voltage adjustment circuit, a process of adjusting the current value of the grid current to the target current value, and adjusting the voltage value of the grid voltage to the target voltage value An image forming apparatus that starts processing at the same time and temporarily reduces the target voltage value in accordance with a timing at which the increase of the grid voltage starts.   The period for temporarily reducing the target voltage value is a period set in advance according to a period during which the voltage value of the grid voltage may exceed the target voltage value before the reduction. The image forming apparatus described. A photoreceptor,
A charger having a charging wire and a grid, and charging the photoreceptor;
A charging voltage generating circuit that is connected to the charger and generates a charging voltage that is a voltage applied to the charging wire of the charger;
A grid voltage adjusting circuit for adjusting a grid voltage, which is a voltage applied to the grid;
A grid current detection circuit for detecting a grid current that is a current flowing through the grid;
A control device,
The control device includes:
Processing for controlling the charging voltage generation circuit based on the grid current detected by the grid current detection circuit and adjusting the current value of the grid current to a target current value;
Controlling the grid voltage adjustment circuit and adjusting the voltage value of the grid voltage to a target voltage value, and
When starting the operation of the charging voltage generation circuit and the grid voltage adjustment circuit, a process of adjusting the current value of the grid current to the target current value, and adjusting the voltage value of the grid voltage to the target voltage value An image forming apparatus that simultaneously starts processing, starts with the target voltage value temporarily increased, and restores the temporarily increased target voltage value after the grid voltage starts increasing . A photoreceptor,
A charger having a charging wire and a grid, and charging the photoreceptor;
A charging voltage generating circuit that is connected to the charger and generates a charging voltage that is a voltage applied to the charging wire of the charger;
A grid voltage adjusting circuit for adjusting a grid voltage, which is a voltage applied to the grid;
A grid current detection circuit for detecting a grid current that is a current flowing through the grid;
A control device,
The control device includes:
Executing the process of controlling the charging voltage generation circuit based on the grid current detected by the grid current detection circuit and adjusting the current value of the grid current to a target current value;
When the operation of the charging voltage generation circuit is started, the target current value is started in a state where the target current value is temporarily increased, and the target current value which has been temporarily increased is restored after the grid voltage starts to increase. Return to the image forming apparatus. The control device includes:
Controlling the grid voltage adjustment circuit and executing a process of adjusting the voltage value of the grid voltage to a target voltage value,
When starting the operation of the charging voltage generation circuit and the grid voltage adjustment circuit, a process of adjusting the current value of the grid current to the target current value, and adjusting the voltage value of the grid voltage to the target voltage value The image forming apparatus according to claim 8, wherein the image forming apparatus starts processing at the same time and starts with the target current value temporarily increased. Charger that has a photoconductor, a charging wire and a grid, and that charges the photoconductor, and is connected to the charger and generates a charging voltage that is a voltage applied to the charging wire of the charger A control method of an image forming apparatus comprising: a circuit; a grid voltage adjustment circuit that adjusts a grid voltage that is a voltage applied to the grid; and a grid current detection circuit that detects a grid current that is a current flowing through the grid. There,
Controlling the charging voltage generation circuit based on the grid current detected by the grid current detection circuit and adjusting the current value of the grid current to a target current value;
Controlling the grid voltage adjustment circuit to adjust the voltage value of the grid voltage to a target voltage value,
When starting the operation of the charging voltage generation circuit and the grid voltage adjustment circuit, after starting the step of adjusting the current value of the grid current to the target current value, the voltage value of the grid voltage is changed to the target voltage value. A control method that starts the step of adjusting to.

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