JP2019079589A - Semiconductor storage device - Google Patents

Abstract

To achieve power saving and high speed during an active period and improvement of yield.SOLUTION: As the configuration of a ferroelectric shadow memory, a control method, and a test method, following techniques are proposed: (1) a bit line non-precharge technique for not performing precharge of a bit line during read/write operation; (2) a plate line charge share technique for sharing the charge of a plate line sequentially driven during store/recall operation; (3) a word line boost technique for boosting a word line during write operation; (4) a plate line driver boost technique for enhancing drive capability of a plate wire driver during store/recall operation; and (5) a test technique for arbitrarily setting electric potential of a bit line from outside of a chip to detect failure of a ferroelectric capacitor.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor memory device.

  BACKGROUND In recent years, non-volatile memory is used in a system on chip (SoC) mounted in many applications. In particular, in applications with low active rates (such as sensor networks and biological monitoring), there are severe restrictions on power consumption at standby in order to reduce battery capacity and system module size.

  If a volatile memory (for example, a static random access memory (SRAM)) is used as a data buffer for the above-described application, the leak current may significantly affect the total power consumption of the system. On the other hand, if a non-volatile memory is used as the data buffer, data can be held in a non-volatile manner without receiving power supply, which can greatly contribute to power saving during standby. From this, it can be said that non-volatile memory is very suitable as a data buffer for applications with low activity rate.

  As a non-volatile memory, FeRAM [ferroelectric random access memory] using a ferroelectric capacitor is put to practical use (for example, contactless IC card). However, the FeRAM has problems in the driving speed and power consumption at the active time, and the durability thereof.

  Conventionally, a shadow memory of 6T-4C structure (or 6T-2C structure) (hereinafter referred to as a ferroelectric shadow memory) in which an SRAM of 6T structure and a ferroelectric capacitor are combined to solve the problem of FeRAM ) Has been proposed.

  The ferroelectric shadow memory operates as a 6T SRAM when active (data read / write operation), and stores data in a ferroelectric capacitor to make it non-volatile during standby. Therefore, in the case of the ferroelectric shadow memory, it is possible to achieve both high speed operation at the active time and power saving (leakage current reduction) at the standby time.

  Note that Non-Patent Document 1 and Non-Patent Document 2 can be given as an example of the prior art related to the above.

S. Masui, W. Yokozeki, et al., "Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read / program cycles and stable recall", In Proc. Of IEEE CICC, pp. 403-406, 2003. T. Miwa, J. Yamada, et al., "NV-SRAM: A Nonvolatile SRAM with Backup Ferroelectric Capacitors", IEEE JSSC, vol. 36, no. 3, pp. 522-527, 2001.

  However, the ferroelectric shadow memory has (1) large power consumption at the time of active, (2) slow operation speed at the time of active, (3) ferroelectric capacitor due to manufacturing variation, etc., compared to 6T structure SRAM. The problem was that it was difficult to diagnose

  SUMMARY OF THE INVENTION In view of the above problems found by the inventors of the present invention, the present invention provides a semiconductor memory device capable of realizing power saving at the active time, speeding up at the active time, or improvement of yield. The purpose is to

  The semiconductor memory device disclosed in the present specification includes a plurality of memory cells, a word line commonly connected to the plurality of memory cells, and a plurality of bit lines and inversions respectively connected to the plurality of memory cells. A memory controller for performing access control to the plurality of memory cells, the plurality of memory cells each including an inverter loop connected between a first node and a second node; Connected between a first access transistor connected between a first node and the bit line and turned on / off according to the voltage applied to the word line, and connected between the second node and the inverted bit line A second access transistor that is turned on / off according to the voltage applied to the word line, and a parasitic capacitor connected to the first node and connected to the first node The memory controller includes a large first node capacitor and a second node capacitor connected to the second node and having a larger capacity than the parasitic capacitor of the inversion bit line, and the memory controller is configured to read / write memory cells. At the time of access, the word line is driven to precharge the first access transistor and the second access transistor without precharging the bit line and the inverted bit line connected to the memory cell other than the read / write target. It is set as the configuration (first configuration).

  The semiconductor memory device having the first configuration further includes a plurality of transmission gates respectively connected between the pair of bit lines and the inverted bit line, and the memory controller is a memory cell to be read / written. It is preferable that the transmission gate between the bit line connected to the memory cell other than the read / write target and the inverted bit line be turned on (second structure) when accessing.

  In the semiconductor memory device having the first or second configuration, the first node capacitor and the second node capacitor are respectively connected between a plate line and the first node and the second node. The memory controller may be configured (the third configuration) to pulse-drive the plate line when storing / recalling data of the memory cell.

  In the semiconductor memory device disclosed in the present specification, a plurality of memory cells, a plurality of plate lines connected to the plurality of memory cells, and a plate line driver for driving the plurality of plate lines, respectively. And a memory controller for controlling access to the plurality of memory cells, the plurality of memory cells each including an inverter loop connected between a first node and a second node; Between a first access transistor connected between the node and the bit line, a second access transistor connected between the second node and the inverted bit line, and between the first node and the plate line And a second ferroelectric capacitor connected between the second node and the plate line. The roller is used to pulse drive the plurality of plate lines sequentially using the plate line driver when storing / recalling data of the memory cells, and is not charged using the plate line driver. A configuration is adopted (fourth configuration) in which charge sharing is performed between the already charged plate line and the uncharged plate line before pulse drive of the plate line.

  The semiconductor memory device having the fourth configuration further includes a plurality of transmission gates connected between adjacent plate lines, and the memory controller pulses the uncharged plate lines using the plate line driver. The transmission gate between the already charged plate line and the uncharged plate line may be turned on (fifth configuration) before driving.

  In addition, the word line driver disclosed in the present specification controls the coupling control of the ferroelectric capacitor in response to the output stage driving the word line of the memory cell in response to the word line enable signal and the boost enable signal. And a boost stage that raises the voltage applied to the word line more than the power supply voltage of the output stage.

  In the word line driver having the sixth configuration, the output stage has an inverter whose input end is connected to the application end of the word line enable signal, a source is connected to a power supply end, and a gate is an output of the inverter A P-channel type first transistor connected to an end, and an N-channel type second transistor having a drain connected to the word line, a source connected to the ground end, and a gate connected to the output end of the inverter , And the boost stage is a P-channel third transistor having a source connected to the drain of the first transistor, a drain connected to the word line, and a gate connected to the application end of the boost enable signal. And a ferroelectric capacitor connected between the application terminal of the boost enable signal and the word line. Better to seventh configuration).

  In addition, the semiconductor memory device disclosed in the present specification comprises a memory cell, a memory controller for controlling access to the memory cell, and a sixth or seventh configuration for driving a word line of the memory cell. A configuration (eighth configuration) having a word line driver is adopted.

  The semiconductor memory device having the eighth configuration may have a configuration (ninth configuration) including a delay stage that delays the word line enable signal by a predetermined delay time to generate the boost enable signal.

  In the semiconductor memory device having the ninth configuration, the delay stage may have a configuration including an inverter chain (10th configuration).

  In the semiconductor memory device having any one of the eighth to tenth configurations, the memory cell includes an inverter loop connected between a first node and a second node, and the first node and the bit line. Is connected between the first access transistor connected between and turned on / off according to the voltage applied to the word line, and connected between the second node and the inverted bit line according to the voltage applied to the word line A second access transistor to be turned on / off, a first node capacitor connected to the first node and having a capacitance larger than that of the parasitic capacitor of the bit line, and the second node connected to the second node An eleventh configuration may include a second node capacitor having a larger capacity than a parasitic capacitor of a line.

  Further, in the semiconductor memory device having an eleventh configuration, the first node capacitor and the second node capacitor are respectively connected between a plate line and the first node and the second node. The memory controller may be configured (12th configuration) to pulse-drive the plate line when storing / recalling data of the memory cell.

  Further, the plate line driver disclosed in the present specification generates a second plate line enable signal in response to the first plate line enable signal, and the first output stage in response to the second plate line enable signal. A second output stage driving a plate line of a memory cell and coupling control of a ferroelectric capacitor according to a boost enable signal pulls down the second plate line enable signal to a negative voltage to perform the second output stage And a boost stage that enhances the driving capability of the drive circuit (13th configuration).

  In the plate line driver having the thirteenth configuration, in the first output stage, the source is connected to the power supply end, the gate is connected to the application end of the first plate line enable signal, and the drain is the second plate A P-channel type first transistor connected to a line enable signal application end, and an N-channel type second transistor having a source connected to the ground end and a gate connected to the first plate line enable signal application end The second output stage has a source connected to the power supply end, a drain connected to the plate line, and a gate connected to the application end of the second plate line enable signal, and a third output stage The transistor and the drain are connected to the plate line, the source is connected to the ground end, and the gate is connected to the application end of the second plate line enable signal. The boost stage includes an inverter having an input end connected to the application end of the boost enable signal, and a drain connected to the application end of the second plate line enable signal. An N-channel fifth transistor connected with the source connected to the drain of the second transistor and the gate connected to the output end of the inverter, and the application of the output end of the inverter and the second plate line enable signal A ferroelectric capacitor connected between the end and the end may be configured (fourteenth configuration).

  The semiconductor memory device disclosed in the present specification comprises a memory cell, a memory controller for controlling access to the memory cell, and a thirteenth or fourteenth structure for driving a plate line of the memory cell. And a plate line driver (fifteenth configuration).

  In the semiconductor memory device having the fifteenth configuration, the memory cell is connected between an inverter loop connected between a first node and a second node, and between the first node and a bit line. A first access transistor, a second access transistor connected between the second node and the inversion bit line, and a first ferroelectric capacitor connected between the first node and the plate line. And a second ferroelectric capacitor connected between the second node and the plate line, wherein the memory controller pulse-drives the plate line when storing / recalling data of the memory cell. The configuration (sixteenth configuration) is preferable.

  In the semiconductor memory device disclosed in the present specification, an inverter loop connected between a first node and a second node, and a first connected between the first node and a bit line An access transistor, a second access transistor connected between the second node and the inversion bit line, a first ferroelectric capacitor connected between the first node and the plate line, the second A second ferroelectric capacitor connected between a node and the plate line, and an external terminal for applying an arbitrary analog voltage to the bit line and the inverted bit line, respectively Configuration).

  In the semiconductor memory device having the seventeenth configuration, the first word line connected to the gate of the first access transistor and the second word line connected to the gate of the second access transistor are separately independent. It is preferable that the configuration (the eighteenth configuration) is included in

  The semiconductor memory device testing method disclosed in the present specification is directed to a semiconductor memory device having a seventeenth or eighteenth configuration, wherein the external terminal is connected to the bit line or the inversion. Applying any reference voltage to one of the bit lines, pulsating the plate line with the inverter loop disabled, both the first access transistor and the second access transistor, or A configuration (19th configuration) includes a step of turning on only one side to which a reference voltage is not applied and a step of comparing each voltage between the bit line and the inversion bit line.

  The semiconductor memory device testing method disclosed in the present specification is directed to a semiconductor memory device having a seventeenth or eighteenth configuration, wherein the external terminal is connected to the bit line or the inversion. Applying any offset voltage to one of the bit lines, turning on the first access transistor and the second access transistor, and pulsing the plate line with the inverter loop disabled And (20th configuration), comprising the steps of: enabling the inverter loop; and comparing respective voltages between the bit line and the inversion bit line.

  According to the semiconductor memory device disclosed in the present specification, it is possible to realize power saving at the active time, speeding up at the active time, or improvement of the yield.

Block diagram showing the entire configuration of a semiconductor memory device A circuit diagram showing a configuration example of a memory cell 11 Timing chart showing one operation example of the memory cell 11 Diagram for explaining the necessity of bit line precharging in SRAM Diagram showing bit line non-precharge method in ferroelectric shadow memory A diagram showing one configuration example for realizing BL / XBL equalization Diagram showing the usefulness of the bit line non-precharge method Diagram showing advantage of short circuit between BL and XBL A diagram showing an exemplary configuration for realizing plate line charge sharing Timing chart showing one operation example of plate line charge sharing Diagram showing the usefulness of the plate line charge sharing method A circuit diagram showing one configuration example of the word line driver 20 Area comparison table of various capacitors Timing chart showing one operation example of word line boost Diagram showing the usefulness of the word line boost method Diagram to explain optimization of boost delay Diagram showing change behavior of Twr with extension of Tbd (Tbd <T0) Diagram showing change behavior of Twr with extension of Tbd (Tbd> T0) Correlation diagram between boost delay Tbd and data rewrite time Twr Diagram to explain the determinants of T1, T2 and T0 Diagram showing the change behavior of T0 according to the WL rise time A circuit diagram showing one configuration example of delay stage 26 Diagram showing the usefulness of delay stage 26 Table showing simulation conditions Comparison diagram of light access time Table showing simulation results of word line boost A circuit diagram showing one configuration example of a plate line driver 40 Timing chart showing one operation example of plate line driver boost Table showing simulation results of plate line driver boost Conceptual diagram showing the application effect to the intermittent start sensing application Active time comparison table Diagram for explaining recall defects due to aged deterioration A circuit diagram showing a first configuration example of a semiconductor memory device to be subjected to a margin test Timing chart showing the pass pattern of the first test Timing chart showing the failure pattern of the first test A circuit diagram showing a second configuration example of a semiconductor memory device to be subjected to a margin test Timing chart showing the pass pattern of the second test Timing chart showing fail pattern of the second test Timing chart showing the pass pattern of the third test Timing chart showing the fail pattern of the third test

<Semiconductor storage device>
FIG. 1 is a block diagram showing an entire configuration of a semiconductor memory device. The semiconductor memory device 100 of this configuration example has a memory block 1 and a memory controller 2.

  Memory block 1 is a circuit block for storing data, and includes memory cell array 10, word line driver 20, X decoder 30, plate line driver 40, Y decoder and column selector 50, and write circuit 60. , And the read circuit 70. The memory controller 2 is a circuit block that performs access control to the memory block 1 (and the plurality of memory cells 11), and, for example, a CPU (central processing unit) can be suitably used.

  Memory cell array 10 includes a plurality of memory cells 11 arranged in a matrix. As the memory cell 11, a ferroelectric shadow memory having a 6T-4C structure or a 6T-2C structure is used. Memory cell 11 includes word line WL for access control at the time of read / write operation, bit line BL and inverted bit line XBL for data input / output at the time of read / write operation, and ferroelectrics at the time of store / recall The first plate line PL1 and the second plate line PL2 for driving the capacitor are connected. The configuration and operation of the memory cell 11 will be described in detail later.

  The word line driver 20 drives the word line WL connected to the memory cell 11 to be read / written in response to an instruction from the X decoder 30.

  The X decoder 30 drives the word line driver 20 in response to an instruction from the memory controller 2.

  The plate line driver 40 drives the plate lines PL1 and PL2 connected to the memory cell 11 to be stored / recalled, in response to an instruction from the Y decoder and column selector 50.

  The Y decoder and column selector 50 drives the plate line driver 40 in response to an instruction from the memory controller 2. In addition, Y decoder and column selector 50 responds to an instruction from memory controller 2 to connect bit line BL and inverted bit line XBL connected to memory cell 11 to be read / written and write circuit 60 or read circuit 70. Selectively conduct between them.

  Write circuit 60 drives bit line BL and inverted bit line XBL in accordance with data to be written to memory cell 11.

  Read circuit 70 includes a sense amplifier for reading data from memory cell 11 by comparing (differential amplifying) each voltage between bit line BL and inverted bit line XBL.

<Memory cell>
FIG. 2 is a circuit diagram showing one configuration example of the memory cell 11. The memory cell 11 of this configuration example is a ferroelectric memory having a 6T-4C structure, and includes N-channel drive transistors M2 and M4, P-channel load transistors M1 and M3, and an N-channel access transistor M5. And M6, and ferroelectric capacitors FC1 to FC4. Hereinafter, for convenience of explanation, the drive transistors M2 and M4, the load transistors M1 and M3, and the access transistors M5 and M6 are abbreviated as transistors M1 to M6, respectively.

  The sources of the transistors M1 and M3 are both connected to the power supply terminal. The drains of the transistors M1 and M2 and the gates of the transistors M3 and M4 are both connected to the internal node Node1. The drains of the transistors M3 and M4 and the gates of the transistors M1 and M2 are both connected to the internal node Node2. The sources of the transistors M2 and M4 are both connected to the ground terminal.

  The transistors M1 and M2 form an inverter whose input end is connected to the internal node Node2 and whose output end is connected to the internal node Node1. The transistors M3 and M4 form an inverter whose input end is connected to the internal node Node1 and whose output end is connected to the internal node Node2. That is, transistors M1 to M4 function as an inverter loop connected between internal node Node1 and internal node Node2.

  The transistor M5 is connected between the internal node Node1 and the bit line BL, and is turned on / off according to the voltage applied to the word line WL connected to the gate. On the other hand, the transistor M6 is connected between the internal node Node2 and the inverted bit line XBL, and is turned on / off according to the voltage applied to the word line WL connected to the gate.

  The ferroelectric capacitor FC1 is connected between the internal node Node1 and the plate line PL2. The ferroelectric capacitor FC2 is connected between the internal node Node1 and the plate line PL2. The ferroelectric capacitor FC3 is connected between the internal node Node1 and the plate line PL1. The ferroelectric capacitor FC4 is connected between the internal node Node2 and the plate line PL1.

  In memory cell 11 configured as described above, internal nodes Node1 and Node2 both function as storage nodes of memory cell 11, and each node voltage is set to logic data "0" or "0" stored in memory cell 11. It becomes a voltage value according to 1 ".

  FIG. 3 is a timing chart showing an operation example ((a) column: write operation, (b) column: read operation, (c) column: store operation, (d) column: recall operation) of the memory cell 11 . In each of columns (a) to (d), word line WL, bit line BL, inverted bit line XBL, plate lines PL1 and PL2, and power supply voltage VDD (enable of inverter loop Corresponding to the disabled state is depicted.

  At the time of the write operation of the memory cell 11, the word line WL is raised to the high level, and the transistors M5 and M6 are turned on. At this time, if the bit line BL is high level and the inverted bit line XBL is low level, the transistors M1 and M4 are turned on and the transistors M2 and M3 are turned off. By thus determining the operating state of the inverter loop, the internal node Node1 is fixed at the high level, and the internal node Node2 is fixed at the low level. This state corresponds to the state where the logic data "1" is written to the memory cell 11, and as long as the power supply voltage VDD is supplied, it is maintained even after the word line WL falls to the low level. Conversely, when writing logic data "0" in the memory cell 11, the bit line BL may be made low during the high level period of the word line WL, and the inverted bit line XBL may be made high. In the write operation of the memory cell 11, the plate lines PL1 and PL2 are both fixed at the low level.

  At the time of the read operation of the memory cell 11, the bit line BL and the inverted bit line XBL are brought into the floating state, and then the word line WL is raised to the high level to turn on the transistors M5 and M6. At this time, voltages applied to internal nodes Node1 and Node2 appear on bit line BL and inverted bit line XBL. Therefore, whether the logical data written in the memory cell 11 is "1" or "0" by comparing (differential amplifying) each voltage between the bit line BL and the inverted bit line XBL Can be read out.

  As described above, in the memory cell 11 having the 6T-4C structure, basically the same read / write operation as that of the SRAM having the 6T structure is performed.

  The store operation of memory cell 11 is an operation of transferring data from internal nodes Node1 and Node2 to ferroelectric capacitors FC1 to FC4 for non-volatilization, transitioning from the active state to the sleep state (power supply voltage VDD for the inverter loop Before the supply is cut off). More specifically, at the time of the store operation of the memory cell 11, the plate lines PL1 and PL2 are both pulse-driven to set the residual polarization states of the ferroelectric capacitors FC1 to FC4.

  For example, it is assumed that the memory cell 11 stores logic data "1", that is, the case where the internal node Node1 is at high level and the internal node Node2 is at low level. In this case, while the plate lines PL1 and PL2 are at a low level, no voltage is applied across the ferroelectric capacitors FC2 and FC4, and the voltages across the ferroelectric capacitors FC1 and FC3 are reversed. A voltage of polarity is applied. On the other hand, while the plate lines PL1 and PL2 are at the high level, no voltage is applied between both ends of the ferroelectric capacitors FC2 and FC4, and the polarities opposite to each other between both ends of the ferroelectric capacitors FC1 and FC3 Voltage is applied. As a result, the remanent polarization state of the ferroelectric capacitors FC1 to FC4 is that the ferroelectric capacitors FC1 and FC3 have opposite polarities, the ferroelectric capacitors FC2 and FC4 have opposite polarities, and the ferroelectric capacitors FC1 and FC2 have opposite polarities. The polarities and the ferroelectric capacitors FC3 and FC4 have opposite polarities to each other. When the logic data "0" is stored in the memory cell 11, the remanent polarization states of the ferroelectric capacitors FC1 to FC4 are reverse to the above.

  Thereafter, the supply of the power supply voltage VDD is cut off, and transition from the active state to the sleep state is performed. However, the remanent polarization states of the ferroelectric capacitors FC1 to FC4 are all maintained in the state before the power is turned off. This state corresponds to a state in which data is transferred from internal nodes Node1 and Node2 to ferroelectric capacitors FC1 to FC4 to be nonvolatile.

  The recall operation of memory cell 11 is an operation of restoring data from ferroelectric capacitors FC1 to FC4 to internal nodes Node1 and Node2, and when returning from the sleep state to the active state (supply of power supply voltage VDD to the inverter loop resumes) Before being done). More specifically, at the time of the recall operation of memory cell 11, one of plate lines PL1 and PL2 is pulse driven, and voltages corresponding to the residual polarization states of ferroelectric capacitors FC1 to FC4 are applied to internal nodes Node1 and Node2. It is induced.

  For example, it is assumed that logic data "1" is stored in the ferroelectric capacitors FC1 to FC4. In this case, when the plate line PL1 is switched from the low level to the high level, a voltage wkH (weak which is relatively higher than the internal node Node2) is applied to the internal node Node1 according to the remanent polarization state of the ferroelectric capacitors FC1 and FC3. high) is induced. On the other hand, a voltage wkL (weak low) relatively lower than that of the internal node Node1 is induced in the internal node Node2 according to the remanent polarization state of the ferroelectric capacitors FC2 and FC4. That is, a voltage difference corresponding to the residual polarization state of the ferroelectric capacitors FC1 to FC4 is generated between the internal node Node1 and the internal node Node2.

  Thereafter, when the supply of power supply voltage VDD to the inverter loop is resumed, internal node Node1 is pulled high from unstable voltage wkH by the amplification action of the inverter loop, and internal node Node2 is pulled low from unstable voltage wkL. It is lowered to the level. In this state, data is restored from the ferroelectric capacitors FC1 to FC4 to the internal nodes Node1 and Node2. When the logic data "0" is stored in the ferroelectric capacitors FC1 to FC4, the voltages induced on the internal nodes Node1 and Node2 by the pulse driving of the plate line PL1 become reverse to the above.

First Embodiment
Next, a bit line non-precharge method in which the bit line and the inverted bit line are not precharged in the read / write operation will be described.

  FIG. 4 is a diagram for explaining the necessity of bit line precharging in the SRAM memory cell of 6T structure. As shown in the figure, a single word line WL is commonly connected to a plurality of SRAM memory cells 11-1 and 11-2 belonging to the same row. On the other hand, bit lines BL1 and BL2 and inverted bit lines XBL1 and XLB2 corresponding to the respective SRAM memory cells 11-1 and 11-2 belonging to different columns are connected.

  When reading / writing to the SRAM memory cell 11-1, the word line WL is raised to the high level. As a result, the SRAM memory cell 11-1 to be read / written is connected to the corresponding bit line BL1 and inverted bit line XBL1. However, the word line WL is also connected to the SRAM memory cell 11-2 which is not the read / write target. Therefore, when the word line WL is raised to the high level, the SRAM memory cell 11-2 other than the read / write target is also connected to the corresponding bit line BL2 and inverted bit line XBL2.

  The internal nodes of the SRAM memory cells 11-1 and 11-2 are only accompanied by a parasitic capacitor Cp1 of very small capacity. On the other hand, a parasitic capacitor Cp2 having a larger capacity is attached to the bit line BL and the inverted bit line XBL, which have a very long wiring length.

  Therefore, when the word line WL is raised to a high level to read / write to the SRAM memory cell 11-1, the bit line BL2 and the inverted bit line XBL2 connected to the SRAM memory cell 11-2 are selected. In the non-precharged state (the parasitic capacitor Cp2 is not charged), charge redistribution between the parasitic capacitor Cp1 and the parasitic capacitor Cp2 may cause data corruption of the SRAM memory cell 11-2.

  In order to prevent the above-described data corruption, in the conventional operation, before the word line WL is raised to the high level, the bit line BL2 and the inverted bit line XBL2 connected to the SRAM memory cell 11-2 other than the read / write target A predetermined voltage (VDD or VDD / 2) is applied to the bit line precharge method to previously charge the parasitic capacitor Cp2.

  On the other hand, ferroelectric capacitors FC1 to FC4 having a much larger capacity than the parasitic capacitance Cp2 are connected to the internal nodes Node1 and Node2 of the memory cell 11 (ferroelectric shadow memory) shown in FIG. Therefore, even when bit line BL and inverted bit line XBL are not precharged when word line WL is raised to the high level, charges of parasitic capacitance Cp2 and ferroelectric capacitors FC1 to FC4 are generated. The voltage fluctuation range of the internal nodes Node1 and Node2 due to the redistribution is extremely small.

  However, conventionally, even during operation of the ferroelectric shadow memory, bit line precharging is performed for semi-blind purposes by following the driving method of the SRAM memory cell as the base.

  The inventors of the present application have doubts over the significance of such bit line precharging, and as a result of intensive studies, ferroelectric capacitors FC1 to FC4 provided mainly for nonvolatility of data are active. The novel knowledge that it can contribute to the prevention of data corruption of the memory cell 11 is acquired, and it is concluded that the bit line precharging is not necessary at the operation of the ferroelectric shadow memory.

  FIG. 5 is a diagram showing a bit line non-precharge method in the ferroelectric shadow memory. As shown in the column (a), at the time of operation of the SRAM memory cell, precharging of the bit line BL and the inverted bit line XBL is performed before raising the word line WL to the high level. On the other hand, as shown in the column (b), during operation of the ferroelectric shadow memory, the word line WL is made high level without precharging the bit line BL and the inverted bit line XBL based on the above-mentioned findings. You can raise it.

  That is, in the semiconductor storage device 100 employing the ferroelectric shadow memory as the memory cell 11, the memory controller 2 is connected to a memory cell other than the read / write target when accessing the read / write target memory cell. It is desirable to configure the operation sequence so as to drive the word line WL and turn on the transistors M5 and M6 without performing the precharging of the bit line BL and the inverted bit line XBL.

  Further, in the case of employing the bit line non-precharge method, it is desirable to provide an equalizer which makes the pair of bit lines BL and the inverted bit line XBL have the same potential.

  FIG. 6 is a diagram showing a configuration example for realizing equalization between the bit line BL and the inverted bit line XBL. In this configuration example, the transmission gate SW is connected between the pair of bit lines BL and the inversion bit line XBL. Although not shown in the figure, the transmission gate SW is provided for each pair of a plurality of bit lines BL and inverted bit lines XBL.

  The transmission gate SW is on / off controlled by the memory controller 2. More specifically, when the memory controller 2 accesses a read / write target memory cell, transmission between the bit line BL and the inverted bit line XBL connected to a read / write non-target memory cell is performed. Turn on the gate SW.

  By turning on the transmission gate SW, the bit line BL and the inverted bit line XBL connected to the memory cell other than the read / write target can be short-circuited to make them have the same potential. Therefore, occurrence of the worst case (for example, a high level is applied to the internal node on the low level side and a low level is applied to the internal node on the high level side) which may cause data corruption of the memory cell 11 Since this can be avoided in advance, the prevention of data corruption of the memory cell 11 can be further ensured.

  As described above, in the first embodiment, using the large capacity ferroelectric capacitors FC1 to FC4 connected to the internal nodes Node1 and Node2 of the memory cell 11, the bit line precharging at the time of read / write operation is performed. A semiconductor memory device 100 is proposed which operates with only equalization using a transmission gate SW while omitting charge. By adopting this configuration, it is possible to significantly reduce the power consumption at the time of read / write operation.

  FIG. 7 shows the usefulness of the bit line non-precharge method. As shown in the figure, by adopting the bit line non-precharge method, it is possible to reduce the power consumption during the write operation by 74% compared to the conventional case, and the power consumption during the read operation compared with the conventional case. It is possible to reduce by%.

  The equalizing method in which the bit line BL and the inverted bit line XBL are shorted by the transmission gate SW is superior to the conventional bit line precharging method also in terms of high speed operation.

  FIG. 8 is a diagram showing the advantages of the above equalization method. As shown in the column (a) of the figure, when the bit line BL and the inverted bit line XBL are precharged with the power supply voltage VDD, the bit line BL and the inverted bit line XBL are at the worst case (BL = XBL = GND). It takes time T1 to reach the power supply voltage VDD. Therefore, the bit line precharge time must be set to time T1 or more.

  On the other hand, as shown in the column (b) of this figure, when shorting between the bit line BL and the inverted bit line XBL, the time T2 required for the bit line BL and the inverted bit line XBL to have the same potential is Even in the worst case (BL = VDD, XBL = GND), it is shorter than the above time T1. Therefore, the equalizing process can be completed promptly to raise the word line WL to the high level, which can shorten the read / write time. In addition, shortening the read / write time directly leads to shortening of the active time (longening of the sleep time), which can also contribute to power saving of the entire system.

  Furthermore, adopting the bit line non-precharge method can contribute to the increase in capacity of the semiconductor memory device 10. Conventionally, when performing read / write of a certain memory cell, all bit lines BL and inverted bit lines XBL connected to memory cells other than the read / write target are precharged. Therefore, in view of the power required for bit line precharging, the number of memory cells 11 connected to one word line WL (and the wiring length of the word line WL) naturally has an upper limit. Further, as the interconnection lengths of the bit line BL and the inverted bit line XBL extend, the capacitance of the parasitic capacitor Cp2 accompanying this increases, and therefore, a larger pre-charge power is required. Therefore, the wiring lengths of the bit line BL and the inverted bit line XBL naturally have an upper limit.

  On the other hand, if the bit line non-precharge method is adopted, the memory cell array 10 can be enlarged (word line WL or extension of bit line BL and inverted bit line XBL) without considering precharge power. Therefore, the area ratio of the memory cell array 10 (area ratio of the memory cell array 10 and the peripheral circuits 20 to 70) occupied in the entire memory block 1 can be increased, so the device size of the semiconductor memory device 100 is unnecessarily increased. It is possible to increase the storage capacity (storage density per unit area) without.

  Although the ferroelectric shadow memory has been exemplified as an application target of the bit line non-precharge method in the above description, the application target is not limited to this, and for example, a 6T structure SRAM memory cell is used as a base If the node capacitor having a capacitance larger than that of the parasitic capacitor Cp2 is connected to the internal node thereof, the above-mentioned bit line non-precharge method can be suitably applied. That is, the node capacitors that can contribute to the data retention of the memory cell 11 are not necessarily limited to the ferroelectric capacitors FC1 to FC4 connected to the plate lines PL1 and PL2.

Second Embodiment
Next, a plate line charge sharing method will be described in which the charges of the plate lines PL1 and PL2, which are sequentially driven at the time of store / recall, are shared.

  FIG. 9 is a diagram showing a configuration example for realizing plate line charge sharing. As described above, semiconductor memory device 100 of this configuration example includes a plurality of memory cells 11 arranged in a matrix, plate lines PL1 (a, b,...) Connected to the plurality of memory cells 11, and A plate line driver 40 for driving PL2 (a, b, ...), plate lines PL1 (a, b, ...) and PL2 (a, b, ...), and a memory for controlling access to a plurality of memory cells 11 And a controller 2.

  The semiconductor memory device 100 of this configuration example further includes a plurality of transmission gates SW1 (ab, bc,...) And SW2 (ab, bc,...) Connected between adjacent plate lines. More specifically, transmission gate SW1ab is connected between plate line PL1a and plate line PL1b, and transmission gate SW1bc is connected between plate line PL1b and plate line PL1c (not shown). ing. Similarly, transmission gate SW2ab is connected between plate line PL2a and plate line PL2b, and transmission gate SW2bc is connected between plate line PL2b and plate line PL2c (not shown).

  The memory controller 2 uses the plate line driver 40 to pulse drive the plate lines PL1 (a, b,...) And PL2 (a, b,...) Sequentially when storing / recalling the data of the memory cell 11 .

  At this time, the memory controller 2 performs charge sharing between the already charged plate line and the uncharged plate line before pulsing the uncharged plate line using the plate line driver 40. More specifically, the memory controller 2 turns on the transmission gate between the charged and uncharged plate lines before pulsing the uncharged plate lines using the plate line driver 40. Short circuit between the two plates. In the following, this will be described in more detail with reference to FIG.

  FIG. 10 is a timing chart showing one operation example of the plate line charge sharing, and from the top, the output enable signal OUT_EN of the plate line driver 40, the applied voltage of the plate line PL1 (a, b, c), and the transmission The on / off state of the gate SW1 (ab, bc) is depicted. The plate line PL2 (a, b, ...) and the transmission gate SW2 (a, b, ...) are similar to the plate line PL1 (a, b, ...) and the transmission gate SW1 (a, b, ...). Because it is controlled by behavior, illustration is omitted here.

  At time t1, when the output enable signal OUT_EN of the plate line driver 40 is raised to a high level (logical level at output enable), the plate line PL1a is charged to the power supply voltage VDD.

  At time t2, when the output enable signal OUT_EN of the plate line driver 40 falls to a low level, the plate line PL1a is brought into a floating state. Therefore, the plate line PL1a is maintained substantially at the power supply voltage VDD even after time t2.

  When transmission gate SW1ab is turned on at time t3, conduction is established between already charged plate line PL1a and uncharged plate line PL1b, and charge sharing is performed until both have the same voltage (= VDD / 2). (Charge redistribution) is performed.

  When transmission gate SW1ab is turned off at time t4, plate line PL1a is disconnected from plate line PL1b. The plate lines PL1a and PL1b are maintained at substantially the same voltage (= VDD / 2) even after time t4.

  At time t5, when output enable signal OUT_EN of plate line driver 40 is raised to a high level (logical level at output enable), plate line PL1b is charged to power supply voltage VDD while plate line PL1a is at ground voltage GND. Is discharged. At this time, the plate line PL1 b is already charged to VDD / 2. Therefore, the power to be supplied from the plate line driver 40 can be less power (ideally 1/2) than when the plate line PL1a is initially charged.

  After time t6, charge sharing is performed between the already charged plate line and the uncharged plate line in the same manner as described above.

  The floating periods shown at time t2 to t3, time t4 to t5, and time t6 to t7 can be shortened or omitted as appropriate.

  As described above, when the plate line charge sharing method is employed, unlike the conventional method in which a plurality of plate lines are charged individually, not all the charges accumulated in the previous plate line charge are discarded, but one of them. Since the part can be diverted to the next plate line charge, the power consumption of the plate line driver 40 can be largely reduced (ideally, to about one half).

  In addition, although the example which drives a plate line | wire one by one sequentially was mentioned in FIG. 10, it is good also as a structure which divides and drives a plurality of plate lines in multiple times, for example. However, as the number of plate lines driven simultaneously increases, the peak value of the drive current increases, and the power required for the first charge increases, so the number of plate lines simultaneously driven considers the trade-off between speed and power. And design appropriately.

  FIG. 11 is a diagram showing the usefulness of the plate line charge sharing method. As shown in the figure, by adopting the plate line charge sharing method, it is possible to reduce the power consumption during store operation by 22% compared to the conventional case, and the power consumption during recall operation compared to the conventional case It is possible to reduce by 11%.

Third Embodiment
As shown in FIG. 2, the ferroelectric shadow memory having the 6T-4C structure has large capacitance ferroelectric capacitors FC1 to FC4 connected to the internal nodes Node1 and Node2. Therefore, the ferroelectric shadow memory requires a long time to write data when active as compared to the SRAM of 6T structure. In the following, as means for solving such a problem, a word line boosting method for boosting the word line WL at the time of write operation will be described.

  FIG. 12 is a circuit diagram showing one configuration example of the word line driver 20. As shown in FIG. The word line driver 20 of this configuration example includes P-channel field effect transistors 21 and 22, an N-channel field effect transistor 23, an inverter 24, and a capacitor element 25.

  The source of the transistor 21 is connected to the power supply terminal. The drain of the transistor 21 is connected to the source of the transistor 22. The drains of the transistors 22 and 23 are both connected to the word line WL. The source of the transistor 23 is connected to the ground terminal. The gates of the transistors 21 and 23 are both connected to the output end of the inverter 24. The input end of the inverter 24 is connected to the application end of the word line enable signal WL_EN. The gate of the transistor 22 is connected to the application end of the boost enable signal BST_EN. Capacitor element 25 is connected between the application end of boost enable signal BST_EN and word line WL.

  The transistors 21 and 23 and the inverter 24 function as an output stage for driving the word line WL of the memory cell 11 according to the word line enable signal WL_EN. The transistor 22 and the capacitor element 25 function as a boost stage that raises the voltage applied to the word line WL more than the power supply voltage VDD of the output stage by performing coupling control of the capacitor element 25 according to the boost enable signal BST_EN. .

  Conventionally, (a) MOS [metal-oxide-semiconductor] capacitor, (c) MIM [metal-insulator-metal] capacitor, or (d) MOM [capacitor element 25 for forming the above-mentioned boost stage. [metal-oxide-metal] capacitors were commonly used. On the other hand, in the word line driver 20 of this configuration example, (b) a ferroelectric capacitor (Fe capacitor) is used as the capacitor element 25.

  FIG. 13 is an area comparison table of various capacitors (the area of the word line driver 20 using various capacitors of the same capacity, and the area of the 16 Kbit memory block 1). As shown in the figure, the ferroelectric capacitor has the same capacitance with a smaller occupied area as compared with other capacitors. Therefore, by using a ferroelectric capacitor as capacitor element 25, it is possible to realize word line boost without unnecessarily increasing the circuit area of word line driver 20 (and memory block 1). .

  Further, for the capacitor element 25 forming the boost stage, since the linearity of the capacitance is not so important, a ferroelectric capacitor having a large polarization characteristic can be used without any problem. In addition, since ferroelectric capacitors are originally incorporated in ferroelectric shadow memories to realize their nonvolatility, the semiconductor memory device 100 can be manufactured even if the ferroelectric capacitors are adopted as the capacitor elements 25. There is no change in the process.

  FIG. 14 is a timing chart showing an operation example of the word line boost, in which the word line enable signal WL_EN, the boost enable signal BST_EN, and the applied voltage of the word line WL are depicted sequentially from the top.

  At the time of the write operation to the memory cell 11, first, the word line enable signal WL_EN is raised to the high level, and the voltage applied to the word line WL is increased. At this point, boost enable signal BST_EN is maintained at low level. Therefore, since a potential difference occurs between both ends of the capacitor element 25, the capacitor element 25 is charged.

  When a predetermined delay time (boost delay) elapses after the word line enable signal BL_EN is raised to the high level, the boost enable signal BST_EN is raised to the high level (for example, VDD = 1.8 V). At this point in time, charge is charged between both ends of the capacitor element 25 (ferroelectric capacitor), and therefore the word line WL is lifted to the power supply voltage VDD + α (for example, 1.8 V + α) according to the charge conservation law.

  As a result, the conductivity of the access transistors M5 and M6 forming the memory cell 11 is larger than when the power supply voltage VDD is applied to the word line WL (without boosting). Therefore, it is possible to shorten the time required for the data writing at the active time without unnecessarily increasing the drive capability of the write circuit 60.

  FIG. 15 shows the usefulness of the word line boosting method. The behavior without word line boost is shown in the (a) column of this figure, and the behavior with word line boost is shown in the (b) column of this figure. As can be seen by comparing the (a) column and the (b) column, by adopting the above-described word line boosting method, the data rewrite time until the applied voltages of the internal nodes Node1 and Node2 cross at the time of the write operation It becomes possible to shorten.

  FIG. 16 is a diagram for describing optimization of boost delay. In the following description, the delay time from the rising of the word line enable signal WL_EN to the high level to the rising of the boost enable signal BST_EN to the high level is referred to as a boost delay Tbd. In addition, the time from the rise of the word line enable signal EN to the high level to the crossing of the voltages applied to the internal nodes Node1 and Node2 is referred to as a data rewrite time Twr. Further, a boost delay that can shorten the data rewrite time Twr most is called an ideal boost delay T0.

  FIG. 17 and FIG. 18 are diagrams showing the change behavior of the data rewrite time Twr accompanying the extension of the boost delay Tbd. FIG. 17 shows the case where the boost delay Tbd is shorter than the ideal boost delay T0 (Tbd <T0), and FIG. 18 shows the case where the boost delay Tbd is longer than the ideal boost delay T0 (Tbd> T0). There is.

  As shown in FIG. 17, in the region of Tbd <T0, the potential of the word line WL after boosting rises as the boost delay Tbd is extended and approaches the ideal boost delay T0, so the improvement effect of the data rewrite time Twr is large. Become.

  On the other hand, as shown in FIG. 18, in the region of Tbd> T0, the longer the boost delay Tbd is made to deviate from the ideal boost delay T0, the shorter the time during which the word line WL is boosted. The improvement effect of

  FIG. 19 is a correlation diagram between the boost delay Tbd and the data rewrite time Twr. As shown in the figure, the data rewrite time Twr is shortest when the boost delay Tbd matches the ideal boost delay T0, and becomes longer as the boost delay Tbd deviates from the ideal boost delay T0. In the following description, the boost delay Tbd where the boost delay Tbd is too short and the data rewrite time Twr becomes equal to that without boost is taken as the lower limit boost delay T1. Further, the boost delay Tbd where the boost delay Tbd is too long and the data rewrite time Twr becomes equal to that without boost is taken as the upper limit boost delay T2.

  FIG. 20 is a diagram for explaining determining factors of the lower limit boost delay T1, the upper limit boost delay T2, and the ideal boost delay T0.

  As shown in column (a) and column (b) of this figure, the lower limit boost delay T1 and the ideal boost delay T0 each receive an applied voltage of the word line WL when the boost enable signal BST_EN is raised to a high level. It is decided by whether it is rising to some extent. On the other hand, as shown in the column (c) of the figure, the upper limit boost delay T2 is determined by how much the potential difference between the internal nodes Node1 and Node2 is reduced when the boost enable signal BST_EN is raised to the high level. .

  FIG. 21 is a diagram showing the change behavior of the ideal boost delay T0 according to the rise time of the word line WL.

  The rise time of the word line WL and the data write time fluctuate due to manufacturing variations of the transistors forming the semiconductor memory device 100 (particularly, the word line driver 20). Therefore, the lower limit boost delay T1, the upper limit boost delay T2, and the ideal boost delay T0 also fluctuate due to manufacturing variations of the transistors.

  For example, as shown in the column (a) of the figure, when the rise time of the word line WL becomes short, the ideal boost delay T0 also becomes short. Conversely, as shown in the column (b) of this figure, when the rise time of the word line WL becomes long, the ideal boost delay T0 also becomes long.

  Thus, the ideal boost delay T0 fluctuates depending on the rise time of the word line WL. Therefore, in order to make the most of the improvement effect of the data rewrite time Twr by the word line boost method, it is necessary to generate the boost delay Tbd according to the fluctuation of the ideal boost delay T0.

  FIG. 22 is a circuit diagram showing an exemplary configuration of delay stage 26. Referring to FIG. The delay stage 26 of this configuration example is incorporated in the front stage of the word line driver 20, and delays the word line enable signal WL_EN by the boost delay Tbd to generate the boost enable signal BST_EN.

  More specifically, the delay stage 26 delays the word line enable signal WL_EN by the boost delay Tbd by providing a predetermined delay to the reference enable signal DRV_EN to generate the word line enable signal WL_EN and the word line enable signal WL_EN. And an y-stage inverter chain 262 for generating a boost enable signal BST_EN.

  The transistors forming the inverter chains 261 and 262 are all formed in the same process as other transistors forming the word line driver 20. Therefore, even if transistor manufacturing variations occur, the characteristics of the word line driver 20 and the delay stage 26 change with the same behavior.

  More specifically, when the drive capability of the word line driver 20 is increased due to the manufacturing variation of the transistor, the rise time of the word line WL is shortened and the ideal boost delay T0 is also shortened (FIG. 21 mentioned earlier). See (a)). At this time, since the drive capability of the inverter chain 262 also increases, the boost delay Tbd follows the ideal boost delay T0 and becomes shorter.

  Conversely, when the drive capability of the word line driver 20 decreases due to manufacturing variations of the transistors, the rise time of the word line WL becomes longer, and the ideal boost delay T0 also becomes longer (preceding FIG. 21 (b) column See). At this time, since the drive capability of the inverter chain 262 also decreases, the boost delay Tbd follows the ideal boost delay T0 and becomes longer.

  As described above, if the delay stage 26 is formed by the inverter chains 261 and 262, the boost delay Tbd can be appropriately varied in accordance with the ideal boost delay T0. Therefore, it is possible to maximize the effect of improving the data rewrite time Twr by the word line boosting method without depending on the manufacturing variation of the transistor.

  FIG. 23 illustrates the usefulness of delay stage 26. Referring to FIG. The boost delay Tbd generated by the delay stage 26 (inverter chain) is adjusted so that the boost delay Tbd matches the ideal boost delay T0 at the TT corner at room temperature (25 ° C.). As shown in the figure, the boost delay Tbd generated by the delay stage 26 has any process corner (FF [fast / fast], SF [slow / fast], TT [typical / typical], FS [fast / fast] Even in [slow] and SS [slow / slow]), they coincide with the ideal boost delay T0. The maximum difference between the ideal boost delay T0 and the boost delay Tbd is -18% of the FF corner at -40.degree.

  FIG. 24 is a table showing various conditions of SPICE simulation used to evaluate the performance of the word line boost method. As shown in the figure, the simulation conditions are: process: 130 nm, temperature: 25 ° C., power supply voltage: 1.5 V, macro configuration: 16 bits / word, number of memory cells connected to word line BL: 256, and The number of memory cells connected to the bit line BL is 256.

  FIG. 25 is a comparison diagram of write access time. As shown in the figure, the SPICE simulation shows that the write access time is improved by at least 21%.

  FIG. 26 is a table showing simulation results (TT corner, 25 ° C.) of word line boost. As shown in the figure, with the adoption of the word line boosting method described above, the power consumption of the word line driver 20 is increased by 47.8% as compared to the case without the boosting. However, in the whole of the 16 Kb memory block 1, the power consumption was increased by only 1.3% as compared with that without the boost.

  That is, according to the word line boosting method described above, it is possible to shorten the write access time by 21% with an increase in power of only 1.3%.

  Although the word line driver for driving the ferroelectric shadow memory has been described above as an example, the application target of the word line boosting method is not limited to this. For example, an SRAM memory cell of 6T structure is used. The word line boosting method described above can be suitably applied even in the case where a drive target is a base whose node is connected to a node capacitor of a larger capacity than the parasitic capacitor Cp2 at its internal node.

Fourth Embodiment
In order to non-volatile the memory cell 11 (ferroelectric shadow memory), the plate line driver 40 is used to pulse-drive the plate lines PL1 and PL2 before blocking / returning the power supply voltage VDD. It is necessary to perform store / recall operation.

  However, since the ferroelectric capacitors FC1 to FC4 connected to the plate lines PL1 and PL2 have large capacitances, it takes a long time to charge the plate lines PL1 and PL2 to a predetermined potential. In the following, as a means for shortening the charge time of plate lines PL1 and PL2 to speed up the store / recall operation, a plate line driver boost method for enhancing the driving capability of plate line driver 40 at the time of store / recall will be described. .

  FIG. 27 is a circuit diagram showing a configuration example of the plate line driver 40. As shown in FIG. The plate line driver 40 includes P-channel field effect transistors 41 and 42, N-channel field effect transistors 43-45, an inverter 46, and a ferroelectric capacitor 47.

  The source of the transistor 41 is connected to the power supply end. The drains of the transistors 41 and 43 are both connected to the application end (corresponding to a boost target node) of the second plate line enable signal PL_EN2. The source of the transistor 43 is connected to the drain of the transistor 44. The source of the transistor 44 is connected to the ground terminal. The gates of the transistors 41 and 44 are both connected to the application end of the plate line enable signal PL_EN. The gate of the transistor 43 is connected to the output end of the inverter 46 (application end of the inverted boost enable signal B_ENB). The input end of the inverter 46 is connected to the application end of the boost enable signal B_EN. The ferroelectric capacitor 47 is connected between the output end of the inverter 46 and the application end of the second plate line enable signal PL_EN2. The source of the transistor 42 is connected to the power supply end. The drains of the transistors 42 and 45 are both connected to the plate line PL. The source of the transistor 45 is connected to the ground terminal. The gates of the transistors 42 and 45 are both connected to the application end of the second plate line enable signal PL_EN2.

  The transistors 41 and 44 function as a first output stage (first inverter stage) that generates a second plate line enable signal PL_EN2 in response to the plate line enable signal PL_EN. The transistors 42 and 45 function as a second output stage (second inverter stage) that drives the plate line PL of the memory cell 11 according to the second plate line enable signal PL_EN2. Also, the transistor 43, the inverter 46, and the ferroelectric capacitor 47 pull down the second plate line enable signal PL_EN2 to a negative voltage by performing coupling control of the ferroelectric capacitor 47 according to the boost enable signal B_EN. Function as a boost stage that enhances the drive capability of the second output stage.

  As in the word line driver 20 described above, it is desirable to use a ferroelectric capacitor 47 having a large capacity per unit area as a capacitor element forming the boost stage. However, in place of the ferroelectric capacitor 47, it is also possible to use a MOS capacitor, an MIM capacitor, or a MOM capacitor.

  FIG. 28 is a timing chart showing an operation example of the plate line driver boost, and the plate line enable signal PL_EN, the inverted boost enable signal B_ENB, the second plate line enable signal PL_EN2, and the plate line PL in this order from the top of the page. The applied voltage of is depicted.

  In the store / recall operation of the memory cell 11, first, the plate line enable signal PL_EN is raised to the high level, and the second plate line enable signal PL_EN2 is pulled to the low level. As a result, the transistor 42 is turned on, and the voltage applied to the plate line PL rises. At this point, the boost enable signal B_EN remains at the low level, and the inverted boost enable signal B_ENB is maintained at the high level. Therefore, since a potential difference occurs between both ends of the ferroelectric capacitor 47, the ferroelectric capacitor 47 is charged.

  Next, at the timing when the second plate line enable signal PL_EN2 becomes the ground voltage GND, the boost enable signal B_EN becomes high level, and the inverted boost enable signal B_ENB falls to low level. At this time, since the charge is charged between both ends of the ferroelectric capacitor 47, the second plate line enable signal PL_EN2 is pulled down to a negative voltage (= GND−α) according to the charge conservation law.

  As a result, the conductivity of the transistor 42 is larger than when the second plate line enable signal PL_EN2 is set to the ground voltage GND (without the boost), and hence the drivability of the second output stage (the transistor 42 On current) is increased. As described above, the charge time of the plate line PL can be shortened to accelerate the store / recall operation by increasing the driving capability of the plate line driver 40 instead of increasing the high level voltage of the plate line PL. It becomes possible.

  FIG. 29 is a table showing simulation results (TT corner, 25 ° C.) of plate line driver boost. The simulation conditions are as shown in FIG. 24 described above. As shown in this figure, if the plate line driver boost method described above is adopted, the result is that the plate line charge time is reduced by about 33% with only a 0.43% increase in power. The

  FIG. 30 is a concept showing the action and effect (shortening of active time and reduction of power consumption) at the system level when the above word line boost method and plate line driver boost method are applied to an intermittent start sensing application. FIG. FIG. 31 is a comparison table of active time.

  In this evaluation, a sensor network for environmental monitoring is assumed as an example of the intermittent activation type application. In this sensor network, the MCU [micro control unit] of the sensor returns from the sleep state to the active state every one second, reads / writes the measurement data of 160 bits, performs the arithmetic processing, and then becomes active again. Transition from state to sleep state. In the sleep state, the power supply to the sensor is cut off.

  As shown in both figures, the active time is reduced by 4% when the word line boost method is adopted alone, and the active time is further reduced by 25% when the plate line driver boost method is adopted. It was done. Finally, when the word line boosting method and the plate line driver boosting method are used in combination, the result is obtained that the total access time can be reduced by 29% by the increase of the active power up to 1.3%.

Fifth Embodiment
FIG. 32 is a diagram for explaining a recall failure due to aged deterioration. As shown in the column (a) of this figure, it may be a normal memory cell having a sufficiently large recall margin (a potential difference between internal nodes Node1 and Node2 generated at the time of recall operation, hereinafter simply referred to as margin) at the manufacturing time. For example, even if the margin is slightly reduced due to aging, data stored before power-off can be correctly recalled.

  On the other hand, as shown in the column (b) of this figure, in the case of a defective memory cell with a small margin at the manufacturing time, the margin is reduced due to age deterioration even though the recall operation can be correctly performed immediately after shipment. , There is a high risk of recall failure. Therefore, in order to improve the reliability of the semiconductor memory device 100, it is important to perform a margin test of the memory cell 11 in a pre-shipment inspection to screen for a defective memory cell.

  Therefore, in the following, a margin test method for detecting a defect of a ferroelectric capacitor by arbitrarily setting the potential of the bit line from outside the chip is proposed.

  FIG. 33 is a circuit diagram showing a first configuration example of a semiconductor memory device to be subjected to a margin test. The semiconductor memory device 100 of this configuration example is basically the same configuration as that of FIG. 2 described above, and has external terminals TA and TB, and transmission gates SWA and SWB.

  The external terminal TA is a terminal for applying an arbitrary analog voltage to the bit line BL from the outside of the semiconductor memory device 100. The external terminal TB is a terminal for applying an arbitrary analog voltage to the inversion bit line XBL from the outside of the semiconductor device 100. The transmission gate SWA is connected between the external terminal TA and the bit line BL, and turned on / off in response to the test enable signal TEST1_E. The transmission gate SWB is connected between the external terminal TB and the inversion bit line XBL, and turned on / off according to the test enable signal TEST2_E.

  Further, in the drawing, power supply switches M7 and M8 for turning on / off power supply to the inverter loop are clearly shown as circuit elements forming the memory cell 11. The power supply switch M7 is a P-channel type field effect transistor connected between the power supply terminal and the inverter loop, and is turned on / off in response to the inverted memory cell enable signal MC_EN. On the other hand, the power switch M8 is an N-channel type field effect transistor connected between the inverter loop and the ground terminal, and is turned on / off according to the memory cell enable signal MC_E. However, these power switches M7 and M8 are only the depiction thereof omitted in FIG. 2 and are not circuit elements newly added separately in this configuration example. The read circuit 70 (sense amplifier) is switched between enable / disable in response to the sense amplifier enable signal SA_E.

  FIG. 34 is a timing chart showing a pass pattern (passing pattern) of the first test targeting the semiconductor memory device 100 of the first configuration example (FIG. 33) as an inspection target, and plate lines PL1 and PL2, word from top to bottom The states of line WL, sense amplifier enable signal SA_E, internal nodes Node1 and Node2, bit line BL, inverted bit line XBL, test enable signals TEST1_E and TEST2_E, and memory cell enable signal MC_E and inverted memory cell enable signal MC_EN are depicted. It is done.

  In period (1), the plate lines PL1 and PL2 are pulse-driven, and data (Node1 = H, Node2 = L in the example of this figure) are stored in the ferroelectric capacitors FC1 to FC4. Thereafter, the memory cell enable signal MC_E is raised to the low level, and the inverted memory cell enable signal MC_EN is raised to the high level, whereby both of the power switches M7 and M8 are turned off to supply the power to the inverter chain. It is cut off.

  In period (2), the test enable signal TEST2_E is raised to a high level for a predetermined period, whereby the transmission gate SWB is turned on, and an arbitrary reference voltage REF is applied from the external terminal TB to the inversion bit line XBL. Ru.

  In period (3), with the inverter loop disabled (MC_E = L, MC_EN = H), the plate line PL1 is pulse-driven (raised to a high level), whereby the recall operation of the memory cell 11 is performed. To be done. At this time, voltages wkH and wkL corresponding to the residual polarization states of the ferroelectric capacitors FC1 to FC4 appear on the internal nodes Node1 and Node2, respectively.

  In period (4), word line WL is raised to a high level to turn on both transistors M5 and M6, whereby internal node Node1 and bit line BL, and internal node Node2 and an inverted bit line Each potential is matched with each other between XBL and XBL. That is, the bit line BL and the internal node Node1 both have the voltage wkH, and the inverted bit line XBL and the internal node Node2 both have the reference voltage REF.

  In period (5), the sense amplifier enable signal SA_E is raised to the high level, and the read operation by the read circuit 70 is performed. That is, the voltage wkH applied to each of the bit line BL and the inverted bit line XBL is compared with the reference voltage REF.

  In the example of the present drawing, the voltage wkH recalled to the internal node Node1 is higher than the reference voltage REF. Therefore, the bit line BL and the internal node Node1 are pulled high by the differential amplification action of the read circuit 70, and the inverted bit line XBL and the internal node Node2 are pulled low. Since this state is the same as the state before power-off, the inspection result is a pass (pass).

  FIG. 35 is a timing chart showing a fail pattern (rejected pattern) of the first test targeting the semiconductor memory device 100 of the first configuration example (FIG. 33) as an inspection target, and plate lines PL1 and PL2, Each state of word line WL, sense amplifier enable signal SA_E, internal nodes Node1 and Node2, bit line BL, inverted bit line XBL, test enable signals TEST1_E and TEST2_E, and memory cell enable signal MC_E and inverted memory cell enable signal MC_EN It is depicted.

  A series of test operations per se (1) to (5) are similar to FIG. 34 described above. However, in the example of the present drawing, the voltage wkH recalled to the internal node Node1 is lower than the reference voltage REF. Therefore, the bit line BL and the internal node Node1 are pulled low by the differential amplification action of the read circuit 70, and the inverted bit line XBL and the internal node Node2 are pulled high. Since this state is the reverse of the state before the power interruption, the inspection result is a failure.

  Note that the absolute value of voltage wkH recalled to internal node Node1 can be known by checking the above inspection results (pass / fail) one by one while sweeping reference voltage REF applied to inverted bit line XBL. it can. For example, when the inspection result when applying the voltage REF1 is a pass and the inspection result when applying the voltage REF2 (> REF1) as the reference voltage REF is fail, it is that REF1 <wkH <REF2 I understand.

  In the period (2), when the test enable signal TEST1_E is raised to a high level, the transmission gate SWA can be turned on to apply an arbitrary reference voltage REF from the external terminal TA to the bit line BL. Therefore, it is possible to know the absolute value of voltage wkL recalled to internal node Node2 by checking the above inspection results while sweeping reference voltage REF applied to bit line BL in the same manner as described above. .

  Thus, the margin Vm (= wkH−wkL) of the memory cell 11 can be checked by knowing the absolute values of the voltages wkH and wkL recalled to the internal nodes Node1 and Node2. Therefore, it becomes possible to screen a defective memory cell which is highly likely to cause a recall failure due to aged deterioration by inspection before shipment.

  When external terminals TA and TB are shared by a plurality of memory cells 11, for memory cells not to be tested, bit line BL (or inverted bit line XBL) to which reference voltage REF is applied and plate lines PL1 and PL2 It is desirable to short between them. With such a configuration, data corruption does not occur in memory cells not to be tested, and therefore, when the memory cells are to be tested, there is no need to rewrite data.

  FIG. 36 is a circuit diagram showing a second configuration example of the semiconductor memory device to be subjected to the margin test. The semiconductor memory device 100 of this configuration example basically has the same configuration as that of FIG. 33 described above, and includes the word line WL1 connected to the gate of the transistor M5 and the word line WL2 connected to the gate of the transistor M6. , Have independently.

  FIGS. 37 and 38 are timing charts showing a pass pattern and a fail pattern of the second test for testing the semiconductor memory device 100 of the second configuration example (FIG. 36), respectively. And PL2, word lines WL1 and WL2, sense amplifier enable signal SA_E, internal nodes Node1 and Node2, bit line BL, inverted bit line XBL, test enable signals TEST1_E and TEST2_E, and memory cell enable signal MC_E and inverted memory cell enable signal Each state of MC_EN is depicted.

  A series of test operations per se (1) to (5) are basically the same as those in FIGS. 34 and 35 described above. However, in the second test, in the period (4), the word line WL1 is set to the high level, and the word line WL2 is maintained at the low level. That is, among the transistors M5 and M6, only the transistor M5 to which the reference voltage REF is not applied is turned on, and the transistor M6 remains turned off.

  As a result, the internal node Node2 is maintained in the state of being disconnected from the inverted bit line XBL to which the reference voltage REF is applied, and thus holds the voltage wkL obtained by the recall operation.

  With such a configuration, data corruption of internal node Node2 does not occur even if reference voltage REF is applied to inverted bit line XBL. Therefore, after measuring the absolute value of internal node Node1, the reference voltage to bit line BL is obtained. When applying the REF to measure the absolute value of the internal node Node2, the operation of rewriting the data in the memory cell 11 is unnecessary.

  FIG. 39 is a timing chart showing a pass pattern (passing pattern) of the third test targeting the semiconductor memory device 100 of the first configuration example (FIG. 33) as an inspection target, and plate lines PL1 and PL2, word from top to bottom The states of line WL, sense amplifier enable signal SA_E, internal nodes Node1 and Node2, bit line BL, inverted bit line XBL, test enable signals TEST1_E and TEST2_E, and memory cell enable signal MC_E and inverted memory cell enable signal MC_EN are depicted. It is done.

  In period (1), the plate lines PL1 and PL2 are pulse-driven, and data (Node1 = H, Node2 = L in the example of this figure) are stored in the ferroelectric capacitors FC1 to FC4. Thereafter, the memory cell enable signal MC_E is raised to the low level, and the inverted memory cell enable signal MC_EN is raised to the high level, whereby both of the power switches M7 and M8 are turned off to supply the power to the inverter chain. It is cut off.

  In period (2), the test enable signal TEST2_E is raised to a high level for a predetermined period, whereby the transmission gate SWB is turned on, and an arbitrary offset voltage OFS is applied from the external terminal TB to the inversion bit line XBL. Ru. At this time, it is desirable that the bit line BL be connected to the ground end.

  In period (3), word line WL is raised to the high level to turn on both transistors M5 and M6, whereby internal node Node1 and bit line BL, and internal node Node2 and the inverted bit line Each potential is matched with each other between XBL and XBL. As a result, the internal node Node1 becomes the ground voltage GND, and the internal node Node2 becomes the offset voltage OFS. Thus, in the third test, an offset is given between the internal node Node1 and the internal node Node2 prior to the recall operation of the memory cell 11. The offset voltage OFS is for setting the margin Vm of the memory cell 11 more strictly. Therefore, the offset voltage OFS is applied to the internal node (the internal node Node2 in the example of the present drawing) from which the relatively low voltage wkL is recalled.

  In period (4), with the inverter loop disabled (MC_E = L, MC_EN = H), the plate line PL1 is pulse-driven (rised to a high level), whereby the recall operation of the memory cell 11 is performed. To be done. At this time, voltages wkH and wkL corresponding to the residual polarization states of the ferroelectric capacitors FC1 to FC4 appear on the internal nodes Node1 and Node2, respectively. However, since the internal node Node2 is pulled up to the offset voltage OFS prior to the recall operation of the memory cell 11, the voltage value after the recall operation is (wkL + OFS).

  In period (5), the inverter loop is enabled (MC_E = H, MC_EN = L), and the logic levels of internal nodes Node1 and Node2 are determined. In the example of this figure, the voltage wkH recalled to the internal node Node1 is higher than the offset voltage (wkL + OFS) recalled to the internal node Node2. Therefore, the internal node Node1 is pulled high by the amplification action of the inverter loop, and the internal node Node2 is pulled low. Since this state is the same as the state before power-off, the inspection result is a pass (pass). In order to know whether or not the recall result of memory cell 11 is correct, a normal read operation is performed using read circuit 70, and each voltage is compared between bit line BL and inverted bit line XBL. Just do it.

  FIG. 40 is a timing chart showing a fail pattern (rejected pattern) of the third test targeting the semiconductor memory device 100 of the first configuration example (FIG. 33), in order from the top to the plate lines PL1 and PL2, Each state of word line WL, sense amplifier enable signal SA_E, internal nodes Node1 and Node2, bit line BL, inverted bit line XBL, test enable signals TEST1_E and TEST2_E, and memory cell enable signal MC_E and inverted memory cell enable signal MC_EN It is depicted.

  A series of test operations per se (1) to (5) are the same as in FIG. 39 described above. However, in the example of the present drawing, the voltage wkH recalled to the internal node Node1 is lower than the voltage with offset (wkL + OFS) recalled to the internal node Node2. Therefore, the amplification action of the inverter loop pulls down the internal node Node1 to the low level, and pulls up the internal node Node2 to the high level. Since this state is the reverse of the state before the power interruption, the inspection result is a failure.

  The absolute value of the margin Vm of the memory cell 11 can be known by checking the above inspection results (pass / fail) one by one while sweeping the offset voltage OFS applied to the inversion bit line XBL. For example, when the inspection result when applying the voltage OFS1 is a pass and the inspection result when applying the voltage OFS2 (> OFS1) is Fail as the offset voltage OFS, OFS1 <Vm <OFS2 I understand.

  In the first test and the second test described above, the node voltage before the logic level is determined in the inverter loop is drawn to bit line BL (or inverted bit line XBL), and read circuit 70 is used to generate reference voltage REF and It is necessary to perform an unusual operation such as comparing. On the other hand, in the case of the third test, if an arbitrary offset voltage OFS is applied before the recall operation, the margin Vm of the memory cell 11 can be obtained by performing the recall operation and the read operation which are not different from normal after that. It can be inspected. Therefore, the margin test can be performed with characteristics closer to actual values (in a state not depending on the parasitic capacitance of the bit line etc.), so that the inspection accuracy can be improved.

  Further, in the case of the third test, unlike the first test and the second test described above, the memory cell 11 can be more directly directly measured without individually measuring the absolute value of the voltage recalled to each of the internal nodes Node1 and Node2. The margin Vm of can be checked. Therefore, compared to the first test and the second test, it is also possible to shorten the time required for the margin test.

<Other Modifications>
In addition to the embodiments described above, various technical features disclosed in the present specification can be modified in various ways without departing from the scope of the technical creation. For example, in the above embodiment, the ferroelectric shadow memory having the 6T-4C structure has been described in detail as an example, but the structure of the ferroelectric shadow memory is not limited to this. A 6T-2C structure may be adopted in which the dielectric capacitors FC3 and FC4 (or ferroelectric capacitors FC1 and FC2) are omitted.

  That is, the above embodiment should be considered as illustrative in all points and not restrictive, and the technical scope of the present invention is shown by the claims rather than the description of the above embodiment. It is to be understood that the present invention includes all modifications that fall within the meaning and scope equivalent to the claims.

  The present invention is preferably used, for example, as a data buffer of an application (for example, a sensor network with a low active rate, biological monitoring, etc.) where "standby power reduction in sleep" and "maximize sleep time" are required. Is possible.

1 memory block 2 memory controller 10 memory cell array 11 memory cell (ferroelectric shadow memory)
Reference Signs List 20 word line driver 21, 22 P-channel field effect transistor 23 N-channel field effect transistor 24 inverter 25 capacitor element (ferroelectric capacitor)
26 delay stage 261, 262 inverter chain 30 X decoder 40 plate line driver 41, 42 P channel type field effect transistor 43 to 45 N channel type field effect transistor 46 inverter 47 capacitor (ferroelectric capacitor)
50 Y decoder and column selector 60 Write circuit 70 Read circuit 100 Semiconductor memory device M1, M3 Load transistor M2, M4 Drive transistor M5, M6 Access transistor M7, M8 Power switch FC1 to FC4 Ferroelectric capacitor SW Transmission gate SW1ab, SW1bc, SW2ab, SW2bc Transmission gate SWA, SWB Transmission gate TA, TB External terminal

Claims (2)

With multiple memory cells,
A plurality of plate lines respectively connected to the plurality of memory cells;
A plate line driver for driving each of the plurality of plate lines;
A memory controller for controlling access to the plurality of memory cells;
Have
Each of the plurality of memory cells is
An inverter loop connected between the first node and the second node;
A first access transistor connected between the first node and a bit line;
A second access transistor connected between the second node and the inverted bit line;
A first ferroelectric capacitor connected between the first node and the plate line;
A second ferroelectric capacitor connected between the second node and the plate line;
Including
The memory controller is configured to pulse drive the plurality of plate lines sequentially using the plate line driver when storing / recalling data of the memory cells, and not using the plate line driver. Perform charge sharing between the charged and uncharged plate lines before pulsing the charged plate lines,
Semiconductor memory device characterized by the above. Further comprising a plurality of transmission gates connected between adjacent plate lines,
The memory controller turns on the transmission gate between the charged and uncharged plate lines before pulsing the uncharged plate lines using the plate line driver.
The semiconductor memory device according to claim 1,