JP2018032652A - Wiring board and semiconductor device mounting structure using the same - Google Patents
Wiring board and semiconductor device mounting structure using the same Download PDFInfo
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- JP2018032652A JP2018032652A JP2016161704A JP2016161704A JP2018032652A JP 2018032652 A JP2018032652 A JP 2018032652A JP 2016161704 A JP2016161704 A JP 2016161704A JP 2016161704 A JP2016161704 A JP 2016161704A JP 2018032652 A JP2018032652 A JP 2018032652A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 120
- 238000010586 diagram Methods 0.000 abstract 1
- 239000004020 conductor Substances 0.000 description 20
- 229910000679 solder Inorganic materials 0.000 description 17
- 229920005989 resin Polymers 0.000 description 12
- 239000011347 resin Substances 0.000 description 12
- 229920001187 thermosetting polymer Polymers 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 239000004744 fabric Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000005422 blasting Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
Abstract
【課題】実装高さの高い第１の半導体素子と実装高さの低い第２の半導体素子とを、所定の実装高さで容易に実装することが可能な配線基板、および実装高さの高い第１の半導体素子と実装高さの低い第２の半導体素子とが所定の実装高さで実装された半導体素子の実装構造を提供すること。【解決手段】上面に実装高さの高い第１の半導体素子１１を実装する第１の実装部１０ａと、第１の半導体素子１１よりも実装高さの低い第２の半導体素子１２を実装する第２の実装部１０ｂとを有する配線基板１０であって、第１の実装部１０ａの高さが第２の実装部１０ｂの高さよりも高く形成されている。【選択図】図１A wiring board capable of easily mounting a first semiconductor element having a high mounting height and a second semiconductor element having a low mounting height at a predetermined mounting height, and a high mounting height. To provide a mounting structure of a semiconductor element in which a first semiconductor element and a second semiconductor element having a low mounting height are mounted at a predetermined mounting height. A first mounting portion for mounting a first semiconductor element having a high mounting height on an upper surface, and a second semiconductor element having a mounting height lower than the first semiconductor element are mounted on an upper surface. In the wiring board 10 having the second mounting portion 10b, the height of the first mounting portion 10a is higher than the height of the second mounting portion 10b. [Selection diagram] Fig. 1
Description
本発明は、複数の半導体素子を搭載する配線基板およびこれを用いた半導体素子の実装構造に関するものである。 The present invention relates to a wiring board on which a plurality of semiconductor elements are mounted and a semiconductor element mounting structure using the wiring board.
従来、図７に示すように、一つの配線基板５０に、第１の半導体素子４１と第２の半導体素子４２とを、その一部が上下に重なるようにして実装する半導体素子の実装構造が知られている。 Conventionally, as shown in FIG. 7, there is a mounting structure of a semiconductor element in which a first semiconductor element 41 and a second semiconductor element 42 are mounted on one wiring board 50 so as to partially overlap each other. Are known.
この実装構造においては、第１の半導体素子４１と第２の半導体素子４２とで配線基板５０への実装高さを異ならせる必要がある。そのため、実装高さの高い第１の半導体素子４１と配線基板５０との間にインターポーザ４３を介在させて実装している。 In this mounting structure, it is necessary to make the mounting height on the wiring board 50 different between the first semiconductor element 41 and the second semiconductor element 42. For this reason, the interposer 43 is interposed between the first semiconductor element 41 having a high mounting height and the wiring board 50 for mounting.
しかしながら、この実装構造においては、図８に示すように、配線基板５０と、第１および第２の半導体素子４１，４２と、インターポーザ４３とを別々に準備するとともに、図９（ａ）に示すように、配線基板５０とインターポーザ４３とを予め接続しておくか、あるいは、図９（ｂ）に示すように、第１の半導体素子４１とンターポーザ４３とを予め接続しておく必要がある。そのため、配線基板５０への第１の半導体素子４１および第２の半導体素子４２の実装が煩雑であった。また、第１の半導体素子４１の実装高さに関しては、配線基板５０とインターポーザ４３との実装高さおよびインターポーザ４３と第１の半導体素子４１との実装高さの両方を制御する必要があり、第１の半導体素子４１の実装高さを所定の実装高さとすることが困難であった。 However, in this mounting structure, as shown in FIG. 8, the wiring board 50, the first and second semiconductor elements 41 and 42, and the interposer 43 are separately prepared and shown in FIG. 9A. Thus, it is necessary to connect the wiring board 50 and the interposer 43 in advance or connect the first semiconductor element 41 and the interposer 43 in advance as shown in FIG. 9B. Therefore, the mounting of the first semiconductor element 41 and the second semiconductor element 42 on the wiring board 50 is complicated. Further, regarding the mounting height of the first semiconductor element 41, it is necessary to control both the mounting height of the wiring board 50 and the interposer 43 and the mounting height of the interposer 43 and the first semiconductor element 41. It was difficult to set the mounting height of the first semiconductor element 41 to a predetermined mounting height.
本発明が解決しようとする課題は、実装高さの高い第１の半導体素子と実装高さの低い第２の半導体素子とを、所定の実装高さで容易に実装することが可能な配線基板および実装高さの高い第１の半導体素子と実装高さの低い第２の半導体素子とが所定の実装高さで実装された半導体素子の実装構造を提供することにある。 A problem to be solved by the present invention is a wiring board capable of easily mounting a first semiconductor element having a high mounting height and a second semiconductor element having a low mounting height at a predetermined mounting height. Another object of the present invention is to provide a semiconductor element mounting structure in which a first semiconductor element having a high mounting height and a second semiconductor element having a low mounting height are mounted at a predetermined mounting height.
本発明の配線基板は、上面に、実装高さの高い第１の半導体素子を実装する第１の実装部と、前記第１の半導体素子よりも実装高さの低い第２の半導体素子を実装する第２の実装部とを有する配線基板であって、前記第１の実装部の高さが前記第２の実装部の高さよりも高く形成されていることを特徴とするものである。 In the wiring board of the present invention, a first mounting portion for mounting a first semiconductor element having a high mounting height and a second semiconductor element having a mounting height lower than that of the first semiconductor element are mounted on an upper surface. A wiring board having a second mounting part, wherein the height of the first mounting part is higher than the height of the second mounting part.
本発明の半導体素子の実装構造は、前記第１の実装部に前記１の半導体素子が実装されているとともに、前記第２の実装部に前記第２の半導体素子が実装されていることを特徴とするものである。 The semiconductor element mounting structure of the present invention is characterized in that the first semiconductor element is mounted on the first mounting portion, and the second semiconductor element is mounted on the second mounting portion. It is what.
本発明の配線基板によれば、実装高さの高い第１の半導体素子が実装される第１の実装部の高さが、実装高さの低い第２の半導体素子を実装する第２の実装部の高さよりも高く形成されていることから、第１の実装部に第１の半導体素子を実装するとともに第２の実装部に第２の半導体素子を実装することで、実装高さの高い第１の半導体素子と実装高さの低い第２の半導体素子とを、所定の実装高さで容易に実装することができる。 According to the wiring board of the present invention, the first mounting portion on which the first semiconductor element having a high mounting height is mounted has the second mounting for mounting the second semiconductor element having a low mounting height. Since the first semiconductor element is mounted on the first mounting portion and the second semiconductor element is mounted on the second mounting portion, the mounting height is high. The first semiconductor element and the second semiconductor element having a low mounting height can be easily mounted at a predetermined mounting height.
また、本発明の半導体素子の実装構造によれば、実装高さが低い第２の半導体素子が実装された第２の実装部よりも高く形成された第１の実装部に実装高さが高い第１の半導体素子が実装されていることから、実装高さの高い第１の半導体素子と実装高さの低い第２の半導体素子とが所定の実装高さで実装された半導体素子の実装構造を提供することができる。 Further, according to the semiconductor element mounting structure of the present invention, the mounting height is higher in the first mounting portion formed higher than the second mounting portion on which the second semiconductor element having a low mounting height is mounted. Since the first semiconductor element is mounted, the mounting structure of the semiconductor element in which the first semiconductor element having a high mounting height and the second semiconductor element having a low mounting height are mounted at a predetermined mounting height. Can be provided.
次に、本発明の配線基板およびこれを用いた半導体素子の実装構造の実施形態の一例を図１〜３を参照して説明する。 Next, an example of an embodiment of a wiring board of the present invention and a semiconductor element mounting structure using the same will be described with reference to FIGS.
図１に示すように、本例の配線基板１０は、絶縁基板１と配線導体２とソルダーレジスト層３とから成る。配線基板１０は、その上面に第１の実装部１０ａと第２の実装部１０ｂとを有している。第１の実装部１０ａには、第１の半導体素子１１が実装される。第２の実装部１０ｂには、第２の半導体素子１２が実装される。また、配線基板１０の下面は、外部の電気回路基板に接続するための外部接続面を形成している。 As shown in FIG. 1, the wiring substrate 10 of this example includes an insulating substrate 1, a wiring conductor 2, and a solder resist layer 3. The wiring board 10 has a first mounting portion 10a and a second mounting portion 10b on the upper surface thereof. The first semiconductor element 11 is mounted on the first mounting portion 10a. The second semiconductor element 12 is mounted on the second mounting portion 10b. The lower surface of the wiring board 10 forms an external connection surface for connection to an external electric circuit board.
絶縁基板１は、コア絶縁層１ａとその上下面に積層されたビルドアップ絶縁層１ｂ〜１ｉとから成る。 The insulating substrate 1 includes a core insulating layer 1a and build-up insulating layers 1b to 1i stacked on upper and lower surfaces thereof.
コア絶縁層１ａは、例えばガラスクロス入りの熱硬化性樹脂から成る。熱硬化性樹脂としては、ビスマレイミドトリアジン樹脂やエポキシ樹脂等が用いられる。コア絶縁層１ａの厚みは０．１〜０．８ｍｍ程度である。コア絶縁層１ａの上面から下面にかけては、複数のスルーホール４が形成されている。スルーホール４の直径は、１００〜２００μｍ程度である。コア絶縁層１ａの上下面およびスルーホール４の内壁には配線導体２が被着されている。配線導体２が被着されたスルーホール４の内部は、孔埋め樹脂５により充填されている。 The core insulating layer 1a is made of, for example, a thermosetting resin containing glass cloth. As the thermosetting resin, bismaleimide triazine resin, epoxy resin, or the like is used. The thickness of the core insulating layer 1a is about 0.1 to 0.8 mm. A plurality of through holes 4 are formed from the upper surface to the lower surface of the core insulating layer 1a. The diameter of the through hole 4 is about 100 to 200 μm. A wiring conductor 2 is attached to the upper and lower surfaces of the core insulating layer 1 a and the inner wall of the through hole 4. The interior of the through hole 4 to which the wiring conductor 2 is attached is filled with a hole filling resin 5.
ビルドアップ絶縁層１ｂ〜１ｉは、ガラスクロス無しの熱硬化性樹脂から成る。熱硬化性樹脂としては、エポキシ樹脂等が用いられる。ビルドアップ絶縁層１ｂ〜１ｉの厚みは、それぞれ１０〜５０μｍ程度である。各ビルドアップ絶縁層１ｂ〜１ｉの上面から下面にかけては、複数のビアホール６が形成されている。ビアホール６の直径は、３０〜１００μｍ程度である。各ビルドアップ絶縁層１ｂ〜１ｉの表面およびビアホール６内には、配線導体２が被着されている。 The build-up insulating layers 1b to 1i are made of a thermosetting resin without glass cloth. An epoxy resin or the like is used as the thermosetting resin. Each of the build-up insulating layers 1b to 1i has a thickness of about 10 to 50 μm. A plurality of via holes 6 are formed from the upper surface to the lower surface of each build-up insulating layer 1b-1i. The diameter of the via hole 6 is about 30 to 100 μm. A wiring conductor 2 is deposited on the surface of each build-up insulating layer 1b-1i and in the via hole 6.
配線導体２は、銅箔や銅めっきから成る。配線導体２の厚みは、コア絶縁層１ａの上下面およびスルーホール４の内壁ならびに各ビルドアップ絶縁層１ｂ〜１ｉの表面で５〜２５μｍ程度である。なお、ビアホール６内は、配線導体２により完全に充填されている。 The wiring conductor 2 is made of copper foil or copper plating. The thickness of the wiring conductor 2 is about 5 to 25 μm on the upper and lower surfaces of the core insulating layer 1a, the inner walls of the through holes 4, and the surfaces of the build-up insulating layers 1b to 1i. The via hole 6 is completely filled with the wiring conductor 2.
配線導体２は、第１の搭載部１０ａにおいて、第１の半導体素子接続パッド７ａを形成している。また、配線導体２は、第２の搭載部１０ｂにおいて、第２の半導体素子接続パッド７ｂを形成している。第１の半導体素子接続パッド７ａには、第１の半導体素子１１の電極端子１３が半田バンプ１４を介して接続される。第２の半導体素子接続パッド７ｂには、第２の半導体素子１２の電極端子１５が半田バンプ１６を介して接続される。 The wiring conductor 2 forms a first semiconductor element connection pad 7a in the first mounting portion 10a. The wiring conductor 2 forms a second semiconductor element connection pad 7b in the second mounting portion 10b. The electrode terminals 13 of the first semiconductor element 11 are connected to the first semiconductor element connection pads 7a via solder bumps 14. The electrode terminal 15 of the second semiconductor element 12 is connected to the second semiconductor element connection pad 7 b via the solder bump 16.
さらに、配線導体２は、配線基板１０の下面において、外部の電気回路基板に接続するための外部接続パッド８を形成している。外部接続パッド８には、外部の電気回路基板の配線導体が半田ボール等を介して接続される。 Furthermore, the wiring conductor 2 forms an external connection pad 8 for connection to an external electric circuit board on the lower surface of the wiring board 10. A wiring conductor of an external electric circuit board is connected to the external connection pad 8 via a solder ball or the like.
ソルダーレジスト層３は、感光性の熱硬化性樹脂から成る。感光性の熱硬化性樹脂としては、例えばアクリル変性エポキシ樹脂等が用いられる。ソルダーレジスト層３の厚みは、１０〜５０μｍ程度である。上面側のソルダーレジスト層３は、第１の半導体素子接続パッド７ａを露出させる開口部および第２の半導体素子接続パッド７ｂを露出させる開口部を有している。下面側のソルダーレジスト層３は、外部接続パッド８を露出させる開口部を有している。 The solder resist layer 3 is made of a photosensitive thermosetting resin. As the photosensitive thermosetting resin, for example, an acrylic-modified epoxy resin or the like is used. The thickness of the solder resist layer 3 is about 10 to 50 μm. The solder resist layer 3 on the upper surface side has an opening for exposing the first semiconductor element connection pad 7a and an opening for exposing the second semiconductor element connection pad 7b. The solder resist layer 3 on the lower surface side has an opening for exposing the external connection pad 8.
ところで、本例の配線基板１０においては、第１の実装部１０ａの高さが第２の実装部１０ｂの高さよりも高くなっている。具体的には、第１の実装部１０ａは、最上層のビルドアップ絶縁層１ｅ上に設けられているのに対して、第２の実装部１０ｂは、その下層のビルドアップ絶縁層１ｄ上に設けられている。このため、第１の実装部１０ａの高さが第２の実装部１０ｂの高さよりもビルドアップ絶縁層１ｅの１層分、つまり１０〜５０μｍ高くなっている。これにより、第１の半導体素子１１の実装高さを、第２の半導体素子１２の実装高さよりも高いものとすることができる。なお、ここでいう実装高さとは、ある基準水平面から第１の半導体素子１１の下面または第２の半導体素子１２の下面までの高さをいう。 By the way, in the wiring board 10 of this example, the height of the 1st mounting part 10a is higher than the height of the 2nd mounting part 10b. Specifically, the first mounting portion 10a is provided on the uppermost buildup insulating layer 1e, whereas the second mounting portion 10b is provided on the lower buildup insulating layer 1d. Is provided. For this reason, the height of the first mounting portion 10a is one layer of the build-up insulating layer 1e, that is, 10 to 50 μm, higher than the height of the second mounting portion 10b. Thereby, the mounting height of the first semiconductor element 11 can be made higher than the mounting height of the second semiconductor element 12. The mounting height here refers to the height from a certain reference horizontal plane to the lower surface of the first semiconductor element 11 or the lower surface of the second semiconductor element 12.
図２に、本例の配線基板１０に第１の半導体素子１１および第２の半導体素子１２を実装した半導体素子の実装構造を示す。本例の配線基板１０によれば、実装高さの高い第１の半導体素子１１が実装される第１の実装部１０ａの高さが、実装高さの低い第２の半導体素子１２を実装する第２の実装部１０ｂの高さよりも高く形成されていることから、第１の実装部１０ａに第１の半導体素子１１を実装するとともに第２の実装部１０ｂに第２の半導体素子１２を実装することで、実装高さの高い第１の半導体素子１１と実装高さの低い第２の半導体素子１２とを、所定の実装高さで容易に実装することができる。 FIG. 2 shows a mounting structure of a semiconductor element in which the first semiconductor element 11 and the second semiconductor element 12 are mounted on the wiring board 10 of this example. According to the wiring board 10 of this example, the second semiconductor element 12 having a low mounting height is mounted on the first mounting portion 10a on which the first semiconductor element 11 having a high mounting height is mounted. Since it is formed higher than the height of the second mounting portion 10b, the first semiconductor element 11 is mounted on the first mounting portion 10a and the second semiconductor element 12 is mounted on the second mounting portion 10b. Thus, the first semiconductor element 11 having a high mounting height and the second semiconductor element 12 having a low mounting height can be easily mounted at a predetermined mounting height.
また、本例の半導体素子の実装構造によれば、実装高さが低い第２の半導体素子１２が実装された第２の実装部１０ｂよりも高く形成された第１の実装部１０ａに実装高さが高い第１の半導体素子１１が実装されていることから、実装高さの高い第１の半導体素子１１と実装高さの低い第２の半導体素子１２とが所定の実装高さで実装された半導体素子の実装構造を提供することができる。 Further, according to the mounting structure of the semiconductor element of this example, the mounting height is higher in the first mounting portion 10a formed higher than the second mounting portion 10b in which the second semiconductor element 12 having a low mounting height is mounted. Since the first semiconductor element 11 having a high height is mounted, the first semiconductor element 11 having a high mounting height and the second semiconductor element 12 having a low mounting height are mounted at a predetermined mounting height. In addition, a mounting structure of a semiconductor element can be provided.
なお、上述した配線基板１０は、例えば以下のようにして製造される。先ず、図３（ａ）に示すように、最上層のビルドアップ絶縁層１ｅおよび上側のソルダーレジスト層３が第２の実装部１０ｂとなる領域を覆うように形成された配線基板１０の前駆体１０Ｐを常法により形成する。次に、図３（ｂ）に示すように、前駆体１０Ｐ上に、第１の実装部１０ａを覆うとともに第２の実装部１０ｂに対応する領域を露出させるマスクＭを形成し、このマスクＭを介してブラスト加工を施すことにより、第２の実装部１０ｂ上のビルドアップ絶縁層１ｅおよびソルダーレジスト層３を除去する。最後に、マスクＭを除去することにより配線基板１０を得る。 In addition, the wiring board 10 mentioned above is manufactured as follows, for example. First, as shown in FIG. 3A, the precursor of the wiring board 10 formed so that the uppermost buildup insulating layer 1e and the upper solder resist layer 3 cover the region to be the second mounting portion 10b. 10P is formed by a conventional method. Next, as shown in FIG. 3B, a mask M that covers the first mounting portion 10a and exposes a region corresponding to the second mounting portion 10b is formed on the precursor 10P. The build-up insulating layer 1e and the solder resist layer 3 on the second mounting portion 10b are removed by performing blasting via Finally, the wiring board 10 is obtained by removing the mask M.
次に、本発明の配線基板およびこれを用いた半導体素子の実装構造の実施形態の他の例を図４〜６を参照して説明する。 Next, another example of the embodiment of the wiring board of the present invention and the mounting structure of the semiconductor element using the wiring board will be described with reference to FIGS.
図４に示すように、本例の配線基板３０は、いわゆるコアレス基板であり、絶縁基板２１と配線導体２２とソルダーレジスト層２３とから成る。配線基板３０は、その上面に第１の実装部３０ａと第２の実装部３０ｂとを有している。第１の実装部３０ａには、第１の半導体素子３１が実装される。第２の実装部３０ｂには、第２の半導体素子３２が実装される。また、配線基板３０の下面は、外部の電気回路基板に接続するための外部接続面を形成している。 As shown in FIG. 4, the wiring substrate 30 of this example is a so-called coreless substrate, and includes an insulating substrate 21, a wiring conductor 22, and a solder resist layer 23. The wiring board 30 has a first mounting portion 30a and a second mounting portion 30b on the upper surface thereof. The first semiconductor element 31 is mounted on the first mounting portion 30a. A second semiconductor element 32 is mounted on the second mounting portion 30b. The lower surface of the wiring board 30 forms an external connection surface for connection to an external electric circuit board.
絶縁基板１は、複数のビルドアップ絶縁層２１ａ〜２１ｇが上下に積層されて成る。ビルドアップ絶縁層２１ａ〜２１ｇは、ガラスクロス入りやガラスクロス無しの熱硬化性樹脂から成る。熱硬化性樹脂としては、エポキシ樹脂等が用いられる。ビルドアップ絶縁層２１ａ〜２１ｇの厚みは、それぞれ１０〜５０μｍ程度である。各ビルドアップ絶縁層２１ａ〜２１ｇの上面から下面にかけては、複数のビアホール２４が形成されている。ビアホール２４の直径は、３０〜１００μｍ程度である。各ビルドアップ絶縁層２１ａ〜２１ｇの表面およびビアホール２４内には、配線導体２２が被着されている。 The insulating substrate 1 is formed by stacking a plurality of build-up insulating layers 21a to 21g vertically. The build-up insulating layers 21a to 21g are made of a thermosetting resin with or without glass cloth. An epoxy resin or the like is used as the thermosetting resin. Each of the build-up insulating layers 21a to 21g has a thickness of about 10 to 50 μm. A plurality of via holes 24 are formed from the upper surface to the lower surface of each buildup insulating layer 21a to 21g. The diameter of the via hole 24 is about 30 to 100 μm. A wiring conductor 22 is deposited on the surface of each of the build-up insulating layers 21 a to 21 g and the via hole 24.
配線導体２２は、銅箔や銅めっきから成る。配線導体２２の厚みは、各ビルドアップ絶縁層２１ａ〜２１ｇの表面で５〜２５μｍ程度である。なお、ビアホール２４内は、配線導体２２により完全に充填されている。 The wiring conductor 22 is made of copper foil or copper plating. The thickness of the wiring conductor 22 is about 5 to 25 μm on the surface of each build-up insulating layer 21a to 21g. The via hole 24 is completely filled with the wiring conductor 22.
配線導体２２は、第１の搭載部３０ａにおいて、第１の半導体素子接続パッド２５ａを形成している。また、配線導体２２は、第２の搭載部３０ｂにおいて、第２の半導体素子接続パッド２５ｂを形成している。第１の半導体素子接続パッド２５ａには、第１の半導体素子３１の電極端子３３が半田バンプ３４を介して接続される。第２の半導体素子接続パッド２５ｂには、第２の半導体素子３２の電極端子３５が半田バンプ３６を介して接続される。 The wiring conductor 22 forms a first semiconductor element connection pad 25a in the first mounting portion 30a. Further, the wiring conductor 22 forms a second semiconductor element connection pad 25b in the second mounting portion 30b. The electrode terminals 33 of the first semiconductor element 31 are connected to the first semiconductor element connection pads 25a through solder bumps 34. The electrode terminals 35 of the second semiconductor element 32 are connected to the second semiconductor element connection pads 25b through solder bumps 36.
さらに、配線導体２２は、配線基板３０の下面において、外部の電気回路基板に接続するための外部接続パッド２６を形成している。外部接続パッド２６には、外部の電気回路基板配線導体が半田ボール等を介して接続される。 Further, the wiring conductor 22 forms an external connection pad 26 for connection to an external electric circuit board on the lower surface of the wiring board 30. An external electric circuit board wiring conductor is connected to the external connection pad 26 via a solder ball or the like.
ソルダーレジスト層２３は、感光性の熱硬化性樹脂から成る。感光性の熱硬化性樹脂としては、アクリル変性エポキシ樹脂等が用いられる。本例の配線基板３０においては、ソルダーレジスト層２３は、絶縁基板２１の下面側のみに被着されている。ソルダーレジスト層２３は、外部接続パッド２６を露出させる開口部を有している。 The solder resist layer 23 is made of a photosensitive thermosetting resin. As the photosensitive thermosetting resin, an acrylic modified epoxy resin or the like is used. In the wiring substrate 30 of this example, the solder resist layer 23 is attached only to the lower surface side of the insulating substrate 21. The solder resist layer 23 has an opening for exposing the external connection pad 26.
ところで、本例の配線基板３０においては、第１の実装部３０ａの高さが第２の実装部３０ｂの高さよりも高くなっている。具体的には、第１の実装部３０ａは、最上層のビルドアップ絶縁層２１ａ上に設けられているのに対して、第２の実装部３０ｂは、その下層のビルドアップ絶縁層２１ｂ上に設けられている。このため、第１の実装部３０ａの高さが第２の実装部３０ｂの高さよりもビルドアップ絶縁層２１ａの１層分、つまり１０〜５０μｍ高くなっている。これにより、第１の半導体素子３１の実装高さを、第２の半導体素子３２の実装高さよりも高いものとすることができる。なお、ここでいう実装高さとは、ある基準水平面から第１の半導体素子３１下面または第２の半導体素子３２の下面までの高さをいう。 By the way, in the wiring board 30 of this example, the height of the first mounting portion 30a is higher than the height of the second mounting portion 30b. Specifically, the first mounting portion 30a is provided on the uppermost buildup insulating layer 21a, while the second mounting portion 30b is provided on the lower buildup insulating layer 21b. Is provided. For this reason, the height of the first mounting portion 30a is one layer of the buildup insulating layer 21a, that is, 10 to 50 μm higher than the height of the second mounting portion 30b. Thereby, the mounting height of the first semiconductor element 31 can be made higher than the mounting height of the second semiconductor element 32. The mounting height here refers to the height from a certain reference horizontal plane to the lower surface of the first semiconductor element 31 or the lower surface of the second semiconductor element 32.
図５に、本例の配線基板３０に第１の半導体素子３１および第２の半導体素子３２を実装した半導体素子の実装構造を示す。本例の配線基板３０によれば、実装高さの高い第１の半導体素子３１が実装される第１の実装部３０ａの高さが、実装高さの低い第２の半導体素子３２を実装する第２の実装部３０ｂの高さよりも高く形成されていることから、第１の実装部３０ａに第１の半導体素子３１を実装するとともに第２の実装部３０ｂに第２の半導体素子３２を実装することで、実装高さの高い第１の半導体素子３１と実装高さの低い第２の半導体素子３２とを、所定の実装高さで容易に実装することができる。 FIG. 5 shows a semiconductor element mounting structure in which the first semiconductor element 31 and the second semiconductor element 32 are mounted on the wiring board 30 of this example. According to the wiring board 30 of the present example, the second semiconductor element 32 having a low mounting height is mounted on the first mounting portion 30a on which the first semiconductor element 31 having a high mounting height is mounted. Since it is formed higher than the height of the second mounting part 30b, the first semiconductor element 31 is mounted on the first mounting part 30a and the second semiconductor element 32 is mounted on the second mounting part 30b. Thus, the first semiconductor element 31 having a high mounting height and the second semiconductor element 32 having a low mounting height can be easily mounted at a predetermined mounting height.
また、本例の半導体素子の実装構造によれば、実装高さが低い第２の半導体素子３２が実装された第２の実装部３０ｂよりも高く形成された第１の実装部３０ａに実装高さが高い第１の半導体素子３１が実装されていることから、実装高さの高い第１の半導体素子３１と実装高さの低い第２の半導体素子３２とが所定の実装高さで実装された半導体素子の実装構造を提供することができる。 Further, according to the mounting structure of the semiconductor element of this example, the mounting height is higher in the first mounting part 30a formed higher than the second mounting part 30b in which the second semiconductor element 32 having a low mounting height is mounted. Since the first semiconductor element 31 having a high height is mounted, the first semiconductor element 31 having a high mounting height and the second semiconductor element 32 having a low mounting height are mounted at a predetermined mounting height. In addition, a mounting structure of a semiconductor element can be provided.
なお、上述した配線基板３０は、例えば以下のようにして製造される。先ず、図６（ａ）に示すように、最上層のビルドアップ絶縁層２１ａが第２の実装部３０ｂとなる領域を覆うように形成された配線基板３０の前駆体３０Ｐを常法により形成する。次に、図６（ｂ）に示すように、前駆体３０Ｐ上に、第１の実装部３０ａを覆うとともに第２の実装部３０ｂに対応する領域を露出させるマスクＭを形成し、このマスクＭを介してブラスト加工を施すことにより、第２の実装部３０ｂ上のビルドアップ絶縁層２１ａを除去する。最後に、マスクＭを除去することにより配線基板３０を得る。 In addition, the wiring board 30 mentioned above is manufactured as follows, for example. First, as shown in FIG. 6A, the precursor 30P of the wiring board 30 formed so as to cover the region where the uppermost build-up insulating layer 21a becomes the second mounting portion 30b is formed by a conventional method. . Next, as shown in FIG. 6B, a mask M is formed on the precursor 30P so as to cover the first mounting portion 30a and expose the region corresponding to the second mounting portion 30b. The buildup insulating layer 21a on the second mounting part 30b is removed by performing blasting via Finally, the wiring board 30 is obtained by removing the mask M.
１０，３０ 配線基板
１０ａ，３０ａ 第１の実装部
１０ｂ，３０ｂ 第２の実装部
１１，３１ 第１の半導体素子
１２，３２ 第２の半導体素子
DESCRIPTION OF SYMBOLS 10, 30 Wiring board 10a, 30a 1st mounting part 10b, 30b 2nd mounting part 11, 31 1st semiconductor element 12, 32 2nd semiconductor element
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