JP2017122867A - Timing controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a timing controller which reliably starts an output IF circuit for controlling operation of a driver circuit of a liquid crystal panel, without using a line buffer.SOLUTION: In a timing controller, a special data extraction circuit extracts special data transmitted only once during vertical blanking period, from received data, in synchronization with the start of a vertical synchronous signal. A line beginning extraction circuit extracts line beginning data representing the beginning of a period in which image data of lines of a liquid crystal panel are transmitted, from the received data. When the special data is extracted, an output IF circuit causes a line counter to start counting, and the line counter counts the line beginning data extracted. The output IF start circuit starts an output IF circuit when a count value of the line counter reaches a count value set in a count setting circuit.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a timing controller that controls the operation of a liquid crystal panel.

The timing controller includes an output IF (interface) circuit (driver IF circuit) that controls the operation of a driver circuit that drives the liquid crystal panel. The output IF circuit includes a buffer that outputs a control signal for controlling the operation of the driver circuit.
In order to reduce power consumption, the output IF circuit may be stopped during the vertical blanking period (see Patent Documents 1 and 2). In this case, it is necessary to output an activation signal for activating the output IF circuit before the start of the image display period of the next frame.

Here, in Patent Document 1, in the liquid crystal display device, the clock signal supplied to the driver circuit that drives the liquid crystal element is stopped in synchronization with the vertical and horizontal blanking periods of the video signal, thereby It describes that power consumption is reduced.
Patent Document 2 discloses that in a liquid crystal display device, a display operation by an internal circuit is stopped in an inactive state of an enable signal or command input from the outside, and a display operation by the internal circuit is restarted in an active state, thereby reducing power consumption. It is described to realize.

JP-A-8-305316 Japanese Patent Laying-Open No. 2015-94806

  In order to output the activation signal retroactively from the image display period and before the start of the image display period, it is necessary to provide a line buffer or the like and delay the image display period itself as shown in the timing chart of FIG. In this example, the activation signal is generated at the start timing of the image display period before the delay before the start of the image display period after the delay. However, this method requires a line buffer or the like, which increases the circuit scale and power consumption.

  On the other hand, as shown in the timing chart of FIG. 7, it is conceivable to generate the activation signal after a certain period from the end timing of the image display period of the previous frame. In this case, in order to lengthen the stop period of the output IF circuit, the start signal generation timing is brought close to the start timing of the image display period of the next frame. This method does not require a line buffer, but has a problem that it cannot cope with the case where the length of the vertical blanking period varies.

  Here, the liquid crystal panel can reduce power consumption by lowering the image update frequency (refresh rate). Therefore, the length of the vertical blanking period is increased when displaying still images or moving images with small motion. The frequency may be lowered. On the other hand, when a moving image with a large amount of motion is displayed when the refresh rate is lowered, it is necessary to reduce the length of the vertical blanking period and consequently increase the refresh rate.

  However, when the length of the vertical blanking period is decreased, as shown in the timing chart of FIG. 7, when the start timing of the image display period of the next frame is earlier than the output timing of the start signal, As described above, there is a problem that the start signal cannot be output.

SUMMARY OF THE INVENTION A first object of the present invention is to provide a timing controller that can solve the problems of the prior art and can reliably start an output IF circuit that controls the operation of a driver circuit of a liquid crystal panel without providing a line buffer. There is to do.
In addition to the first object, a second object of the present invention is to provide a timing controller capable of reliably starting the output IF circuit even when the length of the vertical blanking period is varied. There is.

In order to achieve the above object, the present invention provides a timing controller for controlling the operation of a liquid crystal panel,
An output interface circuit that controls the operation of a driver circuit that drives the liquid crystal panel according to image data extracted from received data received from an external device;
A special data extraction circuit for extracting special data transmitted only once during a vertical blanking period in synchronization with the start timing of the vertical synchronization signal from the received data;
A line head extraction circuit that extracts line head data representing the head of a period in which image data of each line of the liquid crystal panel is transmitted from the received data;
A line counter that counts the number of times the line head data is extracted and outputs a count value;
A count number setting circuit for setting a count number counted by the line counter;
An output interface activation circuit that starts counting the line counter when the special data is extracted and activates the output interface circuit when the count value reaches the count number; A characteristic timing controller is provided.

  Furthermore, it is preferable to include a control data holding circuit that holds control data for controlling the timing at which the external device transmits the special data to the timing controller.

  The control data holding circuit includes a length of the vertical blanking period, a length of a front porch period from the start of the vertical blanking period to the start of the vertical synchronization signal, the length of the vertical synchronization signal, and Two pieces of image timing data differing only in the length of the vertical blanking period and the length of the front porch period among the lengths of the back porch period from the end of the vertical synchronization signal to the end of the vertical blanking period Is preferably held as the control data.

  In addition, when the external device varies the length of the vertical blanking period based on the two image timing data received from the control data holding circuit, only the length of the front porch period is variable. It is determined that there is a variable range of the length of the vertical blanking period and a variable range of the length of the front porch period, and the variable range of the length of the vertical blanking period and the length of the front porch period The vertical blanking period and the front porch period are varied within a variable range of the vertical synchronizing signal after the vertical blanking period and the front porch period are varied. It is preferable to have a function of transmitting the special data to the timing controller in synchronization with the start timing.

  The control data holding circuit includes a length of the vertical blanking period, a length of a front porch period from the start of the vertical blanking period to the start of the vertical synchronization signal, the length of the vertical synchronization signal, and The length of the front porch period is variable among the length of the back porch period from the end of the vertical synchronization signal to the end of the vertical blanking period, and the length of the vertical blanking period is also changed. It is preferable that variable period data to be represented and two front porch period data representing the length of the front porch period are held as the control data.

  In addition, when the external device varies the length of the vertical blanking period based on the variable period data received from the control data holding circuit, only the length of the front porch period is variable. Determining and detecting a variable range of the length of the vertical blanking period and a variable range of the length of the front porch period based on the two front porch period data received from the control data holding circuit, and The length of the vertical blanking period is varied by varying the length of the vertical blanking period and the length of the front porch period within the variable range of the blanking period length and the variable range of the length of the front porch period. And the special data in synchronization with the start timing of the vertical synchronization signal after the length of the front porch period is changed Preferably it has a function of transmitting to the timing controller.

  In the present invention, the special data that is transmitted only once during the vertical blanking period is extracted from the received data in synchronization with the start timing of the vertical synchronizing signal, and then the output interface circuit is activated after a certain period. The

Thus, according to the present invention, since the special data is transmitted in synchronization with the start timing of the vertical synchronization signal, the output interface circuit can be reliably started based on the special data without providing a line buffer. Can do. Since there is no need to provide a line buffer, the circuit scale and power consumption can be reduced.
Even if the length of the vertical blanking period is changed, the special data is transmitted in synchronization with the start timing of the vertical synchronization signal. Therefore, only the length of the front porch period is changed to change the vertical blanking period. When changing the length of the period, the output interface circuit can be reliably started based on the special data.

It is a block diagram of a 1st embodiment showing composition of a timing controller concerning the present invention. It is an example timing chart showing operation | movement of a timing controller. It is a timing chart of an example showing the fluctuation | variation of the length of the vertical blanking period at the time of changing the length of a front porch period. It is a timing chart of another example showing operation of a timing controller. It is a block diagram of 2nd Embodiment showing the structure of the timing controller which concerns on this invention. It is an example timing chart showing operation | movement of the conventional timing controller. It is a timing chart of another example showing operation | movement of the conventional timing controller.

  Hereinafter, a timing controller of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

  FIG. 1 is a block diagram of a first embodiment showing a configuration of a timing controller according to the present invention. The timing controller 10 shown in FIG. 1 controls the operation of the liquid crystal panel, and includes a sink circuit 12, an output data configuration circuit 14, a parallel-serial conversion circuit 16, and an output IF (interface) circuit 18. And a control data holding circuit 20. In the figure, a source circuit (external device) 22 is displayed.

The source circuit 22 and the sink circuit 12 are a display port (DisplayPort) output side device and an input side device, respectively, and are connected by a display port main link (Main Link) and an auxiliary channel (AUX CH). .
The source circuit 22 is a PC (personal computer), video equipment, or the like, and the sink circuit 12 is a liquid crystal display device, a projector, or the like.

  The display port is one of interface standards for connecting a personal computer, a video device, and the like to a display device, and is developed by a standardization organization VESA (Video Electronics Standards Association) regarding an interface standard of video signals. In the display port, the source circuit 22 and the sink circuit 12 are connected using a main link having a maximum of 4 lanes and an auxiliary channel.

The main link is image data, data representing a vertical blanking period, a vertical synchronization signal, special data transmitted only once during the vertical blanking period, and a line representing the beginning of a period in which image data of each line is transmitted. This is a channel for transmitting head data and the like from the source circuit 22 to the sink circuit 12.
The auxiliary channel is a channel for bidirectionally transmitting and receiving data for controlling operations of the output side device and the input side device between the source circuit 22 and the sink circuit 12.

  Transmission data and reception data of packetized serial data are transmitted and received between the source circuit 22 and the sink circuit 12.

  The sink circuit 12 includes an input IF circuit 24, a serial / parallel conversion circuit 26, an MSA extraction circuit 28, a line head extraction circuit 30, a line counter 32, a timing setting register 34, and an output IF activation signal generation circuit 36. The image data extracting circuit 38 and the input / output IF circuit 40 are provided.

Transmission data output from the source circuit 22 is transmitted to the serial / parallel conversion circuit 26 via the main link, and reception data of serial data received by the input IF circuit 24 is input.
The serial / parallel conversion circuit 26 converts received data from serial data to parallel data.
The serial / parallel conversion circuit 26 outputs parallel data reception data.

The MSA extraction circuit (special data extraction circuit of the present invention) 28 receives the parallel data received from the serial / parallel conversion circuit 26.
The MSA extraction circuit 28 extracts MSA (Main Stream Attribute) as special data transmitted only once during the vertical blanking period in synchronization with the start timing of the vertical synchronization signal from the received data of the parallel data. is there.
The MSA extraction circuit 28 outputs an MSA timing signal indicating the timing at which the MSA is extracted.

  MSA is data representing the attribute of image data. For example, the number of pixels per line, the number of lines per frame, the length of a horizontal sync signal, the length of a vertical sync signal, the horizontal sync signal to the horizontal display period. Data such as the length and the length from the vertical synchronization signal to the vertical display period is included.

The line head extraction circuit 30 receives parallel data received from the serial / parallel conversion circuit 26.
The line head extraction circuit 30 extracts line head data representing the head of a period during which image data of each line of the liquid crystal panel is transmitted from the received data of parallel data.
The line head extraction circuit 30 outputs a line head signal indicating the timing at which the line head data is extracted.

The line counter 32 receives a line head signal from the line head extraction circuit 30 and a count start signal described later from the output IF start signal generation circuit 36.
The line counter 32 counts the number of times the line head data is extracted based on the line head signal and outputs the count value when the start of counting is instructed by the count start signal.
From the line counter 32, a line number signal representing the count value is output.

The timing setting register (count number setting circuit of the present invention) 34 sets the count number counted by the line counter 32.
From the timing setting register 34, the set count number is output as an activation signal timing setting value.

The output IF activation signal generation circuit (output interface activation circuit of the present invention) 36 includes an MSA extraction signal from the MSA extraction circuit 28, a line number signal from the line counter 32, and an activation signal timing setting value from the timing setting register 34. Is entered.
When the output IF activation signal generation circuit 36 detects that the MSA is extracted as the special data from the reception data based on the MSA timing signal, that is, when the special data is extracted from the reception data, the line counter A count start signal for starting counting of 32 is generated.
The output IF activation signal generation circuit 36 indicates that the count value counted by the line counter 32 has reached the count number set in the timing setting register 34 based on the line number signal and the activation signal timing setting value. When detected, that is, when the count value of the line counter 32 reaches the count number of the timing setting register 34, an activation signal for activating the output IF circuit 18 is generated.
The output IF activation signal generation circuit 36 outputs a count start signal and an activation signal.

The image data extraction circuit 38 receives parallel data received from the serial / parallel conversion circuit 26.
The image data extraction circuit 38 extracts image data of each line of the liquid crystal panel from the received data of parallel data.
From the image data extraction circuit 38, image data of each line of the liquid crystal panel is output.

Image data is input from the image data extraction circuit 38 to the output data configuration circuit 14.
The output data configuration circuit 14 configures (generates) output data to the liquid crystal panel by performing processing such as image correction, distribution to each of a plurality of driver circuits, timing adjustment, and the like on the image data. It is.
Output data is output from the output data configuration circuit 14.

The parallel-serial conversion circuit 16 receives a reference clock and output data from the output data configuration circuit 14.
The parallel-serial conversion circuit 16 converts output data from parallel data to serial data in synchronization with a reference clock.
The parallel-serial conversion circuit 16 outputs serial data output data.

The output IF circuit 18 receives serial data output data from the parallel-serial conversion circuit 16 and an activation signal from the output IF activation signal generation circuit 36.
The output IF circuit 18 controls the operation of a driver circuit that drives the liquid crystal panel in accordance with output data of serial data, that is, image data extracted from received data.
The output IF circuit 18 is stopped after the vertical blanking period starts, that is, after the image display period of the previous frame ends, and is activated by the activation signal.
A control signal for controlling the operation of the driver circuit is output from the output IF circuit 18.

The control data holding circuit 20 holds two image timing data 1 and 2 as control data for controlling the timing at which the source circuit 22 transmits MSA as special data to the timing controller 10.
Two image timing data 1 and 2 are output from the control data holding circuit 20 as control data.
Image timings 1 and 2 output from the control data holding circuit 20 are input to the sink circuit 12 of the timing controller 10, output from the input / output IF circuit 40, and transmitted to the source circuit 22 through the auxiliary channel.

  The image timing data 1 and 2 are the vertical blanking period length from the end timing of the image display period of the previous frame to the start timing of the image display period of the next frame, and vertical synchronization from the start of the vertical blanking period. Of the length of the front porch period until the start of the signal, the length of the vertical synchronization signal, and the length of the back porch period from the end of the vertical synchronization signal to the end of the vertical blanking period, the length of the vertical blanking period Only the length and the length of the front porch period are different data.

  In the present embodiment, the image timing data 1 and 2 are held as EDID (Extended Display Identification Data) of the display port. The EDID can store a plurality of image timing data in which the transmission timing of special data that can be received by the liquid crystal panel is defined. In this way, the circuit scale can be reduced by using, as the control data holding circuit 20, the holding circuit that holds the EDID that is already arranged outside the timing controller 10.

  Next, the operation of the timing controller 10 will be described with reference to the timing charts shown in FIGS.

  In the case of this embodiment, the output IF circuit 18 is stopped after the vertical blanking period starts, and the supply of power to the buffer of the output IF circuit 18 that outputs a control signal for controlling the operation of the driver circuit is stopped. Shall be.

  First, the source circuit 22 receives the image timing data 1 and 2 as the control data held in the control data holding circuit 20 through the auxiliary channel.

  Based on the two image timing data 1 and 2 received from the control data holding circuit 20, the source circuit 22 determines only the length of the vertical blanking period and the length of the front porch period of the two image timing data 1 and 2. Since the source circuit 22 varies the length of the vertical blanking period, it is determined that only the length of the front porch period is variable.

  The source circuit 22 detects a variable range of the vertical blanking period and a variable range of the length of the front porch period based on the two image timing data 1 and 2. For example, the variable range of the length of the vertical blanking period is a range from the length of the vertical blanking period of the image timing data 1 to the length of the vertical blanking period of the image timing data 2. The variable range of the length of the front porch period can be determined in the same manner.

  The source circuit 22 varies the length of the vertical blanking period and the length of the front porch period within the variable range of the length of the vertical blanking period and the length of the front porch period, and sends it to the timing controller 10. Send. That is, the source circuit 22 can change the length of the vertical blanking period by changing only the length of the front porch period.

  Further, the source circuit 22 transmits MSA as special data to the timing controller 10 in synchronization with the start timing of the vertical synchronization signal after the length of the vertical blanking period and the length of the front porch period are changed.

In the case of this embodiment, as shown in the timing chart of FIG. 2, the vertical synchronization signal is at a low level for a certain period from the end timing of the front porch period. Further, MSA becomes high level for a certain period from the start timing of the vertical synchronization signal.
As will be described in detail later, the activation signal becomes high level for a certain period after a certain period after the MSA is extracted from the received data.

Further, when the front porch period, the vertical synchronization signal period, and the back porch period in the vertical blanking period shown in the upper timing chart of FIG. 3 are standard, as shown in the timing chart in the center of FIG. When the length is increased, the length of the vertical blanking period increases as the length of the front porch period increases.
On the other hand, as shown in the timing chart at the bottom of FIG. 3, when the length of the front porch period is decreased, the length of the vertical blanking period is decreased according to the decrease of the length of the front porch period.
Whether the length of the front porch period is increased or decreased, the length of the vertical synchronization signal period and the length of the back porch period remain the same.

  Further, as shown in the timing chart of FIG. 3, the timing of the start of the vertical synchronization signal varies according to the variation of the length of the front porch period, but the MSA of the special data indicates the start of the varied vertical synchronization signal. Sent in synchronization with the timing.

  Subsequently, the serial / parallel conversion circuit 26 converts the reception data received from the source circuit 22 from serial data to parallel data, and outputs the parallel data reception data.

  Subsequently, the MSA extraction circuit 28 extracts MSA from the received parallel data as special data that is transmitted only once during the vertical blanking period in synchronization with the start timing of the vertical synchronization signal, and extracts the MSA. An MSA timing signal representing the selected timing is output.

  In the case of this embodiment, as shown in the timing chart of FIG. 4, the MSA timing signal is at a high level for a certain period at the timing when the MSA is extracted.

  Further, the line head extraction circuit 30 extracts the line head data representing the head of the period during which the image data of each line of the liquid crystal panel is transmitted from the parallel data received data, and represents the timing at which the line head data is extracted. The line head signal is output.

  In the case of this embodiment, as shown in the timing chart of FIG. 4, the line head signal is at a high level for a certain period at the timing when the line head data is extracted.

  Subsequently, the output IF activation signal generation circuit 36 generates a count start signal for starting the count of the line counter 32 when it is detected that the MSA is extracted as the special data from the received data based on the MSA timing signal. Is done.

  In the case of the present embodiment, the count start signal becomes high level for a certain period after the MSA timing signal becomes high level, as shown in the timing chart of FIG.

  Subsequently, when the line counter 32 is instructed to start counting by the count start signal, the number of times the line head data is extracted is counted based on the line head signal, and a line number signal indicating the count value is obtained. Is output.

  Subsequently, the count value counted by the line counter 32 reaches the count number set in the timing setting register 34 based on the line number signal and the activation signal timing setting value by the output IF activation signal generation circuit 36. When this is detected, a start signal for starting the output IF circuit 18 is generated.

In the case of the present embodiment, it is assumed that the activation signal timing setting value is '03' as shown in the timing chart of FIG.
In this case, the count value of the line counter 32 is sequentially up-counted in the order of “00”, “01”, “02”, “03”, and when the count value becomes “03”, which is the same as the start signal timing setting value, A signal is output.
The activation signal becomes high level after the count value of the line counter 32 becomes “03”, and after a certain period, in the timing chart of FIG. 4, the next line head signal becomes high level and becomes low level. Low level at timing.
When the activation signal is output, the count value of the line counter 32 is reset to “00”, and the line counter 32 operates similarly thereafter.

  The output IF circuit 18 is activated by the activation signal. When the output IF circuit 18 is activated, power is supplied to a buffer of the output IF circuit 18 that outputs a control signal for controlling the operation of the driver circuit, and communication is performed between the output IF circuit 18 and the driver circuit. For this purpose, an initialization code necessary for output is performed and the operation state is obtained.

  Subsequently, at the image display period of the next frame, the image data extraction circuit 38 extracts the image data of each line of the liquid crystal panel from the parallel data received data.

  Subsequently, the output data configuration circuit 14 performs processing such as image correction, distribution to each of the plurality of driver circuits, timing adjustment, and the like on the image data, thereby forming output data for controlling the operation of the driver circuit. The

  Subsequently, the parallel-serial conversion circuit 16 converts the output data from parallel data to serial data in synchronization with the reference clock.

  Then, the output IF circuit 18 outputs a control signal for controlling the operation of the driver circuit in accordance with the output data of the serial data, and the driver circuit drives the liquid crystal panel based on the control signal.

  As described above, the timing controller 10 extracts the special data that is transmitted only once during the vertical blanking period in synchronization with the start timing of the vertical synchronization signal from the received data, and then outputs it after a certain period. The IF circuit 18 is activated.

Thereby, in the timing controller 10, since the special data is transmitted in synchronization with the start timing of the vertical synchronization signal, the output IF circuit 18 can be reliably started based on the special data without providing a line buffer. it can. Since there is no need to provide a line buffer, the circuit scale and power consumption can be reduced.
Even if the length of the vertical blanking period is changed, the special data is transmitted in synchronization with the start timing of the vertical synchronization signal. Therefore, only the length of the front porch period is changed to change the vertical blanking period. When varying the length of the period, the output IF circuit 18 can be reliably started based on the special data.

  Although the holding circuit that holds the EDID of the display port is used as the control data holding circuit 20, similarly, a holding circuit that holds the DPCD (DisplayPort Configuration Data) of the display port can be used.

  FIG. 5 is a block diagram of the second embodiment showing the configuration of the timing controller according to the present invention. The timing controller 50 shown in the figure includes a control data holding circuit 60 instead of the control data holding circuit 20 of the timing controller 10 of the first embodiment shown in FIG. Since the other constituent elements are the same, the same constituent elements are denoted by the same reference numerals, and detailed description thereof is omitted.

The control data holding circuit 60 shown in FIG. 5 holds variable period data and two front porch period data 1 and 2 as control data.
The control data holding circuit 60 outputs variable period data and two front porch period data 1 and 2 as control data.
The variable period data and the front porch period data 1 and 2 output from the control data holding circuit 60 are output from the input / output IF circuit 40 and transmitted to the source circuit 22 via the auxiliary channel.

  The variable period data includes the length of the vertical blanking period, the length of the front porch period, the length of the vertical synchronization signal, and the length of the back porch period. This data represents that the length of the ranking period is also changed. The front porch period data 1 and 2 are data representing the lengths of the different front porch periods.

  In the case of this embodiment, the variable period data and the front porch period data 1 and 2 are held in the sink device specific field of the DPCD of the display port. The DPCD Sink Device Specific Field is an area where the sink circuit 12 can add unique data. In this way, the circuit scale can be reduced by using, as the control data holding circuit 60, the holding circuit that holds the DPCD already arranged in the timing controller 10.

  Next, the operation of the timing controller 50 will be described.

  First, the source circuit 22 receives the variable period data and the front porch period data 1 and 2 as the control data held in the control data holding circuit 60 via the auxiliary channel.

  The source circuit 22 determines that only the length of the front porch period is variable when changing the length of the vertical blanking period based on the variable period data received from the control data holding circuit 60.

  The source circuit 22 detects a variable range of the length of the vertical blanking period and a variable range of the length of the front porch period based on the two front porch period data 1 and 2. For example, the variable range of the length of the front porch period is a range from the length of the front porch period of the front porch period data 1 to the length of the front porch period of the front porch period data 2. The variable range of the length of the vertical blanking period is determined according to the variable range of the length of the front porch period.

  The source circuit 22 varies the length of the vertical blanking period and the length of the front porch period within the variable range of the length of the vertical blanking period and the length of the front porch period, and sends it to the timing controller 10. Send. That is, the source circuit 22 can change the length of the vertical blanking period by changing only the length of the front porch period.

  The source circuit 22 transmits MSA as special data to the timing controller 10 in synchronization with the start timing of the vertical synchronization signal after the length of the vertical blanking period and the length of the front porch period are changed. .

  Since the subsequent operation is the same as in the case of the timing controller 10, it will be omitted, but the timing controller 50 can obtain the same effect as in the case of the timing controller 10.

  In the above embodiment, an example in which the source circuit 22 and the sink circuit 12 are connected by a display port has been described. However, the present invention is not limited to the display port.

  Further, the sink circuit 12, the source circuit 22, the output data configuration circuit 14, the parallel-serial conversion circuit 16, the output IF circuit 18, the control data holding circuits 20, 60, the input IF circuit 24, the serial-parallel conversion circuit 26, and the MSA extraction circuit 28 Specific circuit configurations of the line head extraction circuit 30, the line counter 32, the timing setting register 34, the output IF activation signal generation circuit 36, the image data extraction circuit 38, the input / output IF circuit 40, and the like are not limited at all.

  In the above-described embodiment, the case where an existing holding circuit is used as the control data holding circuits 20 and 60 has been described as an example. However, dedicated control data holding circuits 20 and 60 may be provided, respectively.

  Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10, 50 Timing controller 12 Sink circuit 14 Output data structure circuit 16 Parallel serial conversion circuit 18 Output IF circuit 20, 60 Control data holding circuit 22 Source circuit 24 Input IF circuit 26 Serial parallel conversion circuit 28 MSA extraction circuit 30 Line head extraction circuit 32 Line counter 34 Timing setting register 36 Output IF start signal generation circuit 38 Image data extraction circuit 40 Input / output IF circuit

Claims (6)

A timing controller for controlling the operation of the liquid crystal panel,
An output interface circuit that controls the operation of a driver circuit that drives the liquid crystal panel according to image data extracted from received data received from an external device;
A special data extraction circuit for extracting special data transmitted only once during a vertical blanking period in synchronization with the start timing of the vertical synchronization signal from the received data;
A line head extraction circuit that extracts line head data representing the head of a period in which image data of each line of the liquid crystal panel is transmitted from the received data;
A line counter that counts the number of times the line head data is extracted and outputs a count value;
A count number setting circuit for setting a count number counted by the line counter;
An output interface activation circuit that starts counting the line counter when the special data is extracted and activates the output interface circuit when the count value reaches the count number; A featured timing controller.   The timing controller according to claim 1, further comprising a control data holding circuit that holds control data for controlling a timing at which the external device transmits the special data to the timing controller.   The control data holding circuit includes a length of the vertical blanking period, a length of a front porch period from the start of the vertical blanking period to the start of the vertical synchronization signal, the length of the vertical synchronization signal, and the Of the length of the back porch period from the end of the vertical synchronization signal to the end of the vertical blanking period, two image timing data differing only in the length of the vertical blanking period and the length of the front porch period The timing controller according to claim 2, which is held as control data.   When the external device varies the length of the vertical blanking period based on the two image timing data received from the control data holding circuit, only the length of the front porch period is variable. Determining, detecting a variable range of the length of the vertical blanking period and a variable range of the length of the front porch period, and changing the variable range of the length of the vertical blanking period and the length of the front porch period. Varying the length of the vertical blanking period and the length of the front porch period within a range, and starting the vertical synchronization signal after the length of the vertical blanking period and the length of the front porch period are varied The timing of claim 3, having a function of transmitting the special data to the timing controller in synchronization with the timing of Controller circuit.   The control data holding circuit includes a length of the vertical blanking period, a length of a front porch period from the start of the vertical blanking period to the start of the vertical synchronization signal, the length of the vertical synchronization signal, and the Of the length of the back porch period from the end of the vertical synchronization signal to the end of the vertical blanking period, the length of the front porch period is variable, and the variable indicates that the length of the vertical blanking period is also changed The timing controller according to claim 2, wherein period data and two front porch period data representing a length of the front porch period are held as the control data.   The external device determines that only the length of the front porch period is variable when changing the length of the vertical blanking period based on the variable period data received from the control data holding circuit. Detecting the variable range of the length of the vertical blanking period and the variable range of the length of the front porch period based on the two front porch period data received from the control data holding circuit, and detecting the vertical blanking. The length of the vertical blanking period and the length of the front porch period are varied within the variable range of the length of the period and the variable range of the length of the front porch period, and the length of the vertical blanking period and the The special data is synchronized with the start timing of the vertical synchronization signal after the length of the front porch period is changed. Having a function of transmitting to Lee timing controller, a timing controller according to claim 5.

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