JP2017151604A - Arithmetic processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic processing unit configured to improve efficiency of arithmetic processing by implementing a plurality of arithmetic blocks and a plurality of memories.SOLUTION: An arithmetic processing unit 10 includes a plurality of processing layers connected hierarchically. The processing layers each including a relay unit 13 and a relay unit 12 are connected to each other. The relay unit 13 outputs arithmetic result data to be generated by a pair of arithmetic blocks 11 to a pair of data holding units 14, or outputs accumulated arithmetic result data to the pair of data holding units or a data holding unit arranged in a lower order than the above data holding units. The relay unit 12 outputs the data held in the pair of data holding units to the pair of arithmetic blocks, or outputs the data held in the pair of data holding units to the pair of arithmetic blocks and an arithmetic block arranged in a higher order than the above arithmetic blocks. The arithmetic processing unit is configured to prevent wiring connecting the plurality of arithmetic blocks to a plurality of memories from being complicated, while preventing reduction in processing speed or increase in size of the device.SELECTED DRAWING: Figure 5

Description

  The present invention relates to an arithmetic processing device.

  2. Description of the Related Art Conventionally, there has been considered an arithmetic processing device that executes arithmetic operations using a neural network in which a plurality of processing layers are hierarchically connected. Particularly in arithmetic processing devices that perform image recognition, a so-called convolutional neural network (CNN) is at the core.

Japanese Patent No. 5184824

  By the way, in this kind of arithmetic processing device, in order to cope with the increase in the number of arithmetic processing layers and the complexity of arithmetic processing, a plurality of arithmetic blocks and a plurality of memories are mounted. It is considered to connect a plurality of memories and to connect a plurality of operation blocks to one memory. According to this configuration, one arithmetic block can write data to a plurality of memories, and data can be read from one memory to a plurality of arithmetic blocks. In addition, it is possible to efficiently perform arithmetic processing corresponding to the complexity of arithmetic processing. However, the wiring for connecting a plurality of operation blocks and a plurality of memories becomes complicated, and there is a concern that the processing speed will decrease and the size of the operation processing device will increase.

  Therefore, the present invention provides a complicated wiring for connecting a plurality of operation blocks and a plurality of memories in an operation processing apparatus designed to improve the efficiency of the operation processing by mounting a plurality of operation blocks and a plurality of memories. It is an object of the present invention to provide a configuration that can suppress the decrease in processing speed and increase in the size of the apparatus.

  An arithmetic processing apparatus according to the present invention is an arithmetic processing apparatus that executes an operation by a plurality of processing layers connected in a hierarchy, and each of the operation blocks that executes the operation and a plurality of the operation blocks. A plurality of data holding units, and a plurality of data output units each paired with the plurality of operation blocks. The plurality of calculation blocks, the plurality of data holding units, and the plurality of data output units are respectively arranged in a row from the lower side to the upper side. The plurality of operation blocks sequentially accumulate operation result data from the lower side toward the upper side. The data output unit outputs the operation result data generated by the pair of operation blocks to the data holding unit that forms a pair, or the data holding unit that forms a pair of accumulated operation result data and the data holding unit Is output to the data holding unit on the lower side.

  The arithmetic processing device according to the present invention is an arithmetic processing device that executes arithmetic operations by a plurality of hierarchically connected processing layers, and includes a plurality of arithmetic blocks that execute the arithmetic operations, and a plurality of the arithmetic blocks. A plurality of data holding units each making a pair; and a plurality of data output units each making a pair with the plurality of operation blocks. The plurality of calculation blocks, the plurality of data holding units, and the plurality of data output units are respectively arranged in a row from the lower side to the upper side. The data output unit outputs the data held by the data holding unit that makes a pair to the operation block that makes a pair, or the operation that makes a pair of the data held by the data holding unit that makes a pair The data is output to the block and the calculation block above the calculation block.

  According to the arithmetic processing device according to the present invention, it is possible to write the operation result data of one arithmetic block into a plurality of data holding units by the selection processing by the data output unit. In addition, according to the arithmetic processing device according to the present invention, it is possible to distribute the data held by one data holding unit to a plurality of calculation blocks by the selection process by the data output unit. According to this configuration, it is possible to efficiently read and write data between the plurality of operation blocks and the plurality of data holding units, while suppressing the complexity of the wiring connecting the plurality of operation blocks and the plurality of data holding units. This can be done, and a reduction in processing speed and an increase in the size of the apparatus can be avoided.

A diagram conceptually showing a configuration example of a convolutional neural network The figure which shows the flow of arithmetic processing in the middle layer visually (the 1) A diagram visually showing the flow of arithmetic processing in the intermediate layer (Part 2) Diagram showing general arithmetic expressions and functions used for feature extraction processing 1 is a block diagram schematically showing a configuration example of an arithmetic processing device according to the present embodiment. Block diagram schematically showing an example of the configuration of an arithmetic block Block diagram (part 1) schematically showing an operation example of the arithmetic processing unit Block diagram schematically showing an operation example of the arithmetic processing unit (part 2) Block diagram schematically showing an operation example of the arithmetic processing unit (part 3) Block diagram schematically showing an operation example of the arithmetic processing unit (part 4) The figure which shows the example of the determination of the address of the external memory which a data holding part accesses (the 1) The figure which shows the example of determination of the address of the external memory which a data holding part accesses (the 2)

Hereinafter, an embodiment of an arithmetic processing device will be described with reference to the drawings.
(neural network)
FIG. 1 conceptually shows the configuration of a neural network that is applied to an arithmetic processing unit 10 described later in detail, in this case, a convolutional neural network. The convolutional neural network N is applied to an image recognition technique for recognizing a predetermined shape or pattern from image data D1, which is input data, and includes an intermediate layer Na and a total coupling layer Nb. The intermediate layer Na has a configuration in which a plurality of feature quantity extraction processing layers Na1, Na2,. Each feature amount extraction processing layer Na1, Na2,... Includes a convolution layer C and a pooling layer P, respectively.

  Next, the flow of processing in the intermediate layer Na will be described. As illustrated in FIG. 2, in the first feature amount extraction processing layer Na1, the arithmetic processing unit scans the input image data D1 for each predetermined size by, for example, raster scanning. A plurality of feature amounts included in the input image are extracted by performing a known feature amount extraction process on the scanned data. Note that the first feature amount extraction processing layer Na1 extracts relatively simple single feature amounts such as a linear feature amount extending in the horizontal direction and a linear feature amount extending in the oblique direction. At this time, the arithmetic processing device generates a plurality of feature maps respectively corresponding to the plurality of features included in the input image.

  In the second feature amount extraction processing layer Na2, the arithmetic processing unit scans the input data input from the preceding feature amount extraction processing layer Na1 for each predetermined size by, for example, raster scanning. A plurality of feature amounts included in the input image are extracted by performing a known feature amount extraction process on the scanned data. In addition, in the feature amount extraction processing layer Na2 of the second layer, by integrating the spatial positional relationship of a plurality of feature amounts extracted by the feature amount extraction processing layer Na1 of the first layer, Extract higher-dimensional composite features. At this time, the arithmetic processing device generates a plurality of feature maps respectively corresponding to the plurality of features included in the input image.

  In the third feature quantity extraction processing layer Na3, the arithmetic processing unit scans the input data input from the previous feature quantity extraction processing layer Na2 for each predetermined size by, for example, raster scanning. A plurality of feature amounts included in the input image are extracted by performing a known feature amount extraction process on the scanned data. The feature extraction processing layer Na3 of the third layer is integrated by considering the spatial positional relationship of a plurality of feature amounts extracted by the feature extraction processing layer Na2 of the second layer, Extract higher-dimensional composite features. At this time, the arithmetic processing device generates a plurality of feature maps respectively corresponding to the plurality of features included in the input image. In this way, by repeating the feature amount extraction processing by the plurality of feature amount extraction processing layers, the arithmetic processing device performs image recognition of the detection target object included in the image data D1.

  The arithmetic processing unit extracts various feature amounts included in the input image data D1 in a high dimension by repeating the processing by the plurality of feature amount extraction processing layers Na1, Na2, Na3... In the intermediate layer Na. Then, the arithmetic processing unit outputs the result obtained by the processing of the intermediate layer Na to the all coupling layer Nb as intermediate operation result data.

  The total coupling layer Nb combines a plurality of intermediate calculation result data obtained from the intermediate layer Na and outputs final calculation result data. That is, the total connection layer Nb combines a plurality of intermediate operation result data obtained from the intermediate layer Na, and further performs a sum-of-products operation while varying the weighting coefficient for the combined result, thereby obtaining a final operation. Result data, that is, image data in which the detection target included in the image data D1 as input data is recognized is output. At this time, the part where the value of the result of the product-sum operation is large is recognized as a part or all of the detection target.

  Next, a flow of feature amount extraction processing by the arithmetic processing device will be described. As illustrated in FIG. 3, the arithmetic processing device uses a predetermined size for the input data Dn input from the feature extraction processing layer in the previous hierarchy, in this case, according to the filter size for each 3 × 3 pixel indicated by hatching in the figure. Scan. Note that the pixel size is not limited to 3 × 3 pixels, and can be appropriately changed, for example, 5 × 5 pixels.

  The arithmetic processing unit performs a known convolution operation on the scanned data. Then, the arithmetic processing device performs a well-known activation process on the data after the convolution operation, and outputs the result to the convolution layer C. Then, the arithmetic processing unit performs a well-known pooling process on the output data Cn of the convolution layer C at a predetermined size, in this case, 2 × 2 pixels, and outputs the result to the pooling layer P. Then, the arithmetic processing device outputs the output data Pn of the pooling layer P to the feature amount extraction processing layer of the next layer. The pixel size is not limited to 2 × 2 pixels and can be changed as appropriate.

  FIG. 4 shows general examples of a convolution function used for convolution operation processing, a function used for activation processing, and a function used for pooling processing. That is, the convolution function Yij is a function that accumulates values obtained by multiplying the output Xij of the immediately preceding layer by the weighting factors Wp, q obtained by learning. Note that “N” indicates a pixel size to be processed by one cycle of convolution operation processing. That is, for example, when the pixel size of one calculation cycle is “3 × 3” pixels, the value of N is “2”. Further, the convolution function Yij may be a function for adding a predetermined bias value to the accumulated value. Various functions can be adopted as the convolution function as long as it is a function capable of multiply-accumulate operation that can cope with all-join processing. For the activation process, a well-known logistic sigmoid function, ReLU function (Rectified Linear Units), or the like is used. For the pooling process, a known maximum pooling function that outputs a maximum value of input data, a known average pooling function that outputs an average value of input data, or the like is used.

  According to the convolutional neural network N described above, the processing by the convolution layer C and the processing by the pooling layer P are repeated, so that higher-dimensional feature amounts can be extracted. Next, an embodiment according to an arithmetic processing apparatus to which the convolution neural network N is applied will be described.

(One embodiment)
The arithmetic processing apparatus 10 illustrated in FIG. 5 includes a plurality of arithmetic blocks 11, a plurality of relay units 12 and 13, a plurality of data holding units 14, a plurality of interfaces 15, and the like. In the arithmetic processing device 10, one arithmetic processing unit 16 is configured by one arithmetic block 11, two relay units 12 and 13, and one data holding unit 14. The arithmetic processing unit 10 has a configuration in which a plurality of arithmetic processing units 16 are arranged in a line from the downstream side toward the upstream side. For convenience of explanation, the lower side of the figure is defined as the downstream side, and the upper side of the figure is defined as the upstream side. The arithmetic processing units 16 are each connected to the interconnect unit 17 via the interface 15. The interconnect unit 17 is connected to an external memory 18 provided outside the arithmetic processing apparatus 10.

  As illustrated in FIG. 6, the calculation blocks 11 each include a convolution calculation processing unit 11 a, an accumulation processing unit 11 b, an activation processing unit 11 c, a pooling processing unit 11 d, and the like. These processing units may be configured by hardware such as a circuit, may be configured by software, or may be configured by a combination of hardware and software. The convolution operation processing unit 11a performs a known convolution operation process on the input data input from the previous layer, and outputs the processing result data to the accumulation processing unit 11b.

  The accumulation processing unit 11b is configured by an adder, for example. When the data is input from the accumulation processing unit 11b of the lower-order calculation block 11, the accumulation processing unit 11b adds the data to the data input from the convolution calculation processing unit 11a of the same calculation block 11 as itself. To do. Thereby, the plurality of operation blocks 11 can sequentially accumulate operation result data by the convolution operation processing unit 11a of each operation block 11 from the lower side to the upper side.

  When no data is input from the lower calculation block 11, the accumulation processing unit 11b outputs the data input from the convolution calculation processing unit 11a of the same calculation block 11 to the activation processing unit 11c. In addition, when data is input from the lower calculation block 11, the accumulation processing unit 11 b inputs data input from the convolution calculation processing unit 11 a of the same calculation block 11 from the lower calculation block 11. The accumulated data obtained by adding the data to be output is output to the activation processing unit 11c.

  The activation processing unit 11c executes a well-known activation process on the data input from the accumulation processing unit 11b, and outputs the processing result data to the pooling processing unit 11d. The pooling processing unit 11d executes a well-known pooling process on the processing result data from the activation processing unit 11c, and outputs the processing result data.

  The relay unit 12 is an example of a data output unit for outputting data from the data holding unit 14 to the operation block 11, and includes a multiplexer circuit, a flip-flop circuit, and the like (not shown). The relay unit 12 can output data input from the data holding unit 14 of the same arithmetic processing unit 16 to the arithmetic block 11 of the same arithmetic processing unit 16 as itself. The relay unit 12 selects either one of data input from the data holding unit 14 of the same arithmetic processing unit 16 as that of the relay unit 12 and data input from the relay unit 12 on the lower side than itself. The selected data can be output to the arithmetic block 11 of the same arithmetic processing unit 16 as itself.

  The relay unit 13 is an example of a data output unit for outputting data from the arithmetic block 11 to the data holding unit 14, and includes a multiplexer circuit, a flip-flop circuit, and the like (not shown). The relay unit 13 can output data input from the calculation block 11 of the same arithmetic processing unit 16 to the data holding unit 14 of the same arithmetic processing unit 16 as itself. The relay unit 13 selects either one of data input from the arithmetic block 11 of the same arithmetic processing unit 16 as that of the relay unit 13 and data input from the relay unit 13 on the higher side than itself, The selected data can be output to the data holding unit 14 of the same arithmetic processing unit 16 as itself.

  The data holding unit 14 functions as a so-called internal memory, and temporarily holds input data input during calculation processing in the current hierarchy, that is, calculation result data, and output data output during calculation processing in the next hierarchy. To do. The data holding unit 14 includes two buffers 14a and 14b, respectively. The data holding unit 14 includes a switching function unit (not shown). The switching function unit has a function of switching the buffers 14 a and 14 b for data output to the operation block 11 and data input from the operation block 11.

  That is, the switching function unit switches the buffer 14b to function for data input when the buffer 14a functions for data output, for example. Further, the switching function unit switches the buffer 14b to function for data output when the buffer 14a functions for data input.

  The data holding unit 14 holds input data, that is, calculation result data, input at the time of calculation processing in the current hierarchy in the buffer 14a or the buffer 14b switched for data input. Then, the data holding unit 14 switches the buffer 14a or the buffer 14b, which has been switched for data input in the current layer arithmetic processing, to data output during the next layer arithmetic processing, and the data held in the buffer. Is output to the calculation block 11. Thereby, the data holding unit 14 can send the operation result data of the current layer to the next layer within the operation processing device 10 without saving the operation result data in the operation processing of the current layer to the external memory 18. .

  The external memory 18 is a large-scale storage medium configured by, for example, a Double-Data-Rate-SDRAM, and can store input image data D1, operation result data by the operation block 11, and the like. In this case, the external memory 18 is connected to a plurality of interfaces 15, in other words, a plurality of arithmetic processing units 16 via the interconnect unit 17. The interconnect unit 17 has a function of distributing data read from the external memory 18 to each arithmetic processing unit 16. The interconnect unit 17 has a function of collecting data written from each arithmetic processing unit 16 to the external memory 18 in the external memory 18.

  The arithmetic processing device 10 further includes a redundant data holding unit 19. The redundant data holding unit 19 includes two buffers 19 a and 19 b as with the data holding unit 14. The functions of these buffers 19a and 19b are the same as those of the buffers 14a and 14b described above. The redundant data holding unit 19 holds the data output from the lowermost relay unit 13 redundantly with the lowermost data holding unit 14. The lowest-order calculation block 11 can add the data held in the redundant data holding unit 14 to the calculation result data generated by itself.

  Next, an operation example of the arithmetic processing device 10 will be described. That is, as illustrated in FIG. 7, when the calculation result data by the plurality of calculation blocks 11 are accumulated and processed, as shown by the arrow A <b> 1, the uppermost relay unit 13 performs the same calculation process as itself. Data input from the arithmetic block 11 of the unit 16, that is, accumulated data is selected and output to the data holding unit 14 of the same arithmetic processing unit 16 as itself. Further, the other relay units 13 other than the highest-level relay unit 13 select data input from the relay unit 13 on the higher side than that of the relay unit 13, that is, accumulated data, and hold the data of the same arithmetic processing unit 16 as that of itself. To the unit 14.

  Further, as illustrated in FIG. 8, when the calculation result data by the plurality of calculation blocks 11 are processed in parallel without being accumulated, as shown by the arrow A <b> 2, each relay unit 13 performs the same calculation as itself. Data input from the arithmetic block 11 of the processing unit 16 is selected and output to the data holding unit 14 of the same arithmetic processing unit 16 as itself.

  Also, as illustrated in FIG. 9, when one data is distributed and processed by a plurality of calculation blocks 11, the lowermost relay unit 12 performs the same calculation process as itself, as indicated by an arrow A 3. Data input from the data holding unit 14 of the unit 16 is selected and output to the arithmetic block 11 of the same arithmetic processing unit 16 as itself. Further, the other relay units 12 other than the lowest-order relay unit 12 select data input from the relay unit 12 on the lower side than the relay unit 12 and output the selected data to the operation block 11 of the same processing unit 16 as that of itself. .

  Further, as illustrated in FIG. 10, when the processing is performed in parallel without being distributed by the plurality of operation blocks 11, as indicated by the arrow A <b> 4, each relay unit 12 has the same operation processing unit as itself. The data input from the 16 data holding units 14 is selected and output to the arithmetic block 11 of the same arithmetic processing unit 16 as itself.

  According to the arithmetic processing apparatus 10, one arithmetic processing unit 16 is configured by one arithmetic block 11, two relay units 12 and 13, and one data holding unit 14. The relay unit 13 can output the operation result data generated by the operation block 11 that makes a pair in the same operation processing unit 16 to the data holding unit 14 that makes a pair in the same operation processing unit 16. In addition, the relay unit 13 transfers the calculation result data accumulated by the plurality of calculation blocks 11 to the data holding unit 14 that forms a pair in the same arithmetic processing unit 16 and the data holding unit 14 that is lower than the data holding unit 14. It is possible to output.

  Further, according to the arithmetic processing device 10, the relay unit 12 outputs the data held by the data holding unit 14 that makes a pair in the same arithmetic processing unit 16 to the arithmetic block 11 that makes a pair in the same arithmetic processing unit 16. Is possible. In addition, the relay unit 12 converts the data held in the data holding unit 14 that makes a pair in the same arithmetic processing unit 16 into the arithmetic block 11 that makes a pair in the same arithmetic processing unit 16 and the upper side of the arithmetic block 11. It is possible to output to the calculation block 11.

  That is, according to the arithmetic processing device 10, it is possible to write the calculation result data of one calculation block 11 to the plurality of data holding units 14 by the selection process by the relay unit 13. Further, according to the arithmetic processing device 10, the data held by one data holding unit 14 can be distributed to the plurality of calculation blocks 11 by the selection process by the relay unit 12. According to this configuration, data reading / writing is performed between the plurality of operation blocks 11 and the plurality of data holding units 14 while suppressing the complexity of the wiring connecting the plurality of operation blocks 11 and the plurality of data holding units 14. Can be efficiently performed, and a reduction in processing speed and an increase in the size of the apparatus can be avoided.

  Further, according to the arithmetic processing unit 10, the redundant data holding unit 19 holds the data output from the lowest-order relay unit 13 redundantly with the lowest-order data holding unit 14. That is, the redundant data holding unit 19 holds the same data as the lowest data holding unit 14. The lowest-order calculation block 11 can read the data held in the redundant data holding unit 19 and add it to its own calculation result data.

  According to this configuration, for example, when the number of data to be calculated in a certain processing hierarchy exceeds the number of calculation blocks 11 and calculation cannot be performed on all data in one calculation cycle, first, the calculation block Arithmetic processing is performed on the data corresponding to the number of 11 and the calculation result is held in the redundant data holding unit 19. When the arithmetic processing is performed on the next data corresponding to the number of arithmetic blocks 11, the data held in the redundant data holding unit 19 can be read and cumulatively added. Therefore, even when processing more data than the number of operation blocks 11, that is, when feature map data is processed, the operation processing results obtained by dividing the operation block 11 by the number of operations are sequentially accumulated and added. Thus, a total calculation processing result for all data can be obtained.

  In addition, the arithmetic processing device 10 includes the external memory 18 that can be directly accessed by the plurality of data holding units 14. According to this configuration, when the data size to be stored exceeds the capacity of the buffers 14a and 14b, the data can be saved in the external memory 18, which corresponds to a calculation process for data having a large data size. be able to.

  Further, the arithmetic processing device 10 employs a DMA method (Direct Memory Access) as an access method between the data holding unit 14 and the external memory 18. Therefore, the data writing process and the data reading process between the data holding unit 14 and the external memory 18 can be performed at high speed.

At this time, the external memory 18 may be configured to determine an address to be accessed by the data holding unit 14 by the following equation [1] or equation [2].
A [n] = a [n] + m × d [1]
A [n] = a [0] + m × d (2)
n: Number of the data holding unit
A [n]: Address accessed by the nth data holding unit
a [n]: Offset address of the nth data holding unit
m: Number of feature map generated by the calculation block
d: Data size of the feature map generated by the calculation block

When the address is determined by the expression [1], as illustrated in FIG. 11, for example, the address A [1] accessed by the first, that is, the highest data holding unit 14 is the offset of the first data holding unit 14. If the address a [1] is “1000”, the feature map number generated by the computation block 11 is “1”, and the data size of the feature map 1 created by the computation block 11 is “300” bytes,
A [1] = “1000” + “1” × “300”
= 1300
It becomes.

Further, for example, the address A [2] accessed by the second data holding unit 14 from the second highest, that is, the offset address a [2] of the second data holding unit 14 is “2000”, and the calculation block 11 When the number of the feature map to be generated is “1” and the data size of the feature map 1 generated by the calculation block 11 is “300” bytes,
A [2] = “2000” + “1” × “300”
= 2300
It becomes.

  That is, when the address is determined by the equation [1], the plurality of data holding units 14 access the addresses assigned to each. In other words, the memory area of the external memory 18 is divided and used by the plurality of data holding units 14.

When the address is determined by the expression [2], as illustrated in FIG. 12, for example, the address A [1] accessed by the first, that is, the uppermost data holding unit 14, is a preset a [ 0] is “1000”, the feature map number generated by the computation block 11 is “1”, and the data size of the feature map 1 created by the computation block 11 is “300” bytes.
A [1] = “1000” + “1” × “300”
= 1300
It becomes.

Also, for example, the address A [2] accessed by the second, that is, the second highest data holding unit 14 also has a [0] of “1000” and the feature map number generated by the calculation block 11 of “1”. The data size of the feature map 1 generated by the calculation block 11 is “300” bytes.
A [2] = “1000” + “1” × “300”
= 1300
It becomes.

That is, when the address is determined by the expression [2], all the data holding units 14 access the same address “1300”. In other words, the memory area of the external memory 18 is shared by the plurality of data holding units 14.
Note that the present invention is not limited to the above-described embodiments, and can be applied to various embodiments without departing from the gist thereof.

  In the figure, 10 is an arithmetic processing unit, 11 is an arithmetic block, 12 is a relay unit (data output unit), 13 is a relay unit (data output unit), 14 is a data holding unit, 18 is an external memory, and 19 is redundant data. Indicates the part.

Claims (5)

An arithmetic processing device (10) that executes arithmetic operations by a plurality of processing layers connected in a hierarchical manner,
A plurality of calculation blocks (11) for performing the calculation;
A plurality of data holding units (14) each paired with a plurality of the calculation blocks;
A plurality of data output units (13) each paired with a plurality of the operation blocks;
With
The plurality of operation blocks, the plurality of data holding units, and the plurality of data output units are arranged in a row from the lower side to the upper side,
The plurality of operation blocks sequentially accumulate operation result data from the lower side to the upper side,
The data output unit outputs the operation result data generated by the pair of operation blocks to the data holding unit that forms a pair, or the data holding unit that forms a pair of accumulated operation result data and the data holding unit An arithmetic processing unit that outputs to the data holding unit on the lower side. A redundant data holding unit (19) for holding data output by the data output unit on the lowest side;
The arithmetic processing unit according to claim 1, wherein the lowermost arithmetic block adds data held in the redundant data holding unit to arithmetic result data. An arithmetic processing device (10) that executes arithmetic operations by a plurality of processing layers connected in a hierarchical manner,
A plurality of calculation blocks (11) for performing the calculation;
A plurality of data holding units (14) each paired with a plurality of the calculation blocks;
A plurality of data output units (12) each paired with a plurality of the operation blocks;
With
The plurality of operation blocks, the plurality of data holding units, and the plurality of data output units are arranged in a row from the lower side to the upper side,
The data output unit outputs the data held by the data holding unit that makes a pair to the operation block that makes a pair, or the operation that makes a pair of the data held by the data holding unit that makes a pair An arithmetic processing unit that outputs the block and the arithmetic block on the upper side of the arithmetic block.   The arithmetic processing unit according to any one of claims 1 to 3, further comprising an external memory (18) directly accessible by a plurality of the data holding units. The calculation block generates a plurality of feature maps respectively corresponding to a plurality of features included in input data,
The arithmetic processing apparatus according to claim 4, wherein the external memory determines an address to be accessed by the data holding unit using the following formula [1] or formula [2].
A [n] = a [n] + m × d [1]
A [n] = a [0] + m × d (2)
n: Number of the data holding unit
A [n]: Address accessed by the nth data holding unit
a [n]: Offset address of the nth data holding unit
m: Number of feature map generated by the calculation block
d: Data size of the feature map generated by the calculation block

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