JP2017092299A - Thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor capable of obtaining intended transfer characteristics.SOLUTION: A thin film transistor 10 includes: a gate electrode 12 provided on a substrate 11; a first gate insulation film 13 provided on the gate electrode 12; a second gate insulation film 14 which is provided on the first gate insulation film 13 and thinner than the first gate insulation film 13; a semiconductor layer 15 which is provided on the second gate insulation film 14 and includes an oxide semiconductor; and a source electrode 17 and a drain electrode 18 which are provided on the semiconductor layer 15. A hydrogen content of the second gate insulation film 14 is lower than a hydrogen content of the first gate insulation film 13.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a thin film transistor, for example, a thin film transistor applicable to a liquid crystal display device.

  In recent years, thin film transistors (oxide TFTs) using an oxide semiconductor for a channel layer have been actively developed. Among them, TFTs using an oxide semiconductor material (IGZO) containing indium (In), gallium (Ga), and zinc (Zn) for the channel layer are also examples of commercialization adopted for active matrix liquid crystal displays. It can be said that it is the most mainstream oxide semiconductor material.

  It is known that an oxide semiconductor is easily reduced when exposed to a reducing environment and affects the characteristics of the oxide semiconductor element. For example, in an environment where the oxide semiconductor tends to be oxidized, the TFT transfer characteristics shift in the positive direction, and in an environment where the oxide semiconductor tends to be reduced, the TFT transfer characteristics shift in the negative direction.

  Taking an inverted staggered type oxide TFT as an example, an oxide semiconductor is stacked on the gate insulating film, so the transfer environment (relationship between gate voltage and drain current) depends on whether the interface environment is reducing or oxidizing. Is greatly affected.

  The transfer characteristic is desirably controlled so as to approach a so-called normally-off characteristic in which the drain current is small, for example, 1 nA or less when the gate voltage is 0V. As described above, an oxide semiconductor is easily reduced, and thus easily falls into a normally-on characteristic. That is, it is important to control the transfer characteristics so that the interface between the oxide semiconductor and the insulating film has an oxidation tendency.

  Therefore, it is easily imagined that the insulating film which is stacked with the oxide semiconductor is preferably a film containing an oxide as a main component. In reality, considering productivity and workability, a film containing silicon oxide as a main component (hereinafter referred to as SiOx system) is a better option.

  In the field of giant microelectronics such as TFT, both physical vapor deposition (PVD) and chemical vapor deposition (CVD) are used for SiOx film formation. Since it is difficult to obtain an insulating film, the CVD film is mainly used.

For SiOx-based CVD film formation, for example, a source gas such as monosilane or TEOS (tetraethyl orthosilicate) and an oxidant gas such as oxygen (O ₂ ) or nitrous oxide (N ₂ O) are used.

  However, since such a source gas contains hydrogen as a constituent element, hydrogen is also taken into the deposited SiOx-based film. If an oxide semiconductor is laminated inadvertently, there is a possibility that an interface having a tendency to reduce is formed due to the presence of hydrogen in the SiOx-based film. Alternatively, in the case where an SiOx-based film is stacked on an already formed oxide semiconductor using these source gases, the oxide semiconductor may be reduced by hydrogen dissociated from the source gas. Therefore, the insulating film that forms an interface with the oxide semiconductor is desirably a SiOx-based film that contains as little hydrogen as possible.

  In general, in order to deposit a film containing a small amount of hydrogen, a gas flow rate ratio in a direction in which the source gas containing hydrogen is reduced and the oxidant gas is increased may be used. However, since the raw material gas is reduced, there is a problem that the film formation is delayed and the productivity is lowered.

  In addition, since the SiOx-based film formed by CVD by such a method is amorphous, it is considered that the film quality is maintained by the defect being plugged with hydrogen. Therefore, if the film formation conditions are such that the amount of hydrogen contained is extremely small, there are many defects that cannot be blocked by hydrogen, which may result in a low-quality insulating film.

  However, when an element is manufactured using such a low-quality insulating film, desired electrical characteristics cannot be obtained due to many defects, insulation withstand voltage is poor, or reliability is poor due to poor barrier properties. To do.

  Therefore, a SiOx film, a silicon nitride film (hereinafter, SiNx film) mainly composed of silicon nitride, which has already been used in amorphous silicon TFT liquid crystal displays and has been proved to have a necessary and sufficient quality, and an insufficient quality SiOx film. In combination with the above, a configuration has been proposed in which the quality of the entire insulating film including the interface is ensured while maintaining a reducing environment for the oxide semiconductor.

  Patent Document 1 proposes a configuration in which a SiNx-based film and a SiOx-based film are stacked. When used as a bottom gate insulating film, a SiNx-based film is formed on the gate electrode side and a SiOx-based film is formed on the oxide semiconductor side to prevent the oxide semiconductor from being reduced.

  Patent Document 2 proposes an insulating film containing silicon oxynitride as a main component and containing oxygen having a concentration gradient in the film thickness direction. If used as a bottom gate insulating film, film formation is started from the gate electrode side at a gas flow rate ratio that becomes a composition close to SiNx, and the film flow rate is gradually changed to a gas flow ratio that becomes a composition close to SiOx while continuing the film formation. Thus, an insulating film having a concentration gradient of oxygen contained in the film thickness direction is manufactured. That is, the oxide semiconductor is prevented from being reduced by making the oxide semiconductor side a SiOx-based film.

  However, the SiNx-based film formed by CVD by these methods is also amorphous, and the film quality is maintained by closing defects with hydrogen. Further, since the SiNx-based film is generally formed in a more reducing atmosphere, it is normal that the SiNx-based film contains a larger amount of hydrogen than the SiOx-based film.

  Therefore, these configurations are preconditions that the SiOx film barriers hydrogen contained in a large amount in the SiNx film. If the barrier property of the SiOx-based film is not sufficient, there is a problem that hydrogen permeates to reach the oxide semiconductor and is reduced.

  In fact, the transfer characteristic illustrated in FIG. 4 of Patent Document 2 is not preferable because the S slope is slow. This is presumed to be caused by the poor quality of the SiOx-based film that forms an interface with the oxide semiconductor.

Japanese Patent No. 5409818 JP 2007-259882 A

  The present invention provides a thin film transistor capable of obtaining desired transfer characteristics and reducing variations in transfer characteristics.

  A thin film transistor according to one embodiment of the present invention includes a gate electrode provided over a substrate, a first gate insulating film provided over the gate electrode, and the first gate provided over the first gate insulating film. A second gate insulating film thinner than the insulating film; a semiconductor layer provided on the second gate insulating film and including an oxide semiconductor; and a source electrode and a drain electrode provided on the semiconductor layer. The hydrogen content in the second gate insulating film is lower than the hydrogen content in the first gate insulating film.

  According to the present invention, it is possible to provide a thin film transistor that can obtain desired transfer characteristics and can reduce variations in transfer characteristics.

FIG. 3 is a plan view of the TFT according to the first embodiment. FIG. 2 is a cross-sectional view of the TFT along the line AA ′ in FIG. 1. Sectional drawing which shows the other structural example of TFT. FIG. 3 is a schematic diagram of a single crystal silicon film. The schematic diagram of an amorphous silicon film. The schematic diagram of an amorphous silicon oxide film rich in hydrogen. Schematic diagram of an amorphous silicon oxide film that is hydrogen poor. Sectional drawing explaining the manufacturing process of TFT which concerns on 1st Embodiment. Sectional drawing explaining the manufacturing process of TFT which concerns on 1st Embodiment. Sectional drawing explaining the manufacturing process of TFT which concerns on 1st Embodiment. The circuit diagram of a liquid crystal display device. The graph which shows the transfer characteristic of TFT. FIG. 6 is a diagram for explaining characteristic variation among a plurality of TFTs. Sectional drawing of TFT which concerns on a comparative example. Sectional drawing of TFT which concerns on 2nd Embodiment. Sectional drawing of TFT concerning 3rd Embodiment. Sectional drawing of TFT which concerns on the modification of 3rd Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. However, it should be noted that the drawings are schematic or conceptual, and the dimensions and ratios of the drawings are not necessarily the same as the actual ones. Further, even when the same portion is represented between the drawings, the dimensional relationship and ratio may be represented differently. In particular, the following embodiments exemplify an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention depends on the shape, structure, arrangement, etc. of components. Is not specified. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[First Embodiment]
[1] Configuration of Thin Film Transistor In a liquid crystal display device called an active matrix type, a thin film transistor (TFT) including a semiconductor layer made of, for example, amorphous silicon is used for each pixel. Specifically, the liquid crystal display device includes a TFT substrate including a TFT and a pixel electrode, a color filter substrate (CF substrate) including a color filter and a common electrode, and disposed opposite to the TFT substrate, a TFT substrate, and a CF substrate. And a liquid crystal layer sandwiched between the substrates. The present embodiment relates to a configuration example of a TFT (semiconductor device) used in a liquid crystal display device.

  FIG. 1 is a plan view of the TFT 10 according to the first embodiment. FIG. 2 is a cross-sectional view of the TFT 10 taken along the line AA ′ of FIG. In this embodiment, a bottom gate type (reverse stagger type) TFT will be described as an example. The TFT 10 is, for example, an n-channel TFT.

  The substrate 11 is composed of a transparent substrate, for example, and a glass substrate is used, for example. A gate electrode 12 is provided on the substrate 11. The gate electrode 12 functions as the scanning line GL of the liquid crystal display device. In the example of FIG. 1, the gate electrode 12 protrudes in the Y direction from a part of the scanning line GL extending in the X direction. As the gate electrode 12, it is desirable to use a conductive material having a low resistance. For example, aluminum (Al), molybdenum (Mo), chromium (Cr), copper (Cu), tungsten (W), titanium (Ti), and Any of tantalum (Ta), an alloy containing one or more of these, or a transparent conductive material typified by ITO (indium tin oxide) is used. In addition, for example, Ti / Al / Ti may be used by laminating one or more of these.

  A first gate insulating film 13 is provided on the substrate 11 so as to cover the gate electrode 12. A second gate insulating film 14 is provided on the first gate insulating film 13. The film thickness of the second gate insulating film 14 is smaller than the film thickness of the first gate insulating film 13. Details of the first gate insulating film 13 and the second gate insulating film 14 will be described later.

A semiconductor layer 15 is provided on the gate insulating film 14. The semiconductor layer 15 is provided for each pixel and is formed in an island shape on the gate insulating film 14. The semiconductor layer 15 is made of an oxide semiconductor, and an element InGaZnO containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) as main components is used. The oxide semiconductor InGaZnO is also called IGZO. Further, as the semiconductor layer 15, zinc oxide (ZnO), indium oxide (In ₂ O ₃ ), tin oxide (SnO), or a ternary to quinary compound including one or more of these is used. May be. As the semiconductor layer 15, for example, an amorphous oxide semiconductor or a crystalline oxide semiconductor is used.

  A protective layer (etching stopper layer) 16 is provided at the center in the X direction of the semiconductor layer 15. The protective layer 16 has a function of protecting the semiconductor layer 15 when a source electrode 17 and a drain electrode 18 described later are processed (etched). The length of the protective layer 16 in the Y direction is set to be equal to or longer than the length of the semiconductor layer 15 in the Y direction. As the protective layer 16, for example, silicon oxide (SiOx) is used.

  A source electrode 17 and a drain electrode 18 are provided on the semiconductor layer 15 so as to be spaced apart from each other on both sides in the X direction. The source electrode 17 is disposed so as to contact the semiconductor layer 15 and partially overlap the protective layer 16. Similarly, the drain electrode 18 is disposed so as to contact the semiconductor layer 15 and partially overlap the protective layer 16. The source electrode 17 is electrically connected to a source line SL extending in the Y direction. As the source electrode 17 and the drain electrode 18, any of the materials exemplified as the material of the gate electrode 12 is used.

  In this way, the TFT 10 is formed on the substrate 11. Although illustration is omitted, an insulating layer is disposed on the TFT 10, and a pixel electrode is disposed on the insulating layer. The drain electrode 18 of the TFT 10 is electrically connected to the pixel electrode through a contact that penetrates the insulating layer.

  FIG. 3 is a cross-sectional view showing another configuration example of the TFT 10. A contact layer 19 is provided between the semiconductor layer 15 and the source electrode 17. The contact layer 19 has a function of improving ohmic contact characteristics between the semiconductor layer 15 and the source electrode 17. Similarly, a contact layer 20 is provided between the semiconductor layer 15 and the drain electrode 18.

  The contact layers 19 and 20 are made of, for example, a transparent conductive material typified by ITO or an oxide semiconductor having a carrier concentration higher than that of the semiconductor layer 15. By providing the contact layers 19 and 20, electrical connection between the semiconductor layer 15 and the source electrode 17 and electrical connection between the semiconductor layer 15 and the drain electrode 18 can be improved.

[2] First Gate Insulating Film 13 and Second Gate Insulating Film 14 The first gate insulating film 13 is mainly composed of silicon oxide (SiOx) and contains hydrogen. The second gate insulating film 14 contains silicon oxide (SiOx) as a main component and contains hydrogen.

  The hydrogen content (atomic%) in the second gate insulating film 14 is lower than the hydrogen content in the first gate insulating film 13. The content rate is a ratio of the number of atoms of a specific element to the total number of atoms of all elements in the target substance. That is, relatively, the first gate insulating film 13 is a hydrogen-rich film, and the second gate insulating film 14 is a hydrogen-poor film. The film thickness of the second gate insulating film 14 is smaller than the film thickness of the first gate insulating film 13.

  An example of the structure of the silicon oxide film will be described with reference to FIGS. FIG. 4 is a schematic diagram of a single crystal silicon film. FIG. 5 is a schematic diagram of an amorphous silicon film. In the amorphous silicon film, hydrogen atoms are bonded to a part of silicon atoms.

  FIG. 6 is a schematic diagram of a hydrogen-rich amorphous silicon oxide film. In FIG. 6, oxygen atoms and hydrogen atoms are bonded to silicon atoms. FIG. 7 is a schematic view of a hydrogen poor amorphous silicon oxide film. The hydrogen content in the silicon oxide film in FIG. 7 is lower than the hydrogen content in the silicon oxide film in FIG. In order to express the difference in content between silicon and oxygen, when the amorphous silicon oxide film in FIG. 6 is represented as SiOm and the amorphous silicon oxide film in FIG. 7 is represented as SiOn, a relationship of “1 <m <n <2” is established. Have “M” and “n” are positive real numbers representing the composition ratio of oxygen to silicon.

  The hydrogen-rich amorphous silicon oxide film in FIG. 6 corresponds to the first gate insulating film 13, and the hydrogen-poor amorphous silicon oxide film in FIG. 7 corresponds to the second gate insulating film 14. That is, as can be understood from FIGS. 6 and 7, the hydrogen content in the second gate insulating film 14 is lower than the hydrogen content in the first gate insulating film 13. The oxygen content in the first gate insulating film 13 is lower than the oxygen content in the second gate insulating film.

[3] Manufacturing Method Next, a manufacturing method of the TFT 10 configured as described above will be described with reference to the drawings. Wirings and electrodes described below can be formed by a vacuum deposition method, a sputtering method, or the like, but are not limited to these, and a known general method can be used. The processing (patterning) of the film (or layer) described below can be performed by forming a protective film on the pattern formation portion using, for example, a photolithography method and removing unnecessary portions by etching. It is not limited to this method, A well-known general patterning method can be used.

  As shown in FIG. 8, the gate electrode 12 is formed on the substrate 11. As the substrate 11, for example, non-alkali glass is used. The gate electrode 12 is formed by forming an electrode material on the substrate 11 and then processing the electrode material into a desired shape. As the gate electrode 12, for example, molybdenum (Mo) or an alloy containing the same is used.

Subsequently, a first gate insulating film 13 is formed on the substrate 11 so as to cover the gate electrode 12. At this time, it is preferable that the first gate insulating film 13 contains as little hydrogen as possible within a range that maintains the quality as an insulating film so as not to be a hydrogen supply source. As a result of intensive experiments, the inventors of the present invention have used PECVD (plasma-enhanced chemical vapor deposition) as a film forming method, monosilane (SiH ₄ ) as a source gas, and nitrous oxide (N ₂ O) as an oxidant gas. The conditions for forming a SiOx-based film in an atmosphere having an oxidation tendency as much as possible were found. The insulating film formed under these conditions was a film that took in hydrogen and / or nitrogen as constituent elements of the material gas in addition to silicon and oxygen as main components. Under this film forming condition, the gate insulating film 13 was formed for 340 seconds. The thickness of the gate insulating film 13 is about 400 nm.

Subsequently, as shown in FIG. 9, a second gate insulating film 14 is formed on the first gate insulating film 13. The second gate insulating film 14 preferably contains as little hydrogen as possible so as not to reduce the oxide semiconductor as the channel layer. As a result of repeated experiments, the inventors used PECVD as a film formation method, monosilane (SiH ₄ ) as a source gas, and nitrous oxide (N ₂ O) as an oxidant gas. The flow rate ratio of monosilane was made lower than the film formation conditions used in No. 13, and the conditions for forming the SiOx-based film in an atmosphere having a higher oxidizing property were found. The insulating film formed under these conditions was a film that took in hydrogen and / or nitrogen as constituent elements of the material gas in addition to silicon and oxygen as main components. Under this film forming condition, the second gate insulating film 14 was formed for 30 seconds.

  The film thickness of the second gate insulating film 14 is 50 nm or less (about 10 to 50 nm), more preferably 40 nm or less (about 20 to 40 nm). In the present specification, the notation “to” includes values before and after. Although the thickness of the second gate insulating film 14 is sufficiently thinner than that of the first gate insulating film 13, it may be difficult to measure the thickness more accurately. Can be estimated in consideration of the calculation error, assuming that the source gas flow rate ratio of the second gate insulating film 14 to the first gate insulating film 13 is about 1/4 and the ratio of the film formation time is 30/340.

  Subsequently, as illustrated in FIG. 10, the semiconductor layer 15 is formed on the second gate insulating film 14 by using, for example, a sputtering method. The semiconductor layer 15 is formed in an island shape on the second gate insulating film 14. The planar shape of the semiconductor layer 15 is, for example, a quadrangle. For example, InGaZnO is used as the semiconductor layer 15.

  Subsequently, the protective layer 16 is formed on the semiconductor layer 15 by using, for example, a CVD method. The protective layer 16 is formed at the center of the semiconductor layer 15, and the length of the protective layer 16 in the Y direction is set to be equal to or longer than the length of the semiconductor layer 15 in the Y direction. As the protective layer 16, for example, silicon oxide (SiOx) is used.

  Subsequently, as illustrated in FIG. 2, the source electrode 17 and the drain electrode 18 are formed on the semiconductor layer 15 and the second gate insulating film 14. The source electrode 17 and the drain electrode 18 are formed so as to partially overlap the protective layer 16. As a method for forming the source electrode 17 and the drain electrode 18, a conductive layer is deposited by using, for example, a sputtering method, and this conductive layer is processed by using a photolithography method and, for example, a wet etching method. In this processing step, the protective layer 16 is used as an etching stopper. As the source electrode 17 and the drain electrode 18, for example, molybdenum (Mo) or an alloy containing the same is used.

  As described above, the TFT 10 is formed on the substrate 11. Thereafter, the target active matrix liquid crystal display device is formed through a process for forming an interlayer insulating film, a process for forming a via hole, and a process for forming a pixel electrode using a known manufacturing method.

  3 is formed, the contact layers 19 and 20 are formed after the protective layer 16 is formed. The contact layers 19 and 20 are formed by using, for example, a sputtering method.

[4] Configuration Example of Liquid Crystal Display Device Next, a configuration example of a liquid crystal display device including the above-described TFT 10 will be described. FIG. 11 is a circuit diagram of the liquid crystal display device 50.

  The liquid crystal display device 50 includes a pixel array in which a plurality of pixels 51 are arranged in a matrix. In FIG. 11, four pixels 51 are extracted and shown.

  The pixel 51 includes a TFT 10, a liquid crystal capacitor (liquid crystal element) Clc, and a storage capacitor Cs. The TFT 10 is an n-channel TFT, for example, and has the configuration of FIG. 2 or FIG.

  The source of the TFT 10 is electrically connected to the signal line SL. The gate of the TFT 10 is electrically connected to the scanning line GL. The drain of the TFT 10 is electrically connected to the liquid crystal capacitor Clc. The liquid crystal capacitance Clc as a liquid crystal element is composed of a pixel electrode, a common electrode, and a liquid crystal layer sandwiched between them.

  The storage capacitor Cs is connected in parallel to the liquid crystal capacitor Clc. The storage capacitor Cs has a function of suppressing the potential fluctuation generated in the pixel electrode and holding the drive voltage applied to the pixel electrode until the drive voltage corresponding to the next signal is applied. The storage capacitor Cs includes a pixel electrode, a storage electrode, and an insulating layer sandwiched between them. A common voltage Vcom is applied to the common electrode and the storage electrode.

  Further, the liquid crystal display device 50 includes a scanning driver 52, a signal driver 53, a common voltage supply circuit 54, and the like.

  The scan driver 52 is connected to a plurality of scan lines GL. The scan driver 52 sends a scan signal for turning on / off the TFT 10 included in the pixel 51 to the pixel array based on a vertical control signal sent from a control circuit (not shown).

  The signal driver 53 is connected to a plurality of signal lines SL. The signal driver 53 receives a horizontal control signal and image data from the control circuit. The signal driver 53 sends a gradation signal (drive voltage) corresponding to the image data to the pixel array based on the horizontal control signal.

  The common voltage supply circuit 54 generates a common voltage Vcom and supplies it to the pixel array. For example, in the liquid crystal display device 50, inversion driving (AC driving) is performed in which the polarity of the electric field between the pixel electrode and the common electrode sandwiching the liquid crystal layer is inverted at a predetermined period. In this case, the polarities of the common voltage Vcom and the drive voltage are inverted every predetermined period.

[5] Characteristics of TFT FIG. 12 is a graph showing transfer characteristics of the TFT 10 according to the present embodiment. 12 represents the gate voltage Vg (V) applied to the gate electrode of the TFT 10, and the vertical axis (logarithmic scale) of FIG. 12 represents the drain current Id (A) of the TFT 10. “E” in FIG. 12 represents a power of 10. The graph shown by the solid line in FIG. 12 is the transfer characteristic of the TFT 10 according to this embodiment.

  For example, the gate voltage Vg when the drain current Id flows 1 nA is the threshold voltage Vth of the TFT 10. That is, when a gate voltage Vg that causes the drain current Id to be less than 1 nA is applied to the gate of the TFT 10, the TFT 10 is turned off. From FIG. 12, it can be understood that the TFT 10 according to the present embodiment has a normally-off transfer characteristic.

  FIG. 13 is a diagram for explaining the characteristic variation in the plurality of TFTs 10 according to the present embodiment. The horizontal axis in FIG. 13 represents the threshold voltage Vth (V) of the TFT 10, and the vertical axis (logarithmic scale) in FIG. 13 represents the drain current Id (A) of the TFT 10.

  In FIG. 13, a liquid crystal display device having a plurality of pixels was manufactured, and transfer characteristics were measured for five TFTs included in a range of approximately “30 cm × 30 cm” in the vertical and horizontal directions in the pixel array. White circles shown in FIG. 13 are measurement results of the TFT 10 according to this embodiment.

  The average of the threshold voltages Vth in the measured five TFTs 10 is approximately 0.6V. That is, the five measured TFTs 10 have normally-off characteristics.

  The difference between the maximum threshold voltage Vth and the minimum threshold voltage Vth was ΔVth, and this ΔVth was used as an index of variation in transfer characteristics. In the TFT 10 of this embodiment, ΔVth is approximately 0.2V. Therefore, it can be understood that the TFT 10 of the present embodiment has small variations in transfer characteristics.

[6] Comparative Example FIG. 14 is a cross-sectional view of a TFT according to a comparative example. The TFT according to the comparative example includes a single-layer thick gate insulating film 21. That is, in the comparative example, the gate insulating film is not composed of two layers of different materials. The gate insulating film 21 is made of SiOx.

  Also in the comparative example, a liquid crystal display device having a plurality of pixels was manufactured, and transfer characteristics were measured for five TFTs included in a range of approximately “30 cm × 30 cm” in the vertical and horizontal directions in the pixel array.

  FIG. 12 also shows the transfer characteristics (shown by broken lines) of the TFT according to the comparative example. The transfer characteristics of the TFT according to the comparative example are translated in parallel to the left side (the gate voltage is negative) as compared with the transfer characteristics of the TFT 10 according to this embodiment. The TFT according to the comparative example has normally-on transfer characteristics.

  FIG. 13 also shows the measurement results (indicated by black circles) of the TFT according to the comparative example. The average of the threshold voltages Vth of the five TFTs measured is approximately −1.8V. That is, the TFT according to the comparative example has normally-on characteristics. Further, in the TFT according to the comparative example, ΔVth is approximately 3.2V. Therefore, it can be understood that the TFT according to the comparative example has a large variation in transfer characteristics.

  As described above, in the present embodiment, the threshold voltage Vth is set in the positive direction by including the thick first gate insulating film 13 having excellent insulating characteristics and the thin second gate insulating film 14 that suppresses the reduction of the semiconductor layer 15. In addition, the normally-on characteristic can be improved to the normally-off characteristic. Furthermore, in this embodiment, there is an effect of reducing ΔVth, and the in-plane variation of the transfer characteristics can be improved to 1/15 or less as compared with the comparative example.

[7] Effects of First Embodiment As described in detail above, in the first embodiment, in the bottom gate type (reverse stagger type) TFT 10, the gate insulating film has two layers (thick first gate insulating film 13 and thin layer). The second gate insulating film 14) is configured. The first gate insulating film 13 contains silicon oxide (SiOx) as a main component and contains hydrogen. The second gate insulating film 14 in contact with the semiconductor layer 15 is mainly composed of silicon oxide (SiOx) and contains hydrogen. The hydrogen content (atomic%) in the second gate insulating film 14 is set to be lower than the hydrogen content in the first gate insulating film 13. That is, when the second gate insulating film 14 is expressed as SiOn (n is a positive real number) and the first gate insulating film 13 is expressed as SiOm (m is a positive real number), there is a relationship of “1 <m <n <2”. .

  Therefore, according to the first embodiment, the reduction of the semiconductor layer 15 can be suppressed. Thereby, the TFT 10 having a desired transfer characteristic, for example, a normally-off characteristic can be realized.

  The first gate insulating film 13 is made of a hydrogen poor insulating film. Thereby, it can suppress that the insulation characteristic as the whole gate insulating film deteriorates. As a result, the TFT 10 having desired insulating characteristics can be realized.

  In addition, by using the gate insulating films (the first gate insulating film 13 and the second gate insulating film 14) of the present embodiment, desired transfer characteristics can be obtained and variations in the transfer characteristics can be reduced. A possible TFT 10 can be realized.

  In addition, the thin gate insulating film (second gate insulating film 14) does not improve the oxygen content by modifying the thick gate insulating film (first gate insulating film) by oxidation treatment or the like. For example, the deposition method is different from that for the thick gate insulating film. Thereby, it can suppress that manufacturing cost increases.

[Second Embodiment]
In the second embodiment, the reduction action of the semiconductor layer 15 is further reduced by using a film having a low hydrogen content as a part of the protective layer 16 in contact with the semiconductor layer 15.

  FIG. 15 is a cross-sectional view of the TFT 10 according to the second embodiment. A protective layer 16 is provided on the semiconductor layer 15. The protective layer 16 includes a first protective film 16A in contact with the semiconductor layer 15 and a second protective film 16B provided on the first protective film 16A. The film thickness of the first protective film 16A is thinner than the film thickness of the second protective film 16B.

  The first protective film 16A is made of the same material as the second gate insulating film 14 described above. The second protective film 16B is made of the same material as the first gate insulating film 13 described above. That is, the first protective film 16A is a hydrogen-poor insulating film, and the second protective film 16B is a hydrogen-rich insulating film. When the first protective film 16A is expressed as SiOn ′ (n ′ is a positive real number) and the second protective film 16B is expressed as SiOm ′ (m ′ is a positive real number), the relationship “1 <m ′ <n ′ <2”. Have If this relationship is satisfied, m ′ = m and n ′ = n are not necessarily satisfied. The first protective film 16A can be formed in the same manufacturing process as the second gate insulating film 14, and the second protective film 16B can be formed in the same manufacturing process as the first gate insulating film 13. is there.

  In the TFT 10 configured as described above, reduction from the upper surface of the semiconductor layer 15 can be reduced. Thereby, the reducing action of the semiconductor layer 15 can be controlled using the second gate insulating film 14 and the first protective film 16A. Thereby, the TFT 10 having desired transfer characteristics can be realized.

  In addition, since the second protective film 16B having desired insulating characteristics is provided, the semiconductor layer 15 can be sufficiently protected during etching.

[Third Embodiment]
In the third embodiment, the reducing action of the semiconductor layer 15 is further reduced by using a film having a low hydrogen content as the insulating film in contact with the upper surface of the semiconductor layer 15.

  FIG. 16 is a cross-sectional view of the TFT 10 according to the third embodiment. The protective layer 16 described in the first embodiment is not provided on the semiconductor layer 15. A source electrode 17 and a drain electrode 18 are provided on the semiconductor layer 15 so as to be spaced apart from each other. That is, the source electrode 17 and the drain electrode 18 are disposed with a region 30 therebetween.

  A first insulating film 31 is provided on the semiconductor layer 15 corresponding to the source electrode 17, the drain electrode 18, and the region 30. That is, a part of the semiconductor layer 15 is in contact with the first insulating film 31. The first insulating film 31 is made of the same material as the second gate insulating film 14. The first insulating film 31 can be formed in the same manufacturing process as the second gate insulating film 14.

  A second insulating film 32 is provided on the first insulating film 31. The second insulating film 32 is made of the same material as the first gate insulating film 13. The second insulating film 32 can be formed in the same manufacturing process as the first gate insulating film 13. That is, the first insulating film 31 is a hydrogen poor insulating film, and the second insulating film 32 is a hydrogen rich insulating film. If the first insulating film 31 is represented by SiOn ′ (n ′ is a positive real number) and the second insulating film 32 is represented by SiOm ′ (m ′ is a positive real number), “1 <m ′ <n ′ <2”. Have the relationship. If this relationship is satisfied, m ′ = m and n ′ = n are not necessarily satisfied. The film thickness of the first insulating film 31 is smaller than the film thickness of the second insulating film 32. For example, the first insulating film 31 and the second insulating film 32 are used as an interlayer insulating layer that covers the TFT 10.

  In the TFT 10 configured as described above, reduction from the upper surface of the semiconductor layer 15 can be reduced. Thereby, the effect similar to 2nd Embodiment can be acquired.

  FIG. 17 is a cross-sectional view of a TFT 10 according to a modification. The TFT 10 shown in FIG. 17 includes contact layers 19 and 20 as in FIG. Thus, even when the third embodiment is applied to the TFT 10 of FIG. 3, the same effect as described above can be obtained. Of course, the configuration example of FIG. 3 is applicable to the second embodiment.

  Moreover, in this specification, a board and a film are the expressions which illustrated the member, and are not limited to the structure. The plate or film may be a layer or other member having the functions described in the specification.

  In the above embodiment, a bottom gate type (reverse stagger type) TFT has been described as an example. However, the present invention can also be applied to a top gate type (forward stagger type) TFT.

  In addition, the semiconductor device (TFT 10) according to the above embodiment can be applied to various electronic devices. For example, the present invention can be applied to mobile devices (such as mobile phones, portable information terminals, smartphones, and tablet terminals), game devices, notebook PCs (personal computers), televisions, digital video cameras, digital still cameras, and scanners.

  The present invention is not limited to the above embodiment, and can be embodied by modifying the constituent elements without departing from the scope of the invention. Further, the above embodiments include inventions at various stages, and are obtained by appropriately combining a plurality of constituent elements disclosed in one embodiment or by appropriately combining constituent elements disclosed in different embodiments. Various inventions can be configured. For example, even if some constituent elements are deleted from all the constituent elements disclosed in the embodiments, the problems to be solved by the invention can be solved and the effects of the invention can be obtained. Embodiments made can be extracted as inventions.

  DESCRIPTION OF SYMBOLS 10 ... TFT, 11 ... Substrate, 12 ... Gate electrode, 13, 14 ... Gate insulating film, 15 ... Semiconductor layer, 16 ... Protective layer, 16A, 16B ... Protective film, 17 ... Source electrode, 18 ... Drain electrode, 19, DESCRIPTION OF SYMBOLS 20 ... Contact layer, 21 ... Gate insulating film, 31, 32 ... Insulating film, 50 ... Liquid crystal display device, 51 ... Pixel, 52 ... Scan driver, 53 ... Signal driver, 54 ... Common voltage supply circuit

Claims (7)

A gate electrode provided on the substrate;
A first gate insulating film provided on the gate electrode;
A second gate insulating film provided on the first gate insulating film and thinner than the first gate insulating film;
A semiconductor layer provided on the second gate insulating film and including an oxide semiconductor;
A source electrode and a drain electrode provided on the semiconductor layer,
2. The thin film transistor according to claim 1, wherein the hydrogen content in the second gate insulating film is lower than the hydrogen content in the first gate insulating film.   2. The thin film transistor according to claim 1, wherein each of the first gate insulating film and the second gate insulating film contains silicon and oxygen.   3. The thin film transistor according to claim 1, wherein the second gate insulating film has a thickness of 50 nm or less. When the first gate insulating film is SiOm and the second gate insulating film is SiOn,
1 <m <n <2
The thin film transistor according to claim 2, wherein the relationship is satisfied. A first protective film provided on the semiconductor layer;
A second protective film provided on the first protective film and thinner than the first protective film;
5. The thin film transistor according to claim 1, wherein a hydrogen content in the first protective film is lower than a hydrogen content in the second protective film.   6. The thin film transistor according to claim 5, wherein each of the first protective film and the second protective film contains silicon and oxygen.   The thin film transistor according to claim 1, wherein the oxide semiconductor contains indium, gallium, and zinc.