JP2017076948A - Analog-digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog-digital converter capable of obtaining a digital value from a signal that is the result of multiplication of an input signal by a sine wave, having a simple configuration and a wide level of input signal, and in which fluctuation of the characteristics due to temperature is small.SOLUTION: A signal component corresponding to the product of the third harmonic of a first square wave W1 contained in an output signal Qu1, and an input analog signal Vi, and a signal component corresponding to the product of the fifth harmonic of the first square wave W1 and the input analog signal Vi, are cancelled by a signal component corresponding to the product of the fundamental of a second square wave W2 contained in an output signal Qu2 and the input analog signal Vi, and a signal component corresponding to the product of the fundamental of the second square wave W3 contained in an output signal Qu3, and the input analog signal Vi.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an analog-to-digital converter that converts an analog signal into a digital value.

  In the fields of wireless communication and sensing, it may be necessary to convert the amplitude of a sine wave signal component included in an input signal into a digital value by an analog-digital converter. In this case, simply, a method is used in which a sine wave is rectified using a chopping circuit or the like, a DC signal is extracted from the rectified pulsating signal by a low-pass filter, and the DC signal is converted into a digital value. However, rectifying a sine wave to generate a pulsating flow signal is equivalent to multiplying the sine wave by a square wave that alternately repeats amplitude “1” and amplitude “−1” every half cycle. A square wave includes harmonics having a frequency that is an odd multiple of the frequency of the fundamental wave. If a noise component with the same frequency as the harmonic wave is included in the input signal, the DC signal extracted by the low-pass filter includes a component due to the multiplication of the harmonic wave included in the square wave and the noise component. Become. Therefore, when the noise component of the input signal is large, it is difficult to obtain the correct amplitude of the sine wave.

  The above harmonic problem can be avoided by multiplying the input signal by a sine wave instead of a square wave. When multiplying an input signal by a sine wave, an analog multiplier such as a Gilbert cell is generally used (see Patent Document 1 below).

JP 2000-315919 A

  A Gilbert cell type analog multiplier has been put into practical use, for example, with the configuration shown in FIG. When the Gilbert cell is composed of bipolar transistors, the thermal voltage VT is included as a coefficient in the multiplication result, as shown in the equations (14) and (20) of Patent Document 1. The thermal voltage VT is expressed by “k · T / q”, where k is a Boltzmann constant, T is an absolute temperature, and q is an elementary charge of an electron. Therefore, the multiplication result of the Gilbert cell, that is, the output voltage changes depending on the temperature. The same applies to other analog multipliers composed of MOS transistors. Further, in the analog multiplier, it is necessary to limit the range of the input voltage in order to ensure the multiplication accuracy due to the nonlinearity of the input / output characteristics of the transistor. For this reason, for example, when an analog multiplier is used in a capacitance type input device, securing a dynamic range of a signal and fluctuation due to temperature are problems.

  In addition, when multiplying a sine wave using an analog multiplier, it is necessary to generate a sine wave separately. Therefore, for example, in order to perform high-precision signal extraction by multiplying the input signal by a sine wave, it is necessary to generate a high-precision sine wave, which increases the circuit scale for generating a sine wave and reduces power consumption. There is a problem that increases.

  The present invention has been made in view of such circumstances, and an object of the present invention is to obtain a digital value from a signal obtained by multiplying an input signal by a sine wave, and to have a simple configuration and a level of the input signal. An object of the present invention is to provide an analog-to-digital converter having a wide range and less fluctuation in characteristics due to temperature.

  An analog-to-digital converter according to the present invention is an analog-to-digital converter that multiplies an input analog signal and a sine wave having a predetermined frequency, and converts the resulting signal into an output digital value, each having a different frequency. A plurality of square wave multipliers for multiplying the input analog signal by a square wave, a signal synthesis unit for synthesizing signals of multiplication results in the plurality of square wave multipliers, and a signal indicating a synthesis result of the signal synthesis unit And a digital value acquisition unit that acquires the output digital value based on the digital value. The square wave can be approximated as the sum of a fundamental wave that is a sine wave having the lowest frequency and a plurality of harmonics that are sine waves each having an integer multiple of the fundamental wave. The plurality of square wave multiplication units include one first square wave multiplication unit and one or more second square wave multiplication units. The first square wave multiplication unit multiplies the input analog signal by a first square wave having the sine wave having the predetermined frequency as the fundamental wave. The second square wave multiplication unit is a second square wave having the fundamental wave as a sine wave equal to one harmonic included in the first square wave or a sine wave obtained by inverting the phase of the one harmonic. Is multiplied by the input analog signal. The signal synthesizing unit includes a signal component corresponding to a product of at least one of the harmonics of the first square wave and the input analog signal included in the signal of the multiplication result of the first square wave multiplication unit. It cancels out by a signal component corresponding to the product of the fundamental wave of the second square wave and the input analog signal contained in the signal of the multiplication result of the two square wave multiplier.

According to the above configuration, the signal component corresponding to the product of at least one harmonic of the first square wave and the input analog signal included in the signal of the multiplication result of the first square wave multiplier is the It is canceled by a signal component corresponding to the product of the fundamental wave of the second square wave and the input analog signal contained in the signal of the multiplication result of the second square wave multiplier. Therefore, in the signal resulting from the synthesis of the signal synthesis unit, the signal component corresponding to the product of the harmonic of the first square wave and the input analog signal is reduced, and the fundamental wave of the first square wave (the predetermined wave) The signal component corresponding to the product of the input analog signal becomes the dominant component.
In the analog-to-digital converter, the square wave multiplier is used to multiply the sine wave (the fundamental wave of the first square wave) and the input analog signal. It is difficult to be affected by the characteristics, and there is little fluctuation in characteristics due to temperature. In addition, the use of the square wave multiplication unit makes it difficult to be affected by the input / output nonlinear characteristics of the transistor as in the case of an analog multiplier. Therefore, the level range of the input analog signal that can be multiplied with a sine wave is wide. Become.
Further, in the analog-digital converter, since the sine wave generator can be omitted by using the square wave multiplier, the circuit configuration is simplified.

Preferably, the square wave multiplication unit may include at least one capacitor. The square wave multiplying unit is a charge that accumulates charges corresponding to the input analog signal in the capacitor in each of one half cycle and the other half cycle in one cycle of the square wave multiplied by the input analog signal. The operation and the charge output operation for outputting the charge accumulated in the capacitor by the charging operation to the signal synthesis unit may be alternately repeated at a predetermined interval. In addition, the square wave multiplication unit includes two polarities of the input analog signal during the charging operation, two polarities of charges output from one capacitor to the signal combining unit during the charge output operation, or two during the charge output operation. You may invert the relationship with the polarity of the difference of the electric charge output to the said signal synthetic | combination part from the said capacitor with the said one half cycle and the said other half cycle. The signal synthesis unit may synthesize the charges output from the plurality of square wave multiplication units by the charge output operation. The digital value acquisition unit may acquire the output digital value based on the charges from the plurality of square wave multiplication units synthesized in the signal synthesis unit.
According to the above configuration, the input analog signal and the square wave are multiplied by repeating the charging operation for the capacitor and the charge output operation to the signal synthesis unit. It becomes difficult to be affected by the temperature characteristics and input / output nonlinear characteristics of the transistor.

Preferably, the capacitance of the capacitor in which the first square wave multiplication unit accumulates electric charge in the charging operation and the capacitance of the capacitor in which one second square wave multiplication unit accumulates electric charge in the charging operation. The ratio of the capacitance to the amplitude of the fundamental wave of the first square wave and the harmonics of the first square wave having the same frequency as the fundamental wave of the second square wave in the one second square wave multiplication unit. You may have a value according to ratio with amplitude.
According to the above configuration, based on a capacitance ratio between the capacitor of the first square wave multiplier and the capacitor of the second square wave multiplier, the harmonics of the first square wave and the input analog signal are The signal component corresponding to the product of the second square wave and the signal component corresponding to the product of the fundamental wave of the second square wave and the input analog signal can be canceled out. Since the capacitance ratio of the capacitor is hardly affected by variations due to temperature and manufacturing process, the signal components can be accurately canceled.

  In the first aspect of the present invention, the signal synthesizing unit includes at least one capacitor for accumulating charges repeatedly output by the charge output operation from the plurality of square wave multiplication units. A signal corresponding to the charge to be output may be output. The digital value acquisition unit compares a signal indicating a synthesis result of the signal synthesis unit with a reference value, and outputs a signal indicating the comparison result, and according to an output signal of the first comparator Based on an output signal of the first comparator and a charge generation unit that generates the generated charge and outputs the charge to the signal synthesis unit at a timing synchronized with the charge output operation of the plurality of square wave multiplication units. And a first digital value generation unit that generates an output digital value.

In the first aspect of the present invention, in the analog-digital converter, the first input terminal and the second input terminal to which a differential signal is input as the input analog signal, and the plurality of square wave multiplication units are common. And a first common node and a second common node connected to each other.
The square wave multiplication unit may include a first capacitor and a second capacitor having the same capacitance. In the charging operation, the square wave multiplier applies a voltage generated between one of the first input terminal and the second input terminal and a common potential to the first capacitor, and the first input terminal And a voltage generated between the other of the second input terminals and the common potential is applied to the second capacitor, and the charge accumulated in one of the first capacitor and the second capacitor in the charge output operation. May be output to the first common node, and the charge accumulated in the other of the first capacitor and the second capacitor may be output to the second common node. The square wave multiplication unit may be a charge obtained by subtracting a charge output to the second common node from a charge output to the first common node during the charge output operation and a polarity of the input analog signal during the charge operation. The relationship with the polarity of the difference may be reversed between the one half cycle and the other half cycle.
The signal combining unit may include a third capacitor and a fourth capacitor having the same capacitance. The signal synthesizer accumulates charges output from the plurality of square wave multipliers to the first common node by the charge output operation in the third capacitor, and the charge output operations from the plurality of square wave multipliers. Thus, the charge output to the second common node may be stored in the fourth capacitor, and a signal corresponding to the difference between the charge of the third capacitor and the charge of the fourth capacitor may be output.
The charge generation unit outputs charges to the first common node and the second common node at a timing synchronized with the charge output operation of the plurality of square wave multiplication units, and outputs to the first common node. The charge difference obtained by subtracting the charge output from the charge to be output to the second common node may be set to a value corresponding to the output signal of the first comparator.
According to the above configuration, in the plurality of square wave multipliers, the input analog signal and the square wave are multiplied based on the difference in charge according to the input analog signal, and the multiplication result signal is obtained. The obtained charge difference is synthesized in the signal synthesis unit, whereby an output digital value corresponding to the product of the input analog signal and the sine wave is obtained. Therefore, common-mode noise is easily removed, and noise resistance is improved.

In the first aspect of the present invention, in the analog-digital converter, the first input terminal and the second input terminal to which a differential signal is input as the input analog signal, and the plurality of square wave multiplication units are common. And a first common node and a second common node connected to each other.
The square wave multiplier includes a first capacitor having one end connected to the first common node, a second capacitor having one end connected to the second common node and having the same capacitance as the first capacitor; In the charging operation in one half cycle of the square wave multiplied by the input analog signal, the other end of the first capacitor is connected to the first input terminal and the other end of the second capacitor. Is connected to the second input terminal, and in the charging operation of the other half cycle of the square wave, the other end of the first capacitor is connected to the second input terminal and the second input terminal is connected to the second input terminal. The other end of two capacitors is connected to the first input terminal, and in the charge output operation, the other end of the first capacitor and the other end of the second capacitor are connected to the first input. Provided in a path between the other end of the first capacitor and the other end of the second capacitor, and is turned off in the charging operation. A second switch circuit which is turned on in an output operation; and the first common node and the second common node are connected to the common potential in the charging operation; and the first common node and the second common node in the charge output operation And a third switch circuit for disconnecting from the common potential.
The signal synthesis unit amplifies the voltage difference between the inverting input terminal and the non-inverting input terminal, and outputs the amplification result as a voltage difference between the inverting output terminal and the non-inverting output terminal, and the operational amplifier A third capacitor provided in a path between an inverting input terminal and the non-inverting output terminal; and a third capacitor provided in a path between the non-inverting input terminal and the inverting output terminal of the operational amplifier. When the fourth capacitor having the same capacitance and the plurality of square wave multipliers perform the charging operation, the first common node is disconnected from the inverting input terminal of the operational amplifier and the second common node is When the plurality of square wave calculation units perform the charge output operation by separating from the non-inverting input terminal of the operational amplifier, the first common node is used as the inverting input terminal of the operational amplifier. It may have a fourth switching circuit for connecting the second common node to the non-inverting input terminal of the operational amplifier as well as continue.
The charge generation unit outputs charges to the first common node and the second common node at a timing synchronized with the charge output operation of the plurality of square wave multiplication units, and outputs the charge to the first common node. A charge difference obtained by subtracting the charge output from the charge to the second common node may be set to a value corresponding to the output signal of the first comparator.
Also in the above configuration, since the differential signal is multiplied by the square wave, the in-phase noise is easily removed.

  Preferably, the first comparator may output a signal indicating a comparison between the voltage at the inverting output terminal of the operational amplifier and the voltage at the non-inverting output terminal. The charge generation unit includes a fifth capacitor having one end connected to the first common node, a sixth capacitor having one end connected to the second common node, the other end of the fifth capacitor, and the sixth capacitor. And is turned off when the plurality of square wave multipliers perform the charging operation and turned on when the plurality of square wave multipliers perform the charge output operation. A voltage is supplied to the other end of the fifth capacitor and the other end of the sixth capacitor at the timing synchronized with the charging operation of the switch circuit and the plurality of square wave multipliers, and the output of the first comparator Depending on the signal, the other end of the fifth capacitor is set to a voltage higher than the other end of the sixth capacitor by a predetermined voltage, or the other end of the sixth capacitor is set to the fifth capacitor. It may include a voltage supply circuit for setting the voltage higher the predetermined voltage than the other end.

  In the second aspect of the present invention, the signal synthesis unit is configured to discharge at least one capacitor that accumulates charges repeatedly output by the charge output operation from the plurality of square wave multiplication units, and discharges the charges of the capacitors. And a signal corresponding to the charge accumulated in the capacitor. The digital value acquisition unit is a signal indicating a timing at which the charge accumulated in the capacitor of the signal generation unit becomes equal to a predetermined initial value based on a comparison between a signal indicating a synthesis result of the signal synthesis unit and a reference value. , A second discharge circuit that discharges the electric charge accumulated in the capacitor of the signal synthesizer with a constant current, a counter that counts the input clock signal, and a count value of the counter A second digital value generation unit that acquires and generates the output digital value based on the acquired count value. The first discharge circuit may discharge the charge accumulated in the capacitor of the signal synthesis unit to the initial value. The plurality of square wave multiplication units may repeat the charging operation and the charge output operation for a certain period after the discharging by the first discharging circuit. In the second discharge circuit, after the predetermined period, the charge accumulated in the capacitor of the signal synthesis unit in the state where the plurality of square wave multiplication units stop the charging operation and the charge output operation. You may discharge with an electric current. The second digital value generation unit receives a signal indicating a timing at which the charge accumulated in the capacitor of the signal synthesis unit becomes equal to the initial value from the time when the discharge by the second discharge circuit is started. The count value of the counter may be obtained until the time when it is output in the instrument.

In the second aspect of the present invention, the analog-to-digital converter has the first input terminal and the second input terminal to which a differential signal is input as the input analog signal, and the plurality of square wave multiplication units in common. And a first common node and a second common node connected to each other.
The square wave multiplication unit may include a first capacitor and a second capacitor having the same capacitance. In the charging operation, the square wave multiplier applies a voltage generated between one of the first input terminal and the second input terminal and a common potential to the first capacitor, and the first input terminal And a voltage generated between the other of the second input terminals and the common potential is applied to the second capacitor, and the charge accumulated in one of the first capacitor and the second capacitor in the charge output operation. May be output to the first common node, and the charge accumulated in the other of the first capacitor and the second capacitor may be output to the second common node. The square wave multiplication unit may be a charge obtained by subtracting a charge output to the second common node from a charge output to the first common node during the charge output operation and a polarity of the input analog signal during the charge operation. The relationship with the polarity of the difference may be reversed between the one half cycle and the other half cycle.
The signal synthesis unit includes a third capacitor and a fourth capacitor having the same capacitance, and charges output from the plurality of square wave multiplication units to the first common node by the charge output operation are described above. The charge stored in the third capacitor and output from the plurality of square wave multipliers to the second common node by the charge output operation may be stored in the fourth capacitor.
The first discharge circuit may discharge the charge of the third capacitor and the charge of the fourth capacitor, respectively.
The second discharge circuit may discharge the charge of the third capacitor and the charge of the fourth capacitor with the constant current, respectively.
Also in the above configuration, since the differential signal is multiplied by the square wave, the in-phase noise is easily removed.

In the second aspect of the present invention, the analog-to-digital converter has the first input terminal and the second input terminal to which a differential signal is input as the input analog signal, and the plurality of square wave multiplication units in common. And a first common node and a second common node connected to each other.
The square wave multiplier includes a first capacitor having one end connected to the first common node, a second capacitor having one end connected to the second common node and having the same capacitance as the first capacitor; In the charging operation in one half cycle of the square wave multiplied by the input analog signal, the other end of the first capacitor is connected to the first input terminal and the other end of the second capacitor. Is connected to the second input terminal, and in the charging operation of the other half cycle of the square wave, the other end of the first capacitor is connected to the second input terminal and the second input terminal is connected to the second input terminal. The other end of two capacitors is connected to the first input terminal, and in the charge output operation, the other end of the first capacitor and the other end of the second capacitor are connected to the first input. Provided in a path between the other end of the first capacitor and the other end of the second capacitor, and is turned off in the charging operation. A second switch circuit which is turned on in an output operation; and the first common node and the second common node are connected to the common potential in the charging operation; and the first common node and the second common node in the charge output operation And a third switch circuit for disconnecting from the common potential.
The signal synthesis unit amplifies the voltage difference between the inverting input terminal and the non-inverting input terminal, and outputs the amplification result as a voltage difference between the inverting output terminal and the non-inverting output terminal, and the operational amplifier A third capacitor provided in a path between an inverting input terminal and the non-inverting output terminal; and a third capacitor provided in a path between the non-inverting input terminal and the inverting output terminal of the operational amplifier. When the fourth capacitor having the same capacitance and the plurality of square wave multipliers perform the charging operation, the first common node is disconnected from the inverting input terminal of the operational amplifier and the second common node is When the plurality of square wave calculation units perform the charge output operation by separating from the non-inverting input terminal of the operational amplifier, the first common node is used as the inverting input terminal of the operational amplifier. It may have a fourth switching circuit for connecting the second common node to the non-inverting input terminal of the operational amplifier as well as continue. The first discharge circuit may discharge the charge of the third capacitor and the charge of the fourth capacitor, respectively. The second discharge circuit may discharge the charge of the third capacitor and the charge of the fourth capacitor with the constant current, respectively.
Also in the above configuration, since the differential signal is multiplied by the square wave, the in-phase noise is easily removed.

  Preferably, the second discharge circuit includes a first resistor having one end connected to the first common node and a second resistor having one end connected to the second common node and having the same resistance value as the first resistor. And a sixth switch circuit for connecting the other end of the first resistor and the other end of the second resistor to a reference potential during a discharging operation.

  Preferably, in the first aspect and the second aspect of the present invention, at least a part of the plurality of square wave arithmetic units may share the third switch circuit.

  In the third aspect of the present invention, the signal synthesizer generates a signal corresponding to the sum of the charges output from the plurality of square wave multipliers by the charge output operation every time the charge output operation is performed. Good. The digital value acquisition unit inputs the signal generated in the signal synthesis unit in the first stage, inputs a signal output from the previous stage in the stage after the first stage, and outputs a partial digital signal corresponding to the level of the input signal A plurality of cascade-connected pipeline stages that each output a value, and a third digital value generation unit that generates the output digital value based on the partial digital values output from the plurality of pipeline stages, respectively. It's okay. The pipeline stage samples a signal input from the signal synthesizer or the preceding pipeline stage in synchronization with the charge output operation in the plurality of square wave multipliers, and the sampled signal is amplified by a predetermined amplification factor. The reference signal selected based on the partial digital value may be subtracted from the amplified signal, and the signal resulting from the subtraction may be output to the subsequent stage.

In the third aspect of the present invention, the analog-to-digital converter has a common first input terminal and second input terminal to which a differential signal is input as the input analog signal, and the plurality of square wave multipliers. And a first common node and a second common node connected to each other.
The square wave multiplication unit may include a first capacitor and a second capacitor having the same capacitance. In the charging operation, the square wave multiplier applies a voltage generated between one of the first input terminal and the second input terminal and a common potential to the first capacitor, and the first input terminal And a voltage generated between the other of the second input terminals and the common potential is applied to the second capacitor, and the charge accumulated in one of the first capacitor and the second capacitor in the charge output operation. May be output to the first common node, and the charge accumulated in the other of the first capacitor and the second capacitor may be output to the second common node. The square wave multiplication unit may be a charge obtained by subtracting a charge output to the second common node from a charge output to the first common node during the charge output operation and a polarity of the input analog signal during the charge operation. The relationship with the polarity of the difference may be reversed between the one half cycle and the other half cycle.
The signal synthesis unit includes a third capacitor and a fourth capacitor having the same capacitance, and charges output from the plurality of square wave multiplication units to the first common node by the charge output operation are described above. The charge stored in the third capacitor and output to the second common node by the charge output operation from the plurality of square wave multipliers is stored in the fourth capacitor, and the charge of the third capacitor and the fourth capacitor A signal corresponding to the difference from the electric charge may be output. The signal synthesis unit may discharge the charges of the third capacitor and the fourth capacitor after the output of the signal and before the next charge output operation is performed in the plurality of square wave multiplication units.
Also in the above configuration, since the differential signal is multiplied by the square wave, the in-phase noise is easily removed.

In the third aspect of the present invention, the analog-to-digital converter has a common first input terminal and second input terminal to which a differential signal is input as the input analog signal, and the plurality of square wave multipliers. And a first common node and a second common node connected to each other.
The square wave multiplier includes a first capacitor having one end connected to the first common node, a second capacitor having one end connected to the second common node and having the same capacitance as the first capacitor; In the charging operation in one half cycle of the square wave multiplied by the input analog signal, the other end of the first capacitor is connected to the first input terminal and the other end of the second capacitor. Is connected to the second input terminal, and in the charging operation of the other half cycle of the square wave, the other end of the first capacitor is connected to the second input terminal and the second input terminal is connected to the second input terminal. The other end of two capacitors is connected to the first input terminal, and in the charge output operation, the other end of the first capacitor and the other end of the second capacitor are connected to the first input. Provided in a path between the other end of the first capacitor and the other end of the second capacitor, and is turned off in the charging operation. A second switch circuit that is turned on in the output operation.
The signal synthesis unit amplifies a voltage difference between an inverting input terminal connected to the first common node and a non-inverting input terminal connected to the second common node, and the amplification result is non-inverted with an inverting output terminal. An operational amplifier that outputs a voltage difference from the output terminal, a third capacitor provided in a path between the inverting input terminal and the non-inverting output terminal of the operational amplifier, and the non-inverting input terminal of the operational amplifier And a fourth capacitor having the same capacitance as the third capacitor, and when the plurality of square wave multipliers perform the charging operation, the third capacitor and Each of the fourth capacitors may be short-circuited, and when the plurality of square wave multipliers perform the charge output operation, a first discharge circuit that cancels the short-circuit may be included.
Also in the above configuration, since the differential signal is multiplied by the square wave, the in-phase noise is easily removed.

In the third aspect, the analog-to-digital converter has a first input terminal and a second input terminal to which a differential signal is input as the input analog signal, and the plurality of square wave multipliers are connected in common. A first common node, a second common node, a third common node, and a fourth common node.
The square wave multiplication unit may include a first capacitor and a second capacitor having the same capacitance. In the charging operation, the square wave multiplier applies a voltage generated between one of the first input terminal and the second input terminal and the first common node to the first capacitor, and A voltage generated between the other of the first input terminal and the second input terminal and the second common node is applied to the second capacitor, and in the charge output operation, the first capacitor is connected to the first common node. The second capacitor may be connected between the second common node and the fourth common node while being connected to the third common node. The square wave multiplication unit may be a charge obtained by subtracting the charge accumulated in the second capacitor from the polarity of the input analog signal during the charge operation and the charge accumulated in the first capacitor during the charge output operation. The relationship with the polarity of the difference may be reversed between the one half cycle and the other half cycle.
The signal synthesis unit may adjust the voltage of the third common node and the voltage of the fourth common node so that the voltage of the first common node is equal to the voltage of the second common node.
Also in the above configuration, since the differential signal is multiplied by the square wave, the in-phase noise is easily removed.

In the third aspect of the present invention, the analog-to-digital converter includes a first input terminal and a second input terminal to which a differential signal is input as the input analog signal, and the plurality of square wave multiplication units in common. A first common node, a second common node, a third common node, and a fourth common node that are connected may be provided.
The square wave multiplier includes a first capacitor having one end connected to the first common node, a second capacitor having one end connected to the second common node and having the same capacitance as the first capacitor; In the charging operation in one half cycle of the square wave multiplied by the input analog signal, the other end of the first capacitor is connected to the first input terminal and the other end of the second capacitor. Is connected to the second input terminal, and in the charging operation of the other half cycle of the square wave, the other end of the first capacitor is connected to the second input terminal and the second input terminal is connected to the second input terminal. The other end of two capacitors is connected to the first input terminal, and in the charge output operation, the other end of the first capacitor and the other end of the second capacitor are connected to the first input. Provided in a path between the other end of the first capacitor and the third common node, and is turned off in the charging operation, and in the charge output operation. A seventh switch circuit which is turned on, and an eighth switch circuit which is provided in a path between the other end of the second capacitor and the fourth common node, and which is turned off in the charge operation and turned on in the charge output operation; May be included.
The signal synthesis unit amplifies a voltage difference between an inverting input terminal connected to the first common node and a non-inverting input terminal connected to the second common node, and the amplification result is used as the third common node. An operational amplifier that outputs a voltage difference between the non-inverting output terminal connected to the inverting output terminal connected to the fourth common node and the inverting input terminal and the non-inverting output terminal of the operational amplifier. Provided in a path, and is provided in a path between a non-inverting input terminal and the inverting output terminal of the operational amplifier, and a ninth switch circuit that is turned on in the charging operation and turned off in the charge output operation. A tenth switch circuit that is turned on in operation and turned off in the charge output operation.
Also in the above configuration, since the differential signal is multiplied by the square wave, the in-phase noise is easily removed.

Preferably, the analog-to-digital converter according to the present invention is a noise component included in the input analog signal, from a frequency that is an integral multiple of the frequency at which the charging operation is repeated, to the signal band of the input signal. A first low-pass filter that attenuates the noise component that may cause aliasing noise may be provided.
Thereby, the aliasing noise in the signal generated in the signal synthesis unit is reduced.

Preferably, the analog-to-digital converter of the present invention has the N patterns corresponding to the first to Nth harmonics in the order of decreasing frequency among the harmonics included in the first square wave. N square wave multipliers for multiplying the input signal by a second square wave may be included, in which case the first low-pass filter is the harmonic included in the first square wave, The noise component of the input signal having a frequency corresponding to the (N + 1) th and higher harmonics in order of increasing frequency may be attenuated.
This makes it difficult for a direct current component corresponding to the product of the noise component of the input signal and the harmonic included in the first square wave to be mixed into the signal resulting from the synthesis of the signal synthesis unit.

Preferably, the analog-digital converter of the present invention may include a second low-pass filter and a second low-pass filter that extract a direct current component included in the output digital value.
Thereby, a DC component corresponding to the amplitude of the frequency component of the sine wave included in the input analog signal is extracted.

  According to the present invention, it is possible to obtain a digital value from a signal resulting from multiplying an input signal by a sine wave, an analog that is simple in configuration, has a wide range of input signal levels, and has little fluctuation in characteristics due to temperature. -A digital converter can be provided.

It is a figure which shows the structural example of the circuit which multiplies a square wave to an input signal. 1A shows a block diagram, and FIG. 1B shows an example of a circuit configuration. It is a figure which shows the frequency component of a sine wave and a square wave. FIG. 2A shows the frequency component of a square wave, and FIG. 2B shows the frequency component of a square wave. It is a figure which shows the frequency component of a square wave. 3A shows a frequency component of a square wave having a predetermined frequency, and FIGS. 3B and 3C show a frequency component of a square wave including a fundamental wave equal to the harmonic of the square wave of FIG. 3A. It is a figure which shows an example of a structure of the analog-digital converter which concerns on 1st Embodiment. It is a figure which shows an example of a structure of the analog-digital converter which concerns on 2nd Embodiment. It is a figure for demonstrating the state of each switch element at the time of charge operation and charge output operation. 6A shows the state of the switch element during the charging operation, and FIG. 6B shows the state of the switch element during the charge output operation. It is a timing diagram which shows the state of each switch element in the analog-digital converter which concerns on 2nd Embodiment. It is a figure which shows an example of a structure of the analog-digital converter which concerns on 3rd Embodiment. It is a graph which shows an example of the time change of the output signal of the signal synthetic | combination part in the analog-digital converter which concerns on 3rd Embodiment. It is a figure which shows an example of a structure of the analog-digital converter which concerns on 4th Embodiment. It is a figure which shows an example of a structure of the sine wave multiplication part in the A / D converter shown in FIG. FIG. 12 is a timing diagram illustrating a state of each switch element in the sine wave multiplication unit illustrated in FIG. 11. It is a figure which shows an example of a structure of the square wave multiplication part in the analog-digital converter which concerns on 5th Embodiment. It is a figure for demonstrating the state of each switch element at the time of charge operation of a sine wave multiplication part shown in FIG. 13, and an electric charge output operation. FIG. 14A shows the state of the switch element during the charging operation, and FIG. 14B shows the state of the switch element during the charge output operation. FIG. 14 is a timing diagram illustrating a state of each switch element in the sine wave multiplication unit illustrated in FIG. 13. It is a figure which shows the modification which provided the low pass filter in the input side. It is a figure which shows the modification which provided the low pass filter in the output side. It is a figure which shows the modification at the time of making the fundamental wave of the square wave in a 2nd square wave multiplication part and the harmonic of the square wave in a 1st square wave multiplication part into the same phase.

  First, an outline of a method of multiplying an input signal by a sine wave in an analog-digital converter (hereinafter abbreviated as “A / D converter”) according to an embodiment of the present invention will be described.

  FIG. 1 is a diagram illustrating a configuration example of a circuit that multiplies an input signal Si by a square wave. Square wave multiplication is different from sine wave multiplication, and can be realized by a simple circuit using fixed gain amplifier circuits 2 and 4 and a switch circuit 3, for example, as shown in FIG. 1B. In the square wave multiplication circuit shown in FIG. 1B, the input signal Si or a signal obtained by inverting the input signal Si by the amplifier circuit 2 having a gain “−1” is input to the amplifier circuit 4 having the gain A through the switch circuit 3. In one half cycle of the square wave, the input signal Si is amplified (multiplied by A) by the amplifier circuit 4 having a gain A, and in the other half cycle of the square wave, the input signal Si has a gain A and a gain. Amplified by the amplifier circuit 2 of “−1” (multiplied by −A).

  FIG. 2 is a diagram illustrating frequency components of a sine wave and a square wave. A sine wave consists of only a single frequency component as shown in FIG. 2A, while a square wave consists of a fundamental wave and a harmonic as shown in FIG. 2B. Accordingly, the square wave multiplication result signal shown in FIG. 1 includes a signal component obtained by multiplying the input signal Si by the fundamental wave (input signal Si × fundamental wave) and a signal component obtained by multiplying the input signal Si by the harmonic wave (input signal). (Si × harmonic).

  As shown in FIG. 1, square wave multiplication has an advantage that the circuit configuration is simple, and unlike the case of using an analog multiplier, it is less susceptible to the influence of transistor temperature characteristics and input / output nonlinear characteristics. However, since the signal of the square wave multiplication result includes the harmonic signal component (input signal Si × harmonic) as described above, it cannot be used as it is as the multiplication result of the input signal Si and the sine wave. Therefore, in the A / D converter according to the present embodiment, a plurality of circuits for multiplying the input signal and the square wave are provided, and their outputs are combined to be included in the multiplication result of the input signal and the square wave. Cancels unnecessary signal components (input signal x harmonics).

  FIG. 3 is a diagram illustrating frequency components of a square wave. FIG. 3A shows the frequency component of a square wave of frequency fs. FIG. 3B shows frequency components of a square wave having a frequency (3fs) that is three times that of the square wave of FIG. 3A and an amplitude (A / 3) that is one third. FIG. 3C shows a frequency component of a square wave having a frequency (5 fs) five times that of the square wave of FIG. 3A and an amplitude (A / 5) of one fifth.

  The square wave having the frequency fs includes a fundamental wave having the frequency fs and harmonics having frequencies (3fs, 5fs, 7fs,...) That are odd multiples thereof. When the amplitude of the fundamental wave is “B”, the amplitude of the harmonic having the frequency “K × fs” (hereinafter referred to as “Kth harmonic”) is “B / K”. The fundamental wave in the square wave of frequency 3fs and amplitude B / 3 shown in FIG. 3B is equal to the third harmonic in the square wave of frequency fs and amplitude B shown in FIG. 3A. Further, the fundamental wave in the square wave of frequency 5fs and amplitude B / 5 shown in FIG. 3C is equal to the fifth harmonic in the square wave of frequency fs and amplitude B shown in FIG. 3A.

  Accordingly, by multiplying the input signal Si by the square wave shown in FIG. 3A, multiply the input signal Si by the square wave having the opposite phase to the square wave shown in FIGS. 3B and 3C, and synthesize the multiplication results. The third harmonic component and the fifth harmonic component in the square wave of frequency fs can be canceled out. As described above, the A / D converter according to the present embodiment performs the multiplication of the input signal and a plurality of square waves instead of the direct multiplication of the input signal and the sine wave using the analog multiplier. Thus, the multiplication of the input signal and the sine wave is realized by combining the multiplication results. For this reason, it is difficult to be influenced by the temperature characteristics and input / output nonlinear characteristics of the transistor, and the circuit configuration is simplified.

  Next, several embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 4 is a diagram illustrating an example of the configuration of the A / D converter according to the first embodiment of the present invention. The A / D converter shown in FIG. 4 includes three square wave multipliers U1, U2, U3 for multiplying the input analog signal Vi by square waves W1, W2, W3 having different frequencies, and the square wave multipliers U1, U1. A signal synthesis unit 10 that synthesizes signals Qu1, Qu2, and Qu3 resulting from multiplication of U2 and U3, and a digital value acquisition unit 20 that obtains an output digital value Do based on the signal Vo synthesized by the signal synthesis unit 10. . Hereinafter, an arbitrary one of the three square wave multipliers (U1 to U3) is referred to as a “square wave multiplier U”, and an arbitrary one of the multiplication results signals Qu1 to Qu3 is referred to as a “signal Qu”. Any one of the waves W1 to W3 is referred to as a “square wave W”.

  The square wave W multiplied by the input analog signal Vi in the square wave multiplier U has a waveform in which the amplitude is the same and the polarity is reversed in one half cycle and the other half cycle. This square wave W can be approximated as the sum of a fundamental wave and a harmonic wave as shown in FIGS. 2 and 3, and the Kth harmonic wave has a frequency K times that of the fundamental wave and an amplitude of 1 / K. have.

  The square wave multiplication unit U generates, for example, an output signal Qu that is proportional to the input analog signal Vi in each of one half cycle and the other half cycle in one cycle of the square wave W to be multiplied by the input analog signal Vi. In addition, the absolute value of the ratio between the input analog signal Vi and the output signal Qu is equal in the one half cycle and the other half cycle, and the output signal Qu is generated so that the sign of the ratio is inverted. . That is, the square wave multiplication unit U sets the ratio of the output signal Qu to the input analog signal Vi to “A” in one half cycle in one cycle of the square wave W, and the other half in one cycle of the square wave W. In the period, the ratio of the output signal Qu to the input analog signal Vi is set to “−A”.

  The square wave multiplier U1 (hereinafter referred to as “first square wave multiplier U1”) has a square wave W1 having a sine wave of frequency fs as a fundamental wave (hereinafter referred to as “first square wave W1”). Is multiplied by the input analog signal Vi. In the example of FIG. 4, the frequency of the first square wave W1 is “fs”, and the amplitude is “A”.

Square wave multipliers U2 and U3 (hereinafter referred to as “second square wave multiplier U2” and “second square wave multiplier U3”) are used to generate one harmonic wave included in first square wave W1 having frequency fs. The input analog signal Vi is multiplied by square waves W2 and W3 (hereinafter referred to as “second square wave W2” and “second square wave W3”) each having a sine wave whose phase is inverted as a fundamental wave.
That is, the second square wave multiplier U2 multiplies the input analog signal Vi by the second square wave W2 having a sine wave obtained by inverting the phase of the third harmonic in the first square wave W1 as a fundamental wave. As shown in FIG. 4, the frequency of the second square wave W2 is “3fs” and the amplitude is “A / 3”.
The second square wave multiplier U3 multiplies the input analog signal Vi by a second square wave W3 having a sine wave obtained by inverting the phase of the fifth harmonic in the first square wave W1 as a fundamental wave. As shown in FIG. 4, the frequency of the second square wave W3 is “5fs” and the amplitude is “A / 5”.

  The signal synthesis unit 10 adds the signal Qu1 of the first square wave multiplication unit U1 and the signals Qu2 and Qu3 of the second square wave multiplication units U2 and U3. The signal synthesizer 10 performs addition of the signals Qu1 to Qu3, thereby obtaining a signal component corresponding to the product of the third harmonic of the first square wave W1 included in the signal Qu1 and the input analog signal Vi as the signal Qu2. Is canceled by a signal component corresponding to the product of the fundamental wave of the second square wave W2 included in the input analog signal Vi. Further, the signal synthesizer 10 generates a signal component corresponding to the product of the fifth harmonic of the first square wave W1 included in the signal Qu1 and the input analog signal Vi of the second square wave W3 included in the signal Qu3. It cancels with the signal component according to the product of the fundamental wave and the input analog signal Vi.

  The digital value acquisition unit 20 acquires an output digital value Do corresponding to the product of the input analog signal Vi and a sine wave based on the signal Vo as the addition result of the signals Qu1 to Qu3 in the signal synthesis unit 10. Various methods can be used to acquire a digital value in the digital value acquisition unit 20, for example, A / D conversion such as a delta-sigma type, an integration type, a pipeline type, a successive approximation type, or a flash type. A scheme can be used.

  According to the A / D converter shown in FIG. 4, the signal component corresponding to the product of the third harmonic wave of the first square wave W1 included in the signal Qu1 and the input analog signal Vi is included in the signal Qu2. Canceled by the signal component corresponding to the product of the fundamental wave of the square wave W2 and the input analog signal Vi, and according to the product of the fifth harmonic of the first square wave W1 included in the signal Qu1 and the input analog signal Vi The signal component is canceled by the signal component corresponding to the product of the fundamental wave of the second square wave W3 included in the signal Qu3 and the input analog signal Vi. Therefore, in the signal Vo obtained as a result of combining the signals Qu1 to Qu3, signal components corresponding to the third harmonic and the fifth harmonic of the first square wave W1 are reduced, and the fundamental wave of the first square wave W1 ( The signal component corresponding to the product of the sine wave of frequency fs) and the input analog signal Vi becomes the dominant component. Therefore, based on the signal Vo from the signal synthesizer 10, it is possible to acquire an accurate output digital value Do corresponding to the product of the sine wave having the frequency fs and the input analog signal Vi.

  Further, according to the A / D converter shown in FIG. 4, in the square wave multiplication unit U, the input is performed in one half cycle and the other half cycle in one cycle of the square wave W multiplied by the input analog signal Vi. The output signal Qu is generated so that the absolute value of the ratio between the analog signal Vi and the output signal Qu is equal and the sign of the ratio is inverted. That is, the sign of the input analog signal Vi and the square wave W is inverted by inverting the sign of the square wave W every half cycle while maintaining the absolute value of the ratio (signal gain) of the output signal Qu to the input analog signal Vi. Multiplication is performed. Such multiplication of the square wave W is discrete signal processing in which a fixed signal gain is switched every half cycle, and the influence of the analog characteristics of the transistor current and voltage on the multiplication result is reduced. Therefore, it is possible to make it difficult to be influenced by the temperature characteristics and input / output nonlinear characteristics of the transistor as in the case of using an analog multiplier.

<Second Embodiment>
Next, an example of an A / D converter using a delta-sigma conversion method will be described as a second embodiment of the present invention.

  FIG. 5 is a diagram illustrating an example of a configuration of an A / D converter according to the second embodiment. The A / D converter shown in FIG. 5 has a first square wave multiplier UA1 that multiplies an input analog signal Vi by a first square wave W1, and a second that multiplies an input analog signal Vi by second square waves W2 and W3. Square wave multipliers UA2 and UA3, a signal synthesizer 10A for synthesizing signals of multiplication results of the first square wave multiplier UA1 and the second square wave multipliers UA2 and UA3, and a signal indicating the synthesized result of the signal synthesizer 10A It has a digital value acquisition unit 20A that acquires an output digital value Do based on Vo. In the following description, the first square wave multiplication unit UA1 and the second square wave multiplication units UA2 and UA3 may be referred to as “square wave multiplication unit UA” without distinction.

  Further, the A / D converter according to the present embodiment includes a first input terminal Ti1 and a second input terminal Ti2 to which a differential signal is input as an input analog signal Vi, and three square wave multipliers (UA1 to UA3). Have a first common node N1 and a second common node N2 connected in common.

  The square wave multiplication unit UA includes two capacitors (first capacitor C1 and second capacitor C2) having the same capacitance. The square wave multiplication unit UA converts the input analog signal Vi into the input analog signal Vi in each of one half cycle and the other half cycle in one cycle of a square wave (first square wave or second square wave) to be multiplied with the input analog signal Vi. The charging operation for accumulating the corresponding charges in the capacitors (C1, C2) and the charge output operation for outputting the charges accumulated in the capacitors (C1, C2) by the charging operation to the signal synthesis unit 10A are alternately repeated at predetermined intervals. To do. Further, the square wave multiplication unit UA has a relationship between the polarity of the input analog signal Vi during the charging operation and the polarity of the difference between the charges output from the two capacitors (C1, C2) to the signal combining unit 10A during the charge output operation. Inverted between one half cycle and the other half cycle in one cycle of the square wave. For example, when the polarity of the input analog signal Vi is “positive”, the polarity of the difference between the charges output from the two capacitors (C1, C2) to the signal combining unit 10A is set to “positive” in one half cycle of the square wave. In the other half cycle of the square wave, the polarity of the charge difference is “negative”. The square wave multiplication unit UA performs multiplication of the input analog signal Vi and a square wave (first square wave or second square wave) by such polarity inversion every half cycle.

  For example, in the charging operation, the square wave multiplication unit UA generates a voltage generated between one of the first input terminal Ti1 and the second input terminal Ti2 and the common potential (the reference potential Vref in the example of FIG. 5) in the first capacitor C1. In addition, a voltage generated between the other of the first input terminal Ti1 and the second input terminal Ti2 and the common potential is applied to the second capacitor C2. In the charge output operation, the square wave multiplication unit UA outputs the charge accumulated in one of the first capacitor C1 and the second capacitor C2 to the first common node N1, and the other of the first capacitor C1 and the second capacitor C2. Is stored in the second common node N2. The square wave multiplication unit UA outputs the charges of the first capacitor C1 and the second capacitor C2 to the signal synthesis unit 10A via the first common node N1 and the second common node N2. In addition, the square wave multiplication unit UA has a charge difference obtained by subtracting the charge output to the second common node N2 from the polarity output to the first common node N1 during the charge output operation and the polarity of the input analog signal Vi during the charge operation. The relationship with the polarity is reversed between one half cycle and the other half cycle in one cycle of the square wave.

  In the example of FIG. 5, the first square wave multiplication unit UA1 includes a first capacitor C1 and a second capacitor C2 having the same capacitance, a first switch circuit 31, a second switch circuit 32, and a third switch circuit 33. Have

The first capacitor C1 has one terminal connected to the first common node N1 and the other terminal connected to the first input terminal Ti1 or the second input terminal Ti2 via the first switch circuit 31.
The second capacitor C2 has one terminal connected to the second common node N2, and the other terminal connected to the first input terminal Ti1 or the second input terminal Ti2 via the first switch circuit 31.

  The first switch circuit 31 connects the other terminal of the first capacitor C1 to the first input terminal Ti1 in one half-cycle charging operation in one cycle of the first square wave W1 multiplied by the input analog signal Vi. In addition, the other terminal of the second capacitor C2 is connected to the second input terminal Ti2. The first switch circuit 31 connects the other terminal of the first capacitor C1 to the second input terminal Ti2 and the second capacitor in the charging operation of the other half cycle in one cycle of the first square wave W1. The other terminal of C2 is connected to the first input terminal Ti1. In the charge output operation, the first switch circuit 31 disconnects the other terminal of the first capacitor C1 and the other terminal of the second capacitor C2 from the first input terminal Ti1 and the second input terminal Ti2.

  The first switch circuit 31 includes, for example, four switch elements (S1 to S4) as shown in FIG. The switch element S1 is provided in a path between the other terminal of the first capacitor C1 and the first input terminal Ti1. The switch element S2 is provided in a path between the other terminal of the first capacitor C1 and the second input terminal Ti2. The switch element S3 is provided in a path between the other terminal of the second capacitor C2 and the first input terminal Ti1. The switch element S4 is provided in a path between the other terminal of the second capacitor C2 and the second input terminal Ti2. In one half cycle charging operation in one cycle of the first square wave W1, the switch elements S1 and S4 are turned on and the switch elements S2 and S3 are turned off. In the charging operation of the other half cycle in one cycle of the first square wave W1, the switch elements S1 and S4 are turned off and the switch elements S2 and S3 are turned on. In the charge output operation, all the switch elements S1 to S4 are turned off.

  The second switch circuit 32 is provided in a path between the other terminal of the first capacitor C1 and the other terminal of the second capacitor C2, and is turned off in the charging operation of the square wave multiplier UA, and the charge output operation Turn on at. For example, as shown in FIG. 5, the second switch circuit 32 has a switch element S5 connected to the other terminal of the first capacitor C1 and the other terminal of the second capacitor C2.

  The third switch circuit 33 connects the first common node N1 and the second common node N2 to the reference potential Vref in the charging operation of the square wave multiplication unit UA, and the first common node N1 in the charge output operation of the square wave multiplication unit UA. The second common node N2 is disconnected from the reference potential Vref. For example, as shown in FIG. 5, the third switch circuit 33 includes a switch element S6 connected to the first common node N1 and the reference potential Vref, and a switch element S7 connected to the second common node N2 and the reference potential Vref. Have.

  The second square wave multipliers UA2 and UA3 have the same configuration as that obtained by omitting the third switch circuit 33 from the first square wave multiplier UA1. In the example of FIG. 5, the three square wave multipliers (UA1 to UA3) share one third switch circuit 33.

  The capacitances of the first capacitor C1 and the second capacitor C2 in the first square wave multiplier UA1 and the second square wave multipliers UA2 and UA3 are the harmonics of the first square wave W1 and the second square waves W2 and W3. It is set so that the fundamental wave has the same amplitude.

That is, the capacitance of the capacitors (C1, C2) in the second square wave multiplication unit UA2 is set to 1/3 of the capacitance of the capacitors (C1, C2) in the first square wave multiplication unit UA1. . The ratio of the capacitances is that the amplitude of the fundamental wave of the first square wave W1 and the amplitude of the third harmonic of the first square wave W1 having the same frequency (3 fs) as the fundamental wave of the second square wave W2. The ratio is the same. Since the amount of charge with respect to the same voltage becomes 1/3 because the capacitance becomes 1/3, the amplitude of the second square wave W2 multiplied by the input analog signal Vi in the second square wave multiplication unit UA2 is: It becomes 1/3 of the amplitude of the first square wave W1.
Further, the capacitance of the capacitors (C1, C2) in the second square wave multiplication unit UA3 is set to 1/5 of the capacitance of the capacitors (C1, C2) in the first square wave multiplication unit UA1. . The ratio of the capacitances is that the amplitude of the fundamental wave of the first square wave W1 and the amplitude of the fifth harmonic of the first square wave W1 having the same frequency (5 fs) as the fundamental wave of the second square wave W3. The ratio is the same. Since the amount of charge with respect to the same voltage becomes 1/5 because the electrostatic capacity becomes 1/5, the amplitude of the second square wave W3 multiplied by the input analog signal Vi in the second square wave multiplication unit UA3 is: It becomes 1/5 of the amplitude of the first square wave W1.

  The capacitances of the first capacitor C1 and the second capacitor C2 in the first square wave multiplication unit UA1 are “Cu1”, and the capacitances of the first capacitor C1 and the second capacitor C2 in the second square wave multiplication unit UA2 are “Cu2”. If the capacitances of the first capacitor C1 and the second capacitor C2 in the second square wave multiplication unit UA3 are “Cu3”, these capacitances are set as follows.

  Cu1: Cu2: Cu3 = 1: 1/3: 1/5 = 15: 5: 3 (1)

This is a value obtained by subtracting the charge output from the second capacitor C2 to the second common node N2 from the charge output from the first capacitor C1 of the first square wave multiplier UA1 to the first common node N1 by the charge output operation. The charge difference is “ΔQ1”, and the component corresponding to the product of the third harmonic (frequency 3 fs) of the first square wave W1 and the input analog signal Vi in the charge difference ΔQ1 is “ΔQ1 (3fs)”. . In the charge difference ΔQ1, a component corresponding to the product of the fifth harmonic (frequency 5fs) of the first square wave W1 and the input analog signal Vi is referred to as “ΔQ1 (5fs)”.
On the other hand, a value obtained by subtracting the charge output from the second capacitor C2 to the second common node N2 from the charge output from the first capacitor C1 to the first common node N1 of the second square wave multiplication unit UA2 by the charge output operation. The charge difference is “ΔQ2”, and the component corresponding to the product of the fundamental wave (frequency 3fs) of the second square wave W2 and the input analog signal Vi in the charge difference ΔQ2 is “ΔQ2 (3fs)”. I write.
Further, a value obtained by subtracting the charge output from the second capacitor C2 to the second common node N2 from the charge output from the first capacitor C1 of the second square wave multiplication unit UA3 to the first common node N1 by the charge output operation. The charge difference is “ΔQ3”, and the component corresponding to the product of the fundamental wave (frequency 5 fs) of the second square wave W3 and the input analog signal Vi in the charge difference ΔQ3 is “ΔQ3 (5 fs)”. I write.
By setting the capacitances of the capacitors (C1, C2) of each square wave multiplier as shown in Expression (1), the following relationship is established for the above-described charge difference components.

ΔQ1 (3fs) = − ΔQ2 (3fs) (2)
ΔQ1 (5fs) = − ΔQ3 (5fs) (3)

  However, the phase relationship between the first square wave W1 and the second square wave W2 is set so that the third harmonic of the first square wave W1 and the fundamental wave of the second square wave W2 are in opposite phases. . The phase relationship between the first square wave W1 and the second square wave W3 is set so that the fifth harmonic of the first square wave W1 and the fundamental wave of the second square wave W3 are in reverse phase.

  Since the relations of the expressions (2) and (3) are established, the charge differences ΔQ1, ΔQ2, and ΔQ3 are combined (added) in the signal combining unit 10A, so that the third harmonic of the first square wave W1 and The component ΔQ1 (3fs) corresponding to the product of the input analog signal Vi is canceled by the component ΔQ2 (3fs) corresponding to the product of the fundamental wave of the second square wave W2 and the input analog signal Vi. The component ΔQ1 (5fs) corresponding to the product of the fifth harmonic of the first square wave W1 and the input analog signal Vi corresponds to the product of the fundamental wave of the second square wave W3 and the input analog signal Vi. It is canceled out by the component ΔQ3 (5fs). That is, the signal component resulting from the third harmonic and the fifth harmonic of the first square wave W1 is removed by addition with the signal components output from the second square wave multipliers UA2 and UA3.

  The signal synthesizer 10A has a third capacitor C3 and a fourth capacitor C4 having the same capacitance, and is output from the three square wave multipliers (UA1 to UA3) to the first common node N1 by the charge output operation. The stored charge is stored in the third capacitor C3, and the charge output from the three square wave multipliers (UA1 to UA3) to the second common node N2 by the charge output operation is stored in the fourth capacitor C4. The signal synthesis unit 10A outputs a signal Vo corresponding to the difference between the charge of the third capacitor C3 and the charge of the fourth capacitor C4.

  In the example of FIG. 5, the signal synthesis unit 10 </ b> A includes a third capacitor C <b> 3 and a fourth capacitor C <b> 4 having the same capacitance, an operational amplifier 11, and a fourth switch circuit 12.

  The operational amplifier 11 amplifies the voltage difference between the inverting input terminal and the non-inverting input terminal, and outputs the amplification result as the voltage difference between the inverting output terminal and the non-inverting output terminal, that is, the signal Vo.

  The third capacitor C3 is provided in a path between the inverting input terminal and the non-inverting output terminal of the operational amplifier 11. The fourth capacitor C4 is provided in a path between the non-inverting input terminal and the inverting output terminal of the operational amplifier 11.

  The fourth switch circuit 12 disconnects the first common node N1 from the inverting input terminal of the operational amplifier 11 and the second common node N2 when the three square wave multipliers (UA1 to UA3) perform the charging operation. When the three square wave arithmetic units (UA1 to UA3) perform the charge output operation by disconnecting from the non-inverting input terminal of the operational amplifier 11, the first common node N1 is connected to the inverting input terminal of the operational amplifier 11 and the second common node N2 Is connected to the non-inverting input terminal of the operational amplifier 11. For example, as shown in FIG. 5, the fourth switch circuit 12 includes a switch element S8 connected between the inverting input terminal of the operational amplifier 11 and the first common node N1, the non-inverting input terminal of the operational amplifier 11, The switch element S9 is connected between the two common nodes N2.

  In the example of FIG. 5, the digital value acquisition unit 20 </ b> A includes a first comparison unit 21, a charge generation unit 22, and a first digital value generation unit 23.

  The first comparison unit 21 compares the signal Vo indicating the synthesis result of the signal synthesis unit 10A with a reference value, and outputs a signal B1 indicating the comparison result. For example, the first comparison unit 21 outputs a 1-bit signal B1 indicating whether the polarity of the signal Vo that is a differential signal is positive.

  The first digital value generation unit 23 acquires an output digital value Do corresponding to the input analog signal Vi based on the output signal B1 of the first comparison unit 21. For example, the first digital value generation unit 23 acquires the output digital value Do from the frequency of occurrence of the signal B1 having a predetermined value.

  The charge generation unit 22 generates a charge corresponding to the output signal B1 of the first comparison unit 21, and generates the charge at a timing synchronized with the charge output operation of the three square wave multiplication units (UA1 to UA3). Output to. For example, the charge generation unit 22 outputs charges to the first common node N1 and the first common node N1 at the timing synchronized with the charge output operations of the three square wave multiplication units (UA1 to UA3), and the first common node The charge difference obtained by subtracting the charge output to the second common node N2 from the charge output to the node N1 (hereinafter referred to as “charge difference ΔQf”) is set to a value corresponding to the output signal B1 of the first comparison unit 21. To do. Specifically, when the signal B1 indicating that the polarity of the signal Vo is positive is input, the charge generation unit 22 sets the charge difference ΔQf having a polarity that decreases the voltage of the signal Vo to the signal Vo. When the signal B1 indicating that the polarity is positive is input, the charge difference ΔQf having a polarity for increasing the voltage of the signal Vo is set.

  In the example of FIG. 5, the charge generation unit 22 includes a fifth capacitor C5 having one terminal connected to the first common node N1, a sixth capacitor C6 having one terminal connected to the second common node N2, A fifth switch circuit 221 and a voltage supply circuit 222 are included.

  The fifth switch circuit 221 is provided in a path between the other terminal of the fifth capacitor C5 and the other terminal of the sixth capacitor C6, and the three square wave multipliers (UA1 to UA3) perform the charging operation. Turns off when performing, and turns on when performing charge output operation. For example, as shown in FIG. 5, the fifth switch circuit 221 includes a switch element S10 connected between the other terminal of the fifth capacitor C5 and the other terminal of the sixth capacitor C6.

  The voltage supply circuit 222 supplies a voltage to the other terminal of the fifth capacitor C5 and the other terminal of the sixth capacitor C6 at a timing synchronized with the charging operation of the two square wave multipliers (UA1 to UA3), respectively. Depending on the output signal B1 of the first comparator, the other terminal of the fifth capacitor C5 is set to a voltage higher by a predetermined voltage (VDD) than the other terminal of the sixth capacitor C6, or the sixth capacitor C6 Is set to a voltage higher than the other terminal of the fifth capacitor C5 by a predetermined voltage (VDD).

  The voltage supply circuit 222 includes switch elements S11 to S14 in the example of FIG. The switch element S11 is connected between the other terminal of the fifth capacitor C5 and the power supply voltage VDD, the switch element S12 is connected between the other terminal of the fifth capacitor C5 and the ground GND, and the switch element S13 is The other terminal of the six capacitor C6 is connected between the power supply voltage VDD and the switch element S14 is connected between the other terminal of the sixth capacitor C6 and the ground GND. When the switch elements S11 and S14 are turned on and the switch elements S12 and S13 are turned off, the other terminal of the fifth capacitor C5 becomes a voltage higher than the other terminal of the sixth capacitor C6 by the voltage VDD, and the switch elements S11 and S14 When the switch elements S12 and S13 are turned on, the other terminal of the sixth capacitor C6 becomes a voltage higher than the other terminal of the fifth capacitor C5 by the voltage VDD.

  Here, the operation of the A / D converter according to this embodiment having the above-described configuration will be described.

  FIG. 6 is a diagram for explaining the state of each switch element during the charging operation and the charge output operation. 6A shows the state of the switch element during the charging operation, and FIG. 6B shows the state of the switch element during the charge output operation.

  In the example of FIG. 6, only the first square wave multiplication unit UA1 is shown, but the second square wave multiplication units UA2 and UA3 are also in the same switch state in the charging operation and the charge output operation. For the charge generation unit 22, the switch element S 10 of the fifth switch circuit 221 is regarded as the switch element S 5 of the second switch circuit 32, and the switch elements S 11 to S 14 of the voltage supply circuit 222 are the switch elements of the first switch circuit 31. When the fifth capacitor C5 and the sixth capacitor C6 are regarded as the first capacitor C1 and the second capacitor C2 as S1 to S4, the switch state similar to that of the first square wave multiplication unit UA1 in the charge operation and the charge output operation Become.

  During the charging operation, as shown in FIG. 6A, the first capacitor C1 is connected between the first input terminal Ti1 and the reference potential Vref, and the second capacitor C2 is connected between the second input terminal Ti2 and the reference potential Vref. The At this time, since the switch elements S8 and S9 of the fourth switch circuit 12 are in the OFF state, the charge accumulated in the third capacitor C3 and the fourth capacitor C4 is held at the same value as the charge in the previous charge output operation. .

  The difference voltage obtained by subtracting the voltage of the second input terminal Ti2 from the voltage of the first input terminal Ti1 is “Vi”, the capacitances of the first capacitor C1 and the second capacitor C2 are “C”, and the first capacitor in the charging operation If the charge accumulated in C1 is “Qa” and the charge accumulated in the second capacitor C2 in the charging operation is “Qb”, the charge difference “Qa− obtained by subtracting the charge Qb from the charge Qa in the switch state shown in FIG. 6A”. Qb "is represented by the following equation.

  Qa−Qb = Vi × C (4)

  During the charge output operation, as shown in FIG. 6B, the other terminals of the first capacitor C1 and the second capacitor C2 are short-circuited by the second switch circuit 32. Since the voltages at the first common node N1 and the second common node N2 become substantially equal due to the negative feedback operation of the operational amplifier 11, the voltages at the first capacitor C1 and the second capacitor C2 become substantially equal and are stored in both. The charges are almost equal. Since the total charge of “Qa + Qb” is accumulated in the first capacitor C1 and the second capacitor C2 by the charging operation, the charge accumulated in each of the first capacitor C1 and the second capacitor C2 is “(( Qa + Qb) / 2 ".

  Since the charge of the first capacitor C1 changes from “Qa” to “(Qa + Qb) / 2”, the change amount “(Qa−Qb) / 2” is transferred from the first capacitor C1 to the third capacitor C3. The Further, since the charge of the second capacitor C2 changes from “Qb” to “(Qa + Qb) / 2”, the change amount “− (Qa−Qb) / 2” is changed from the second capacitor C1 to the fourth capacitor C3. Forwarded to Therefore, if the charge difference obtained by subtracting the charge accumulated in the fourth capacitor C4 from the charge accumulated in the third capacitor C3 is “ΔQS”, the increase in the charge difference ΔQS due to the charge output operation of the first square wave multiplier UA1. Becomes “Qa−Qb = Vi × C”.

  However, this result is obtained in the switch state of the first switch circuit 31 shown in FIG. 6A. The first switch circuit 31 is in the other switch state (the switch elements S1 and S4 are off, the switch elements S2 and S3 are In the ON state), the positive and negative polarities are reversed. That is, in this case, the increase in the charge difference ΔQS due to the charge output operation of the first square wave multiplication unit UA1 is “− (Qa−Qb) = − Vi × C”.

  From the above, the charge difference ΔQ1 added to the charge difference ΔQS by one charge output operation of the first square wave multiplier UA1 is expressed by the following equation.

  ΔQ1 = ± Vi × C (5)

  The positive and negative polarities shown on the right side of Expression (5) are switched between one half cycle and the other half cycle of the first square wave W1 (frequency fs).

  Similarly, the charge difference ΔQ2 added to the charge difference ΔQS by one charge output operation of the second square wave multiplication unit UA2 and the charge difference ΔQS by one charge output operation of the second square wave multiplication unit UA3. The charge difference ΔQ3 to be added is expressed by the following equations, respectively.

ΔQ2 = ± Vi × (C / 3) (6)
ΔQ3 = ± Vi × (C / 5) (7)

  The positive and negative polarities shown on the right side of Expression (6) are switched between one half cycle and the other half cycle of the second square wave W2 (frequency 3fs). Moreover, the positive / negative polarity shown on the right side of Formula (7) switches with one half cycle and the other half cycle of 2nd square wave W3 (frequency 5fs).

  The charge difference ΔQf added to the charge difference ΔQS by the charge output operation of the charge generation unit 22 is expressed by the following equation.

  ΔQf = ± VDD × Cf (8)

  In Expression (8), “Cf” indicates the capacitances of the fifth capacitor C5 and the sixth capacitor C6. The positive and negative polarities shown on the right side of Expression (8) are switched according to the output signal B1 of the first comparison unit 21. That is, when the polarity of the signal Vo of the signal synthesis unit 10A is positive (when the voltage at the non-inverted output terminal is higher than the voltage at the inverted output terminal), the polarity of the right side of the equation (8) becomes negative, When the polarity of the signal Vo is negative (when the voltage at the non-inverting output terminal is lower than the voltage at the inverting output terminal), the polarity on the right side of the equation (8) is positive.

  The signal synthesizer 10A operates as an integrator that accumulates the charge differences ΔQ1 to ΔQ3 and ΔQf output from the three square wave multipliers (UA1 to UA3) in a constant cycle in the third capacitor C3 and the fourth capacitor C4. . The charge generation unit 22 suppresses an increase in the charge difference ΔQS of the signal synthesis unit 10A that operates as an integrator by switching the polarity of the charge difference ΔQf according to the output signal B1 of the first comparison unit 21.

  If the value of the signal B1 when the signal Vo of the signal synthesizer 10A is positive is “1”, and the value of the signal B1 when the polarity of the signal Vo is negative is “−1”, the input analog signal Vi is positive. As the input analog signal Vi increases to the positive side, the signal “B1” “−1” from the first comparison unit 21 becomes easier to output as the input analog signal Vi increases toward the positive side. As the input analog signal Vi becomes close to zero, the “1” and “−1” signals B <b> 1 are easily output equally. The first digital value generation unit 23 acquires the output digital value Do corresponding to the input analog signal Vi from the frequency of occurrence of “1” in the signal B1.

  FIG. 7 is a timing chart showing the state of each switch element in the A / D converter according to the second embodiment. In the timing chart of FIG. 7, a high level indicates an on state of the switch element, and a low level indicates an off state of the switch element.

  In the example of FIG. 7, the switch elements that are alternately turned on (switch elements S1 to S4 and switch element S5, switch elements S11 to S14 and switch element S10, switch elements S6 and S7, and switch elements S8 and S9) are turned on / off. In order to avoid crosstalk due to the delay, the on-states are controlled so as not to overlap each other.

  In the example of FIG. 7, the charging operation and the charge output operation are performed once every period T. One period (1 / fs) of the first square wave W1 is set to 60 cycles (60T) of the period T, and one period (1/3 fs) of the second square wave W2 is set to 20 cycles (20T of the period T). ) And one period (1/5 fs) of the second square wave W3 is set to 12 cycles (12T) of the period T.

  The number of cycles of period T (30 cycles in the example of FIG. 7) defining the half period of the first square wave W1 is the first square wave W1 to be canceled by the output of the second square wave multiplier (UA2, UA3). The harmonic frequencies (3fs, 5fs) are set to be a common multiple of the magnification (3 times, 5 times) of the fundamental frequency fs. In the A / D converter shown in FIG. 5, since the third harmonic and the fifth harmonic of the first square wave W1 are harmonics to be canceled, they are common multiples of “3” and “5”. “30” is set as the number of cycles of the period T in the half cycle of the first square wave W1. Thus, by determining the number of cycles of the period T in the half cycle of the first square wave W1, the number of cycles of the period T in the half cycle of the second square wave (W2, W3) can be made an integer value. The ratio between the period of the first square wave W1 and the period of the second square waves W2, W3 can be strictly set by the number of cycles of the period T.

  Here, an operation mode in which the polarity shown on the right side of the equations (5), (6), and (7) is “positive” is called “forward rotation mode”, and the polarity shown on the right side of these equations is “negative”. This operation mode is called “inversion mode”. As shown in FIG. 7, the square wave multipliers (UA1 to UA3) are in the “forward rotation mode” in one half cycle in one cycle of the square wave and in the “inversion mode” in the other half cycle. In the “forward rotation mode”, the switch elements S1 and S4 of the first switch circuit 31 are turned on and the switch elements S2 and S3 are turned off during the charging operation. In the “inversion mode”, the switch elements S1 and S4 of the first switch circuit 31 are turned off and the switch elements S2 and S3 are turned on during the charging operation.

  In the first square wave multiplication unit UA1, the operation in the normal rotation mode is repeated 30 cycles in the first half period (30T) of the first square wave W1, and the inversion mode is performed in the second half period (30T) of the first square wave W1. This operation is repeated 30 cycles.

  In the second square wave multiplication unit UA2, the operation in the inversion mode is repeated 10 cycles in the first half cycle (10T) of the second square wave W2, and the forward rotation mode is performed in the second half cycle (10T) of the second square wave W2. Is repeated 10 cycles. When the operation in the normal rotation mode is started in the first square wave multiplication unit UA1, the operation in the inversion mode is started in the second square wave multiplication unit UA2, so that the fundamental wave of the second square wave W2 is the first square wave W1. It has an opposite phase to the third harmonic.

  In the second square wave multiplication unit UA3, the operation in the inversion mode is repeated 6 cycles in the first half cycle (6T) of the second square wave W3, and the normal rotation mode in the second half cycle (6T) of the second square wave W3. The above operation is repeated 6 cycles. When the operation in the normal mode is started in the first square wave multiplication unit UA1, the operation in the inversion mode is started in the second square wave multiplication unit UA3. Therefore, the fundamental wave of the second square wave W3 is the first square wave W1. Have the opposite phase to the fifth harmonic.

  In the charge generation unit 22 of the digital value acquisition unit 20A, the states of the switch elements S11 to S14 during the charging operation are switched according to the value (“1” or “−1”) of the output signal B1 of the first comparison unit 21. . When the value of the signal B1 is “1” (when the polarity of the signal Vo is positive), the switch elements S11 and S14 are turned off, the switch elements S12 and S13 are turned on, and the charge generator 22 adds the charge difference ΔQS. The polarity (formula (8)) of the charged charge difference ΔQf is negative. Thereby, the charge difference ΔQS is reduced, and the increase in the signal Vo in the positive direction is suppressed. When the value of the signal B1 is “−1” (when the polarity of the signal Vo is negative), the switch elements S11 and S14 are turned on, the switch elements S12 and S13 are turned off, and the polarity of the charge difference ΔQf ( Since Expression (8) becomes positive, an increase in the negative direction of the signal Vo is suppressed.

  As described above, according to the A / D converter according to the present embodiment, the charging operation and the charge output operation of the capacitors (C1, C2) are repeated at regular intervals in the square wave multiplication unit UA. The input analog signal Vi is multiplied by the square wave W by inverting the polarity of the output charge in the charge output operation every half cycle. Therefore, the period and phase of the square wave in the square wave multiplication unit UA can be strictly set by the number of cycles of the period T.

  Further, according to the A / D converter according to the present embodiment, the capacitance ratio of the capacitors in the square wave multiplication unit UA is not easily affected by variations due to temperature and manufacturing process, and therefore, in each square wave multiplication unit UA. The amplitude ratio of the square wave W multiplied by the input analog signal Vi can be set with high accuracy. Therefore, the signal component (charge) corresponding to the product of the harmonic of the first square wave W1 included in the output of the first square wave multiplier UA1 and the input analog signal Vi is supplied to the second square wave multipliers UA2 and UA3. The signal components (charges) corresponding to the product of the fundamental waves of the second square waves W2 and W3 and the input analog signal Vi at the output can be accurately canceled.

  Furthermore, according to the A / D converter according to the present embodiment, in each of the three square wave multipliers (UA1 to UA3), square wave multiplication is performed based on the difference in charge according to the differential signal (Vi). The signal difference (ΔQ1 to ΔQ3) obtained as a signal of the multiplication result is synthesized in the signal synthesis unit, so that the output digital value Do corresponding to the product of the differential signal (Vi) and the sine wave is obtained. Is obtained. Therefore, common-mode noise superimposed on each differential signal can be easily removed, and noise resistance can be improved.

<Third Embodiment>
Next, as a third embodiment of the present invention, an example of an A / D converter using an integral conversion method will be described.

  FIG. 8 is a diagram illustrating an example of a configuration of an A / D converter according to the third embodiment. The A / D converter shown in FIG. 8 is obtained by replacing the signal synthesis unit 10A in the A / D converter shown in FIG. 5 with a signal synthesis unit 10B and replacing the digital value acquisition unit 20A with a digital value acquisition unit 20B. Other configurations are the same as those of the A / D converter shown in FIG.

  The signal synthesis unit 10B has the same configuration (the operational amplifier 11, the fourth switch circuit 12, the third capacitor C3, and the fourth capacitor C4) as the signal synthesis unit 10A in FIG. 5, and the third capacitor C3 and the fourth capacitor. It has the 1st discharge circuit 13 which discharges the electric charge of C4, respectively. In the example of FIG. 8, the first discharge circuit 13 includes a switch element S15 connected in parallel to the third capacitor C3 and a switch element S16 connected in parallel to the fourth capacitor C4.

  The digital value acquisition unit 20B acquires the output digital value Do based on the signal Vo indicating the synthesis result of the signal synthesis unit 10B. That is, the digital value acquisition unit 20B acquires the output digital value Do based on the charges from the three square wave multiplication units (UA1 to UA3) synthesized by the signal synthesis unit 10B. In the example of FIG. 8, the digital value acquisition unit 20B includes a second comparator 24, a second discharge circuit 25, a counter 26, and a second digital value generation unit 27.

  Based on the comparison between the signal Vo indicating the synthesis result of the signal synthesis unit 10B and the reference value, the second comparator 24 determines that the charge accumulated in the capacitors (C3, C4) of the signal generation unit 10B has a predetermined initial value. A signal B2 indicating the equal timing is output. For example, the second comparator 24 outputs a 1-bit signal B2 indicating whether or not the polarity of the signal Vo, which is a differential signal, is positive, similarly to the first comparator 21 in FIG. If the value of the signal B2 when the polarity of the signal Vo is positive is “1” and the value of the signal B2 when the polarity is negative is “0”, the change of the signal B2 from “1” to “0” or “ A change from “0” to “1” indicates the above timing. At this timing, the charge difference ΔQS obtained by subtracting the charge accumulated in the fourth capacitor C4 from the charge accumulated in the third capacitor C3 becomes zero.

  The second discharge circuit 25 is a circuit that discharges charges accumulated in the third capacitor C3 and the fourth capacitor C4 of the signal synthesis unit 10A with a constant current. In the example of FIG. 8, the second resistor R1 and the second resistor The resistor R2 and the sixth switch circuit 251 are included. The first resistor R1 has one end connected to the first common node N1 and the other end connected to the reference potential Vref via the sixth switch circuit 251. The second resistor R2 has one end connected to the second common node N2, and the other end connected to the reference potential Vref via the sixth switch circuit 251. The sixth switch circuit 251 connects the other end of the first resistor R1 and the other end of the second resistor R2 to the reference potential Vref during the discharging operation. The sixth switch circuit 251 includes a switch element S17 connected between the other end of the first resistor R1 and the reference potential Vref, and a switch connected between the other end of the second resistor R2 and the reference potential Vref. Including element S18. When the switch elements S17 and S18 are turned on, one end of the third capacitor C3 and the third capacitor C3 is short-circuited via the first resistor R1 and the second resistor R2, so that the third capacitor C3 and the fourth capacitor C4 have the same voltage. It is discharged to become. That is, discharging is performed such that the charge difference ΔQS between the third capacitor C3 and the third capacitor C3 becomes zero.

  The counter 26 counts the input clock signal CLK.

  The second digital value generation unit 27 acquires the count value of the counter 26 according to the timing indicated by the output signal B2 of the second comparator 24, and generates the output digital value Do based on the acquired count value.

  FIG. 9 is a graph illustrating an example of a temporal change in the output signal Vo of the signal synthesis unit 10B in the A / D converter according to the present embodiment. In FIG. 9, “L1” indicates that the input analog signal Vi is relatively small, “L3” indicates that the input analog signal Vi is relatively large, and “L2” indicates that the input analog signal Vi is medium. Show.

  In the A / D converter according to the present embodiment, first, the first discharge circuit 13 discharges the charges of the third capacitor C3 and the fourth capacitor C4 to the initial value (zero), respectively. After the first discharge circuit 13 stops the discharge operation, the three square wave multipliers (UA1 to UA3) periodically repeat the charging operation and the charge output operation described above for a certain period Ts. As a result, the charge difference ΔQS between the third capacitor C3 and the fourth capacitor C4 increases, so that the output signal Vo of the signal synthesis unit 10B also increases as shown in FIG. In the example of FIG. 9, the output signal Vo increases to the positive side. However, when the input analog signal Vi has a negative polarity, the output signal Vo increases to the negative side.

  The three square wave multipliers (UA1 to UA3) repeat the electric operation and the charge output operation for a predetermined period Ts, and then stop the charging operation and the charge output operation. The second discharge circuit 25 has charges accumulated in the third capacitor C3 and the fourth capacitor C4 of the signal synthesis unit 10B in a state where the three square wave multiplication units (UA1 to UA3) stop the charging operation and the charge output operation. Is discharged at a constant current. When the discharge operation of the second discharge circuit 25 starts, the output signal Vo of the signal synthesizer 10B decreases at a constant speed as shown in FIG.

  When the charge difference ΔQS between the third capacitor C3 and the third capacitor C3 becomes zero by the discharge operation of the second discharge circuit 25 and the output signal Vo of the signal synthesis unit 10B also becomes zero, the output signal B2 of the second comparator 24 becomes It changes from “1” to “0”. The second digital value generation unit 27 starts from the time ts when the discharge by the second discharge circuit 25 starts to the times t1, t2, and t3 when the output signal B2 of the second comparator 24 changes from “1” to “0”. The count value of the counter 26 during the period is acquired. For example, the second digital value generation unit 27 resets the count value of the counter 26 to zero before the time ts, and starts the counting operation of the counter 26 at the time ts. Then, the count value of the counter 26 is acquired at the time when the output signal B2 of the second comparator 24 changes from “1” to “0” or from “0” to “1”.

  As shown in FIG. 9, the elapsed time from the start time ts of discharge by the second discharge circuit 25 to the time t1, t2, t3 when the output signal B2 of the second comparator 24 changes from “1” to “0”. T1, T2, and T3 are proportional to the magnitude of the signal Vo at time ts, and the magnitude of the signal Vo is proportional to the input analog signal Vi. The count value of the counter 26 corresponding to the elapsed time T1, T2, T3 has a value proportional to the input analog signal Vi. Accordingly, the second digital value generation unit 27 can acquire the output digital value Do corresponding to the input analog signal Vi based on the count value of the counter 26 corresponding to the elapsed times T1, T2, and T3.

  The A / D converter according to the present embodiment described above can achieve the same effects as those of the A / D converter according to the first and second embodiments.

<Fourth Embodiment>
Next, as a fourth embodiment of the present invention, an example of an A / D converter using a pipeline type conversion method will be described.

  FIG. 10 is a diagram illustrating an example of a configuration of an A / D converter according to the fourth embodiment. The A / D converter shown in FIG. 10 obtains an output digital value Do based on a sine wave multiplier 30 that multiplies an input analog signal Vi by a sine wave, and a signal V1 that is input from the sine wave multiplier 30 as a multiplication result. And a digital value acquisition unit 20C.

  In the example of FIG. 10, the digital value acquisition unit 20C includes n stages of cascade-connected pipeline stages PS1, PS2,..., PSn and partial digital values PD1 output from the pipeline stages PS1, PS2,. , PD2,..., PDn, a third digital value generator 28 that generates an output digital value Do is included.

  The pipeline stages PS1, PS2,..., PSn receive the multiplication result signal V1 of the sine wave multiplication unit 30 in the first pipeline stage PS1, and are output from the previous stage in the second and subsequent pipeline stages PS2 to PSn. Input signals (V2 to Vn).

  The pipeline stage PSi (i indicates an integer from 1 to n) outputs a partial digital value PDi corresponding to the level of the input signal Vi. For example, the pipeline stage PSi compares a threshold value set to half the full scale with the signal Vi and outputs a 1-bit partial digital value PDi corresponding to the comparison result. The pipeline stage PSi samples the signal Vi in synchronization with the charge output operation of the square wave multipliers (UA1 to UA3) included in the sine wave multiplier 30 described later, and amplifies the sampled signal Vi by a predetermined amplification. Amplify at a rate (eg, 2x). The pipeline stage PSi subtracts a reference signal (for example, either half of full scale or zero) selected based on the partial digital value PDi from the signal of the amplification result, and the signal of the subtraction result is the subsequent stage (pipe). Output to line stage PSi + 1).

  The pipeline stage PSi performs the above signal processing by, for example, a differential switched capacitor circuit.

  FIG. 11 is a diagram illustrating an example of the configuration of the sine wave multiplication unit 30 in the A / D converter illustrated in FIG. 10. The sine wave multiplier 30 shown in FIG. 11 includes a first input terminal Ti1 and a second input terminal Ti2 to which an input analog signal Vi is input, a first square wave multiplier UC1, and second square wave multipliers UA2 and UA3. A first common node N1 and a second common node N2, and a signal synthesis unit 10C. Among these, the first input terminal Ti1 and the second input terminal Ti2, the second square wave multipliers UA2 and UA3, the first common node N1 and the second common node N2 are components having the same reference numerals already described in FIG. Is the same.

  The first square wave multiplier UC1 is obtained by omitting the third switch circuit 33 in the first square wave multiplier UA1 (FIG. 5), and the other configuration is the same as that of the first square wave multiplier UA1.

  The signal synthesizer 10C generates a signal corresponding to the sum of charges output by the charge output operation from the three square wave multipliers (UC1, UA2, UA3) every time the charge output operation is performed. For example, the signal synthesis unit 10C includes a third capacitor and a fourth capacitor having the same capacitance, and the first common node N1 is generated by the charge output operation from the three square wave multiplication units (UC1, UA2, UA3). Is stored in the third capacitor C3, and the charge output from the three square wave multipliers (UC1, UA2, UA3) to the second common node N2 by the charge output operation is stored in the fourth capacitor C4. . The signal synthesis unit 10C outputs a signal V1 corresponding to the difference (charge difference ΔQS) between the charge of the third capacitor C3 and the charge of the fourth capacitor C4. Further, the signal combining unit 10C outputs the signal V1 and outputs the third capacitor C3 and the fourth capacitor C4 before the next charge output operation is performed in the three square wave multiplication units (UC1, UA2, UA3). Discharge the charge.

  The signal synthesizer 10C shown in FIG. 11 is the same as the signal synthesizer 10B shown in FIG. 8 except for the fourth switch circuit 12 in the signal synthesizer 10B shown in FIG.

  FIG. 12 is a timing chart showing the state of each switch element in the sine wave multiplication unit 30 shown in FIG.

  As shown in FIG. 12, during the charging operation, the third capacitor C3 and the fourth capacitor C4 are short-circuited by the discharge circuit 13 (switch elements S15 and S16 are turned on). Therefore, due to the negative feedback operation of the operational amplifier 11, the potentials of the first common node N1 and the second common node N2 become substantially equal. When the potential of the first common node N1 and the second common node N2 is a common potential, a voltage generated between one of the first input terminal Ti1 and the second input terminal Ti2 and the common potential is applied to the first capacitor C1. A voltage generated between the other of the first input terminal Ti1 and the second input terminal Ti2 and the common potential is applied to the second capacitor C2.

  In the charge output operation, as shown in FIG. 12, the short circuit of the third capacitor C3 and the fourth capacitor C4 by the discharge circuit 13 is released (the switch elements S15 and S16 are off), and the switch element of the second switch circuit 32 S5 turns on. In this case, the charge difference accumulated in the first capacitor C1 and the second capacitor C2 is transferred to the third capacitor C3 and the fourth capacitor C4 via the first common node N1 and the first common node N1. The charge differences (ΔQ1, ΔQ2, ΔQ2) transferred from the three square wave multipliers (UC1, UA2, UA3) to the third capacitor C3 and the fourth capacitor C4 by the power output operation are expressed by equations (5) and (6), respectively. ), (7). The charge difference ΔQS between the third capacitor C3 and the fourth capacitor C4 is expressed as the sum of these charge differences (ΔQS = ΔQ1 + ΔQ2 + ΔQ3).

  Since the capacitances of the third capacitor C3 and the fourth capacitor C4 are equal, the output signal Vo of the operational amplifier 11 is proportional to the charge difference ΔQS between the third capacitor C3 and the fourth capacitor C4. Further, since the charge difference ΔQS is the sum of the charge differences ΔQ1, ΔQ2, and ΔQ3, the charge difference ΔQS is proportional to the input signal Vi from the relationships of the equations (5) to (7). Therefore, the output signal Vo of the operational amplifier 11 increases or decreases in proportion to the input signal Vi.

  Further, from the relationship of the equations (2) and (3), the harmonic component (third harmonic and fifth harmonic) of the charge difference ΔQ1 included in the charge difference ΔQS is removed. Therefore, in the output signal Vo of the operational amplifier 11, the signal component corresponding to the product of the input signal Vi and the sine wave (frequency fs) becomes dominant, and the product of the input signal Vi and the harmonics (frequency 3fs, 5fs). The signal component corresponding to is reduced.

  The first discharge circuit 13 of the signal synthesis unit 10C short-circuits the third capacitor C3 and the fourth capacitor C4 during the charging operation (switch elements S15 and S16 are turned on). Therefore, the charge difference ΔQS between the third capacitor C3 and the fourth capacitor C4 is updated each time the charge output operation is performed. That is, the signal synthesis unit 10C holds the charge difference ΔQS corresponding to the multiplication result of the input analog signal Vi and the sine wave every time the charge output operation is performed, and outputs the signal V1 corresponding to the charge difference ΔQS. Therefore, the sine wave multiplication unit 30 also has a function as a sample hold circuit that samples and holds the input analog signal Vi for each period T.

  Also in the A / D converter according to the present embodiment described above, the result of multiplication of the input analog signal Vi and the sine wave by adding the outputs of the square wave multiplication units (UA1 to UA3) in the sine wave multiplication unit 30. Is obtained. Therefore, the same effect as the A / D converter according to the first to third embodiments can be obtained.

<Fifth Embodiment>
Next, another example of the A / D converter using a pipeline type conversion system will be described as a fifth embodiment of the present invention.

  The A / D converter according to this embodiment is obtained by changing the sine wave multiplication unit 30 in the A / D converter shown in FIG. 10 to a sine wave multiplication unit 30D, and the other configuration is the A / D converter shown in FIG. It is the same as the D converter.

  FIG. 13 is a diagram illustrating an example of the configuration of the sine wave multiplication unit 30D in the A / D converter according to the present embodiment. The sine wave multiplication unit 30D shown in FIG. 13 includes a first input terminal Ti1 and a second input terminal Ti2 to which an input analog signal Vi is input, and a first square wave multiplication that multiplies the input analog signal Vi by a first square wave W1. Unit UD1, second square wave multipliers UD2 and UD3 for multiplying input analog signal Vi by second square waves W2 and W3, first common node N1 and second common node N2, third common node N3 and 4 common nodes N4, and a signal synthesis unit 10D that synthesizes signals resulting from multiplication of the first square wave multiplication unit UD1 and the second square wave multiplication units UD2 and UD3. In the following description, the first square wave multiplication unit UD1 and the second square wave multiplication units UD2 and UD3 may be referred to as “square wave multiplication unit UD” without distinction.

  The square wave multiplication unit UD has two capacitors (first capacitor C1 and second capacitor C2) having the same capacitance, and, like the already described square wave multiplication unit UA, charging operation and charge output The operation is repeated alternately at regular intervals. In the charging operation, the square wave multiplication unit UD accumulates charges corresponding to the input analog signal Vi in the capacitors (C1, C2). For example, in the charging operation, the square wave multiplier UD applies a voltage generated between one of the first input terminal Ti1 and the second input terminal Ti2 and the first common node N1 to the first capacitor C1, and A voltage generated between the other of the first input terminal Ti1 and the second input terminal Ti2 and the second common node N2 is applied to the second capacitor C2.

  In the charge output operation, the square wave multiplication unit UD outputs the charge accumulated in the capacitors (C1, C2) by the charging operation to the signal synthesis unit 10D. For example, the square wave multiplier UD connects the first capacitor C1 between the first common node N1 and the third common node N3, and connects the second capacitor C2 to the second common node N2 and the fourth common node N4. Connect between.

  Further, the square wave multiplication unit UD has a relationship between the polarity of the input analog signal Vi during the charging operation and the polarity of the difference between the charges output from the two capacitors (C1, C2) to the signal combining unit 10D during the charge output operation. Inverted between one half period and the other half period in one period of the square wave. For example, the square wave multiplication unit UD has a polarity of the input analog signal Vi during the charging operation and a polarity of the charge difference obtained by subtracting the charge accumulated in the second capacitor C2 from the charge accumulated in the first capacitor C1 during the charging operation. Is inverted between one half period and the other half period in one period of the square wave.

  In the example of FIG. 13, the square wave multiplication unit UD includes a first capacitor C1 and a second capacitor C2 having the same capacitance, a first switch circuit 31, a seventh switch circuit 34, and an eighth switch circuit 35. . Among these, the first capacitor C1, the second capacitor C2, and the first switch circuit 31 are the same as the components having the same reference numerals in FIG.

  The seventh switch circuit 34 is provided in a path between the other terminal of the first capacitor C1 and the third common node N3, and is turned off in the charging operation of the square wave multiplier UD and turned on in the charge output operation. In the example of FIG. 13, the seventh switch circuit 34 has a switch element S19 connected between the other terminal of the first capacitor C1 and the third common node N3.

  The eighth switch circuit 35 is provided in a path between the other terminal of the second capacitor C2 and the fourth common node N4, and is turned off in the charging operation of the square wave multiplier UD and turned on in the charge output operation. In the example of FIG. 13, the eighth switch circuit 35 includes a switch element S20 connected between the other terminal of the second capacitor C2 and the fourth common node N4.

  The second square wave multiplication units UD2 and UD3 have the same configuration as the first square wave multiplication unit UD1. However, the capacitances of the first capacitor C1 and the second capacitor C2 in the first square wave multiplier UD1 and the second square wave multipliers UD2 and UD3 are the square wave multipliers (UA1 to UA3) in FIG. Similarly, the harmonics of the first square wave W1 and the fundamental waves of the second square waves W2, W3 are set to have the same amplitude.

That is, the capacitance of the capacitors (C1, C2) in the second square wave multiplication unit UD2 is set to 1/3 of the capacitance of the capacitors (C1, C2) in the first square wave multiplication unit UD1. . The ratio of the capacitances is that the amplitude of the fundamental wave of the first square wave W1 and the amplitude of the third harmonic of the first square wave W1 having the same frequency (3 fs) as the fundamental wave of the second square wave W2. The ratio is the same. The capacitance of the capacitors (C1, C2) in the second square wave multiplication unit UD3 is set to 1/5 of the capacitance of the capacitors (C1, C2) in the first square wave multiplication unit UD1. . The ratio of the capacitances is that the amplitude of the fundamental wave of the first square wave W1 and the amplitude of the fifth harmonic of the first square wave W1 having the same frequency (5 fs) as the fundamental wave of the second square wave W3. The ratio is the same.
The capacitances of the first capacitor C1 and the second capacitor C2 in the first square wave multiplication unit UD1 are “Cu1”, and the capacitances of the first capacitor C1 and the second capacitor C2 in the second square wave multiplication unit UD2 are “Cu2”. ”, When the capacitances of the first capacitor C1 and the second capacitor C2 in the second square wave multiplication unit UD3 are“ Cu3 ”, these capacitances are equal to the relationship shown in the equation (1) already described. .

A charge difference that is a value obtained by subtracting the charge accumulated in the second capacitor C2 from the charge accumulated in the first capacitor C1 of the first square wave multiplier UD1 during the charging operation is defined as “ΔQ1D”. Therefore, a component corresponding to the product of the third harmonic (frequency 3fs) of the first square wave W1 and the input analog signal Vi is denoted as “ΔQ1D (3fs)”. In the charge difference ΔQ1D, a component corresponding to the product of the fifth harmonic (frequency 5fs) of the first square wave W1 and the input analog signal Vi is referred to as “ΔQ1D (5fs)”.
On the other hand, a charge difference that is a value obtained by subtracting the charge accumulated in the second capacitor C2 from the charge accumulated in the first capacitor C1 of the second square wave multiplier UD2 during the charging operation is defined as “ΔQ2D”, and this charge difference ΔQ2D The component corresponding to the product of the fundamental wave (frequency 3fs) of the second square wave W2 and the input analog signal Vi is denoted as “ΔQ2D (3fs)”.
Further, a charge difference that is a value obtained by subtracting the charge accumulated in the second capacitor C2 from the charge accumulated in the first capacitor C1 of the second square wave multiplier UD3 during the charging operation is defined as “ΔQ3D”, and this charge difference ΔQ3D The component corresponding to the product of the fundamental wave (frequency 5 fs) of the second square wave W3 and the input analog signal Vi is denoted as “ΔQ2D (3fs)”.
By setting the capacitances of the capacitors (C1, C2) of each square wave multiplier as shown in Expression (1), the following relationship is established for the above-described charge difference components.

ΔQ1D (3fs) = − ΔQ2D (3fs) (9)
ΔQ1D (5fs) = − ΔQ3D (5fs) (10)

  However, the phase relationship between the first square wave W1 and the second square wave W2 is set so that the third harmonic of the first square wave W1 and the fundamental wave of the second square wave W2 are in opposite phases. . The phase relationship between the first square wave W1 and the second square wave W3 is set so that the fifth harmonic of the first square wave W1 and the fundamental wave of the second square wave W3 are in reverse phase.

  Since the relationships of Expressions (9) and (10) are established, the charge difference ΔQ1D, ΔQ2D, ΔQ3D during the charging operation is combined (added) by the signal combining unit 10D during the charge output operation, whereby the first square wave The component ΔQ1D (3fs) corresponding to the product of the third harmonic of W1 and the input analog signal Vi is obtained by the component ΔQ2D (3fs) corresponding to the product of the fundamental wave of the second square wave W2 and the input analog signal Vi. Offset. Further, the component ΔQ1D (5fs) corresponding to the product of the fifth harmonic of the first square wave W1 and the input analog signal Vi corresponds to the product of the fundamental wave of the second square wave W3 and the input analog signal Vi. It is canceled out by the component ΔQ3D (5fs). That is, the signal components resulting from the third harmonic and the fifth harmonic of the first square wave W1 are removed by addition with the signal components output from the second square wave multipliers UD2 and UD3.

  The signal synthesis unit 10D adjusts the voltage of the third common node N3 and the voltage of the fourth common node N4 so that the voltage of the first common node N1 and the voltage of the second common node N2 are equal. The signal synthesizer 10D determines the voltage difference between the third common node N3 and the fourth common node N4 according to the sum of charges output from the three square wave multipliers (UD1 to UD3) by the charge output operation. Output as V1.

In the example of FIG. 13, the signal synthesis unit 10 </ b> D includes an operational amplifier 11, a ninth switch circuit 14, and a tenth switch circuit 15.
The operational amplifier 11 amplifies the voltage difference between the inverting input terminal connected to the first common node N1 and the non-inverting input terminal connected to the second common node N2, and the amplification result is supplied to the third common node N3. A voltage difference between the connected non-inverting output terminal and the inverting output terminal connected to the fourth common node N4, that is, a signal V1 is output.

  The ninth switch circuit 14 is provided in a path between the inverting input terminal and the non-inverting output terminal of the operational amplifier 11, and is turned on in the charging operation of the square wave multiplication unit UD and turned off in the charge output operation. For example, as shown in FIG. 13, the ninth switch circuit 14 includes a switch element S21 connected between the inverting input terminal and the non-inverting output terminal of the operational amplifier 11.

  The tenth switch circuit 15 is provided in a path between the non-inverting input terminal and the inverting output terminal of the operational amplifier 11, and is turned on in the charging operation of the square wave multiplication unit UD and turned off in the charge output operation. For example, as shown in FIG. 13, the tenth switch circuit 15 includes a switch element S22 connected between the non-inverting input terminal and the inverting output terminal of the operational amplifier 11.

  Here, the operation of the sine wave multiplier 30D having the above-described configuration will be described.

  FIG. 14 is a diagram for explaining the state of each switch element during the charging operation and the charge output operation of the sine wave multiplication unit 30D shown in FIG. FIG. 14A shows the state of the switch element during the charging operation, and FIG. 14B shows the state of the switch element during the charge output operation.

  Although only the first square wave multiplier UD1 is shown in the example of FIG. 14, the second square wave multipliers UD2 and UD3 are also in the same switch state in the charging operation and the charge output operation.

  During the charging operation, as shown in FIG. 14A, the first capacitor C1 is connected between the first input terminal Ti1 and the first common node N1, and the second capacitor C2 is connected between the second input terminal Ti2 and the first common node N1. Connected between. At this time, since the ninth switch circuit 14 and the tenth switch circuit 15 are turned on, the voltages of the first common node N1 and the second common node N2 become substantially equal due to the negative feedback operation of the operational amplifier 11.

  The voltage obtained by subtracting the voltage of the second input terminal Ti2 from the voltage of the first input terminal Ti1 is “Vi”, and the capacitances of the first capacitor C1 and the second capacitor C2 are “C”. In this case, the charge difference ΔQ1D between the first capacitor C1 and the second capacitor C2 of the first square wave multiplier UD1 and the charge difference ΔQ2D between the first capacitor C1 and the second capacitor C2 of the second square wave multiplier UD2 during the charging operation. The charge difference ΔQ3D between the first capacitor C1 and the second capacitor C2 of the second square wave multiplier UD3 is expressed by the following equations, respectively.

ΔQ1D = ± Vi × C (11)
ΔQ2D = ± Vi × (C / 3) (12)
ΔQ3D = ± Vi × (C / 5) (13)

  The positive and negative polarities shown on the right side of Expression (11) are switched between one half cycle and the other half cycle of the first square wave W1 (frequency fs). The positive and negative polarities shown on the right side of Expression (12) are switched between one half cycle and the other half cycle of the second square wave W2 (frequency 3fs). Further, the positive and negative polarities shown on the right side of the equation (13) are switched between one half cycle and the other half cycle of the second square wave W3 (frequency 5 fs).

  During the charge output operation, as shown in FIG. 14B, the other terminal of the first capacitor C1 is connected to the third common node N3. Accordingly, the first capacitor C1 of the first square wave multiplication unit UD1 is connected to the first common node N1 together with the first capacitor C1 of the second square wave multiplication unit UD2 and the first capacitor C1 of the second square wave multiplication unit UD3. The third common node N3 is connected in parallel. The charges accumulated in the first capacitors C1 of the three square wave multipliers (UD1 to UD3) during the charging operation are directly combined by connecting the first capacitors C1 in parallel during the charge output operation.

  During the charge output operation, as shown in FIG. 14B, the other terminal of the second capacitor C2 is connected to the fourth common node N4. Accordingly, the second capacitor C2 of the first square wave multiplication unit UD1 is connected to the second common node N2 together with the second capacitor C2 of the second square wave multiplication unit UD2 and the second capacitor C2 of the second square wave multiplication unit UD3. The fourth common node N4 is connected in parallel. The charges accumulated in the second capacitors C2 of the three square wave multipliers (UD1 to UD3) during the charging operation are directly combined by connecting the second capacitors C2 in parallel during the charge output operation.

  In the charge output operation, a charge difference is a value obtained by subtracting the total charge synthesized by connecting the three second capacitors C2 in parallel from the total charge synthesized by connecting the three first capacitors C1 in parallel. Is represented by “ΔQSD”, the charge difference ΔQSD is expressed by the following equation.

  ΔQSD = ΔQ1D + ΔQ2D + ΔQ3D (14)

  Since the combined capacitance of the three first capacitors C1 connected in parallel in the charge output operation and the combined capacitance of the three second capacitors C2 are substantially equal, the signal V1 output from the operational amplifier 11 has a charge difference. It is proportional to ΔQSD. Further, as shown in the equation (14), the charge difference ΔQSD is the sum of the charge differences ΔQ1D, ΔQ2D, and ΔQ3D, and therefore the charge difference ΔQSD is proportional to the input analog signal Vi from the relationship of the equations (11) to (13). To do. Therefore, the output signal Vo of the operational amplifier 11 increases or decreases in proportion to the input signal Vi.

  Furthermore, from the relationship of the expressions (9) and (10), the harmonic component (third harmonic and fifth harmonic) of the charge difference ΔQ1D included in the charge difference ΔQSD is removed. Therefore, in the signal V1 output from the operational amplifier 11, the signal component corresponding to the product of the input analog signal Vi and the sine wave (frequency fs) becomes dominant, and the input analog signal Vi and the harmonics (frequency 3fs, 5fs). ) And the signal component corresponding to the product.

  FIG. 15 is a timing chart showing the state of each switch element in sine wave multiplier 30D shown in FIG.

  In the example of FIG. 15, as in the example of FIG. 7, the charging operation and the charge output operation of the square wave multiplication unit UD are performed once every period T. One period (1 / fs) of the first square wave W1 is set to 60 cycles (60T) of the period T, and one period (1/3 fs) of the second square wave W2 is set to 20 cycles (20T of the period T). ) And one period (1/5 fs) of the second square wave W3 is set to 12 cycles (12T) of the period T. The switching patterns of the switch elements (S1 to S4) of the first switch circuit 31 in the square wave multiplier UD are the same as the switching patterns of the switch elements (S1 to S4) of the square wave multiplier UA shown in FIGS. It is.

  As shown in FIG. 15, the switch elements (S21, S22) of the ninth switch circuit 14 and the tenth switch circuit 15 are turned on during the charging operation and turned off during the charge output operation. The switch elements (S19, S20) of the seventh switch circuit 34 and the eighth switch circuit 35 are turned off during the charging operation and turned on during the charge output operation. As a result, the three square wave multipliers (UD1 to UD3) sample the charge difference (ΔQ1D, ΔQ2D, ΔQ3D) proportional to the input analog signal Vi every time the charging operation is performed, and the signal synthesis unit 10D The charge differences (ΔQ1D, ΔQ2D, ΔQ3D) of the square wave multipliers (UD1 to UD3) are combined and held each time the charge output operation is performed. Therefore, the sine wave multiplication unit 30D also has a function as a sample hold circuit that samples and holds the input analog signal Vi for each period T.

  Also in the A / D converter according to the present embodiment described above, the result of multiplication of the input analog signal Vi and the sine wave by adding the outputs of the square wave multiplication units (UD1 to UD3) in the sine wave multiplication unit 30D. Is obtained. Therefore, the same effect as the A / D converter according to the first to fourth embodiments can be obtained.

  Further, according to the A / D converter according to the present embodiment, the capacitors (C1, C2) of the respective square wave multipliers UD are connected in parallel in the signal synthesizer 10D, so that the electric charges accumulated in these capacitors are reduced. Since they are synthesized directly, the charge / discharge current of the capacitors (C1, C2) by the operational amplifier 11 hardly flows. That is, the current driving speed in the operational amplifier 11 does not significantly affect the charge synthesis in the signal synthesis unit 10D. As a result, charge synthesis can be performed at high speed in the signal synthesis unit 10D without being limited by the speed of the operational amplifier 11, and thus the speed of A / D conversion can be increased.

  As mentioned above, although several embodiment of this invention was described, this invention is not limited only to these embodiment, Furthermore, a various variation is included.

  In the A / D converter according to each of the embodiments described above, since the input analog signal Vi is discretely processed in the square wave multipliers (U1 to U3, UA1 to UA3, UD1 to UD3), the output of the square wave multiplier is provided. May cause aliasing noise. Therefore, a low-pass filter that attenuates high-frequency components may be provided on the input side of the A / D converter according to each of the embodiments described above. FIG. 16 shows a modification in which a first low-pass filter 40 is provided on the input side of the A / D converter shown in FIG.

  The first low-pass filter 40 is for reducing aliasing noise due to discrete processing of the input analog signal Vi, and attenuates the high-frequency component of the input analog signal Vi input to the square wave multiplication unit. That is, the first low-pass filter 40 is a noise component included in the input analog signal Vi, and a signal band of the input analog signal Vi from a frequency that is an integral multiple of the frequency (1 / T) at which the charging operation is repeated. Noise components that may cause aliasing noise are attenuated. As a result, even when the input analog signal Vi includes noise having a relatively high frequency, aliasing noise in the signal band of the input analog signal Vi can be prevented and highly accurate multiplication processing can be performed.

  In the A / D converters according to the above-described embodiments, the outputs of the square wave multipliers (U1 to U3, UA1 to UA3, UD1 to UD3) are combined to generate the third order of the first square wave W1. A component (harmonic × input analog signal Vi) due to the harmonic and the fifth harmonic is canceled out. However, since there are other harmonics that are not canceled out in the first square wave W1, if the input analog signal Vi includes noise having a high frequency, the components resulting from those harmonics are converted into the signal synthesis unit ( 10, 10A, 10D). In particular, the seventh harmonic having the next largest amplitude after the fifth harmonic may affect the accuracy of the multiplication result.

  In addition, as shown in FIG. 3, the second square waves W2 and W3 (FIGS. 3B and 3C) are not only the fundamental wave, but also their harmonics are some harmonics of the first square wave W1 (FIG. 3A). Is equal to In the example of FIG. 3, the third and fifth harmonics of the second square wave W2 are equal to the ninth and fifteenth harmonics of the first square wave W1. Further, the third harmonic of the second square wave W3 is equal to the fifteenth harmonic of the first square wave W1. Accordingly, the 15th harmonic of the first square wave W1 is subtracted by both the second square wave W2 and the second square wave W3, which causes an error.

  The first low-pass filter 40 attenuates the high-frequency component of the input analog signal Vi before inputting it to the square wave multipliers (U1 to U3, UA1 to U3, UD1 to UD3), so that the harmonics and the input signal Vi described above are attenuated. The influence of the error due to the product of can be reduced. Since the lowest harmonic that may affect the accuracy is the seventh harmonic (frequency 7 fs) of the first square wave W1, the frequency characteristic of the first low-pass filter 30 is, for example, a frequency higher than the frequency 7 fs. It is set so that the component attenuates to the extent that it does not affect the multiplication accuracy.

  In the A / D converter according to the present embodiment, an output digital value Do corresponding to the multiplication result of the input analog signal Vi and the sine wave (frequency fs) is obtained. Therefore, when the input analog signal Vi has a signal component having the frequency fs, the output digital value Do has a DC component proportional to the amplitude of the signal component and a frequency (2fs) twice that of the sine wave. Ingredients included. Therefore, when an A / D converter is used as a circuit (narrowband bandpass filter circuit) that extracts only the signal component of the frequency fs included in the input analog signal Vi, the frequency (2fs) that is twice the sine wave is used. It is desirable to provide a low-pass filter that can remove the components and extract the DC component. FIG. 17 shows a modification in which the A / D converter shown in FIG. 16 is provided with a second low-pass filter 50 for extracting the DC component DoA included in the output digital value Do. The second low-pass filter 50 may be configured by a digital filter that further discretely processes the output digital value Do, or the digital value acquisition unit 20 has a function of a low-pass filter so as to extract the DC component DoA. Also good.

  In the A / D converter shown in FIG. 4, the phase of the fundamental wave of the second square waves W2 and W3 multiplied by the input analog signal Vi in the second square wave multipliers U2 and U3 is changed to the harmonic of the first square wave W1. Although reversed with respect to phase, the present invention is not limited to this example. In another embodiment of the present invention, for example, as shown in FIG. 18, the phase of the fundamental waves of the second square waves W2, W3 multiplied by the input analog signal Vi in the second square wave multipliers U2, U3 is set to the first square wave. You may make it become the same phase as the phase of the harmonic in wave W1. In this case, the signal combining unit 10 combines the signals so as to subtract the output signals Qu2 and Qu3 of the second square wave multipliers U2 and U3 from the output signal Qu1 of the first square wave multiplier U1. As in the A / D converter shown in FIG.

  In the embodiment described above, the signal components corresponding to the third harmonic and the fifth harmonic in the first square wave W1 are canceled by the signal components corresponding to the fundamental waves of the second square waves W2 and W3. The present invention is not limited to this example. In another embodiment of the present invention, the number of square wave multipliers may be three or more so that signal components corresponding to higher harmonics can be canceled.

  In the second to fifth embodiments described above, the input analog signal Vi is a differential signal, and the charge difference corresponding to the differential signal is added in the signal synthesis unit (10A to 10D). The present invention is not limited to this. In another embodiment of the present invention, a single-ended signal based on the ground may be input as an input analog signal, and charges corresponding to the input analog signal may be added in the signal synthesis unit. In this case, the square wave multiplication unit determines the relationship between the polarity of the input analog signal during the charging operation and the polarity of the charge output from the capacitor to the signal synthesis unit during the charge output operation, as one half cycle in one cycle of the square wave. And the other half cycle, the multiplication process of the input analog signal and the square wave may be performed.

  In the above-described embodiment, square wave multiplication processing and multiplication result synthesis processing are performed by analog circuits. However, in other embodiments of the present invention, these signal processing may be performed by digital signal processing.

DESCRIPTION OF SYMBOLS 10, 10A, 10B, 10C, 10D ... Signal synthesis | combination part, 11 ... Operational amplifier, 12 ... 4th switch circuit, 13 ... 1st discharge circuit, 14 ... 9th switch circuit, 15 ... 10th switch circuit, 20, 20A , 20B, 20C ... digital value acquisition unit, 21 ... first comparison unit, 22 ... charge generation unit, 221 ... fifth switch circuit, 222 ... voltage supply circuit, 23 ... first digital value generation unit, 24 ... second comparison 25 ... second discharge circuit, 251 ... sixth switch circuit, 26 ... counter, 27 ... second digital value generation unit, 28 ... third digital value generation unit, 30, 30D ... sine wave multiplication unit, 31 ... first DESCRIPTION OF SYMBOLS 1 switch circuit, 32 ... 2nd switch circuit, 33 ... 3rd switch circuit, 34 ... 7th switch circuit, 35 ... 8th switch circuit, 40 ... 1st low-pass filter, 50 ... 2nd low-pass filter, U1 U3, UA1 to UA3, UD1 to UD3 ... square wave multiplier, C1 ... first capacitor, C2 ... second capacitor, C3 ... third capacitor, C4 ... fourth capacitor, C5 ... fifth capacitor, C6 ... sixth capacitor , PS1 to PSn ... pipeline stage, S1 to S22 ... switch element, R1 ... first resistor, R2 ... second resistor, Ti1 ... first input terminal, Ti2 ... second input terminal, N1 ... first common node, N2 ... second common node, N3 ... third common node, N4 ... fourth common node, Vi ... input analog signal, Do ... output digital value, PD ... partial digital value, Vref ... reference potential

Claims (20)

An analog-to-digital converter that multiplies an input analog signal by a sine wave of a predetermined frequency and converts the signal of the multiplication result into an output digital value,
A plurality of square wave multipliers for multiplying the input analog signal by square waves of different frequencies,
A signal synthesis unit for synthesizing signals of multiplication results in the plurality of square wave multiplication units;
A digital value acquisition unit that acquires the output digital value based on a signal indicating a synthesis result of the signal synthesis unit;
The square wave can be approximated as the sum of a fundamental wave that is the lowest sine wave and a plurality of harmonics that are sine waves each having an integer multiple of the fundamental wave,
The plurality of square wave multiplication units include one first square wave multiplication unit and one or more second square wave multiplication units,
The first square wave multiplication unit multiplies the input analog signal by a first square wave having the sine wave of the predetermined frequency as the fundamental wave,
The second square wave multiplication unit is a second square wave having the fundamental wave as a sine wave equal to one harmonic included in the first square wave or a sine wave obtained by inverting the phase of the one harmonic. Multiplied by the input analog signal,
The signal synthesizing unit includes a signal component corresponding to a product of at least one of the harmonics of the first square wave and the input analog signal included in the signal of the multiplication result of the first square wave multiplication unit. An analog-to-digital converter characterized by canceling out with a signal component corresponding to a product of the fundamental wave of the second square wave and the input analog signal included in a signal of a multiplication result of a two-square wave multiplication unit. The square wave multiplication unit has at least one capacitor, and in each of one half cycle and the other half cycle in one cycle of the square wave to be multiplied by the input analog signal, The charging operation for accumulating the corresponding charge in the capacitor and the charge output operation for outputting the charge accumulated in the capacitor by the charging operation to the signal synthesis unit are alternately repeated at a predetermined interval, The difference between the polarity of the input analog signal and the polarity of the charge output from one capacitor to the signal synthesis unit during the charge output operation or the charge output from the two capacitors to the signal synthesis unit during the charge output operation The relationship with the polarity is inverted between the one half cycle and the other half cycle,
The signal synthesis unit synthesizes the charges output by the charge output operation from the plurality of square wave multiplication units,
2. The analog-digital conversion according to claim 1, wherein the digital value acquisition unit acquires the output digital value based on charges from the plurality of square wave multiplication units synthesized in the signal synthesis unit. vessel. The capacitance of the capacitor in which the first square wave multiplication unit accumulates electric charge in the charging operation, and the capacitance of the capacitor in which one second square wave multiplication unit accumulates electric charge in the charging operation. The ratio of the amplitude of the fundamental wave of the first square wave to the amplitude of the harmonic wave of the first square wave having a frequency equal to the fundamental wave of the second square wave in the one second square wave multiplication unit. The analog-digital converter according to claim 2, wherein the analog-digital converter has a value corresponding to the ratio. The signal synthesizer has at least one capacitor for accumulating charges repeatedly output by the charge output operation from the plurality of square wave multipliers, and outputs a signal corresponding to the charges accumulated in the capacitors. ,
The digital value acquisition unit
A first comparator that compares a signal indicating a combination result of the signal combining unit with a reference value and outputs a signal indicating the comparison result;
A charge generation unit that generates a charge according to an output signal of the first comparator and outputs the charge to the signal synthesis unit at a timing synchronized with the charge output operation of the plurality of square wave multiplication units;
4. The analog-digital converter according to claim 2, further comprising a first digital value generation unit that generates the output digital value based on an output signal of the first comparator. 5. A first input terminal and a second input terminal to which a differential signal is input as the input analog signal;
A first common node and a second common node to which the plurality of square wave multiplication units are connected in common;
The square wave multiplication unit includes a first capacitor and a second capacitor having the same capacitance. In the charging operation, one of the first input terminal and the second input terminal and a common potential And a voltage generated between the other of the first input terminal and the second input terminal and the common potential is applied to the second capacitor, and the charge output operation is performed. , The charge accumulated in one of the first capacitor and the second capacitor is output to the first common node, and the charge accumulated in the other of the first capacitor and the second capacitor is output to the second capacitor. The second common node is output from the polarity of the input analog signal during the charging operation and the charge output to the first common node during the charge output operation. The relationship between the polarity of the charge difference by subtracting the charge to be outputted to de, reversed at the half cycle and the other half period of the one,
The signal synthesis unit includes a third capacitor and a fourth capacitor having the same capacitance, and charges output from the plurality of square wave multiplication units to the first common node by the charge output operation are described above. The charge stored in the third capacitor and output to the second common node by the charge output operation from the plurality of square wave multipliers is stored in the fourth capacitor, and the charge of the third capacitor and the fourth capacitor Outputs a signal corresponding to the difference between
The charge generation unit outputs charges to the first common node and the second common node at a timing synchronized with the charge output operation of the plurality of square wave multiplication units, and outputs the charge to the first common node. 5. The analog-digital converter according to claim 4, wherein a charge difference obtained by subtracting a charge output from the charge to the second common node is set to a value corresponding to an output signal of the first comparator. A first input terminal and a second input terminal to which a differential signal is input as the input analog signal;
A first common node and a second common node to which the plurality of square wave multiplication units are connected in common;
The square wave multiplier is
A first capacitor having one end connected to the first common node;
A second capacitor having one end connected to the second common node and having the same capacitance as the first capacitor;
In the charging operation in one half cycle of the square wave multiplied by the input analog signal, the other end of the first capacitor is connected to the first input terminal and the other end of the second capacitor. Is connected to the second input terminal, and in the charging operation of the other half cycle of the square wave, the other end of the first capacitor is connected to the second input terminal and the second input terminal is connected to the second input terminal. The other end of two capacitors is connected to the first input terminal, and in the charge output operation, the other end of the first capacitor and the other end of the second capacitor are connected to the first input terminal and the second input terminal. A first switch circuit disconnected from the input terminal;
A second switch circuit provided in a path between the other end of the first capacitor and the other end of the second capacitor, turned off in the charging operation, and turned on in the charge output operation;
A third switch circuit that connects the first common node and the second common node to the common potential in the charging operation, and disconnects the first common node and the second common node from the common potential in the charge output operation; Have
The signal synthesizer
An operational amplifier that amplifies a voltage difference between the inverting input terminal and the non-inverting input terminal and outputs the amplification result as a voltage difference between the inverting output terminal and the non-inverting output terminal;
A third capacitor provided in a path between the inverting input terminal and the non-inverting output terminal of the operational amplifier;
A fourth capacitor provided in a path between the non-inverting input terminal and the inverting output terminal of the operational amplifier and having the same capacitance as the third capacitor;
When the plurality of square wave multipliers perform the charging operation, the first common node is disconnected from the inverting input terminal of the operational amplifier and the second common node is disconnected from the non-inverting input terminal of the operational amplifier. When the plurality of square wave arithmetic units perform the charge output operation, the first common node is connected to the inverting input terminal of the operational amplifier and the second common node is connected to the non-inverting input terminal of the operational amplifier. A fourth switch circuit to be connected,
The charge generation unit outputs charges to the first common node and the second common node at a timing synchronized with the charge output operation of the plurality of square wave multiplication units, and outputs the charge to the first common node. 5. The analog-digital converter according to claim 4, wherein a charge difference obtained by subtracting a charge output from the charge to the second common node is set to a value corresponding to an output signal of the first comparator. The first comparator outputs a signal indicating a comparison between the voltage at the inverting output terminal of the operational amplifier and the voltage at the non-inverting output terminal;
The charge generator is
A fifth capacitor having one end connected to the first common node;
A sixth capacitor having one end connected to the second common node;
Provided in a path between the other end of the fifth capacitor and the other end of the sixth capacitor, and is turned off when the plurality of square wave multipliers perform the charging operation, and the plurality of square wave multipliers are A fifth switch circuit that is turned on when performing the charge output operation;
Voltages are supplied to the other end of the fifth capacitor and the other end of the sixth capacitor at a timing synchronized with the charging operation of the plurality of square wave multipliers, and according to an output signal of the first comparator The other end of the fifth capacitor is set to a voltage higher than the other end of the sixth capacitor by a predetermined voltage, or the other end of the sixth capacitor is set higher than the other end of the fifth capacitor. The analog-to-digital converter according to claim 6, further comprising: a voltage supply circuit that sets the voltage higher by the predetermined voltage. The signal synthesis unit includes at least one capacitor for accumulating charges repeatedly output by the charge output operation from the plurality of square wave multiplication units, and a first discharge circuit for discharging the charges of the capacitors. , Output a signal corresponding to the charge accumulated in the capacitor,
The digital value acquisition unit
A second comparator for outputting a signal indicating a timing at which the charge accumulated in the capacitor of the signal generation unit becomes equal to a predetermined initial value based on a comparison between a signal indicating a synthesis result of the signal synthesis unit and a reference value; When,
A second discharge circuit for discharging the electric charge accumulated in the capacitor of the signal synthesis unit with a constant current;
A counter for counting input clock signals;
A second digital value generation unit that acquires a count value of the counter and generates the output digital value based on the acquired count value;
The first discharge circuit discharges the electric charge accumulated in the capacitor of the signal synthesis unit to the initial value,
The plurality of square wave multiplication units repeat the charging operation and the charge output operation for a certain period after the discharging by the first discharging circuit,
In the second discharge circuit, after the predetermined period, the charge accumulated in the capacitor of the signal synthesis unit in the state where the plurality of square wave multiplication units stop the charging operation and the charge output operation. Discharging with current,
The second digital value generation unit receives a signal indicating a timing at which the charge accumulated in the capacitor of the signal synthesis unit becomes equal to the initial value from the time when the discharge by the second discharge circuit is started. The analog-to-digital converter according to claim 2, wherein the count value of the counter is obtained until a time point when the counter is output. A first input terminal and a second input terminal to which a differential signal is input as the input analog signal;
A first common node and a second common node to which the plurality of square wave multiplication units are connected in common;
The square wave multiplication unit includes a first capacitor and a second capacitor having the same capacitance. In the charging operation, one of the first input terminal and the second input terminal and a common potential And a voltage generated between the other of the first input terminal and the second input terminal and the common potential is applied to the second capacitor, and the charge output operation is performed. , The charge accumulated in one of the first capacitor and the second capacitor is output to the first common node, and the charge accumulated in the other of the first capacitor and the second capacitor is output to the second capacitor. The second common node is output from the polarity of the input analog signal during the charging operation and the charge output to the first common node during the charge output operation. The relationship between the polarity of the charge difference by subtracting the charge to be outputted to de, reversed at the half cycle and the other half period of the one,
The signal synthesis unit includes a third capacitor and a fourth capacitor having the same capacitance, and charges output from the plurality of square wave multiplication units to the first common node by the charge output operation are described above. Accumulating in the third capacitor, accumulating in the fourth capacitor the charge output from the plurality of square wave multipliers to the second common node by the charge output operation,
The first discharge circuit discharges the charge of the third capacitor and the charge of the fourth capacitor,
The analog-digital converter according to claim 8, wherein the second discharge circuit discharges the charge of the third capacitor and the charge of the fourth capacitor with the constant current. A first input terminal and a second input terminal to which a differential signal is input as the input analog signal;
A first common node and a second common node to which the plurality of square wave multiplication units are connected in common;
The square wave multiplier is
A first capacitor having one end connected to the first common node;
A second capacitor having one end connected to the second common node and having the same capacitance as the first capacitor;
In the charging operation in one half cycle of the square wave multiplied by the input analog signal, the other end of the first capacitor is connected to the first input terminal and the other end of the second capacitor. Is connected to the second input terminal, and in the charging operation of the other half cycle of the square wave, the other end of the first capacitor is connected to the second input terminal and the second input terminal is connected to the second input terminal. The other end of two capacitors is connected to the first input terminal, and in the charge output operation, the other end of the first capacitor and the other end of the second capacitor are connected to the first input terminal and the second input terminal. A first switch circuit disconnected from the input terminal;
A second switch circuit provided in a path between the other end of the first capacitor and the other end of the second capacitor, turned off in the charging operation, and turned on in the charge output operation;
A third switch circuit that connects the first common node and the second common node to the common potential in the charging operation, and disconnects the first common node and the second common node from the common potential in the charge output operation; Have
The signal synthesizer
An operational amplifier that amplifies a voltage difference between the inverting input terminal and the non-inverting input terminal and outputs the amplification result as a voltage difference between the inverting output terminal and the non-inverting output terminal;
A third capacitor provided in a path between the inverting input terminal and the non-inverting output terminal of the operational amplifier;
A fourth capacitor provided in a path between the non-inverting input terminal and the inverting output terminal of the operational amplifier and having the same capacitance as the third capacitor;
When the plurality of square wave multipliers perform the charging operation, the first common node is disconnected from the inverting input terminal of the operational amplifier and the second common node is disconnected from the non-inverting input terminal of the operational amplifier. When the plurality of square wave arithmetic units perform the charge output operation, the first common node is connected to the inverting input terminal of the operational amplifier and the second common node is connected to the non-inverting input terminal of the operational amplifier. A fourth switch circuit to be connected,
The first discharge circuit discharges the charge of the third capacitor and the charge of the fourth capacitor,
The analog-digital converter according to claim 8, wherein the second discharge circuit discharges the charge of the third capacitor and the charge of the fourth capacitor with the constant current. The second discharge circuit includes:
A first resistor having one end connected to the first common node;
A second resistor having one end connected to the second common node and having the same resistance value as the first resistor;
The analog-digital converter according to claim 9, further comprising: a sixth switch circuit that connects the other end of the first resistor and the other end of the second resistor to a reference potential during a discharge operation. The analog-digital converter according to any one of claims 6, 7, 10, and 11, wherein at least a part of the plurality of square wave calculation units share the third switch circuit. The signal synthesizer generates a signal corresponding to the sum of charges output by the charge output operation from the plurality of square wave multipliers for each charge output operation,
The digital value acquisition unit
The signal generated in the signal synthesis unit is input in the first stage, the signal output from the previous stage is input in the stage after the first stage, and a plurality of partial digital values corresponding to the level of the input signal are output. Subordinately connected pipeline stages;
A third digital value generation unit that generates the output digital value based on the partial digital value output from each of the plurality of pipeline stages,
The pipeline stage samples a signal input from the signal synthesizer or the preceding pipeline stage in synchronization with the charge output operation in the plurality of square wave multipliers, and the sampled signal is amplified by a predetermined amplification factor. 4. The analog-digital according to claim 2, wherein a reference signal selected based on the partial digital value is subtracted from the amplified signal and a signal resulting from the subtraction is output to a subsequent stage. converter. A first input terminal and a second input terminal to which a differential signal is input as the input analog signal;
A first common node and a second common node to which the plurality of square wave multiplication units are connected in common;
The square wave multiplication unit includes a first capacitor and a second capacitor having the same capacitance. In the charging operation, one of the first input terminal and the second input terminal and a common potential And a voltage generated between the other of the first input terminal and the second input terminal and the common potential is applied to the second capacitor, and the charge output operation is performed. , The charge accumulated in one of the first capacitor and the second capacitor is output to the first common node, and the charge accumulated in the other of the first capacitor and the second capacitor is output to the second capacitor. The second common node is output from the polarity of the input analog signal during the charging operation and the charge output to the first common node during the charge output operation. The relationship between the polarity of the charge difference by subtracting the charge to be outputted to de, reversed at the half cycle and the other half period of the one,
The signal synthesis unit includes a third capacitor and a fourth capacitor having the same capacitance, and charges output from the plurality of square wave multiplication units to the first common node by the charge output operation are described above. The charge stored in the third capacitor and output to the second common node by the charge output operation from the plurality of square wave multipliers is stored in the fourth capacitor, and the charge of the third capacitor and the fourth capacitor A signal corresponding to the difference between the charge and the third capacitor is output, and after the output of the signal, the charges of the third capacitor and the fourth capacitor are output before the next charge output operation is performed in the plurality of square wave multipliers. The analog-digital converter according to claim 13, wherein the analog-digital converter is discharged. A first input terminal and a second input terminal to which a differential signal is input as the input analog signal;
A first common node and a second common node to which the plurality of square wave multiplication units are connected in common;
The square wave multiplier is
A first capacitor having one end connected to the first common node;
A second capacitor having one end connected to the second common node and having the same capacitance as the first capacitor;
In the charging operation in one half cycle of the square wave multiplied by the input analog signal, the other end of the first capacitor is connected to the first input terminal and the other end of the second capacitor. Is connected to the second input terminal, and in the charging operation of the other half cycle of the square wave, the other end of the first capacitor is connected to the second input terminal and the second input terminal is connected to the second input terminal. The other end of two capacitors is connected to the first input terminal, and in the charge output operation, the other end of the first capacitor and the other end of the second capacitor are connected to the first input terminal and the second input terminal. A first switch circuit disconnected from the input terminal;
A second switch circuit provided in a path between the other end of the first capacitor and the other end of the second capacitor, turned off in the charging operation, and turned on in the charge output operation;
The signal synthesizer
Amplifying a voltage difference between an inverting input terminal connected to the first common node and a non-inverting input terminal connected to the second common node, and amplifying the voltage difference between the inverting output terminal and the non-inverting output terminal An operational amplifier that outputs as
A third capacitor provided in a path between the inverting input terminal and the non-inverting output terminal of the operational amplifier;
A fourth capacitor provided in a path between the non-inverting input terminal and the inverting output terminal of the operational amplifier and having the same capacitance as the third capacitor;
When the plurality of square wave multipliers perform the charging operation, the third capacitor and the fourth capacitor are short-circuited, respectively, and when the plurality of square wave multipliers perform the charge output operation, the short circuit is released. The analog-digital converter according to claim 13, further comprising a first discharge circuit. A first input terminal and a second input terminal to which a differential signal is input as the input analog signal;
A first common node, a second common node, a third common node, and a fourth common node to which the plurality of square wave multipliers are connected in common;
The square wave multiplication unit includes a first capacitor and a second capacitor having the same capacitance, and in the charging operation, the first common terminal and the second input terminal are common to the first capacitor. A voltage generated between the first capacitor and the second common node is applied to the second capacitor, and a voltage generated between the other of the first input terminal and the second input terminal and the second common node is applied to the first capacitor. In the charge output operation, the first capacitor is connected between the first common node and the third common node, and the second capacitor is connected between the second common node and the fourth common node. The charge stored in the second capacitor from the polarity of the input analog signal during the charging operation and the charge stored in the first capacitor during the charging operation. The relationship between the polarity of the stomach charge differential, reversed at a half cycle and the other half period of the one,
The signal synthesis unit adjusts the voltage of the third common node and the voltage of the fourth common node so that the voltage of the first common node is equal to the voltage of the second common node, and the third common node The voltage difference between a node and the fourth common node is output as a signal corresponding to a sum of charges output from the plurality of square wave multipliers by the charge output operation. Analog-to-digital converter. A first input terminal and a second input terminal to which a differential signal is input as the input analog signal;
A first common node, a second common node, a third common node, and a fourth common node to which the plurality of square wave multipliers are connected in common;
The square wave multiplier is
A first capacitor having one end connected to the first common node;
A second capacitor having one end connected to the second common node and having the same capacitance as the first capacitor;
In the charging operation in one half cycle of the square wave multiplied by the input analog signal, the other end of the first capacitor is connected to the first input terminal and the other end of the second capacitor. Is connected to the second input terminal, and in the charging operation of the other half cycle of the square wave, the other end of the first capacitor is connected to the second input terminal and the second input terminal is connected to the second input terminal. The other end of two capacitors is connected to the first input terminal, and in the charge output operation, the other end of the first capacitor and the other end of the second capacitor are connected to the first input terminal and the second input terminal. A first switch circuit disconnected from the input terminal;
A seventh switch circuit provided in a path between the other end of the first capacitor and the third common node, which is turned off in the charging operation and turned on in the charge output operation;
An eighth switch circuit provided in a path between the other end of the second capacitor and the fourth common node, which is turned off in the charging operation and turned on in the charge output operation;
The signal synthesizer
Amplifying a voltage difference between an inverting input terminal connected to the first common node and a non-inverting input terminal connected to the second common node, and amplifying the amplified result to a non-inverting terminal connected to the third common node An operational amplifier that outputs a voltage difference between an output terminal and an inverting output terminal connected to the fourth common node;
A ninth switch circuit provided in a path between the inverting input terminal and the non-inverting output terminal of the operational amplifier, which is turned on in the charging operation and turned off in the charge output operation;
10. A tenth switch circuit provided in a path between the non-inverting input terminal and the inverting output terminal of the operational amplifier and turned on in the charging operation and turned off in the charge output operation. Item 14. The analog-digital converter according to Item 13. A first noise component that is included in the input analog signal and attenuates the noise component that may cause aliasing from a frequency that is an integral multiple of the frequency at which the charging operation is repeated to the signal band of the input signal. The analog-digital converter according to any one of claims 2 to 17, further comprising a low-pass filter. N of the harmonics included in the first square wave are multiplied by the input signal by N patterns of the second square waves corresponding to the first to Nth harmonics in order of decreasing frequency. The square wave multiplier
The first low-pass filter is a harmonic component included in the first square wave, and a noise component of the input signal having a frequency corresponding to the (N + 1) th and subsequent harmonics in order of increasing frequency. The analog-to-digital converter according to claim 18, wherein the analog-to-digital converter is attenuated. The analog-to-digital converter according to any one of claims 1 to 19, further comprising a second low-pass filter that extracts a direct current component included in the output digital value.

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