JP2016212238A - Circuit device, electro-optical device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit device capable of suppressing electric power consumed in a single operation, and an electro-optical device and an electronic apparatus.SOLUTION: A circuit device 100 includes: a driving circuit 110 driving a display panel 200; a clock signal generation circuit 120 generating a clock signal; a control circuit 130 performing control processing; and a clock terminal CLK for supplying the clock signal to a slave side circuit device. Further, the control circuit 130 performs control outputting the clock signal to the slave side circuit device via the clock terminal CLK in a master mode, and performs control stopping output of the clock signal from the clock terminal CLK in a single operation mode.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a circuit device, an electro-optical device, an electronic apparatus, and the like.

  Patent Document 1 discloses an electro-optical device in which a display panel is driven by a master driver IC and a slave driver IC. In this electro-optical device, the driver IC on the master side generates a display control signal, and the driver IC on the slave side has an input terminal for inputting the display control signal via an external wiring.

JP 2001-92424 A

  As described above, there has been a conventional technique for driving the display panel by the master / slave operation of the master side driver IC and the slave side driver IC. However, depending on the product, the display panel may be driven by a single operation instead of a master / slave operation. In the case of this single operation, a buffer circuit that outputs a display control signal operates even though there is no slave-side IC, and power is wasted in this buffer circuit.

  According to some aspects of the present invention, it is possible to provide a circuit device, an electro-optical device, an electronic apparatus, and the like that can suppress power consumed in a single operation.

  One embodiment of the present invention is a drive circuit that drives a display panel, a clock signal generation circuit that generates a clock signal, a control circuit that performs control processing, and a circuit for supplying the clock signal to a slave-side circuit device. A clock terminal, and the control circuit performs control to output the clock signal to the slave side circuit device via the clock terminal in the master mode, and from the clock terminal in the single operation mode. The present invention relates to a circuit device that performs control to stop the output of the clock signal.

  In one embodiment of the present invention, in the master mode, control is performed to output a clock signal to the slave circuit device via the clock terminal, and in the single operation mode, output of the clock signal from the clock terminal is stopped. Therefore, power consumed in a single operation can be suppressed.

  In one embodiment of the present invention, a display control terminal for supplying a display control signal to the slave side circuit device is included, and the control circuit is configured to display the display via the display control terminal in the master mode. Control for outputting a control signal to the slave side circuit device may be performed, and control for stopping output of the display control signal from the display control terminal may be performed in the single operation mode.

  Thereby, in the single operation mode, power consumed to output the display control signal can be suppressed.

  In one embodiment of the present invention, the clock signal I / O circuit may be included, and the control circuit may stop the operation of the output buffer of the I / O circuit in the single operation mode.

  This makes it possible to stop the output of the clock signal in the single operation mode.

  In one embodiment of the present invention, the display control signal I / O circuit may be included, and the control circuit may stop the operation of the output buffer of the I / O circuit in the single operation mode.

  Thereby, it becomes possible to stop the output of the display control signal in the single operation mode.

  In one embodiment of the present invention, the I / O circuit controls an output buffer for outputting the clock signal, an input buffer for inputting the clock signal, the output buffer, and the input buffer. And an I / O control circuit for inputting the I / O switching signal and the data enable signal to the I / O control circuit.

  As a result, the clock signal I / O control circuit can perform any one of the master mode, the single operation mode, and the slave mode based on the input I / O switching signal and the data enable signal. It becomes possible.

  In the aspect of the invention, the I / O circuit may include an output buffer for outputting the display control signal, an input buffer for inputting the display control signal, the output buffer, and the input buffer. An I / O control circuit for controlling, and the control circuit may input an I / O switching signal and a data enable signal to the I / O control circuit.

  Thus, the display control signal I / O control circuit performs any one of the master mode, the single operation mode, and the slave mode based on the input I / O switching signal and the data enable signal. Is possible.

  In the aspect of the invention, in the master mode, the output buffer is enabled and the input buffer is disabled by the I / O switching signal, and in the single operation mode, the data enable signal The output of the output buffer may be set to a fixed voltage level, and the input buffer may be disabled by the I / O switching signal.

  As a result, in the master mode, the clock signal and display control signal are output to the outside, and in the single operation mode, the clock signal and display control signal are not output to the outside and the input of the clock signal and display control signal from the outside is accepted. It is possible to eliminate it.

  According to another aspect of the present invention, the master has a first mode setting terminal and a second mode setting terminal, and the master is based on voltage levels of the first mode setting terminal and the second mode setting terminal. The mode, the single operation mode, and the slave mode may be switched.

  As a result, it is possible to cause the circuit device to perform any one of the operation in the master mode, the single operation mode, and the slave mode.

  In another aspect of the present invention, a drive circuit for driving the display panel, a control circuit for performing a control process, and a display control terminal for supplying a display control signal to the slave side circuit device, The control circuit performs control to output the display control signal to the slave side circuit device via the display control terminal in the master mode, and the display control signal from the display control terminal in the single operation mode. The present invention relates to a circuit device that performs control to stop the output of.

  Thereby, the power consumed in the single operation can be suppressed.

  Another aspect of the invention relates to an electro-optical device including the circuit device and the display panel.

  Another aspect of the invention relates to an electronic apparatus including the circuit device.

The circuit block diagram of this embodiment. Explanatory drawing of the example of mounting of the circuit apparatus and display panel at the time of single operation mode. Explanatory drawing of the example of mounting of a master side circuit device and a slave side circuit device. The relationship between the voltage level of a mode setting terminal and each operation mode. The circuit block diagram of an I / O circuit. Explanatory drawing of the connection relation of several I / O circuit. FIG. 6 is an operation explanatory diagram of the I / O circuit in the master mode. FIG. 5 is an operation explanatory diagram of the I / O circuit in a single operation mode. Explanatory drawing of the other example of mounting of the master side circuit device and the slave side circuit device.

  Hereinafter, this embodiment will be described. In addition, this embodiment demonstrated below does not unduly limit the content of this invention described in the claim. In addition, all the configurations described in the present embodiment are not necessarily essential configuration requirements of the present invention.

1. Overview As described above, electro-optical devices that drive a display panel by master / slave operation of a master driver IC and a slave driver IC are widely used. However, depending on the product, the display panel may be driven by a single operation instead of a master / slave operation. When performing this single operation, the slave side IC is not originally mounted on the circuit board. Nevertheless, the buffer circuit that outputs the display control signal operates, and power is consumed wastefully.

  The circuit device or the like of the present embodiment described below suppresses power consumed in the single operation mode. Specifically, in the present embodiment, in the master mode, the master side circuit device outputs a clock signal to the slave side circuit device via the clock terminal, and in the single operation mode, the clock signal is output from the clock terminal. Stop. In the single operation mode, since the output of the clock signal is stopped, the power consumption due to the charging / discharging of the wiring on the circuit board and the wasteful operation of the internal circuit is suppressed, so that the consumption can be reduced.

2. Circuit Configuration FIG. 1 is a circuit configuration diagram of a circuit device 100 according to the present embodiment. The circuit device 100 according to the present embodiment is provided for a drive circuit 110 that drives the display panel 200, a clock signal generation circuit 120 that generates a clock signal, a control circuit 130 that performs control processing, and a slave circuit device (not shown). A clock terminal CLK for supplying a clock signal, and a display RAM 160. Further, the circuit device 100 according to the present embodiment can be applied to an electro-optical device including the circuit device 100 and the display panel 200. Furthermore, the circuit device 100 of the present embodiment can be applied to an electronic device including the circuit device 100. For example, a specific example of an electronic device is a vehicle-mounted monitor. Note that the circuit device 100, the electro-optical device, and the electronic apparatus are not limited to the configuration in FIG. 1, and various modifications may be made such as omitting some of these components or adding other components. Is possible.

  Display data is written into the display RAM 160 from an external processing unit (not shown) via the control circuit 130. The drive circuit 110 reads display data from the display RAM 160, performs MLS decoding processing (MLS: Multi Line Selection) on the display data, and uses the display panel 200 with a driving voltage corresponding to the display data subjected to the MLS decoding processing. Drive the segment. In MLS driving, pixels of a plurality of lines (a plurality of common lines) of the display panel 200 are driven simultaneously. For example, in MLS driving in which four lines of pixels are driven simultaneously, the same four lines of pixels are driven four times with display data that has undergone MLS decoding.

  The control circuit 130 performs control to output a clock signal to the slave side circuit device via the clock terminal CLK in the master mode, and stops outputting the clock signal from the clock terminal CLK in the single operation mode. Take control.

  FIG. 2 is an explanatory diagram of a mounting example of the circuit device and the display panel in the single operation mode. When the circuit device 100 is driven in the single operation mode, as shown in FIG. 2, the driver IC which is the circuit device 100 is mounted on the circuit board, and the slave circuit device is not mounted. The driver IC is connected to the display panel 200 and operates based on a command from an external MPU (Micro-processing unit) or the like. As described above, since the slave circuit device is not mounted, the clock signal is not output to the slave circuit device as described above. Therefore, power consumed in the single operation (single operation mode) can be suppressed.

  On the other hand, when the circuit device 100 is driven in the master mode, as shown in FIG. 3, the master side circuit device and the slave side circuit device are mounted on the circuit board, and the master side circuit device and the slave side circuit device are Connected to each other. Specifically, the clock terminal CLK of the master side circuit device and the clock terminal CLK of the slave side circuit device are connected, and a clock signal is output from the master side circuit device to the slave side circuit device. For example, a master side circuit device and a slave side circuit device are connected to half of the display panel 200, respectively.

  FIG. 3 is an explanatory diagram of an implementation example of the master side circuit device and the slave side circuit device. As shown in FIG. 1, the circuit device 100 of the present embodiment includes a display control terminal SYNC for supplying a display control signal to the slave side circuit device. In the example of FIG. 3, there are five display control terminals (SYNC1 to SYNC5), and the display control terminal of the master side circuit device and the display control terminal of the slave side circuit device are respectively connected. In the master mode, the control circuit 130 performs control to output a display control signal to the slave side circuit device via the display control terminal SYNC (SYNC1 to SYNC5 in FIG. 3), and in the single operation mode, the display control is performed. Control to stop the output of the display control signal from the terminal SYNC is performed.

  For example, as an example of the display control signal, a signal for notifying an on state and an off state of the display panel, a signal used for MLS calculation, a liquid crystal alternating signal, a signal for synchronizing display timing, and the like can be considered.

  As a result, the power consumed in the single operation mode can be suppressed as in the case of stopping the output of the clock signal in the single operation mode.

  As shown in FIG. 1, the circuit device 100 of this embodiment includes an I / O circuit 140 for clock signals. Then, the control circuit 130 stops the operation of the output buffer of the I / O circuit 140 in the single operation mode. A method for stopping the operation of the output buffer of the I / O circuit 140 will be described in detail later.

  This makes it possible to stop the output of the clock signal in the single operation mode.

  Further, as shown in FIG. 1, the circuit device 100 of the present embodiment includes an I / O circuit 150 for display control signals. Then, the control circuit 130 stops the operation of the output buffer of the I / O circuit 150 in the single operation mode. A method for stopping the operation of the output buffer of the I / O circuit 150 will be described in detail later.

  Thereby, it becomes possible to stop the output of the display control signal in the single operation mode.

  In addition, as shown in FIG. 1, the circuit device 100 of the present embodiment includes a first mode setting terminal MS1 and a second mode setting terminal MS2. Then, based on the voltage levels of the first mode setting terminal MS1 and the second mode setting terminal MS2, switching between the master mode, the single operation mode, and the slave mode is performed.

  FIG. 4 is a relationship diagram between the voltage level of the mode setting terminal and each operation mode. In the example of FIG. 4, when the voltage levels of the first mode setting terminal MS1 and the second mode setting terminal MS2 are both H level, the circuit device 100 is set to the single operation (1 chip) mode. When the voltage level of the first mode setting terminal MS1 is H level and the voltage level of the second mode setting terminal MS2 is L level, the circuit device 100 is set to the master mode. Further, when the voltage levels of the first mode setting terminal MS1 and the second mode setting terminal MS2 are both L level, the circuit device 100 is set to the slave mode. It should be noted that when the voltage level of the first mode setting terminal MS1 is L level and the voltage level of the second mode setting terminal MS2 is H level, it is a prohibited mode, and the mode setting is made so as not to enter this prohibited mode. It is necessary to set the voltage level of the terminal. However, the present embodiment is not limited to this, and a fourth mode may be set. In the present embodiment, it is assumed that when the circuit device 100 is mounted on the circuit board, the voltage levels of the first mode setting terminal MS1 and the second mode setting terminal MS2 are always fixed. ing. However, the voltage levels of the first mode setting terminal MS1 and the second mode setting terminal MS2 may be variably settable.

  For example, the first mode setting terminal MS1 and the second mode setting terminal MS2 are connected to a low-potential-side power supply voltage (for example, ground voltage) on the circuit board, so that the voltage level of these terminals is set to the L level. By connecting to the high potential side power supply voltage (for example, the logic power supply voltage of the display driver), the voltage level of these terminals is set to the H level.

  As a result, the circuit device 100 can be operated in any one of the master mode, the single operation mode, and the slave mode.

  The voltage level set in the mode setting terminal may be stored in a memory included in the circuit device 100. For example, the voltage level setting information of the first mode setting terminal MS1 and the second mode setting terminal MS2 may be stored in a fuse circuit or a nonvolatile memory and input to the control circuit 130.

3. I / O Circuit Configuration FIG. 5 is a specific circuit configuration diagram of an I / O circuit. As shown in FIG. 5, the clock signal I / O circuit 140 includes an output buffer 141 for outputting the clock signal, an input buffer 143 for inputting the clock signal, an output buffer 141, and an input buffer 143. An I / O control circuit 145 for controlling. Then, the control circuit 130 inputs the I / O switching signal INOUT, the data enable signal EN_DATA, and the data signal DATA_O to the I / O control circuit 145.

  The output buffer 141 includes a PMOS transistor (TR1 in FIG. 5) and an NMOS transistor (TR2 in FIG. 5). The input buffer 143 includes an inverter IN3. The I / O control circuit 145 includes an inverter IN1, an inverter IN2, a NAND circuit NA1, a NAND circuit NA2, and a NOR circuit NO1.

  The input / output terminal I / O is a bidirectional signal terminal. The input / output terminal I / O outputs an output signal from the output buffer 141. The input / output terminal I / O inputs an input signal to the input buffer 143.

  An I / O switching signal INOUT is input to the inverter IN1, and signals are output from the inverter IN1 to the NAND circuit NA1 and the NAND circuit NA2. The NAND circuit NA2 receives the output of the inverter IN1, the data enable signal EN_DATA, and the data signal DATA_O, and the NAND circuit NA2 outputs a signal to the inverter IN2. Further, the output signal of the NAND circuit NA2 is input to the inverter IN2, and the signal is output from the inverter IN2 to the NAND circuit NA1 and the NOR circuit NO1. Then, the output signal of the inverter IN1 and the output signal of the inverter IN2 are input to the NAND circuit NA1, and a signal is output from the NAND circuit NA1 to the PMOS transistor (TR1). The output signal of the inverter IN2 and the I / O switching signal INOUT are input to the NOR circuit NO1, and a signal is output from the NOR circuit NO1 to the NMOS transistor (TR2). TR1 and TR2 output an output signal from the input / output terminal I / O. The NAND circuit NA3 receives an I / O switching signal INOUT and an input signal from the input / output terminal I / O, and outputs a signal from the NAND circuit NA3 to the inverter IN3. An output signal of the NAND circuit NA3 is input to the inverter IN3, and an input signal DATA_I to the control circuit 130 is output.

  Here, the I / O switching signal INOUT is a signal used for switching input / output of the I / O circuit 140. In other words, the output buffer 141 and the input buffer 143 are enabled or disabled based on the I / O switching signal INOUT. In this example, when the I / O switching signal INOUT is set to the H level, the I / O circuit 140 is in an input enabled state (slave mode), and when the I / O switching signal INOUT is set to the L level. The I / O circuit 140 is ready for output.

  The data enable signal EN_DATA is a signal used to determine whether or not to validate the data signal DATA_O input to the I / O circuit 140. Specifically, when the data enable signal EN_DATA is at the H level, the data signal DATA_O becomes valid and the data signal DATA_O is output from the input / output terminal I / O. On the other hand, when the data enable signal EN_DATA is at the L level, the data signal DATA_O is invalid, and the output signal output to the input / output terminal I / O is always at the fixed voltage level (L level). Details will be described later.

  The control circuit 130 sets the I / O switching signal INOUT and the data enable signal EN_DATA based on the voltage levels of the mode setting terminals MS1 and MS2.

  As a result, the I / O control circuit 145 can perform any one of a master mode, a single operation mode, and a slave mode based on the input I / O switching signal INOUT and the data enable signal EN_DATA. become.

  Further, the display control signal I / O circuit 150 may be configured by the same I / O circuit as the I / O circuit 140. Similar to the clock signal I / O circuit 140, an output buffer 151 for outputting a display control signal, an input buffer 153 for inputting a display control signal, and an I for controlling the output buffer and the input buffer. / O control circuit 155. Then, the control circuit 130 inputs the I / O switching signal INOUT and the data enable signal EN_DATA to the I / O control circuit 155.

  As a result, the I / O control circuit 155, like the I / O control circuit 145, can select any of the master mode, the single operation mode and the slave mode based on the input I / O switching signal INOUT and the data enable signal EN_DATA. It is possible to perform such operations. Note that the I / O circuit is not limited to the configuration shown in FIG. 5, and various modifications such as omitting some of these components or adding other components are possible.

  FIG. 6 is an explanatory diagram of a connection relationship between a plurality of I / O circuits. An I / O circuit is provided for each terminal. That is, as shown in FIG. 6, an I / O circuit IOC for a clock terminal is provided for the clock terminal CLK, and an I / O for each display control terminal is provided for each display control terminal (SYNC1 to SYNC5). O circuits (IOS1 to IOS5) are provided.

  Next, a specific operation of the I / O circuit will be described using a clock signal as an example. First, an I / O switching signal INOUT and a data enable signal EN_DATA are input to the clock terminal I / O circuit IOC.

  As shown in FIG. 4, the voltage level of the I / O switching signal INOUT is set to a voltage level obtained by inverting the voltage level of the first mode setting terminal MS1. That is, when the voltage level of the first mode setting terminal MS1 is L level, the voltage level of the I / O switching signal INOUT becomes H level, and the voltage level of the first mode setting terminal MS1 is H level. In some cases, the voltage level of the I / O switching signal INOUT becomes L level.

  Further, as shown in FIG. 4, when the voltage levels of the first mode setting terminal MS1 and the second mode setting terminal MS2 are both H level, the voltage level of the data enable signal EN_DATA is set to L level. . When the voltage level of the first mode setting terminal MS1 is H level and the voltage level of the second mode setting terminal MS2 is L level, the voltage level of the data enable signal EN_DATA is set to H level. When the voltage levels of the first mode setting terminal MS1 and the second mode setting terminal MS2 are both L level, the data enable signal EN_DATA may be either H level or L level. .

  When the voltage level of the first mode setting terminal MS1 is L level and the voltage level of the second mode setting terminal MS2 is H level, the voltage levels of the I / O switching signal INOUT and the data enable signal EN_DATA are set. Is not defined as a specification. Such setting of the mode setting terminal is prohibited.

  In the master mode, the output buffer 141 is enabled and the input buffer 143 is disabled by the I / O switching signal INOUT. In this case, the clock signal CLK_O is further input as the data signal DATA_O to the clock terminal I / O circuit IOC, and is output from the input / output terminal I / O as a voltage signal having the same logic level as the input clock signal. .

  FIG. 7 is an explanatory diagram of the operation of the I / O circuit in the master mode. In order to explain more specifically, the voltage level of each signal in the master mode is shown in FIG. As shown in FIG. 7, in the master mode, an I / O switching signal INOUT at L level and a data enable signal EN_DATA at H level are input to the I / O control circuit 145. Further, since the data signal DATA_O is a clock signal, the voltage level of the data signal DATA_O can be either L level or H level. In this case, when the voltage level of the data signal DATA_O is L level, the PMOS transistor of the output buffer 141 is turned off and the NMOS transistor is turned on, so that the L level clock signal is output to the outside. On the other hand, when the voltage level of the data signal DATA_O is H level, the PMOS transistor of the output buffer 141 is turned on and the NMOS transistor is turned off, so that the H level clock signal is output to the outside. That is, a signal having the same logic level as that of the data signal DATA_O that is a clock signal is output from the input / output terminal I / O of the I / O circuit 140. Also, as shown in FIG. 7, since an H level signal is input to the input buffer 143, the output of the input buffer 143 is always at the L level (disabled). Although detailed description is omitted, the I / O circuit 140 performs the same operation on the display control signal. Thereby, in the master mode, it is possible to output a clock signal and a display control signal to the outside.

  When the I / O circuit operates in the slave mode, the signal DATA_I input from the master side circuit device is output to the control circuit 130 as the clock signal CLK_I. In the slave mode, since both the PMOS transistor and the NMOS transistor of the output buffer 141 are turned off, the output of the output buffer 141 is in a high impedance state. Thereby, in the slave mode, an input clock signal and display control signal can be received from the input / output terminal I / O.

  Next, in the single operation mode, the output of the output buffer 141 is set to a fixed voltage level (L level) by the data enable signal EN_DATA, and the input buffer 143 is disabled by the I / O switching signal INOUT.

  FIG. 8 is an operation explanatory diagram of the I / O circuit in the single operation mode. In order to explain more specifically, FIG. 8 shows the voltage level of each signal in the single operation mode. As shown in FIG. 8, in the single operation mode, an I / O switching signal INOUT at L level and a data enable signal EN_DATA at L level are input to the I / O control circuit 145. As described above, the voltage level of the data signal DATA_O can be L level or H level. In this case, the PMOS of the output buffer 141 is always off regardless of the voltage level of the data signal DATA_O. , NMOS is always on. As a result, the voltage level of the output signal to the outside can always be set to a fixed voltage level (L level). Also, as shown in FIG. 8, since an H level signal is input to the input buffer 143, the output of the input buffer 143 is always at the L level (disabled). The same applies to the display control signal. As a result, in the single operation mode, it is possible not to output the clock signal and the display control signal to the outside, and to not accept the input of the clock signal and the display control signal from the outside.

4). Modification FIG. 9 is an explanatory diagram of another implementation example of the master side circuit device and the slave side circuit device. In this embodiment, the clock signal generation circuit 120 may be provided outside the circuit device 100, and the circuit device 100 may acquire the clock signal from the external clock signal generation circuit 120. For example, as shown in FIG. 9, a clock signal is input from the outside to the master, and the input clock signal is output from the master to the slave.

  In this case, in the circuit device 100 according to the modification of the present embodiment, a drive circuit 110 that drives the display panel 200, a control circuit 130 that performs control processing, and a display control signal for supplying a display control signal to the slave side circuit device. Display control terminal SYNC. In the master mode, the control circuit 130 performs control to output a display control signal to the slave side circuit device via the display control terminal SYNC. In the single operation mode, the control circuit 130 receives the display control signal from the display control terminal SYNC. Control to stop output.

  As a result, it is not necessary for the circuit device to drive the clock signal generation circuit 120, and power saving can be achieved.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. Further, the configurations and operations of the circuit device, the electro-optical device, and the electronic apparatus are not limited to those described in this embodiment, and various modifications can be made.

100 circuit device, 110 drive circuit, 120 clock signal generation circuit,
130 control circuit, 140 I / O circuit for clock signal, 141 output buffer,
143 input buffer, 145 I / O control circuit,
150 I / O circuit for display control signal, 151 output buffer,
153 input buffer, 155 I / O control circuit, 200 display panel

Claims (11)

A drive circuit for driving the display panel;
A clock signal generation circuit for generating a clock signal;
A control circuit for performing control processing;
A clock terminal for supplying the clock signal to the slave side circuit device;
Including
The control circuit includes:
In the master mode, control is performed to output the clock signal to the slave circuit device via the clock terminal,
In the single operation mode, the circuit device performs control to stop the output of the clock signal from the clock terminal. In claim 1,
A display control terminal for supplying a display control signal to the slave side circuit device;
The control circuit includes:
In the master mode, control to output the display control signal to the slave side circuit device through the display control terminal,
In the single operation mode, the circuit device performs control to stop the output of the display control signal from the display control terminal. In claim 1 or 2,
Including an I / O circuit for the clock signal;
The control circuit includes:
In the single operation mode, the operation of the output buffer of the I / O circuit is stopped. In claim 2,
Including an I / O circuit for the display control signal,
The control circuit includes:
In the single operation mode, the operation of the output buffer of the I / O circuit is stopped. In claim 3,
The I / O circuit is
An output buffer for outputting the clock signal;
An input buffer for inputting the clock signal;
An I / O control circuit for controlling the output buffer and the input buffer;
Including
The control circuit includes:
A circuit device, wherein an I / O switching signal and a data enable signal are input to the I / O control circuit. In claim 4,
The I / O circuit is
An output buffer for outputting the display control signal;
An input buffer for inputting the display control signal;
An I / O control circuit for controlling the output buffer and the input buffer;
Including
The control circuit includes:
A circuit device, wherein an I / O switching signal and a data enable signal are input to the I / O control circuit. In claim 5 or 6,
In the master mode, the output buffer is enabled and the input buffer is disabled by the I / O switching signal,
In the single operation mode, the output of the output buffer is set to a fixed voltage level by the data enable signal, and the input buffer is set to be disabled by the I / O switching signal. In any one of Claims 1 thru | or 7,
A first mode setting terminal and a second mode setting terminal;
The circuit device, wherein the master mode, the single operation mode, and the slave mode are switched based on voltage levels of the first mode setting terminal and the second mode setting terminal. A drive circuit for driving the display panel;
A control circuit for performing control processing;
A display control terminal for supplying a display control signal to the slave side circuit device;
Including
The control circuit includes:
In the master mode, control to output the display control signal to the slave side circuit device through the display control terminal,
In the single operation mode, the circuit device performs control to stop the output of the display control signal from the display control terminal.   An electro-optical device comprising the circuit device according to claim 1 and the display panel.   An electronic apparatus comprising the circuit device according to claim 1.

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