JP2016207934A - Nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device which can improve a short-circuit safe operating area while ensuring a voltage withstanding property to improve reliability of an element.SOLUTION: A nitride semiconductor device comprises: a nitride semiconductor layer (100) including a channel layer (103), a barrier layer (104) and a superlattice layer (102); and a transistor element part including a source electrode (107) and a drain electrode (109) which are arranged on the nitride semiconductor layer (100), an insulation film (105) formed between the source electrode (107) and the drain electrode (109) and on the nitride semiconductor layer (100), and a gate electrode (108) formed between the source electrode (107) and the drain electrode (109) and on the nitride semiconductor layer (100). The transistor element part is configured to make a power density at the time of a load short-circuit be equal to or less than a predetermined value; and the superlattice layer (102) is configured to make voltage withstanding between the source electrode (107) and the drain electrode (109) be equal to or larger than a predetermined voltage.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a nitride semiconductor device, and more particularly to a nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a nitride semiconductor layer.

  As a conventional nitride semiconductor device, as shown in FIG. 10, there is a GaN field effect transistor having a hetero structure including a channel layer and a barrier layer, and the field effect transistor having an insulating film on the surface of the transistor element. By depositing an insulating film on the surface, the number of surface states is reduced, the polarization effect at the heterointerface is increased, the two-dimensional electron gas concentration is increased, and a high output can be obtained (for example, JP, 2013-229493, A (patent documents)).

  In FIG. 10, 601 is a Si substrate, 602 is a buffer layer, 603 is an undoped GaN layer as a channel layer, 604 is an undoped AlGaN layer as a barrier layer, 605 is an insulating film, and 606 is a two-dimensional electron gas (2DEG). 607 is a source electrode, 608 is a gate electrode, and 609 is a drain electrode.

JP 2013-229493 A

  By the way, in the conventional nitride semiconductor device, when a large current flows (short circuit) in a state where a high voltage is applied to the element, the element generates heat at a stretch by applying energy of voltage × current. There is a problem of causing deterioration and destruction.

  For example, in a normally-on GaN HFET (Hetero-junction Field Effect Transistor), in the OFF state where -10 V is continuously applied to the gate electrode, 0 V is applied to the source electrode and the drain electrode is applied. When 400 V is applied, if a large current of several A to several hundred A flows through the element due to a short circuit between the source electrode and the drain electrode due to some factor, energy of several kW to several hundred kW is instantaneously applied to the element. As a result, heat is generated at once and the device is destroyed.

  In general, depending on the usage environment such as an inverter circuit, the transistor element may be short-circuited due to abnormal fluctuations in the load or power supply, and the transistor will not break even in the short-circuit state until the protection circuit works. Is required. Conventionally, in Si devices, when a large current flows (short-circuited) when a high voltage (for example, 400 V) is applied, it has been required that the device does not break for 10 μsec or more. Due to this reduction, the amount of heat generated per unit area increases, and it has become difficult to ensure a short circuit time of 10 μsec or more.

  In particular, GaN is expected to have a significantly higher breakdown voltage / lower resistance than Si devices due to its superior material properties, and as the chip area shrinks, the increase in short-circuit time has become a major issue. Suppression of heat generation and dispersion of heat generation are important.

  Accordingly, an object of the present invention is to reduce the amount of heat generated during a short circuit while ensuring the breakdown voltage characteristics, thereby reducing the amount of heat generated by the element, improving the short circuit resistance, and improving the reliability of the element It is to provide a semiconductor device.

In order to solve the above problems, the nitride semiconductor device of the present invention is
A nitride semiconductor layer having a heterostructure including a channel layer, a barrier layer, and a superlattice layer;
A source electrode and a drain electrode which are formed on the nitride semiconductor layer or in the nitride semiconductor layer and spaced apart from each other;
An insulating film formed between the source electrode and the drain electrode and on the nitride semiconductor layer;
A transistor element portion having a gate electrode formed between the source electrode and the drain electrode and on the nitride semiconductor layer;
The transistor element portion is configured such that a power density that is a product of a drain current density and a drain voltage when a load is short-circuited is equal to or lower than a predetermined power density,
The superlattice layer is configured such that a withstand voltage between the source electrode and the drain electrode is equal to or higher than a predetermined voltage.

In the nitride semiconductor device of one embodiment,
The barrier layer has a thickness of 30 nm or less.

In the nitride semiconductor device of one embodiment,
The number of layers constituting the superlattice layer is 20 or more and 80 or less.

In the nitride semiconductor device of one embodiment,
The superlattice layer has a layer thickness of 0.3 μm or more and 1.5 μm or less.

In the nitride semiconductor device of one embodiment,
The superlattice layer includes AlGaN,
The product of the thickness of the superlattice layer and the average Al composition ratio of the superlattice layer is not less than 5 μm% and not more than 30 μm%.

In the nitride semiconductor device of one embodiment,
When the drain voltage is 400 V, the breakdown time when the load is short-circuited is 1 microsecond or more, and the power density, which is the product of the drain current density and the drain voltage when the load is short-circuited, is 850 kW / cm ² or less.

In the nitride semiconductor device of one embodiment,
On the nitride semiconductor layer in which the drain electrode and the source electrode are disposed, a heat radiating portion is provided via an interlayer insulating film.

  As is clear from the above, according to the present invention, the transistor element portion is configured such that the power density, which is the product of the drain current density and the drain voltage at the time of load short-circuiting, is equal to or lower than the predetermined power density, and the source electrode By configuring the superlattice layer so that the breakdown voltage between the drain electrode and the drain electrode is equal to or higher than a predetermined voltage, the energy generated in the element is reduced by reducing the energy applied to the element during a short circuit while ensuring the breakdown voltage characteristics. Can be improved, the short circuit tolerance can be improved, and the reliability of the element can be improved.

FIG. 1 is a sectional view of a GaN-based HFET as an example of a nitride semiconductor device according to the first embodiment of the present invention. FIG. 2 is a schematic diagram of a typical IV curve of a normally-on GaN HFET. FIG. 3 is a schematic diagram showing the change over time in the drain current when the load of the normally-on GaN HFET is short-circuited. FIG. 4 is a graph plotting the short circuit time (breakdown time) tp against the product of the drain current density (Id / S) at the time of short circuit and the drain voltage Vd in the GaN HFET of the first embodiment. FIG. 5 is a diagram for explaining heat conduction when heat is generated at the drain end when the load is short-circuited in the GaN-based HFET of the first embodiment. FIG. 6 is a graph plotting the short circuit time (breakdown time) tp against the product of the drain current density (Id / S) and the drain voltage Vd at the time of the short circuit in the GaN HFET shown in the second embodiment. FIG. 7 is a plan view of a GaN-based HFET as an example of the nitride semiconductor device according to the second embodiment of the present invention. FIG. 8 is a plan view of a GaN-based HFET as an example of the nitride semiconductor device according to the third embodiment of the present invention. FIG. 9 is a plan view of a GaN-based HFET as an example of the nitride semiconductor device according to the fourth embodiment of the present invention. FIG. 10 is a cross-sectional view of a conventional GaN HFET.

  Hereinafter, the present invention will be described in detail with reference to illustrated embodiments. Each figure is a simplified diagram for understanding the present invention, and does not necessarily match an actual device such as shape and film thickness. Further, numerical values such as materials and film thicknesses described for the purpose of explanation in the embodiments are merely examples.

(First embodiment)
FIG. 1 is a sectional view of a normally-on type GaN-based HFET as an example of the nitride semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 1, the GaN HFET of the first embodiment includes, for example, a buffer layer 102 as an example of a superlattice layer formed on an Si substrate 101, and a channel layer formed on the buffer layer 102. An undoped GaN layer 103 as an example and an undoped AlGaN layer 104 as an example of a barrier layer formed on the undoped GaN layer 103 are provided. The buffer layer 102, the undoped GaN layer 103, and the undoped AlGaN layer 104 constitute the nitride semiconductor layer 100.

  The buffer layer 102 has a structure in which, for example, a laminated body in which AlGaN and AlN are grown is taken as one period, and this laminated body is laminated over a plurality of periods, and the number of layers is 20 or more and 80 or less. The layer thickness of the buffer layer 102 is, for example, 1 μm, but can be set to a suitable value according to the design within the range of 0.3 μm to 5 μm.

  The undoped GaN layer 103 has a thickness of 2 μm, for example, but can be set to a suitable value according to the design within a range of 0.5 μm to 5 μm.

  In addition, the undoped AlGaN layer 104 can be set to a suitable value according to the design. However, the thinner the thickness of the AlGaN layer 104, the shallower the threshold voltage, so that the saturation current can be reduced. Yes, 30 nm or less is preferable.

  Next, on the undoped AlGaN layer 104, a first insulating film 105a such as a silicon nitride film formed by using, for example, a plasma CVD method and a silicon nitride film or the like formed on the first insulating film 105a. Two insulating films 105b are provided. The insulating film 105 is composed of the first insulating film and the second insulating film 105b.

  The source electrode 107 includes a source ohmic electrode 107a and a source metal wiring 107b. Similarly, the drain electrode 109 includes a drain ohmic electrode 109a and a drain metal wiring 109b. The source ohmic electrode 107a and the drain ohmic electrode 109a are made of Ti / Al / TiN or the like.

  Further, the source electrode 107 and the drain electrode 109 that are spaced apart from each other include a first insulating film 105a, a second insulating film 105b, and a third insulating film 111 formed on the second insulating film 105b, The interlayer insulating film 112 formed on the third insulating film 111 and the undoped AlGaN layer 104 are formed so as to reach the two-dimensional electron gas (2DEG) 106. A passivation film 113 and an interlayer insulating film 114 are sequentially formed on the drain electrode 109 and the source electrode 107.

  The gate electrode 108 is formed between the source electrode 107 and the drain electrode 109 and on the undoped AlGaN layer 104 with the gate insulating film 110 interposed therebetween. The gate electrode 108 is made of Ni / Au or the like.

  The gate electrode 108 is an MISH (Metal Insulator Semiconductor Heterostructure) formed on the insulating film 105 formed on the undoped AlGaN layer 104. The gate electrode 108 is formed on the undoped AlGaN layer 104, which is an example of the barrier layer of the nitride semiconductor layer 100, with a base 108a joined via the gate insulating film 110, and from the upper part of the base 108a toward the drain electrode 109. And an extended gate field plate portion 108b.

  A two-dimensional electron gas (2DEG) 106 is generated at the interface between the undoped GaN layer 103 and the undoped AlGaN layer 104.

  The nitride semiconductor layer 100, the insulating film 105, the source electrode 107, the gate electrode 108, the drain electrode 109, the third insulating film 111, and the interlayer insulating film 112 constitute a transistor element portion.

  By setting the number of layers constituting the buffer layer 102 to 20 or more and 80 or less, the withstand voltage (withstand voltage) between the source electrode 107 and the drain electrode 109 can be 800 V or more.

  FIG. 2 is a schematic diagram of a typical IV curve of a normally-on GaN HFET. In FIG. 2, Idmax is a saturation current flowing through the drain electrode.

  Here, the saturation current Idmax is the applied voltage Vg = 0 V to the gate electrode 108 with respect to the applied voltage Vd to the drain electrode 109 (about 10 V or more) in the GaN HFET of the first embodiment shown in FIG. The current flowing through the drain electrode 109 when the applied voltage Vs to the source electrode 107 is 0 V and the substrate potential is 0 V is shown.

  As shown in FIG. 2, when the load is short-circuited, the operating point of the transistor shifts from a point A where the transistor element is turned off to a point B where a large current flows while maintaining a high voltage. At this time, when the power of voltage × current is applied, the element generates heat at a stretch and causes deterioration or destruction of the element.

  Next, FIG. 3 shows the change with time of the waveform of the current flowing through the element when the load is short-circuited. In FIG. 3, the horizontal axis represents time [arbitrary scale], and the vertical axis represents drain current I [arbitrary scale].

  When the load is short-circuited, a large current flows through the element, and the drain current I decreases due to heat generated by the energy of voltage × current, and the element is destroyed at a certain time tp.

  At this time, if the temperature rise due to heat generation is ΔTj [° C.], the transient thermal resistance of the element is Zth [° C./W], and the energy at the time of short circuit is Pd [W], the following equation (1) is satisfied.

      ΔTj = Zth × Pd (1)

  Assuming that the time at which the device breaks down is tp [sec], the transient thermal resistance Zth is approximately proportional to the 1/2 power of tp in a sufficiently short time on the order of microseconds. 1) can be transformed into the following equation (2).

ΔTj≈K · (tp) ^0.5 · Pd Equation (2)

Further, the proportionality constant K is calculated by using the element area S [cm ² ] and the proportionality constant M,
K = (M / S)
It is represented by

  When the drain current at the time of short circuit is Id [A] and the drain voltage is Vd [V], the above equation (2) is as follows.

ΔTj≈ (M / S) · (tp) ^0.5 · Pd
= M · (tp) ^0.5 · (Id / S) · Vd
= M · (tp) ^0.5 · (Id / S) · Vd Equation (3)

Normally, when the pitch between the source and the drain is Lsd [cm] and the gate width is W [cm], the element area S is:
S = Lsd × W [cm ² ]
It is represented by

  From the above equation (3), the short circuit time (breakdown time) tp is expressed as the following equation (4).

tp = (ΔTj / M) ² × ((Id / S) × Vd) ⁻² Equation (4)

When a short circuit causes a large current to flow through the element and the element breaks down due to heat generated by the energy of voltage × current, assuming that the element breaks down at a certain critical temperature ΔTc, ΔTj = ΔTc (constant) is obtained. Is
tp = (ΔTc / M) ² × ((Id / S) × Vd) ⁻² Equation (5)
Thus, the short circuit time (breakdown time) tp is proportional to approximately −2 to the product of the drain current density (Id / S) and the drain voltage Vd at the time of the short circuit.

On the other hand, in the GaN-based HFET shown in the first embodiment, the short-circuit time (breakdown time) is calculated with respect to the product of the drain current density (Id / S) and the drain voltage Vd at the time of short-circuit by experiments under predetermined conditions. When tp is plotted, the graph shown in FIG. 4 is obtained. In FIG. 4, the vertical axis represents the short circuit time (breakdown time) tp [μsec], and the horizontal axis represents the power density (Id / S × Vd) [product of drain current density (Id / S) and drain voltage Vd]. kW / cm ² ].

If (Id / S × Vd) is a variable y and tp is a variable x, the relationship between x and y is
y = 7.70 × 10 ⁵ x− ^2.16
It is expressed by the approximate expression of

  As shown in FIG. 4, the short circuit time (breakdown time) tp was found to be approximately proportional to the −2 power. This indicates that the transistor element is short-circuit broken at a certain critical temperature. That is, the above formula (5) is established, and in order to improve the short circuit time (breakdown time) tp, reducing the power density ((Id / S) × Vd) is one means. It turns out that it is very effective.

Therefore, in the GaN HFET, for example, when the target value of the short circuit time (breakdown time) when the drain voltage is 400 V is set to 1 μsec (microseconds) or more, the drain current density (Id / S) and the drain voltage Vd when the load is short circuited. And the product (power density) range of 500 kW / cm ² or less, and when expressed in terms of drain current density (Id / S) at the time of short circuit, it is 5 × 10 ⁵ / Vd [A / cm ² ] or less. It is desirable.

  Further, the gate length Lg is defined by the width of the base portion 108a of the gate electrode 108 shown in FIG. 1, but as the gate length Lg increases, the saturation current can be reduced. In the range of ≧ 1 μm, it is desirable to set as large as possible in consideration of a trade-off relationship with on-resistance.

  As described above, in order to increase the short circuit time (breakdown time) tp, it is very important to suppress the heat generation during the short circuit, that is, to reduce the drain current (saturation current) during the short circuit.

  In the first embodiment, the GaN-based HFET using the Si substrate 101 has been described. However, the present invention is not limited to the Si substrate, and a sapphire substrate or SiC substrate may be used, and a nitride semiconductor is formed on the sapphire substrate or SiC substrate. A layer may be grown, or a nitride semiconductor layer may be grown on a substrate made of a nitride semiconductor, such as growing an AlGaN layer on a GaN substrate.

  Further, a buffer layer may be appropriately formed between the substrate and each layer.

  Further, an AlN layer having a thickness of about 1 nm may be formed as a hetero improvement layer between the undoped GaN layer 103 and the undoped AlGaN layer 104.

  Further, a GaN cap layer may be formed on the undoped AlGaN layer 104.

  For example, when heat is generated in the drain end region A shown in FIG. 5 when the load is short-circuited, heat conduction is performed toward the substrate side and the upper side as indicated by arrows, but in several microseconds to several tens of microseconds, heat conduction is performed. Is several μm to several tens of μm, and in particular, when there is a buffer layer 102 of a superlattice layer with poor thermal conductivity, heat dissipation on the substrate side is limited, so heat is generated and destruction due to heat generation becomes significant. .

When a thermal simulation was performed with a power density per unit area of 125 [kW / cm ² ] for a temperature increase after 10 microseconds, the number of buffer layers 102 was, for example, 160 (AlGaN layer and AlN layer respectively) In the case where the total thickness of the buffer layer 102 is 2.5 μm, it is 430 ° C., whereas when the number of layers of the buffer layer 102 is 80, 350 It was found that the temperature could be reduced to 0 ° C. (250 ° C. when there was no superlattice).

Therefore, according to the first embodiment, compared to the case where the number of layers of the buffer layer 102 is 160, the M value of the above equation (5) can be reduced to 350/430 = 0.81,
tp = (ΔTc / M) ² × ((Id / S) × Vd) ⁻² Equation (5)
Therefore, if the current density (Id / S), the drain voltage Vd, and the critical temperature ΔTc are the same, the short circuit time (destruction time) tp is proportional to (1 / M) ² , so the short circuit time (destruction time) is (1 / 0.81) ² = 1.52 times, which can be greatly improved.

Therefore, when the short circuit time (breakdown time) tp is plotted against the product (power density) of the drain current density (Id / S) and the drain voltage Vd at the time of short circuit, it is as shown in FIG. When the target value of time (breakdown time) is 1 μsec (microseconds) or more, the product (power density) range of drain current density (Id / S) and drain voltage Vd at the time of short circuit is 850 kW / cm ² or less It is good to. Moreover, it is preferably 8.5 × 10 ⁵ / Vd [A / cm ² ] or less in terms of drain current density (Id / S) at the time of short circuit.

In FIG. 6, the vertical axis represents the short circuit time (breakdown time) tp [μsec], and the horizontal axis represents the power density (Id / S × Vd) [product of the drain current density (Id / S) and the drain voltage Vd]. kW / cm ² ].

If (Id / S × Vd) is a variable y and tp is a variable x, the relationship between x and y is
y = 2.31 ^-6 x ^-2.16
It is expressed by the approximate expression of

(Second Embodiment)
FIG. 7 is a plan view of a GaN-based HFET as an example of the nitride semiconductor device according to the second embodiment of the present invention. The GaN HFET of the second embodiment has the same configuration as the GaN HFET of the first embodiment except for the layer thickness of the buffer layer which is a superlattice layer. In FIG. 7, 201 is a Si substrate, 202 is a buffer layer, 203 is an undoped GaN layer, 204 is an undoped AlGaN layer, 205a is a first insulating film, 205b is a second insulating film, 206 is a two-dimensional electron gas (2DEG), 207 is a source electrode, 207a is a source ohmic electrode, 207b is a source metal wiring, 208 is a gate electrode, 209 is a drain electrode, 209a is a drain ohmic electrode, 209b is a drain metal wiring, 210 is a gate insulating film, and 211 is a third insulating film Reference numeral 212 denotes an interlayer insulating film, 213 denotes a passivation film, and 214 denotes an interlayer insulating film.

  The first insulating film 205a and the second insulating film 205b constitute the insulating film 205.

  The buffer semiconductor layer 202, the undoped GaN layer 203, the undoped GaN layer 203, and the undoped AlGaN layer 204 constitute the nitride semiconductor layer 200. The buffer layer 202 has a thickness in the range of 0.3 μm to 1.5 μm.

  The nitride semiconductor layer 200, the insulating film 205, the source electrode 207, the gate electrode 208, the drain electrode 209, the gate insulating film 210, the third insulating film 211, and the interlayer insulating film 212 constitute a transistor element portion.

  The second embodiment is characterized in that the buffer layer 202 has a layer thickness of 0.3 μm to 1.5 μm.

  By setting the layer thickness of the buffer layer 202 to 0.3 μm to 1.5 μm, the withstand voltage between the source electrode 207 and the drain electrode 209 can be increased to 760V or more.

For a temperature increase after 10 microseconds, a thermal simulation was performed with a power density per unit area of 125 [kW / cm ² ]. As a result, the number of buffer layers 202 was 160 (AlGaN layers and AlN layers, for example). As a single layer, AlGaN / AlN is counted as a total of 2), and when the thickness of the buffer layer 202 is 2.5 μm, it is 430 ° C., whereas when the thickness of the buffer layer 202 is 1.5 μm, 330 It was found that the temperature could be reduced to 0 ° C. (250 ° C. when there was no superlattice).

Therefore, according to the second embodiment, compared to the case where the layer thickness of the buffer layer 202 is 2.5 μm, the M value of the above equation (5) can be reduced to 330/430 = 0.77,
tp = (ΔTc / M) ² × ((Id / S) × Vd) ⁻² Equation (5)
Therefore, if the current density (Id / S), the drain voltage Vd, and the critical temperature ΔTc are the same, the short circuit time (destruction time) tp is proportional to (1 / M) ² , so the short circuit time (destruction time) is (1 / 0.77) ² = 1.69 times, which can be greatly improved.

(Third embodiment)
FIG. 8 is a plan view of a GaN-based HFET as an example of the nitride semiconductor device according to the third embodiment of the present invention. The GaN HFET of the third embodiment has the same configuration as the GaN HFET of the first embodiment except for the configuration of the buffer layer that is a superlattice layer. 8, 301 is a Si substrate, 302 is a buffer layer, 303 is an undoped GaN layer, 304 is an undoped AlGaN layer, 305a is a first insulating film, 305b is a second insulating film, 306 is a two-dimensional electron gas (2DEG), 307 is a source electrode, 307a is a source ohmic electrode, 307b is a source metal wiring, 308 is a gate electrode, 309 is a drain electrode, 309a is a drain ohmic electrode, 309b is a drain metal wiring, 310 is a gate insulating film, and 311 is a third insulation. 312 is an interlayer insulating film, 313 is a passivation film, and 314 is an interlayer insulating film.

  The first insulating film 305a and the second insulating film 305b constitute the insulating film 305.

  The buffer semiconductor layer 302, the undoped GaN layer 303, the undoped GaN layer 303, and the undoped AlGaN layer 304 constitute a nitride semiconductor layer 300.

  The nitride semiconductor layer 300, the insulating film 305, the source electrode 307, the gate electrode 308, the drain electrode 309, the gate insulating film 310, the third insulating film 311, and the interlayer insulating film 312 constitute a transistor element portion.

  The third embodiment is characterized in that the product of the layer thickness of the buffer layer 302 and the average Al composition ratio of the buffer layer 302 is not less than 5 μm% and not more than 30 μm%.

  By setting the product of the layer thickness of the buffer layer 302 and the average Al composition ratio of the buffer layer 302 to 5 μm% or more and 30 μm% or less, the withstand voltage between the source electrode 307 and the drain electrode 309 is set to 780 V or more. Can do.

When a thermal simulation was performed with a power density of 125 [kW / cm ² ] per unit area for a temperature increase after 10 microseconds, the number of buffer layers 302 was, for example, 160 (AlGaN layer and AlN layer respectively) In the case where the layer thickness of the buffer layer 302 is 2.5 μm, it is 430 ° C., while the layer thickness of the buffer layer 302 and the average Al composition of the buffer layer 302 are one layer. It was found that when the product with the ratio is 30 μm%, the temperature can be reduced to 290 ° C. (250 ° C. when there is no superlattice).

Therefore, according to the third embodiment, compared with the case where the layer thickness of the buffer layer 302 is 2.5 μm, the M value of the above equation (5) can be reduced to 290/430 = 0.67,
tp = (ΔTc / M) ² × ((Id / S) × Vd) ⁻² Equation (5)
Therefore, if the current density (Id / S), the drain voltage Vd, and the critical temperature ΔTc are the same, the short circuit time (destruction time) tp is proportional to (1 / M) ² , so the short circuit time (destruction time) is (1 / 0.67) ² = 2.23 times, which can be greatly improved.

(Fourth embodiment)
FIG. 9 is a plan view of a GaN-based HFET as an example of the nitride semiconductor device according to the fourth embodiment of the present invention. The GaN-based HFET of the fourth embodiment has the same configuration as the GaN-based HFET of the first embodiment except for the heat dissipation portion. In FIG. 7, 401 is an Si substrate, 402 is a buffer layer, 403 is an undoped GaN layer, 404 is an undoped AlGaN layer, 405a is a first insulating film, 405b is a second insulating film, 406 is a two-dimensional electron gas (2DEG), 407 is a source electrode, 407a is a source ohmic electrode, 407b is a source metal wiring, 408 is a gate electrode, 409 is a drain electrode, 409a is a drain ohmic electrode, 409b is a drain metal wiring, 410 is a gate insulating film, 411 is a third insulating film 412 is an interlayer insulating film, 413 is a passivation film, and 414 is an interlayer insulating film.

  The first insulating film 405a and the second insulating film 405b constitute an insulating film 405.

  Further, the buffer semiconductor layer 402, the undoped GaN layer 403, the undoped GaN layer 403, and the undoped AlGaN layer 404 constitute a nitride semiconductor layer 400.

  The nitride semiconductor layer 400, the insulating film 405, the source electrode 407, the gate electrode 408, the drain electrode 409, the gate insulating film 410, the third insulating film 411, and the interlayer insulating film 412 constitute a transistor element portion.

  As shown in FIG. 7, the fourth embodiment includes a drain electrode 409 and a source electrode 407 on the upper surface of the nitride semiconductor layer 400, and further via an interlayer insulating film 414 or a through hole (not shown). A metal wiring 415 is provided on the upper surface. The metal wiring 415 is an example of a heat dissipation part.

  As a result, the heat generated at the drain end when the load is short-circuited is dissipated to the metal wiring 415 via the interlayer insulating film 414 or the through hole (not shown), thereby improving the heat dissipation when the load is short-circuited. The M value in the equation (5) can be reduced, and the short circuit time (breakdown time) tp can be improved.

  Obviously, this effect does not change when applied to any of the first to third embodiments.

  As described above, according to the present invention, it is possible to significantly improve the short-circuit time (breakdown time) by reducing the energy generated at the time of short-circuiting, improving the critical temperature at the time of short-circuit breakdown, and improving heat dissipation.

In the first to fourth embodiments, the nitride semiconductor layers 100, 200, 300, and 400 are composed of GaN layers or AlGaN layers, but Al _x In _y Ga _1-xy N (x ≧ 0, y It may include a GaN-based semiconductor layer represented by ≧ 0, 0 ≦ x + y <1). That is, the nitride semiconductor layers 100, 200, 300, and 400 may include AlGaN, GaN, InGaN, or the like. In the first to fourth embodiments, the normally-on type HFET has been described, but the same effect can be obtained even in a normally-off type.

  In the first to fourth embodiments, the silicon oxide film is used as the material of the insulating films 105, 205, 305, and 405. However, a silicon nitride film, polyimide, or SOG (Spin On Glass) is used. Alternatively, an insulating material such as BPSG (Boron Phosphorus Silicon Glass) may be used. Further, for example, a multilayer film structure including a silicon oxide film and a silicon nitride film may be used.

  In the first to fourth embodiments, the transistor element unit is configured such that the power density, which is the product of the drain current density and the drain voltage when the load is short-circuited, is equal to or lower than the predetermined power density. The power density may be appropriately set according to the configuration of the transistor element portion of the nitride semiconductor device, the drain voltage, the target value of the short circuit time (breakdown time), and the like.

  Although specific embodiments of the present invention have been described, the present invention is not limited to the first to fourth embodiments, and various modifications can be made within the scope of the present invention. For example, what combined suitably the content described in the said 1st-4th embodiment is good also as one Embodiment of this invention.

  The present invention and the embodiments are summarized as follows.

The nitride semiconductor device of the present invention is
A nitride semiconductor layer 100, 200, 300, 400 having a heterostructure including channel layers 103, 203, 303, 403, barrier layers 104, 204, 304, 404 and superlattice layers 102, 202, 302, 402;
Source electrodes formed at least partially on nitride semiconductor layer 100, 200, 300, 400 or in nitride semiconductor layer 100, 200, 300, 400 and spaced from each other 107,207,307,407 and drain electrodes 109,209,309,409,
Insulating films 105, 205, 305, formed between the source electrodes 107, 207, 307, 407 and the drain electrodes 109, 209, 309, 409 and on the nitride semiconductor layers 100, 200, 300, 400 405,
Gate electrodes 108, 208, 308, formed between the source electrodes 107, 207, 307, 407 and the drain electrodes 109, 209, 309, 409 and on the nitride semiconductor layers 100, 200, 300, 400, respectively. 408 and a transistor element portion,
The transistor element portion is configured such that a power density that is a product of a drain current density and a drain voltage when a load is short-circuited is equal to or lower than a predetermined power density,
The superlattice layers 102, 202, 302, and 402 are configured such that the withstand voltage between the source electrodes 107, 207, 307, and 407 and the drain electrodes 109, 209, 309, and 409 is equal to or higher than a predetermined voltage. It is characterized by.

  According to the nitride semiconductor device of the present invention, the transistor element portion is configured such that the power density, which is the product of the drain current density and the drain voltage when the load is short-circuited, is equal to or lower than the predetermined power density. The superlattice layer is configured so that the withstand voltage between the electrodes is equal to or higher than a predetermined voltage. For this reason, while ensuring the breakdown voltage characteristics between the source electrodes 107, 207, 307, and 407 and the drain electrodes 109, 209, 309, and 409, reducing the energy applied to the transistor element portion at the time of short circuit, the heat generation of the element The amount can be reduced, the short circuit tolerance can be improved, and the reliability of the element can be improved.

In the nitride semiconductor device of one embodiment,
The barrier layers 104, 204, and 304 have a layer thickness of 30 nm or less.

  According to the above embodiment, by setting the thickness of the barrier layers 104, 204, and 304 to 30 nm or less, the threshold voltage is lowered and the saturation current can be reduced, so that the energy generated at the time of a short circuit can be reduced.

In the nitride semiconductor device of one embodiment,
The number of layers constituting the superlattice layers 102, 202, 302, 402 is 20 or more and 80 or less.

  According to the above embodiment, the number of layers constituting the superlattice layers 102, 202, 302, 402 is 20 or more and 80 or less, whereby the source electrodes 107, 207, 307, 407 and the drain electrodes 109, 209, The short circuit time (breakdown time) can be improved while setting the withstand voltage between 309 and 409 to 800 V or higher.

In the nitride semiconductor device of one embodiment,
The superlattice layers 102, 202, 302, 402 have a layer thickness of 0.3 μm or more and 1.5 μm or less.

  According to the embodiment described above, the layer thicknesses of the superlattice layers 102, 202, 302, 402 are 0.3 μm or more and 1.5 μm or less, whereby the source electrodes 107, 207, 307, 407 and the drain electrodes 109, The short circuit time (breakdown time) can be improved while setting the withstand voltage between 209, 309, and 409 to 760 V or higher.

In the nitride semiconductor device of one embodiment,
The superlattice layers 102, 202, 302, 402 include AlGaN,
The product of the layer thickness of the superlattice layers 102, 202, 302, 402 and the average Al composition ratio of the superlattice layers 102, 202, 302, 402 is 5 μm% or more and 30 μm% or less.

  According to the above embodiment, the product of the layer thickness of the superlattice layers 102, 202, 302, 402 and the average Al composition ratio of the superlattice layers 102, 202, 302, 402 is set to 5 μm% or more and 30 μm% or less. Thus, the short-circuit time (breakdown time) can be improved while the withstand voltage between the source electrodes 107, 207, 307, and 407 and the drain electrodes 109, 209, 309, and 409 is set to 780 V or higher.

In the nitride semiconductor device of one embodiment,
There is no superlattice layer in the nitride semiconductor layer 1300, the breakdown time when the load is short-circuited is 1 microsecond or more when the drain voltage is 400 V, and the drain current density and drain voltage when the load is short-circuited And the power density is 850 kW / cm ² or less.

In the nitride semiconductor device of one embodiment,
On the nitride semiconductor layer 400 on which the drain electrode 409 and the source electrode 407 are disposed, a heat radiation portion 415 formed through an interlayer insulating film 414 is provided.

  According to the embodiment, the heat generated at the drain end when the load is short-circuited is dissipated to the heat radiating portion 415, so that the heat dissipation when the load is short-circuited is improved, so that the short-circuit time (breakdown time) can be improved.

100, 200, 300, 400 Nitride semiconductor layer 101, 201, 301, 401 Si substrate 102, 202, 302, 402 Buffer layer 103, 203, 303, 403 Undoped GaN layer 104, 204, 304, 404 Undoped AlGaN layer 105 , 205, 305, 405 Insulating film 106, 206, 306, 406 Two-dimensional electron gas 107, 207, 307, 407 Source electrode 108, 208, 308, 408 Gate electrode 109, 209, 309, 409 Drain electrode 108a, 208a, 309a, 409a Base part 108b, 208b, 309b, 409b Gate field plate part 110, 210, 310, 410 Gate insulating film 105a, 205a, 305a, 405a First insulating film 105b, 205b, 305b, 405b Second insulating film 111, 211 , 311, 411 Third insulating film 112, 2 2,312,412 interlayer insulating film 113,213,313,413 passivation film 114,214,314,414,514 interlayer insulating film 415 metal wires

Claims (5)

A nitride semiconductor layer having a heterostructure including a channel layer, a barrier layer, and a superlattice layer;
A source electrode and a drain electrode which are formed on the nitride semiconductor layer or in the nitride semiconductor layer and spaced apart from each other;
An insulating film formed between the source electrode and the drain electrode and on the nitride semiconductor layer;
A transistor element portion having a gate electrode formed between the source electrode and the drain electrode and on the nitride semiconductor layer;
The transistor element portion is configured such that a power density that is a product of a drain current density and a drain voltage when a load is short-circuited is equal to or lower than a predetermined power density,
The nitride semiconductor device, wherein the superlattice layer is configured such that a breakdown voltage between the source electrode and the drain electrode is equal to or higher than a predetermined voltage. The nitride semiconductor device according to claim 1,
The nitride semiconductor device, wherein the number of layers constituting the superlattice layer is 20 or more and 80 or less. The nitride semiconductor device according to claim 1,
A nitride semiconductor device, wherein the superlattice layer has a layer thickness of 0.3 μm or more and 1.5 μm or less. The nitride semiconductor device according to claim 1,
The superlattice layer includes AlGaN,
A nitride semiconductor device, wherein a product of a thickness of the superlattice layer and an average Al composition ratio of the superlattice layer is 5 μm% or more and 30 μm% or less. In the nitride semiconductor device according to any one of claims 1 to 4,
A nitride semiconductor device comprising: a heat radiating portion formed through an interlayer insulating film on the nitride semiconductor layer on which the drain electrode and the source electrode are disposed.

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