JP2016111354A - Semiconductor template substrate for led, and led element using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor template substrate for LEDs excellent in flatness by planarizing a substrate having a fine uneven structure in growing a first semiconductor on the substrate.SOLUTION: A semiconductor template substrate (80) for LEDs includes a base substrate (10) including an uneven structure (20) comprising a plurality of projecting portions (21) with an array of substantially n-fold symmetry and a flat portion (22) on at least a part of a main surface, and a first semiconductor layer (30) formed on the uneven structure. An average pattern gap (PGave) between the projecting portions satisfies 5 nm<PGave<400 nm, an average pitch (Pave) between projecting portions most adjacent to each other among the plurality of projecting portions satisfies 50 nm<Pave≤1,800 nm, and an angle (Θ) between an array axis (La) of the plurality of projecting portions and a crystal growth axis (Lb) of the first semiconductor layer satisfies 70°<Θ≤90°.SELECTED DRAWING: Figure 8

Description

  The present invention relates to a semiconductor template substrate for LED having excellent flatness, and an LED element using the same.

A GaN (gallium nitride) based semiconductor element typified by a blue LED is manufactured by laminating an n-type first semiconductor, a light emitting layer, and a p-type first semiconductor on a single crystal substrate such as sapphire by epitaxial growth. However, for example, there is a large difference in lattice constant between sapphire and GaN, and threading dislocations are generated by this lattice mismatch (see, for example, Non-Patent Document 1). The dislocation density reaches 1 × 10 ⁹ pieces / cm ² . It is known that this dislocation reduces the internal quantum efficiency inside the LED, resulting in a decrease in the light emission efficiency of the LED.

  In addition, since the refractive index of the GaN-based semiconductor layer is larger than that of the sapphire substrate, the light generated in the semiconductor light emitting layer does not emit from the interface with the sapphire substrate at an angle greater than the critical angle, and enters the light guide mode. As a result, the external quantum efficiency is lowered.

  In view of this, a technique has been proposed in which concavities and convexities are provided on the substrate in order to suppress dislocations generated in the semiconductor and change the light guiding direction in the semiconductor layer to increase the external quantum efficiency (see, for example, Patent Document 1). ).

  In addition, a sapphire substrate in which the size of the concavo-convex structure provided on the substrate is nano-sized and the pattern of the concavo-convex structure is randomly arranged has been proposed (for example, see Patent Document 2). In addition, it has been reported that by making the pattern size provided on the substrate nano-sized, the light emission efficiency of the LED is improved as compared with the case of the micro-sized pattern (for example, see Non-Patent Document 2). Processing time can be shortened.

  Apart from these, when a blue light emitting diode is produced by vapor-depositing a semiconductor layer on a sapphire substrate, a GaN-based or AlN (aluminum nitride) -based buffer is generally used on the sapphire substrate. After forming the layer in the range of several nm to several hundred nm, an undoped GaN layer and / or an n-type semiconductor GaN layer doped with Si or the like is formed as the first semiconductor, and then the light emitting layer And the remaining LED layer structure including the p-type semiconductor layer is deposited. However, since the light emitting layer is an extremely thin layer on the order of nanometers, if the surface flatness of the first semiconductor, which is the foundation for forming the light emitting layer, is low, the thickness and composition of the light emitting layer are disturbed, resulting in leakage current. It is conceivable that the basic LED characteristics such as

  From the above, in the case of LEDs, a technique for growing a first semiconductor layer with higher flatness on a substrate having a fine concavo-convex structure is desired. In particular, when the concavo-convex structure is nano-sized, the growth process of the first semiconductor is expected to be complicated, but such a detailed report has not been made.

JP 2003-318441 A JP 2007-294972 A

IEEE photo. Tech. Lett. , 20, 13 (2008) J. et al. Appl. Phys. , 103, 014314 (2008)

  This invention is made | formed in view of this subject, and when growing a 1st semiconductor on the board | substrate which has a fine concavo-convex structure, it aims at providing the semiconductor template substrate for LED excellent in surface flatness. And It is another object of the present invention to provide an LED element having a high light emission output and a small leakage current when Ir, that is, reverse bias is applied, using the LED semiconductor template substrate of the present invention.

  The LED semiconductor template substrate according to the present invention includes a base substrate having a concavo-convex structure including a plurality of convex portions and flat portions having a substantially n-fold symmetric arrangement on at least a part of a main surface, and the concavo-convex structure. A first semiconductor layer formed thereon, an average pattern gap (PGave) between the protrusions is 5 nm <PGave <400 nm, and between the adjacent protrusions of the plurality of protrusions The average pitch (Pave) is 50 nm <Pave ≦ 1800 nm, and the angle (Θ) formed by the arrangement axis (La) of the plurality of convex portions and the crystal growth axis (Lb) of the first semiconductor layer is 70 It is characterized by satisfying ° <Θ ≦ 90 °.

  Thus, in a predetermined range of Pave, the range of the average pattern gap (PGave) between the protrusions of the base substrate, the array axis (La) of the plurality of protrusions, and the crystal growth axis ( By optimizing the range of the angle (Θ) formed with Lb), the flatness of the surface of the LED semiconductor template substrate can be enhanced.

  In the present invention, the average pattern gap (PGave) is preferably 25 nm ≦ PGave ≦ 300 nm.

  Moreover, in this invention, it is preferable that the average pitch (Pave) between the convex parts nearest to the said several convex part is 300 nm <= Pave <= 1800 nm.

  In the present invention, the ratio (Bave / Pave) between the average diameter (Bave) of the convex portions and the average pitch (Pave) between the convex portions in the plurality of convex portions is 0.60 ≦ (Bave / Pave) ≦ It is preferable to satisfy 0.96.

  Moreover, in this invention, it is preferable that the top part of the said convex part is a corner | angular part with a curvature radius over 0.

  In the present invention, it is preferable that the n-fold n is n = 3, n = 4, or n = 6.

  In the present invention, it is preferable that the base substrate is made of sapphire, silicon, silicon carbide, gallium nitride, aluminum nitride, or graphite.

  Moreover, in this invention, it is preferable that the material of the said base substrate is sapphire and the main surface of the said base substrate is c surface.

  In the present invention, it is preferable that the first semiconductor layer is formed of a III-V group semiconductor.

  In the present invention, it is preferable that the first semiconductor layer is formed of a hexagonal crystal containing Ga and N.

  In addition, the LED element of the present invention is manufactured using the above-described semiconductor template substrate for LED. By using the LED semiconductor template substrate of the present invention, the light emission output of the LED element can be improved and Ir can be reduced.

  ADVANTAGE OF THE INVENTION According to this invention, when producing the semiconductor template substrate for LED using the board | substrate which has a fine uneven structure, the flatness of the semiconductor template substrate surface can be improved. Further, by using the LED semiconductor template substrate of the present invention, the light emission output of the LED element can be improved and Ir can be reduced.

It is explanatory drawing of the convex part which has an n times symmetrical arrangement | sequence based on this Embodiment. It is explanatory drawing of the 1st semiconductor growth initial stage on the base substrate of FIG. 1C. It is explanatory drawing of the convex part arrangement | sequence axis | shaft (La) which concerns on this Embodiment. It is explanatory drawing of the crystal growth axis (Lb) of the 1st semiconductor layer which concerns on this Embodiment. It is explanatory drawing of the angle ((theta)) which La and Lb which concern on this Embodiment form. It is explanatory drawing of (theta) at the time of using the base substrate which comprises the uneven structure which has a 6 times symmetrical arrangement | sequence which concerns on this Embodiment. It is explanatory drawing of (theta) at the time of using the base substrate which comprises the uneven structure which has a 4-fold symmetrical arrangement | sequence which concerns on this Embodiment. It is a section schematic diagram of a semiconductor template substrate for LED concerning this embodiment. It is the cross-sectional schematic of the LED element which concerns on this Embodiment.

  Hereinafter, embodiments of the present invention (hereinafter abbreviated as “embodiments”) will be described in detail. In addition, this invention is not limited to the following embodiment, It can implement by changing variously within the range of the summary. Definitions relating to symbols (PGave, Pave, Have, Bave, Θ, La, Lb, Asave, and Duty) used in this specification will be described later.

  The LED semiconductor template substrate according to the present embodiment includes, on at least a part of the main surface, a base substrate having a concavo-convex structure including a plurality of convex portions and flat portions having a substantially n-fold symmetrical arrangement, A first semiconductor layer formed on the concavo-convex structure.

  The first semiconductor layer according to the present embodiment is thicker than the average convex portion height (Have) directly on the base substrate or through a buffer layer having a thickness less than the average convex portion height (Have). This means a growing semiconductor layer, and the base substrate on which the first semiconductor layer is formed is referred to as a semiconductor template substrate. In addition, the 1st semiconductor which concerns on this Embodiment shall point out the semiconductor which forms said 1st semiconductor layer.

Hereinafter, the contents relating to the present invention will be subdivided and described in detail.
<Uneven structure>
The concavo-convex structure according to the present embodiment has a plurality of convex portions having a substantially n-fold symmetric arrangement and a flat portion on at least a part of the main surface of the base substrate. Here, the position of the concave portion corresponds to the flat portion when viewed from the convex portion. The flat portion is preferably a single crystal plane parallel to the main surface of the base substrate, which is effective in obtaining a semiconductor template substrate having a flat surface. In addition, it is preferable that the plurality of protrusions are independent from the viewpoint of uniformly growing the first semiconductor in the gap between adjacent protrusions.

  Moreover, in this Embodiment, although the average pattern gap (PGave) between convex parts is made into the value larger than 5 nm and smaller than 400 nm, the reason is mentioned later.

<N-fold symmetrical arrangement>
The “n-fold symmetry” according to the present embodiment means “rotation symmetry”. For this reason, n is a positive integer of 2 or more. The rotational symmetry of the plurality of convex portions can be confirmed by observing the surface with a scanning electron microscope (SEM), an atomic force microscope, or the like. For example, the plurality of convex portions having an n-fold symmetric arrangement are the same convexity arrangement before and after the rotation when rotated by (360 / n) ° about an axis perpendicular to the base substrate, or , Refers to having the property of overlapping other array axes. Here, the “substantially n-fold symmetric arrangement” means not only the arrangement of convex portions that are completely the same before and after rotation when rotated (360 / n) around an axis perpendicular to the base substrate. In addition, a convex arrangement that deviates within ± 15 ° before and after rotation is also included.

  The present invention is characterized in that an angle (Θ) formed by an array axis (La) of the plurality of convex portions and a crystal growth axis (Lb) of the first semiconductor layer is 70 ° <Θ ≦ 90 °.

  Since the effect of the present invention can be obtained by adjusting the angle (Θ) formed in this way, it is necessary that the plurality of convex portions substantially have n-fold symmetry. FIG. 1 is an explanatory diagram of convex portions having an n-fold symmetrical arrangement according to the present embodiment. FIG. 1A shows an example of a convex portion having a three-fold symmetric arrangement, FIG. 1B shows an example of a convex portion having a four-fold symmetric arrangement, and FIG. 1C shows an example of a convex portion having a six-fold symmetric arrangement. 1 indicates a base substrate, 2 indicates a convex portion, and 3 indicates a flat portion.

<Convex shape>
The convex shape of the base substrate according to the present embodiment is such that the area of the flat portion at the bottom of the convex portion is larger than the area of the top of the convex portion from the viewpoint of efficiently forming the growth nuclei of the first semiconductor on the flat portion of the base substrate. Larger is preferred.

  Moreover, it is preferable that the convex part top part is a corner | angular part whose curvature radius is more than zero. Here, the corner having a radius of curvature exceeding 0 means that the top of the convex portion is formed of a curved surface. For example, a cone-shaped body, a lens-shaped body, a dome-shaped body, and a shell body with rounded tips are included. In addition, when the side surface of the convex portion is observed, it is preferable that the side surface is curved so as to swell from the top portion of the convex portion to the bottom portion of the convex portion, and the inclination angle of the side surface is changed in multiple stages. Since the side surface bulges and curves, the side surface of the convex portion is less exposed to the same crystal plane, and the growth of the first semiconductor is preferentially grown from the flat portion of the concavo-convex structure. Is easy to obtain. Even if the top of the convex portion of the concavo-convex structure is a flat surface, i.e., a table top shape, the effect of improving the flatness in the present invention is obtained. However, in the case of a table top, the first semiconductor has a convex surface and a convex surface at the bottom of the convex portion. It grows from both the flat surfaces of the top portions, and the variation in the growth height of the first semiconductor in the direction perpendicular to the base substrate surface becomes large. Therefore, from the viewpoint of obtaining a semiconductor template substrate with higher flatness, the shape of the top of the convex portion is preferably a corner having a radius of curvature exceeding 0 (see FIG. 8 described later).

In addition, if the area of the flat surface of the top of the convex portion of the table top is small, the amount of growth of the first semiconductor that grows from the flat surface of the top of the convex portion inevitably decreases, so the first in the direction perpendicular to the base substrate surface. Since variation in the growth height of the semiconductor is suppressed and flattening is facilitated, when a base substrate having a convex portion of the table top is used, the area of the individual convex portion top portions may be 7850 nm ² or less. More preferably, it is preferably 1962 nm ² or less.

  As an example of the bottom shape of the convex portion of the concavo-convex structure according to the present embodiment, when the convex portion is observed from the upper part of the main surface of the base substrate, an n-gon (n ≧ 3) and an n-gon with rounded corners (n ≧ 3) 3), shapes such as a circle, an ellipse, a line, a star, and a lattice. In particular, the shape of the bottom of the convex portion is preferably circular from the viewpoint of uniformly growing the first semiconductor from the flat portion of the bottom of the convex portion toward the in-plane direction of the base substrate. Similarly, examples of the shape of the flat part of the top of the convex part of the table top include an n-gon (n ≧ 3), an n-corner with a rounded corner (n ≧ 3), a circle, an ellipse, a line, a star, and a lattice And the like.

<Average pitch between protrusions (Pave)>
In the base substrate according to the present embodiment, it is preferable that the average pitch (Pave) between the adjacent convex portions of the concavo-convex structure on the base substrate satisfies 50 nm <Pave ≦ 1800 nm. From the viewpoint of producing a stable convex shape, Pave is preferably larger than 50 nm, more preferably 100 nm or more, further preferably 200 nm or more, and most preferably 300 nm or more. Further, as will be described later, the present invention can obtain the effect of improving flatness by controlling the angle (Θ) formed by La and Lb in the range where PGave is larger than 5 nm and smaller than 400 nm. Further, when PGave is constant, it means that the ratio of the flat portion on the main surface of the base substrate decreases as Pave increases. Therefore, Pave is preferably 1800 nm or less from the viewpoint of securing a flat portion for good nucleus growth of the first semiconductor on the base substrate and improving flatness.

The average pitch (Pave) is calculated according to the following definition. Among the plurality of convex portions on the base substrate, (1) arbitrary 30 convex portions A1, A2,... A30 are selected. (2) The distance P _AMBM between the tops of the convex portions (BM) closest to the convex portions AM (1 ≦ M ≦ 30) is measured (see, for example, FIG. 1). (3) For the convex portions A1 to A30, the interval P is measured as in (2). (4) An arithmetic average value of the intervals P _{A1B1 to} P _A30B30 is defined as an average pitch (Pave).

<Average pattern gap between convex parts (PGave)>
The average pattern gap (PGave) between the most adjacent convex portions according to the present specification is defined as a difference (Pave−Bave) between the average pitch (Pave) and a convex portion bottom average diameter (Bave) described later. At this time, PGave <Pave. The pattern gap (PG) itself refers to, for example, the portion shown in FIG. 1, but the averaged pattern gap obtained by the above definition is used as the average pattern gap (PGave) between the convex portions in the present embodiment.

  The base substrate according to the present embodiment includes at least a plurality of convex portions and a flat portion, and an average pattern gap (PGave) between the adjacent convex portions among the plurality of convex portions is larger than 5 nm and 400 nm. It is characterized by a smaller value. The reason will be described together with the following specific examples.

  FIG. 2 is an explanatory diagram of an initial stage of first semiconductor growth on the base substrate of FIG. 1C. As an example, as shown in FIG. 2, a simple hexagonal pattern is formed on a base substrate 1 having a concavo-convex structure composed of a plurality of convex portions (dots arranged in a regular hexagon) 2 having a sixfold symmetry and flat portions 3. When the first semiconductor 4 having a growth unit of the Bravey lattice is vapor-phase grown, if the same single crystal plane is continuously exposed in the flat portion 3, the exposed area of the flat portion 3 as shown in FIG. The first semiconductor 4 grows preferentially from the large region. When a plurality of island-like first semiconductors 4 growing from the flat portion 3 are to be associated with each other to form a first semiconductor layer, the convex portions 2 are formed by the space between the plurality of adjacent convex portions 2 being too narrow. From the viewpoint of preventing the uniform growth of the first semiconductor layer in the surface of the base substrate in the steric hindrance and obtaining a highly flat semiconductor template substrate, PGave is preferably greater than 5 nm, more preferably It is 10 nm or more, More preferably, it is 25 nm or more, More preferably, it is 29 nm or more.

  In addition, when PGave is large, the first semiconductor 4 easily grows between the adjacent convex portions 2, so that the influence of steric hindrance due to the convex portions 2 can be reduced. Therefore, from the viewpoint of obtaining an effect of improving flatness by controlling an angle (Θ) formed between La and Lb, which will be described later, PGave is preferably a value smaller than 400 nm, and more preferably 300 nm or less. In addition, the smaller the PGave, the larger the area ratio of the convex portion of the concavo-convex structure (convex portion and flat portion) on the base substrate. Therefore, from the viewpoint of increasing the light extraction efficiency of the LED, the PGave is 300 nm. The following is more preferable.

<Average aspect ratio of protrusions (ASave)>
The average aspect ratio (ASave) of the plurality of convex portions on the base substrate is preferably 0.1 or more and 5.0 or less. Asave in the present specification is defined as a value obtained by dividing the average height of the convex portion (Have) by the average diameter of the convex portion bottom (Bave).

  The measurement method of Asave is to observe 30 points of arbitrary convex parts on the base substrate by cross-sectional SEM observation, measure 30 points from the base substrate main surface flat part to the convex part top part, and the arithmetic mean value thereof Is the average height of convex portions (Have). Also, arbitrary convex portions on the base substrate are observed from the top surface of the base substrate main surface by plane SEM observation at 30 points, the diameter of the circumscribed circle with respect to the bottom of each convex portion is measured at 30 points, and the arithmetic average value is calculated. , And convex portion bottom average diameter (Bave). The unit of Have and Bave is both nm.

  First, since the ASave is 0.1 or more, the volume of the convex portion seen from the photons generated from the light emitting layer is increased. Therefore, when the semiconductor template substrate in the present embodiment is applied to an LED, light extraction is performed. Efficiency LEE can be improved. In particular, it is preferable that ASave is 0.3 or more because the number of modes of light diffraction with respect to emitted light can be increased and the scattering property can be enhanced. From the same viewpoint, ASave is more preferably 0.4 or more, and most preferably 0.5 or more. On the other hand, the inclination angle of the side surface of the convex portion can be managed small by setting ASave to 5.0 or less. This makes it easy to grow the first semiconductor layer between adjacent convex portions, and it can be considered that particles generated when the convex portions are detached from the base substrate when obtaining the LED element can be suppressed. . For the same reason, ASave is preferably 3.0 or less, more preferably 2.0 or less, and most preferably 1.1 or less.

<Duty of uneven structure>
As a ratio of the convex portion and the flat portion on the base substrate, a ratio (Bave / Pave) between the convex portion bottom average diameter (Bave) and the average pitch (Pave) between the adjacent convex portions is defined as Duty. When an LED element is manufactured using the semiconductor template substrate according to the present embodiment, it is necessary to disturb the mode of the emitted light to be guided in order to improve the light extraction efficiency LEE. Here, considering that the traveling direction of the emitted light is effectively disturbed, the waveguide mode is destroyed, and the light extraction efficiency LEE is improved, the duty is preferably larger than a predetermined value. In addition, since the present invention makes it possible to obtain a semiconductor template substrate with high flatness by facilitating crystal growth of the first semiconductor between extremely narrow convex portions on the base substrate, PGave is larger than 5 nm. As long as the duty is larger within a range satisfying the condition of less than 400 nm, an effect of improving flatness by controlling an angle (Θ) formed by La and Lb described later can be obtained.

  For the above reasons, the duty is preferably 0.55 or more, more preferably 0.60 or more, still more preferably 0.70 or more, and most preferably 0.80 or more. Further, when Pave is constant, the ratio of the flat portion in the base substrate decreases as Duty increases. As a result, when the first semiconductor layer is crystal-grown, it becomes difficult to take over the crystal orientation of the flat portion serving as a base, and the crystal orientation is likely to be disturbed, so that flattening becomes difficult. Accordingly, from the viewpoint of achieving good crystal growth between the narrow protrusions on the base substrate and flattening, the duty is preferably 0.96 or less, more preferably 0.95 or less. More preferably, it is 0.94 or less.

<Angle (Θ) formed by La and Lb>
The angle (Θ) formed by the arrangement axis (La) of the plurality of convex portions according to the present embodiment and the crystal growth axis (Lb) of the first semiconductor layer grown on the base substrate is 70 ° <Θ ≦ 90. By arranging the plurality of convex portions so as to be at an angle, an LED semiconductor template substrate with high surface flatness can be obtained. Then, by manufacturing an LED element using the semiconductor template substrate according to the present embodiment, an LED element having a high light emission output and capable of suppressing Ir can be obtained.

<Arrangement axis (La) of a plurality of convex portions>
The arrangement axis (La) of the plurality of protrusions according to the present embodiment is the distance between the tops of the most adjacent protrusions among the plurality of protrusions having the n-fold symmetry array formed on the base substrate. It is defined as an axis connected in a direction parallel to the main surface of the base substrate. FIG. 3 is an explanatory diagram of the convex portion arrangement axis (La) according to the present embodiment. As an example, FIG. 3A shows a base substrate 1 having a plurality of convex portions 2 having a six-fold symmetry arrangement (regular hexagonal arrangement) on the surface, and an arrangement axis La is described. In this case, there are three arrangement axes of the convex portions 2 of La-1, La-2, and La-3 with respect to the specific convex portion 2. Further, FIG. 3B illustrates the base substrate 1 having a plurality of convex portions 2 having a four-fold symmetry on the surface, and the arrangement axis La is described. In this case, the array axis of the two convex portions 2 of La-1 and La-2 exists for the specific convex portion.

<Crystal growth axis (Lb) of first semiconductor>
The crystal growth axis (Lb) of the first semiconductor grown on the base substrate according to the present embodiment will be described. In general, a crystal has seven crystal systems (triclinic, monoclinic, orthorhombic, hexagonal, trigonal, tetragonal, cubic) focusing on point symmetry of the lattice and 14 Bravais lattices ( Simple triclinic, simple monoclinic, bottom-centered monoclinic, simple oblique, body-centered oblique, face-centered oblique, bottom-centered oblique, simple hexagonal, simple rhombohedral, simple square, body-centered square, simple cube, body Center cube, face center cube). Therefore, when the first semiconductor crystal grows on the base substrate, the first semiconductor grows on the base substrate using one of the 14 types of Bravay lattices as a crystal growth unit.

  The definition of the crystal growth axis (Lb) of the first semiconductor layer in this specification is described below. First, focusing on the first semiconductor Bravai lattice grown on the base substrate, n points (n is an integer of 3 to 6) Brabé lattice present in a plane substantially parallel to the crystal plane of the main surface of the base substrate. Connect the vertices to create an n-gon. At this time, the vertices are connected so that the area of the n-gon is maximized. Thereafter, straight lines that bisect each of the n corners of the n-gon are drawn in a plane substantially parallel to the crystal plane of the main surface of the base substrate, and the straight line is defined as a crystal growth axis (Lb) in this specification. From the viewpoint of controlling the crystal growth axis (Lb) of the first semiconductor and the array axis (La) of the plurality of protrusions to a predetermined angle, the Bravay lattice is hexagonal in order to correspond to the rotational symmetry of the protrusion array. It is preferably at least one of simple hexagonal, trigonal simple rhombohedron, cubic simple cube, body centered cube and face centered cubic. In particular, when a base substrate having a plurality of convex portions having a six-fold symmetry is used, it is preferable for the Bravay lattice that the c-axis of the simple hexagonal first semiconductor is perpendicular to the crystal plane of the base substrate main surface. Further, when using a base substrate in which a plurality of convex portions have a four-fold symmetrical arrangement, the Bravay lattice is preferably at least one of a simple cube, a body-centered cube, and a face-centered cube. The (00X) plane (X is a positive integer of 1 or more) is preferably parallel to the crystal plane of the main surface of the base substrate.

  As a specific example, a method of determining a crystal growth axis of a first semiconductor that grows on a base substrate using a simple hexagonal Bravay lattice as a crystal growth unit will be described. FIG. 4 is an explanatory diagram of the crystal growth axis (Lb) of the first semiconductor layer according to the present embodiment. FIG. 4A assumes a case where crystal growth is performed such that the c-axis of the first semiconductor having a simple hexagonal Bravey lattice 5 is perpendicular to the crystal plane 1 a of the main surface of the base substrate 1. For the sake of simple explanation, the uneven structure on the base substrate 1 is not shown in FIG. 4A. There are six points of K1, K2, K3, K4, K5, and K6 as vertices of the Bravay lattice 5 existing in a plane substantially parallel to the crystal plane 1a of the main surface of the base substrate 1. When hexagons are connected so that the area of the polygon connecting these six vertexes is maximized, and straight lines that bisect each of the formed six corners are drawn, the six crystal growth axes Lb-1, Lb -2, Lb-3, Lb-4, Lb-5, and Lb-6. In this case, since Lb-1 and Lb-4, Lb-2 and Lb-5, and Lb-3 and Lb-6 can be regarded as the same growth axis, there are substantially three crystal growth axes. .

  Similarly, an example in which the first semiconductor having a simple cubic Bravay lattice 5 with respect to the crystal plane of the main surface of the base substrate grows as shown in FIG. 4B is shown. For the sake of simplicity, the description will be made assuming a substrate without the uneven structure on the base substrate 1 in FIG. 4B. There are four vertices K1, K2, K3, and K4 of the Bravay lattice 5 existing in a plane substantially parallel to the crystal plane 1a of the main surface of the base substrate 1. When a square is connected so that the area of the polygon connecting these four vertices is maximized, and a straight line that bisects each of the four formed corners is drawn, the four crystal growth axes Lb-1, Lb- 2, Lb-3 and Lb-4 are obtained, but Lb-1 and Lb-3, and Lb-2 and Lb-4 can be regarded as the same axis, so there are substantially two crystal growth axes. It will be.

<Optimum value of Θ>
In the present invention, the angle (Θ) formed by the array axis (La) of the plurality of convex portions and the crystal growth axis (Lb) of the first semiconductor grown on the base substrate is 70 ° <Θ ≦ 90 °. Thus, it has been found that a semiconductor template substrate having high surface flatness can be obtained by arranging a plurality of convex portions on the main surface of the base substrate. As described above, when attention is paid to a specific convex portion on the base substrate, a plurality of convex portion arrangement axes (La) and crystal growth axes (Lb) may exist. In this specification, the angle (Θ) formed by La and Lb satisfies 70 ° <Θ ≦ 90 °, and 70 ° <Θ ≦ 90 ° is satisfied for any Lb among a plurality of Lb. It is defined that there is a satisfying La. FIG. 5 is an explanatory diagram of an angle (Θ) formed by La and Lb according to the present embodiment. Further, as shown in FIG. 5, when the angle between La and Lb is not 90 °, Θ can be considered in two ways, Θ1 and Θ2 (Θ1 <Θ2). In that case, the smaller angle (Θ1 <90 °) is defined as the angle (Θ) formed by La and Lb in this specification. In addition, as described above, since there are a plurality of La and a plurality of Lb, when there are a plurality of Θ with respect to a specific Lb, the largest angle among the possible Θ (≦ 90 °) is set in this specification. Θ in the calligraphy.

  Based on the definitions of La and Lb described above, the reason why the flatness of the surface of the semiconductor template substrate is improved when Θ is 70 ° <Θ ≦ 90 ° will be discussed below with specific examples. FIG. 6 is an explanatory diagram of Θ when using a base substrate having a concavo-convex structure having a six-fold symmetrical arrangement according to the present embodiment. FIG. 6A shows the case of Θ = 90 °, and FIG. 6B shows the case of Θ = 60 °. 6A and 6B assume the case where the crystal plane of the flat portion 3 of the main surface of the base substrate 1 is c-plane sapphire, the shape of the bottom of the convex portion 2 is circular, and the top of the convex portion 2 is This is illustrated assuming a corner having a radius of curvature greater than zero. When the GaN of the first semiconductor 4 is vapor-grown on the sapphire substrate by MOCVD (metal organic vapor phase epitaxy), priority is given to the flat portion 3 of the sapphire c-plane where the same crystal plane is continuously exposed. GaN grows. When vapor-phase-growing GaN on a c-plane sapphire substrate, it grows so that the c-axis direction of the sapphire substrate and the c-axis direction of hexagonal (simple hexagonal) GaN coincide with each other. A hexagon can be formed by connecting the vertices of the GaN Bravay lattice 5 existing in a plane parallel to the crystal plane. Therefore, for simplicity, the GaN Bravais lattice (crystal growth unit) 5 grown in FIGS. 6A and 6B is indicated by a hexagon. Note that the hexagonal size is intentionally larger than the actual Bravay lattice 5 for easy understanding.

  First, in the case of Θ = 90 ° in FIG. 6A, focusing on the region A in the figure, when two different GaN island-like growth nuclei meet between the adjacent convex portions 2, It was found that the hexagonal corners of the Bravais lattice (crystal growth unit) 5 were associated with the corners facing each other, and at this time, GaN easily grew in a narrow space between the convex portions 2. As shown in FIG. 6A, GaN having a simple hexagonal Bravaic lattice 5 forms growth nuclei preferentially at locations where the c-plane exposed area of the base substrate 1 having a concavo-convex structure is large. Planarization proceeds by forming island-shaped GaN and adjoining island-shaped GaN. At that time, the growth rate of the GaN {11Y} plane (Y is a positive integer) with respect to the GaN {1-1X} plane (X is a positive integer) is relatively fast, and Θ = 60 ° when Θ = 90 °. Compared to the case, it is conceivable that the steric hindrance due to the convex portion 2 is alleviated and the adjacent island-like GaN is likely to associate with each other. Then, before each island-like GaN grows high in the sapphire c-axis direction and the height variation increases, adjacent GaN growth nuclei associate and flatten, so that the flattening of GaN is efficiently performed. It is considered that a semiconductor template substrate with high flatness can be obtained.

  On the other hand, in the case of Θ = 60 ° in FIG. 6B, focusing on the region B in the figure, when two different GaN island-like growth nuclei meet between the adjacent convex portions 2, two different GaN The hexagonal sides of the Bravai lattice (crystal growth unit) 5 meet in a state where the sides face each other. In particular, when the gap between the projections 2 is narrow, GaN hardly grows in a narrow space between the projections 2. As shown in FIG. 6B, GaN having a simple hexagonal Bravay lattice 5 forms growth nuclei preferentially at locations where the c-plane exposed area of the base substrate 1 having a concavo-convex structure is large. GaN is formed. Planarization progresses due to the association between adjacent island-shaped GaN. At this time, the growth rate of the GaN {11Y} plane (Y is a positive integer) with respect to the GaN {1-1X} plane (X is a positive integer). Is relatively fast, and it is considered that Θ = 60 ° is more susceptible to steric hindrance by the convex portion 2 than Θ = 90 °. As a result, it takes time for the neighboring island-shaped GaN to meet each other, and in the stage before the association, each island-shaped GaN grows high in the sapphire c-axis direction and the height variation increases, so Θ = 60 ° is It is considered that it is difficult to obtain a semiconductor template substrate having higher flatness than Θ = 90 °. In addition, the semiconductor template substrate in which the mirror growth produced in this example and the comparative example was confirmed, regardless of Θ = 60 ° and Θ = 90 °, in any of the examination results, the cross-section SEM observation showed that One semiconductor was well embedded.

  For the reasons described above, Θ is preferably greater than 70 °, more preferably 75 ° or more, still more preferably 80 ° or more, and most preferably 90 °.

  Another example in which the Θ is preferably 70 ° <Θ ≦ 90 ° will be described. FIG. 7 is an explanatory diagram of Θ when a base substrate having a concavo-convex structure having a four-fold symmetrical arrangement according to the present embodiment is used. FIG. 7A and FIG. 7B show a cubic simple cubic (which may be a body-centered cube and a face-centered cube) 5 on a base substrate 1 having a plurality of convex portions 2 and flat portions 3 having a four-fold symmetry arrangement. The effect of the difference in Θ when growing the first semiconductor 4 having a thickness will be described. Here, the shape of the bottom part of the convex part 2 is circular, and the case where the top part of the convex part 2 is a corner | angular part whose curvature radius is more than 0 is assumed. When the simple cubic first semiconductor 4 is vapor-phase grown on the base substrate 1, the first semiconductor 4 is preferentially given from the flat portion 3 of the main surface of the base substrate 1 where the same crystal plane is continuously exposed. Grow. In this example, the first semiconductor 4 grows so that the crystal plane of the main surface of the base substrate 1 and the {00X} plane (X is a positive integer) of the first semiconductor 4 are substantially parallel planes. Is assumed. In this case, a square can be formed by connecting the apexes of the Bravey lattice 5 of the first semiconductor 4 existing in a plane parallel to the crystal plane of the main surface of the base substrate 1. The square is derived from the lattice apex of the crystal growth unit, and is represented by a square in FIG. 7A. In the case of Θ = 90 ° in FIG. 7A, when attention is paid to the region A in the figure, the simple cubic Bravay lattice 5 forms an aggregate to form a first semiconductor growth nucleus, and two different first semiconductor growths in the initial stage of growth. When the nuclei meet between the adjacent convex portions, the square corners of the Bravay lattice are associated with each other, so that the crystal growth of the first semiconductor 4 occurs particularly when the gap between the convex portions 2 is narrow. Nuclei can easily meet each other.

  On the other hand, in the case of Θ = 45 ° in FIG. 7B, focusing on the region B in the figure, two different first semiconductor growth nuclei in the initial stage of growth meet between the convex portions 2 that are adjacent to each other to form the convex portion 2. When filling the gap, since the square sides of the Bravay lattice 5 are associated with each other facing each other, the crystal growth nuclei of the first semiconductor 4 are hardly associated with each other, particularly when the gap between the convex portions 2 is narrow. . Therefore, in the case of Θ = 45 °, the crystal growth nuclei of the first semiconductor 4 are associated with each other, and the growth of the {001} plane of the first semiconductor 4 proceeds before the planarization progresses. It is considered that the variation in the height of the growth nuclei becomes larger and flattening becomes difficult. Accordingly, similarly to the description with reference to FIG. 6, the angle Θ formed by the arrangement axis (La) of the protrusions 2 and the crystal growth axis (Lb) of the first semiconductor 4 satisfies 70 ° <Θ ≦ 90 °, specifically Is preferably greater than 70 °, more preferably 75 ° or more, even more preferably 80 ° or more, and most preferably 90 °.

<How to check Θ>
The following confirmation method of Θ is an example, and other confirmation methods may be used for the above-described crystal growth axis (Lb).

  First, a first semiconductor layer having a known crystal system and Bravay lattice type is grown on the base substrate, and 2θ / θ measurement is performed by ordinary out-of-plane XRD (X-ray diffraction). The crystal growth surface on the surface of the first semiconductor layer grown on the surface is specified, and then the in-plane diffraction vector direction is specified by in-plane XRD measurement.

  Regarding all of the present examples and comparative examples, the confirmation method of Θ used will be specifically described below. A sapphire substrate having an a-plane orientation flat (orientation flat) and having a plurality of convex portions and an c-plane flat portion having an n-fold symmetrical arrangement, and GaN is formed by MOCVD on a c-plane sapphire substrate A semiconductor template substrate was produced by vapor phase growth. In general, when vapor-phase growth of GaN on a c-plane sapphire substrate, it is known that the sapphire c-plane and hexagonal (simple hexagonal) GaN c-plane grow in parallel. The produced semiconductor template substrate is subjected to 2θ / θ measurement by ordinary out-of-plane XRD (X-ray diffraction), and the growth surface of GaN growing parallel to the crystal surface of the base substrate main surface is the (00X) plane. It was confirmed that (X is a positive integer). Next, in-plane XRD measurement specifies the direction of the in-plane diffraction vector on the surface of the semiconductor template substrate, specifies the simple hexagonal m-axis and a-axis directions, and thereby the semiconductor crystal growth axis (Lb) described above. Was able to identify the direction. In this case, the a-axis is Lb. In addition, an angle formed by the arrangement axis (La) of the plurality of convex portions with respect to the orientation flat direction is specified in advance by SEM observation, and the surface of the semiconductor template substrate surface (GaN) with respect to the orientation flat orientation by the XRD measurement. By measuring the direction of the diffraction vector, the angle Θ formed by La and Lb was specified. After confirming the angle of Θ, when changing Θ, after confirming that the m-plane of GaN grows parallel to the a-plane of the c-plane sapphire, the sapphire orientation flat (a-plane) and By adjusting the angle formed by the array axes (La) of the plurality of convex portions, semiconductor template substrates having different Θ were obtained.

  FIG. 8 is a schematic cross-sectional view of the LED semiconductor template substrate according to the present embodiment. The LED semiconductor template substrate 80 according to the present embodiment includes a base substrate 10. At least a part of the main surface of the base substrate 10 forms a concavo-convex structure 20 including a plurality of convex portions 21 and flat portions 22 having a substantially n-fold symmetric arrangement. The concave portion between the convex portions 21 constitutes a flat portion 22.

  As shown in FIG. 8, the first semiconductor layer 30 is formed on the surface of the concavo-convex structure 20, and the plurality of convex portions 21 and flat portions 22 are covered with the first semiconductor layer 30. When the first semiconductor layer 30 is hetero-growth in which the materials of the first semiconductor and the base substrate are different, the base substrate 10 is interposed via the buffer layer 33 having a thickness less than Have in order to alleviate the difference between the lattice constants of both. It is preferable to grow it on top.

  In the present embodiment, in the LED semiconductor template substrate 80 shown in FIG. 8, the average pattern gap (PGave) between the convex portions 21 is set to a value larger than 5 nm and smaller than 400 nm.

  Further, the angle (Θ) formed by the arrangement axis (La) of the plurality of convex portions 21 and the crystal growth axis (Lb) of the first semiconductor layer 30 satisfies 70 ° <Θ ≦ 90 °.

  Thereby, the flatness of the surface of the semiconductor template substrate 80 (referring to the surface 30a of the first semiconductor layer 30 in FIG. 8) can be improved.

  Hereafter, each structure of the semiconductor template substrate 80 for LED which concerns on this Embodiment is demonstrated in detail.

<Base substrate>
The material of the base substrate is not particularly limited, but the following materials can be exemplified. Sapphire, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), graphite, silicon nitride (Si ₃ N ₄ ), silicon (Si), copper tungsten (W-Cu), oxidation Zinc, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron oxide, magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium gallium oxide, lithium aluminum oxide, neodymium gallium oxide, lanthanum strontium aluminum tantalum, strontium oxide A substrate such as titanium, titanium oxide, hafnium, tungsten, molybdenum, GaP, or GaAs can be used. In particular, when a group III-V semiconductor is grown as a first semiconductor on a base substrate for LED applications, sapphire and silicon that are generally used as a base substrate for LEDs from the viewpoint of availability and lattice constant. , Silicon carbide, gallium nitride, aluminum nitride, graphite base substrate is preferably used, sapphire substrate is preferred, and when growing a hexagonal first semiconductor, the convex arrangement of rotational symmetry From the viewpoint of properties, a sapphire substrate having a c-plane as a main surface is most preferable. In addition, impurities or intentional additive elements may be added to the base substrate as long as the effects of the present invention can be obtained.

  In addition, about the material of the base substrate which concerns on this specification, even the flat part surface observed on the convex part bottom part of the uneven structure of the base substrate which grows a 1st semiconductor is formed with the material mentioned above, and the material of a convex part is Other materials may be used. That is, the base substrate may be formed integrally with the convex portions or separately. When the convex portions are separate bodies, the convex portions can be formed in a predetermined arrangement on a substrate having a flat surface. Moreover, when a convex part is a different body, a convex part can be left as a permanent agent of a transfer material so that it may demonstrate with the following manufacturing methods, for example.

  Further, in the present invention, the effect of improving the flatness of the surface of the semiconductor template substrate is that the alignment axis (La) of the plurality of convex portions on the base substrate and the crystal growth axis (Lb) of the first semiconductor grown thereon. Is obtained by controlling the angle (Θ) between Therefore, in the present invention, the material of the base substrate to be used is not particularly limited. The effect is determined solely by the relative relationship between the crystal growth axis (Lb) of the first semiconductor and the projection array axis (La). Therefore, for example, even when the sapphire substrate has an a-plane, m-plane, or r-plane sapphire substrate, by controlling so that the angle between La and Lb satisfies 70 ° <Θ ≦ 90 °, The effect of the present invention can be obtained.

  The size of the base substrate is not particularly limited, and examples thereof include 2 inch φ, 4 inch φ, 6 inch φ, and 8 inch φ. These may have a disk shape or a shape with an orientation flat (orientation flat) as a crystal orientation mark. In order to control a plurality of convex portion arrangement axes (La), it is preferable to use a base substrate with an orientation flat in which the crystal orientation is known in advance. For example, a general sapphire substrate is provided with an orientation flat corresponding to the sapphire a surface.

<Method for producing uneven structure>
In the method for manufacturing the base substrate according to the present embodiment, it is preferable to form the concavo-convex structure on the surface of the base substrate by a transfer method using a mold having a fine pattern on the surface.

  The uneven structure of the base substrate is manufactured by a transfer method, a photolithography method, a thermal lithography method, an electron beam drawing method, an interference exposure method, a lithography method using a nanoparticle mask, a lithography method using a self-organized structure as a mask, or the like. be able to. In particular, it is preferable to employ a transfer method from the viewpoint of processing accuracy and processing speed of the concavo-convex structure of the base substrate.

  By adopting the transfer method to produce the concavo-convex structure, the base substrate can be manufactured without using an excessive apparatus or control mechanism. In particular, by adopting the transfer method, a base substrate having a diameter of 6 inches or more, which is difficult to manufacture, can be manufactured with high accuracy and efficiency.

  The transfer method according to the present embodiment is defined as a method including a step of transferring a concavo-convex structure of a mold having a concavo-convex structure on a surface to an object to be processed (a base substrate before producing the concavo-convex structure). That is, it is a method including at least a step of bonding the concavo-convex structure of the mold and the object to be processed through a transfer material and a step of peeling the mold.

  More specifically, the transfer method can be classified into two. First, the transfer material transferred to the object to be processed is used as a permanent agent. In this case, the materials constituting the subject and the concavo-convex structure are different. The uneven structure remains as a permanent agent and is used as an LED element. Since the LED element is used over a long period of tens of thousands of hours, when the transfer material is used as a permanent agent, the material constituting the transfer material preferably contains a metal element. In particular, it is preferable to include a metal alkoxide that generates a hydrolysis / polycondensation reaction or a metal alkoxide condensate as a raw material because the performance as a permanent agent is improved. Secondly, there is a nanoimprint lithography method. The nanoimprint lithography method includes a step of transferring a texture of a mold onto a target object, a step of providing a mask for processing the target object by etching, and a step of etching the target object. For example, when one type of transfer material is used, first, the object to be processed and the mold are bonded via the transfer material. Subsequently, the transfer material is cured by heat or light (UV), and the mold is peeled off. Etching typified by oxygen ashing is performed on the concavo-convex structure made of a transfer material to partially expose the object to be processed. Thereafter, the object to be processed is processed by etching using the transfer material as a mask. As a processing method at this time, dry etching and wet etching can be employed. Dry etching is useful for increasing the height of the concavo-convex structure. For example, when two types of transfer materials are used, a first transfer material layer is first formed on the object to be processed. Subsequently, the first transfer material layer and the mold are bonded via the second transfer material. Thereafter, the transfer material is cured by heat or light (UV), and the mold is peeled off. Etching typified by oxygen ashing is performed on the concavo-convex structure formed of the second transfer material to partially expose the first transfer material. Subsequently, the first transfer material layer is etched by dry etching using the second transfer material layer as a mask. Thereafter, the object to be processed is processed by etching using the transfer material as a mask. As a processing method at this time, dry etching and wet etching can be employed, but dry etching is useful when it is desired to increase the height of the concavo-convex structure.

  As described above, by adopting the transfer method, the uneven structure of the mold can be reflected on the object to be processed, so that a good base substrate can be obtained.

  The material of the imprint mold is not particularly limited, and non-flexible glass, quartz, sapphire, nickel, or flexible resin can be used. Among them, it is preferable to use a flexible mold because the transfer accuracy of the texture of the mold is improved and the accuracy of the concavo-convex structure of the base substrate is improved.

<First semiconductor growth>
The method of vapor phase growth of the first semiconductor on the base substrate is not particularly limited, but the well-known metal organic vapor phase growth method (MOCVD method), molecular beam epitaxy method (MBE method), halide vapor phase growth method (HVPE method). It can be formed by sputtering, ion plating, electron shower, or the like. When the LED structure is formed on the base substrate, the MOCVD method is preferable because it is necessary to control the film formation rate to control the film thickness.

  In the present invention, the angle (Θ) formed by the arrangement axis (La) of the plurality of convex portions on the base substrate and the crystal growth axis (Lb) of the first semiconductor layer grown thereon is adjusted within a predetermined range. Thus, since a semiconductor template substrate for LED with high flatness can be obtained, the type of semiconductor to be vapor-phase grown on the base substrate is not limited. Examples of the first semiconductor include III-V group semiconductors (Group III elements include Al, Ga, In, etc., and Group V elements include N, P, As, Sb, etc.). In the case of using a sapphire substrate having a plurality of convex portions having a c-plane as a main surface and six-fold symmetry, the first semiconductor may be hexagonal undoped GaN from the viewpoint of rotational symmetry of the convex portion arrangement. preferable. The first semiconductor may be an n-type semiconductor or a p-type semiconductor to which various dopants are added. Examples of the dopant for GaN of the n-type semiconductor include monosilane, disilane, and trimethylsilane. Other examples of the first semiconductor include elemental semiconductors such as ZnSe, Si, and Ge, and compound semiconductors such as II-VI group and VI-VI group are also applicable in principle.

  In this embodiment, in the case of hetero-growth in which the materials of the first semiconductor and the base substrate are different, the first semiconductor is formed on the base via a buffer layer having a thickness less than Have in order to alleviate the difference in lattice constant between the two. It is preferable to grow on the substrate. When the thickness of the buffer layer is smaller than Have, when the first semiconductor grown on the base substrate flat portion grows in a direction parallel to the main surface of the base substrate, it is sterically hindered by a plurality of convex portions on the base substrate. Therefore, the effect of improving the flatness by controlling Θ can be obtained. When a sapphire substrate is used as the base substrate, the buffer layer is preferably a GaN-based or AlN-based low-temperature buffer layer grown by MOCVD. The buffer layer can be grown not only by MOCVD at a low temperature but also by sputtering.

<Production of LED element using semiconductor template substrate>
FIG. 9 is an example of a schematic cross-sectional view of the LED element according to the present embodiment. As shown in FIG. 9, the LED element 100 includes a semiconductor template substrate 80 having a base substrate 10 and a first semiconductor layer 30, a second semiconductor layer 35, a light emitting layer 40, a third semiconductor layer 50, a transparent conductive material. A film 60, a first electrode 70, and a second electrode 85 are included. The first semiconductor layer 30 is, for example, an undoped semiconductor layer, the second semiconductor layer 35 is, for example, an n-type semiconductor layer, and the third semiconductor layer 50 is, for example, a p-type semiconductor layer. In such a case, the first electrode 70 is a p-electrode and the second electrode 85 is an n-electrode. Note that the transparent conductive film 60 may not be formed.

  When the LED element 100 shown in FIG. 9 is face-up mounted, the emitted light generated in the light emitting layer 40 is extracted from the third semiconductor layer 50 side or the end of the LED element 100. Furthermore, the first semiconductor layer 30 and the second semiconductor layer 35 are different semiconductor layers.

  The LED elements are manufactured by dividing into individual light emitting element units using a laser from a laminated substrate on which a large number of LED elements are integrally formed.

  In the present embodiment, the range of the average pattern gap (PGave) between the protrusions of the base substrate 10, the arrangement axis (La) of the plurality of protrusions, and the crystal growth axis (Lb) of the first semiconductor layer 30. By optimizing the range of the formed angle (Θ), the flatness of the surface of the semiconductor template substrate 80 can be improved. As a result, the LED element 100 manufactured using the semiconductor template substrate 80 has an effect of suppressing Ir. Ir is a leakage current measured with a reverse bias voltage applied between the electrodes 70 and 85. In the present embodiment, the flatness of the surface of the semiconductor template substrate 80 can be improved, and as a result, the layers formed on the semiconductor template substrate 80 can be appropriately stacked with a predetermined thickness. . Therefore, the interface between the layers can be formed closely with high accuracy, and the occurrence of leakage current can be suppressed.

  EXAMPLES Hereinafter, although this invention is further explained in full detail based on an Example, these are described for description and the range of this invention is not limited to the following Example.

Hereinafter, the common part of the Example and comparative example which were performed in order to confirm the effect of this invention is demonstrated. The symbols used in the following description have the following meanings.
・ DACHP: Fluorine-containing urethane (meth) acrylate (OPTOOL (registered trademark) DAC HP (manufactured by Daikin Industries))
M350: trimethylolpropane (EO-modified) triacrylate (manufactured by Toagosei Co., Ltd.)
・ I. 184 ... 1-hydroxycyclohexyl phenyl ketone (Irgacure (registered trademark, the same applies hereinafter) 184 (manufactured by BASF))
・ I. 369 ... 2-benzyl-2-dimethylamino-1- (4-morpholinophenyl) -butanone-1 (Irgacure 369 (manufactured by BASF))
-TTB: Titanium (IV) tetrabutoxide monomer (Wako Pure Chemical Industries, Ltd.)
SH710: Phenyl-modified silicone (Toray Dow Corning)
・ 3APTMS ... 3-acryloxypropyltrimethoxysilane (KBM5103 (manufactured by Shin-Etsu Silicone))
-DIBK ... diisobutyl ketone-PGME-propylene glycol monomethyl ether-MEK-methyl ethyl ketone-MIBK-methyl isobutyl ketone-DR833 ... tricyclodecane dimethanol diacrylate (SR833 (manufactured by SARTOMER))
SR368 ... Tris (2-hydroxyethyl) isocyanurate triacrylate (SR833 (manufactured by SARTOMER))

<Examples and Comparative Examples>
A base substrate having various uneven structures on the surface was produced, and a first semiconductor was vapor-phase grown on the base substrate to produce a semiconductor template substrate. The Θ of the manufactured semiconductor template substrate was determined. The way of obtaining Θ was obtained by the same method as the above-described <Method for confirming Θ>.

  Then, each layer which comprises an LED element was grown on the semiconductor template board | substrate, and comparative evaluation was performed regarding LED characteristics.

  In the following examination, in order to produce a base substrate having a concavo-convex structure on the surface, first, (1) a cylindrical master mold is produced, and (2) an optical transfer method is applied to the cylindrical master mold. A reel-shaped resin mold was produced. (3) Thereafter, the reel-shaped resin mold was processed into a film for nano-processing of an optical substrate. Subsequently, (4) using a film for nano-processing, forming a mask on the object to be processed (base substrate before producing the concavo-convex structure), and performing dry etching through the obtained mask, A base substrate having an uneven structure was produced. (5) The first semiconductor is vapor-phase grown on the base substrate to produce a semiconductor template substrate. Finally, (6) an LED element is produced using the semiconductor template substrate, and the following (7) and (9) Each performance was evaluated.

(1) Production of cylindrical master mold An uneven structure was formed on the surface of cylindrical quartz glass by a direct drawing lithography method using a semiconductor laser. First, a resist layer was formed on the surface of the cylindrical quartz glass by a sputtering method. The sputtering method was carried out using φ3 inch CuO (containing 8 atm% Si) as a target (resist layer) with a power of RF 100 W to form a 20 nm resist layer. Thereafter, the entire surface of the cylindrical quartz glass was exposed once. Subsequently, exposure was performed using a semiconductor laser having a wavelength of 405 nm while rotating the cylindrical quartz glass. Next, the resist layer after exposure was developed. The resist layer was developed using a 0.03 wt% glycine aqueous solution for 240 seconds. Next, using the developed resist layer as a mask, the etching layer (quartz glass) was etched by dry etching. Dry etching was performed using SF ₆ as an etching gas under the conditions of a processing gas pressure of 1 Pa, a processing power of 300 W, and a processing time of 5 minutes. Finally, only the resist layer residue was peeled off from the cylindrical quartz glass having a concavo-convex structure on its surface using hydrochloric acid having a pH of 1. The peeling time was 6 minutes.

  Optool (registered trademark) HD-2100TH (manufactured by Daikin Chemical Industries), which is a fluorine-based mold release agent, was applied to the concavo-convex structure of the obtained cylindrical quartz glass, heated at 60 ° C. for 1 hour, and then at room temperature for 24 hours. It was left to stand for immobilization. Then, it wash | cleaned 3 times by Optool HD-TH (made by Daikin Chemical Industries), and the cylindrical master mold was obtained.

(2) Production of reel-shaped resin mold Using the produced cylindrical master mold as a mold, the optical nanoimprint method was applied to continuously produce a reel-shaped resin mold G1. Subsequently, a reel-shaped resin mold G2 was continuously obtained by an optical nanoimprint method using the reel-shaped resin mold G1 as a template.

The material 1 shown below was apply | coated to the easily bonding surface of PET film A-4100 (Toyobo Co., Ltd .: width 300mm, thickness 100micrometer) by micro gravure coating (manufactured by Yurai Seiki Co., Ltd.) so that it might become a coating film thickness of 5 micrometers. . Next, the PET film coated with the material 1 is pressed against the cylindrical master mold with a nip roll so that the integrated exposure amount under the center of the lamp is 1500 mJ / cm ^{2 at} 25 ° C. and 60% humidity in the air. In addition, ultraviolet curing was performed using a UV exposure apparatus (H bulb) manufactured by Fusion UV Systems Japan, and photocuring was continuously performed. And the reel-shaped resin mold G1 (length 200m, width 300mm) by which the texture was transcribe | transferred on the surface was obtained.
Material 1 ... DACHP: M350: I. 184: I.D. 369 = 17.5 g: 100 g: 5.5 g: 2.0 g

  Next, the reel-shaped resin mold G1 was regarded as a template, and the optical nanoimprint method was applied to continuously produce the reel-shaped resin mold G2.

Material 1 was applied to an easily adhesive surface of PET film A-4100 (manufactured by Toyobo Co., Ltd .: width 300 mm, thickness 100 μm) by microgravure coating (manufactured by Yurai Seiki Co., Ltd.) so as to have a coating thickness of 3 μm. Next, the PET film coated with the material 1 is pressed against the concavo-convex structure surface of the reel-shaped resin mold G1 with a nip roll (0.1 MPa) and integrated under the center of the lamp at 25 ° C. and 60% humidity in the air. Ultraviolet rays were irradiated using a UV exposure apparatus (H bulb) manufactured by Fusion UV Systems Japan Co., Ltd. so that the exposure amount was 1200 mJ / cm ^2, and photocuring was performed continuously. A plurality of reel-shaped resin molds G2 (length 200 m, width 300 mm) having a concavo-convex structure transferred on the surface were obtained.

(3) Production of Nano-Processing Film A diluent of the following material 2 was applied to the concavo-convex structure surface of the reel-shaped resin mold G2. Subsequently, a dilution liquid of the following material 3 was applied on the concavo-convex structure surface of the reel-shaped resin mold G2 enclosing the material 2 in the concavo-convex structure to obtain a nano-processing film.
Material 2 ... TTB: 3APTMS: SH710: I. 184: I.D. 369 = 65.2 g: 34.8 g: 5.0 g: 1.9 g: 0.7 g
Material 3 ... Binding polymer: SR833: SR368: I.I. 184: I.D. 369 = 77.1 g: 11.5 g: 11.5 g: 1.47 g: 0.53 g
Binding polymer: Methyl ethyl ketone solution of binary copolymer of 80% by mass of benzyl methacrylate and 20% by mass of methacrylic acid (solid content 50%, weight average molecular weight 56000, acid equivalent 430, dispersity 2.7)

  Using a device similar to the production of the reel-shaped resin mold in (2), the material 2 diluted with PGME was directly applied onto the texture surface of the reel-shaped resin mold G2. Here, the dilution concentration was set so that the solid content contained in the coating raw material per unit area (material 2 diluted with PGME) was 20% or more smaller than the volume of the concavo-convex structure per unit area. . After coating, the material was passed through an air-drying oven at 80 ° C. for 5 minutes, and the reel-shaped resin mold G2 containing the material 2 inside the concavo-convex structure was wound and collected.

  Subsequently, the reel-shaped resin mold G2 including the material 2 in the concavo-convex structure is unwound, and the material 3 diluted with PGME and MEK is used using the same apparatus as that for the production of the reel-shaped resin mold in (2). And coated directly on the textured surface. Here, the dilution concentration was set such that the distance between the interface between the material 2 disposed inside the texture and the coated material 3 and the surface of the material 3 was 400 nm to 800 nm. After coating, the material was passed through an air-drying oven at 80 ° C. for 5 minutes, and a cover film made of polypropylene was put on the surface of the material 3 and wound up and collected.

(4) Production of base substrate Using the produced nano-processing film, an attempt was made to impart a surface uneven structure to the base substrate. A sapphire substrate having a c-plane surface was used as the object to be processed (base substrate before producing the concavo-convex structure). A 2-inch single-side polished sapphire substrate was used as the sapphire substrate.

The sapphire substrate was subjected to UV-O ₃ treatment for 5 minutes to remove surface particles and to make it hydrophilic. Then, the material 3 surface of the film for nano processing was bonded with respect to the sapphire substrate. At this time, the sapphire substrate was bonded in a state heated to 80 ° C. Subsequently, using a high-pressure mercury lamp light source, light was irradiated through the reel-shaped resin mold G2 so that the integrated light amount was 1200 mJ / cm ² . Thereafter, the reel-shaped resin mold G2 was peeled off.

Etching using oxygen gas is performed from the material 2 surface side of the obtained laminate (material 2 / material 3 / substrate laminate), and the material 3 is nano-processed using the material 2 as a mask. Partially exposed. Oxygen etching was performed by adjusting the time so as to partially expose the surface of the sapphire substrate under the conditions of pressure 1 Pa and power 300 W. Subsequently, reactive ion etching (RIE-101iPH, manufactured by Samco Co., Ltd.) using BCl ₃ gas was performed from the material 2 surface side to nano-process the surface of the sapphire substrate. In the etching using BCl ₃ , the etching time was adjusted so that the concavo-convex structure on the sapphire substrate used in Examples and Comparative Examples was obtained under the conditions of ICP: 150 W, BIAS: 50 W, and pressure 0.2 Pa.

  Finally, it was washed with a solution in which sulfuric acid and hydrogen peroxide solution were mixed at a weight ratio of 2: 1 to obtain a base substrate having an uneven structure on the surface. In addition, the shape of the concavo-convex structure produced on sapphire is mainly the shape of the concavo-convex structure produced in the cylindrical master mold, the nip pressure condition when manufacturing the resin mold, and the filling rate of the material 2 for the film for nano-processing. The film thickness of the material 3 and the etching time of reactive ion etching were appropriately controlled.

(5) Production of Semiconductor Template Substrate A first semiconductor film was formed on the base substrate obtained in (4) using the MOCVD apparatus in the following order. First, thermal cleaning with hydrogen gas was performed on the base substrate at a temperature of 1000 ° C. to 1150 ° C. Subsequently, a low temperature buffer layer (thickness 30 nm) of GaN was formed at 450 to 550 ° C. using TMG (trimethylgallium) and NH ₃ (ammonia) as source gases. The film thickness of the low temperature buffer layer is thinner than the average height (Have) of the protrusions in any of the examples and comparative examples, and the unevenness on the base substrate may be flattened by the film formation of the low temperature buffer layer. There was no condition setting.

Thereafter, undoped GaN, which is the first semiconductor, was formed at 1000 ° C. to 1150 ° C. using TMG and NH ₃ as source gases to form a flat surface, thereby obtaining a semiconductor template substrate. In the examples, comparative examples, and reference examples in this specification, the semiconductor with respect to the angle (Θ) formed by the alignment axis (La) of the protrusions on the base substrate and the crystal growth axis (Lb) of the first semiconductor layer. In order to confirm the influence of the flatness of the template substrate surface, the MOCVD film formation was intentionally unified with the same film formation conditions up to the first semiconductor.

  The surface flatness of the obtained semiconductor template substrate was observed with a field of view of 200 μm × 200 μm by AFM, and the mean square surface roughness (RMS) at that time was measured for comparative evaluation. In addition, only when the flattening is not performed by the first semiconductor after the first semiconductor film is formed and the surface of the semiconductor template substrate is not mirror-growth at the visual stage, that is, when the surface of the semiconductor template substrate becomes cloudy due to the unevenness of the surface of the semiconductor template substrate. In the evaluation results, it was described that mirror growth did not occur. Regarding the examination results not described, mirror growth was confirmed visually.

(6) Production of LED element using semiconductor template substrate On the semiconductor template substrate obtained in (5), 5 μm of Si-doped GaN (n-type semiconductor) is formed at the same temperature as the film formation temperature of the first semiconductor. Filmed. Subsequently, a strained superlattice structure, which is a laminated periodic structure of a Si-doped GaN layer and a Si-doped In _X Ga _1-X N layer (x = 0.05 to 0.10), was formed at 800 ° C. to 850 ° C. Further, a multiple quantum well (MQW) having a laminated periodic structure of a Si-doped GaN layer and an In _X Ga _1-X N layer (x = 0.12 to 0.16) was formed at 750 ° C. to 800 ° C. The thicknesses of the MQW GaN layer and the In _X Ga _1-X N layer were set to 13 nm and 3 nm, respectively. Further, at 1050 ° C. to 1150 ° C., an Mg-doped AlGaN layer (electroblocking layer) and an Mg-doped GaN layer were formed as p-type semiconductor layers with a total thickness of 110 nm. Subsequently, an ITO film was formed on the surface of the p-type semiconductor, and after various etching processes, an electrode pad was provided to obtain a face-up type 0.35 mm LED element (wafer state). In the examples, comparative examples, and reference examples in the present embodiment, the film forming conditions shown in (5) and (6) were unified for comparative evaluation.

(7) Ir measurement When -5 V (reverse bias) is applied between the p-electrode pad and the n-electrode pad using an autoprober for 10000 or more LED elements obtained on a 2-inch sapphire substrate. Leakage current (Ir) was measured. The ratio (%) of the element whose leakage current was less than 0.23 μA was measured as the Ir yield (%).

(8) Packaging of LED elements After the above Ir measurement, sapphire back surface polishing and dicing are performed, and 20 of the 10000 or more LED elements are mounted on a TO can using a die bond material, and then Au The LED package was produced by bonding with a wire.

(9) Measurement of light emission output For the LED package obtained in (8), the arithmetic average value (P0) of light emission output when a current of 20 mA was passed in the forward direction was obtained by an integrating sphere, and Reference Example 1 described later. The light emission output ratio was calculated. In addition, it confirmed that all of the arithmetic mean value of the light emission peak wavelength of the LED element of a present Example, a comparative example, and the reference example 1 were 450 +/- 10nm. In Tables 1 to 3, the phase of each light emission output of the example according to the present embodiment or the comparative example with respect to the arithmetic average value (P1) of the light emission output of the reference example when the flat sapphire substrate described later is used. When the ratio (P0 / P1) of the arithmetic mean value was 1.1 or more, it was indicated as ◯, and when it was less than 1.1, it was indicated as ×.

(Reference Example 1)
As a reference example, when a flat sapphire substrate having a c-plane surface and no concavo-convex structure was used as a base substrate, a current of 20 mA was passed forward through 20 LED packages fabricated in the same manner as (5) and (6). The arithmetic average value (P1) of the luminescence output was obtained with an integrating sphere to obtain the luminescence output ratio.

  Regarding Examples 1 to 17 and Comparative Examples 1 to 12 described later, when a cross section of a mirror-grown semiconductor template substrate was observed with an SEM, no gap was confirmed at the interface between the concavo-convex structure and the first semiconductor under any conditions, Well embedded by the first semiconductor.

  In addition, as information regarding the concavo-convex structure on the sapphire substrate used in Examples and Comparative Examples, n value (a plurality of convex portions having an n-fold symmetric arrangement), Pave, PGave, Have, Bave, Duty (ratio (Bave / Pave)), the top shape of the convex part is shown in Tables 1 to 3.

(Examples 1 to 8 and Comparative Examples 1 to 4)
Examples 1 to 8 and Comparative Examples 1 to 4 in Table 1 are the results of examining the optimum range of the angle (Θ) formed by La and Lb. Using the sapphire substrate (the principal surface is the c-plane) composed of a plurality of convex portions and a regular hexagonal array (six-fold symmetry array) described in FIG. 1C, the angle (Θ) formed by La and Lb is 60 It was changed from ° to 90 °. The first semiconductor layer has a simple hexagonal Bravey lattice as the growth unit. The formed angle (Θ) could be changed by changing each condition of the “base substrate surface uneven structure” shown in each table.

  Moreover, when the convex part shape of Example 1- Example 8 and Comparative Example 1- Comparative Example 4 was cross-sectional-observed with SEM, the shape of each convex part seems to swell the side surface from a convex part top part to a convex part bottom part. The inclination angle of the side surface changed in multiple stages, and the top of the convex part was a corner part with a radius of curvature exceeding zero.

  When Θ of Examples 1 to 8 was 90 °, 85 °, and 75 °, the RMS was low, and the flatness of the semiconductor template substrate surface was high. On the other hand, when Θ of Comparative Examples 1 to 4 was 60 °, a tendency for RMS to increase was confirmed. Therefore, it was found that Θ preferably satisfies 70 ° <Θ ≦ 90 ° from the viewpoint of obtaining a semiconductor template substrate for LED with high flatness.

  Moreover, the tendency for the Ir yield of the LED element produced using the semiconductor template substrate for LED to increase because the flatness of the semiconductor template substrate surface became high was confirmed. Moreover, in Examples 1 to 8 and Comparative Examples 1 to 4, the light emission output of the LED element is 10% or more higher than the light emission output of the LED element produced using the flat sapphire of Reference Example 1. Was confirmed. Therefore, by setting the angle (Θ) formed by La and Lb within a predetermined range, a semiconductor template substrate with high flatness can be obtained, and the LED element manufactured using the semiconductor template substrate has a high light emission output, and It was found that a substrate with a high Ir yield was obtained. Further, in each of Examples 1 to 8 and Comparative Examples 1 to 4, it was visually confirmed that the surface of the semiconductor template substrate was specularly grown (no white turbidity).

(Examples 9 to 16 and Comparative Examples 5 to 11)
Examples 9 to 16 and Comparative Examples 5 to 11 in Table 2 are the results of investigating the optimal range of PGave. In Example 9 to Example 16 and Comparative Example 5 to Comparative Example 11, a sapphire substrate (main surface) composed of a flat portion described in FIG. 1C and a plurality of convex portions arranged in a regular hexagonal arrangement (six-fold symmetry arrangement). Was used to change the average pattern gap (PGave) between the convex portions. At that time, the presence or absence of an effect of improving the flatness of the surface of the semiconductor template substrate by controlling Θ, the Ir yield, and the light emission output ratio were confirmed. In addition, the cross-section observation of the convex part shape of Example 9- Example 16 and Comparative Example 5- Comparative Example 11 was carried out by SEM. As a result, the shape of each convex portion is a curved shape so that the side surface from the top of the convex portion to the bottom of the convex portion swells, the inclination angle of the side surface changes in multiple steps, and the top of the convex portion has a radius of curvature. The corner was more than 0.

First, it was confirmed whether or not there was an effect of improving the flatness of the surface of the semiconductor template substrate by controlling Θ. As a confirmation method, a semiconductor template substrate of Θ = 90 ° was produced for various substrates having a concavo-convex structure on the surface of the base substrate. Then, the root mean square roughness (RMS _{Θ90 °} ) of the surface of the semiconductor template substrate, the Ir yield of the LED element using the semiconductor template substrate, and the light emission output ratio were determined. At that time, regarding various substrates having a concavo-convex structure on the surface of the base substrate, a semiconductor template substrate of Θ = 60 ° was also produced, and the root mean square roughness (RMS _{Θ60 °} ) was obtained. Then, when the value of RMS _{Θ90 °} / RMS _{Θ60 °} is 0.90 or less, the surface flatness improvement effect of the semiconductor template substrate by the Θ control is assumed.

In Example 9 to Example 16 where _PGave satisfies a value larger than 5 nm and smaller than 400 nm, the value of RMS _{Θ90 °} / RMS _{Θ60 °} shows a value of 0.90 or less, and the semiconductor template by controlling Θ It was confirmed to have an effect of improving the flatness of the substrate surface. On the other hand, in Comparative Examples 9 to 11 that satisfy PGave ≧ 400 nm, it is confirmed that the flatness improvement effect on the surface of the semiconductor template substrate by controlling Θ is lower than the value of RMS _{Θ90 °} / RMS _{Θ60 °.} It was. This is because the increase in PGave between the nearest projections makes it easy for the first semiconductor to grow between the projections, and therefore the effect of improving the flatness of the semiconductor template substrate surface by controlling Θ is considered to be small. It is done.

  Moreover, when comparing with the same Pave, since the area which the convex part with respect to a base substrate main surface occupies becomes small as PGave becomes large, the tendency for the light emission output ratio of a LED element to fall was also confirmed. Therefore, from the viewpoint of increasing the light emission output, PGave is preferably a value smaller than 400 nm.

  Further, in Comparative Examples 5 to 8 satisfying PGave ≦ 5 nm, since the distance between the adjacent adjacent convex portions is extremely narrow, a sufficient substrate flat surface cannot be secured for crystal growth of the first semiconductor, and the interval between the convex portions is not ensured. The crystal growth of the first semiconductor is inhibited by the steric hindrance of the convex portion. For this reason, the surface of the semiconductor template substrate was not mirror-grown, and white turbidity was observed visually. In addition, about the thing by which the semiconductor template board | substrate surface was not mirror-growth, it described that it did not carry out mirror-growth in Table 2, and it was confirmed that all others carried out mirror-growth visually.

  In Comparative Example 8, PGave is a value larger than 5 nm and smaller than 400 nm and satisfies 70 ° <Θ ≦ 90 °, but since Pave is as large as 3000 nm, it relatively occupies the base substrate surface. The ratio of the flat part is reduced. Therefore, the flat surface necessary for the first semiconductor to grow the crystal by taking over the crystal orientation of the base substrate cannot be secured sufficiently, resulting in no mirror growth. Therefore, when PGave is a value larger than 5 nm and smaller than 400 nm, it is preferable that Pave ≦ 1800 nm, and from the viewpoint of manufacturing a base substrate having a stable pattern shape, it is preferable that 50 nm <Pave.

  Further, from Example 13 and Comparative Example 10, when a semiconductor template is used for an LED, it is preferable that 0.60 ≦ Duty from the viewpoint of increasing light extraction efficiency and increasing light output.

  Further, from Comparative Examples 5 to 8, it is preferable that Duty ≦ 0.96 from the viewpoint of sufficiently securing a flat surface necessary for crystal growth of the first semiconductor taking over the crystal orientation of the base substrate.

  From the above results, it is possible to obtain a semiconductor template substrate with high flatness by satisfying 70 ° <Θ ≦ 90 ° and 50 nm <Pave ≦ 1800 nm when PGave is a value larger than 5 nm and smaller than 400 nm, It was found that an LED device manufactured using a semiconductor template substrate has a high light emission output and a high Ir yield.

  It was also found that PGave is more preferably 25 nm ≦ PGave ≦ 300 nm. Furthermore, PGave is preferably 29 nm ≦ PGave ≦ 300 nm. Moreover, it turned out that it is preferable that Duty is 0.60 <= (Bave / Pave) <= 0.96. Further, it was found that Pave is preferably 50 nm <Pave ≦ 1800 nm, and more preferably 300 nm ≦ Pave ≦ 1800 nm.

(Example 17 and Comparative Example 12)
Example 17 and Comparative Example 12 in Table 3 are the results of investigating a preferable convex shape on the base substrate. In Example 17 and Comparative Example 12, a sapphire substrate (a principal surface is a c-plane) composed of a plurality of convex portions arranged in a regular hexagonal arrangement (six-fold symmetry arrangement) described in FIG. 1C is used as a base substrate. Although it is used and is the same as Table 1, the convex shape is different. In Table 3, the top of the convex portion is circular (100 nmφ) and flat (table top) with a truncated cone shape, whereas in Table 1, corners with a radius of curvature greater than 0 are used. .

  In Tables 1 and 3, when comparing Example 3 and Example 17 in which n, Pave, PGave, Have, Bave, Duty, and Θ are all semiconductor template substrates under substantially the same conditions, the top shape of the convex portion is the tip. It was found that the RMS value of Example 3 having rounded corners tends to be lower than that of Example 17. In addition, when comparing LED elements manufactured using a semiconductor template substrate, the Ir peak is higher when the convex top shape has a rounded corner, so that the convex top shape has a radius of curvature of 0. It turned out that it is preferable that it is a super-corner part. Further, from Example 17 and Comparative Example 12, it was found that even if the top of the convex portion is a table top, the effect of improving flatness by controlling Θ can be obtained.

  The semiconductor template substrate for LED of the present invention can be applied to the production of LED elements. Thereby, it is possible to manufacture an LED element having a high light emission output and a small leakage current when Ir, that is, a reverse bias is applied.

DESCRIPTION OF SYMBOLS 1 Base substrate 2, 21 Convex part 3, 22 Flat part 4 1st semiconductor 5 Bravay lattice 10 Base substrate 20 Uneven structure 30 First semiconductor layer 33 Buffer layer 35 Second semiconductor layer 40 Light emitting layer 50 Third semiconductor layer 60 Transparent conductive Film 70 First electrode 80 Semiconductor template substrate 85 Second electrode 100 LED element

Claims (11)

A base substrate having a concavo-convex structure comprising a plurality of convex portions and a flat portion having a substantially n-fold symmetric arrangement on at least a part of the main surface; and a first semiconductor layer formed on the concavo-convex structure; Have
The average pattern gap (PGave) between the convex portions is 5 nm <PGave <400 nm, and
The average pitch (Pave) between the most adjacent convex portions of the plurality of convex portions is 50 nm <Pave ≦ 1800 nm,
An angle (Θ) formed by an array axis (La) of the plurality of convex portions and a crystal growth axis (Lb) of the first semiconductor layer satisfies 70 ° <Θ ≦ 90 °. Semiconductor template substrate.   2. The LED semiconductor template substrate according to claim 1, wherein the average pattern gap (PGave) is 25 nm ≦ PGave ≦ 300 nm.   3. The LED semiconductor template substrate according to claim 1, wherein an average pitch (Pave) between adjacent convex portions of the plurality of convex portions is 300 nm ≦ Pave ≦ 1800 nm.   The ratio (Bave / Pave) of the convex bottom average diameter (Bave) and the average pitch (Pave) between the convexes in the plurality of convexes satisfies 0.60 ≦ (Bave / Pave) ≦ 0.96. The semiconductor template substrate for LED according to any one of claims 1 to 3, wherein:   The top part of the said convex part is a corner | angular part with a curvature radius more than 0, The semiconductor template substrate for LED in any one of Claims 1-4 characterized by the above-mentioned.   6. The LED semiconductor template substrate according to claim 1, wherein the n-fold symmetric n is n = 3, n = 4, or n = 6.   7. The LED semiconductor according to claim 1, wherein a material of all or part of the base substrate is sapphire, silicon, silicon carbide, gallium nitride, aluminum nitride, or graphite. Template board.   8. The LED semiconductor template substrate according to claim 1, wherein a material of the base substrate is sapphire, and a main surface of the base substrate is a c-plane. 9.   The semiconductor template substrate for LED according to any one of claims 1 to 8, wherein the first semiconductor layer is formed of a III-V group semiconductor.   The LED semiconductor template substrate according to any one of claims 1 to 9, wherein the first semiconductor layer is formed of a hexagonal crystal containing Ga and N.   An LED element produced using the LED semiconductor template substrate according to claim 1.

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