JP2016177864A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the stand-by power consumption by reducing the leakage current of a system LSI including a memory.SOLUTION: A power source switch N1 is provided in a logic circuit in a system LSI, data in the static memory cell are held, and in the standby state where the readout from or writing to the static memory cell is not carried out, the switch is disconnected to reduce the leakage current. At the same time, in the SRAM circuit, the substrate bias voltage is controlled to reduce the leakage current.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device in which a logic circuit and a static memory (SRAM) circuit are mixedly mounted.

  Japanese Patent Application Laid-Open No. 7-86916 (Patent Document 1) discloses a configuration in which a power switch is provided in a logic circuit and a back gate bias is applied to a MOS transistor constituting the logic circuit. Japanese Patent Laid-Open No. 2000-207884 (Patent Document 2) discloses a substrate bias control technique for a low-voltage operation compatible system LSI including a static memory. Japanese Patent Laying-Open No. 2001-93275 (Patent Document 3) discloses a configuration in which a logic power source is provided in a logic circuit and a memory power source is provided in a memory circuit.

JP-A-7-86916 JP 2000-207884 A JP 2001-93275 A

  Currently, a semiconductor integrated circuit called a system LSI (Large Scale Integrated Circuit) in which an SRAM circuit and a logic circuit are integrated on the same semiconductor chip is widely manufactured. Here, the SRAM circuit refers to a circuit that functions as a memory only with the circuit including SRAM memory cells arranged in an array and peripheral circuits for accessing the memory cells. A logic circuit is specified as an input signal other than a memory circuit including a memory cell arranged in an array such as SRAM, dynamic memory (DRAM), and nonvolatile memory and a circuit for accessing the memory cell. This means the circuit that performs the process and outputs it. Therefore, even if there is a circuit that holds data such as a flip-flop in the logic circuit, it is considered as a part of the logic circuit.

  The demand for low power consumption of the system LSI and the miniaturization of transistors in the LSI reduce the power supply voltage of the LSI. For example, in a 0.13 μm process, an LSI that operates with a power supply voltage of 1.2 V is manufactured. When the power supply voltage decreases, the current of the MOS transistor decreases and the circuit performance deteriorates. In order to suppress this deterioration in performance, an LSI in which the threshold voltage of the MOS transistor is lowered is manufactured.

  When the threshold value of the MOS transistor is lowered, a leak current called a subthreshold current of the MOS transistor increases. The leakage current continues to flow regardless of whether the circuit is operating or not. In the standby state, the SRAM does not perform write / read operations, but continues to hold data. Therefore, the power consumption in the standby state of the system LSI is the leakage current of the MOS transistor in the circuit. When the threshold voltage of the MOS transistor is lowered, the power consumption in the standby state increases. Here, in the system LSI, a state where the logic circuit does not operate and the SRAM circuit holds data is referred to as a standby state.

  Since the logic circuit is not operating during standby, the leakage current can be reduced by shutting off the power supply using a switch. In addition, since the SRAM memory cell has a flip-flop structure, the leakage current is relatively small. In the conventional system LSI, the capacity of the mounted SRAM circuit is not large or the SRAM transistor is a high threshold MOS transistor. Therefore, the leakage current in the SRAM circuit was not a problem. However, if MOS transistors are miniaturized and a large-capacity SRAM is mounted on the system LSI and the threshold voltage of the MOS transistors constituting the SRAM memory cells is lowered, the leakage current in the SRAM memory cells can be ignored. Disappear. In the logic circuit, the leakage current during standby can be reduced by shutting off the power supply with a switch. However, since the SRAM circuit needs to hold the data in the standby state, the power supply cannot be shut down and the leakage current is reduced. The current cannot be reduced. Further, when the voltage is lowered and the threshold voltage of the MOS transistor is lowered, the leakage current in the circuit attached to access the memory cell in the SRAM circuit increases.

Of the inventions disclosed in the present application, the outline of typical ones will be described as follows.
(1) In an LSI in which a logic circuit and an SRAM circuit are mixedly mounted, the power supply of the logic circuit is cut off by a switch during standby, and the SRAM circuit controls the substrate potential of the MOS transistor so that the leakage current can be reduced.
(2) The power supply of the control circuit for accessing the memory cells in the SRAM circuit is divided and cut off to reduce power consumption.
(3) The SRAM circuit is divided so that some SRAMs hold data during standby, and SRAMs that do not hold data shut off the power and reduce leakage current.

  According to the present invention, it is possible to reduce power consumption during standby in an LSI in which a logic circuit and an SRAM circuit are mounted together.

It is a figure showing the outline of the relationship between the logic circuit and SRAM circuit of the system LSI to which this invention was applied, and its power supply. It is a schematic diagram of the layout of the system LSI of FIG. FIG. 2 is a diagram showing a change in potential of each node in the circuit shown in FIG. 1. It is a figure showing the example of the circuit of the control circuit CNTS in FIG. It is a wave form diagram of the signal for changing the state of the circuit of FIG. FIG. 6 is a diagram illustrating an example of a circuit that generates the signal illustrated in FIG. 5. It is a figure showing the relationship between the internal structure of the SRAM circuit to which this invention was applied, and its power supply. It is the figure which showed the structure of the logic circuit to which this invention was applied. It is the figure which showed the structure of the transistor of the system LSI to which this invention was applied. It is a figure showing the 1st modification of the switch of a logic circuit. It is the figure which showed the change of the electric potential of each node in the circuit shown in FIG. It is a figure showing the 2nd modification of the switch of a logic circuit. It is a figure showing the 3rd modification of the switch of a logic circuit. It is a figure of the application example of FIG. It is the figure which applied the step-down circuit to the SRAM circuit. FIG. 16 is a diagram showing a change in potential of each node in the circuit shown in FIG. 15. It is a circuit diagram of switch circuit CNTV1 in FIG. 8 is a first modification of the SRAM circuit of FIG. 8 is a second modification of the SRAM circuit of FIG. It is the figure which applied substrate bias control to a logic circuit. It is a figure showing the 1st modification which divided | segmented the SRAM circuit part. FIG. 22 is a diagram showing a structure of a transistor constituting a plurality of SRAM circuits in FIG. 21. It is a figure showing the application example of the system of invention of FIG. It is a figure showing the 2nd modification which divided | segmented the SRAM circuit. It is a figure showing the 3rd modification which divided | segmented the SRAM circuit. FIG. 25 is a diagram showing a circuit configuration example of a power supply control circuit CNVT2 in FIG. 24.

<Example 1>
FIG. 1 schematically shows the overall configuration of an LSI in which a logic circuit and an SRAM circuit using the present invention are mounted together. In FIG. 1, CHIP, which is an embedded LSI, includes an input / output circuit IO (IO circuit) that uses external power supply potential lines VssQ and VddQ as operating potentials, a logic circuit LOGIC that performs predetermined processing on data, and data The static memory circuit SRAM to be stored, the nMOS transistor N1 serving as a switch between the ground potential line Vss and the operating potential supply line Vssl on the low potential side of the logic circuit, and the signal stby input during the standby state are input. A control circuit CNTS that is connected to the gate electrode and outputs a signal cntn that controls N1 and a substrate bias control circuit VBBC that controls the substrate potentials Vbn and Vbp of the SRAM when stby is input are included. Hereinafter, unless otherwise specified, a power source having a symbol starting from Vdd is a power source supplying a high potential (high potential), and a power source having a symbol starting from Vss is a power source supplying a low potential (low potential). To do. The operating potential difference (VssQ−VddQ) supplied to the IO circuit is generally determined by the standard and is larger than the operating potential difference (Vss−Vdd) of the logic circuit or the SRAM circuit. As an example, 3.3V is supplied to VddQ, 1.2V is supplied to Vdd, and 0V is supplied to Vss and VssQ. The signal stby used for the control circuit CNTS is used via the IO circuit. The layout of the circuit of FIG. 1 on the semiconductor chip is shown in FIG. A core circuit (a logic circuit, an SRAM circuit, or the like) is disposed inside the input / output circuit IO (IO circuit). The IO circuit is connected to the input / output pad. For the IO circuit, a MOS transistor having a thicker gate insulating film than the MOS transistor used in the core circuit is used. This is because, in general, a higher power supply voltage is applied to an IO circuit than to a core circuit, so that a breakdown voltage is required. The power switch, the substrate bias control circuit VBBC, and the power switch control circuit CNTS included in the power control system POW in FIG. 1 can be integrated to increase the degree of integration. This is advantageous when the transistor size (channel length, channel width) is different from that of the logic circuit or SRAM circuit. The substrate bias control circuit includes a control switch, a charge pump circuit, and the like.

  N1 in FIG. 1 uses a thick nMOS transistor used for an IO circuit. The substrate potential of the power switch N1 is connected to the source side. Hereinafter, it is assumed that the substrate potential of the MOS transistor constituting the switch connected to the power source is connected to the source potential of both the N-channel and P-channel MOS transistors unless otherwise specified. Use of a thick-film MOS transistor is effective for countermeasures against gate tunnel leakage current. Further, since the withstand voltage is excellent, the voltage applied to the gate of the switch N1 can be made larger than the operating voltage, and the leakage current when the nMOS is made non-conductive can be suppressed. When the transistor constituting the LSI has only one type of film thickness, or when the MOS transistor used in the IO circuit by design cannot be used in the core portion, a MOS transistor having a thin insulation film thickness can be used as a switch. In that case, the leakage current cannot be completely cut off by the switch N1. Therefore, when this leakage current is within the allowable range, the MOS switch may be formed only by a thin film MOS transistor. However, when the leakage current exceeds the allowable value, the logic circuit and the switch N1 or the switch N1 are used. It is necessary to take a method such as reducing the leakage current by controlling only the substrate potential.

  The reason why the nMOS transistor is used as a switch for shutting off the power supply is that the current flowing in the nMOS is larger than that in the pMOS, so that the size of the switch can be reduced when the same current is attempted to flow. Therefore, if the size of the switch is not taken into consideration, such as when there is a margin in the area, it is possible to turn on the pMOS switch that cuts off the power supply Vdd instead of turning on the nMOS switch that cuts off the ground power supply Vss. FIG. 3 shows examples of potentials in the active state ACT and the standby state STB of each part of the circuit. Here, the active state ACT represents a state in which the logic circuit and the SRAM circuit are operating. Vdd and Vss in FIG. 1 are a power source of a core including an SRAM circuit and a logic circuit, and the voltage of Vdd is 1.2V and the voltage of Vss is 0.0V. In the active state, since the standby signal stby is low, the switch control signal is high and the nMOS switch is on. The substrate potentials Vbn and Vbp of the nMOS transistor and pMOS transistor of the SRAM circuit are 0V and 1.2V, respectively, and the substrate bias Vbs applied to the MOS transistor in the SRAM circuit is 0V. Therefore, the threshold voltage of the MOS transistor constituting the SRAM circuit is not changed from a value determined by the transistor structure (gate width, gate length, implantation amount).

  In the standby state, the standby signal stby becomes high. Accordingly, the signal cntn for controlling the nMOS switch becomes low and the nMOS switch becomes non-conductive. At the same time, the substrate potentials Vbn and Vbp of the nMOS transistor and the pMOS transistor constituting the SRAM circuit become −1.2V and 2.4V, respectively. As a result, a substrate bias of 1.2 V is applied to the MOS transistor in the SRAM circuit, the threshold voltage of the MOS transistor increases, and the leakage current of the MOS transistor decreases.

  A circuit for generating the signal cntn for controlling the switch using the input standby signal stby can be realized by a simple circuit as shown in FIG.

  Further, when the circuit of FIG. 4 is used, it is necessary to always input high as the standby signal stby in the standby state STB as shown in FIG. Here, for example, the standby signal stby is input only when the standby state STB is entered, and the active signal ack is input when the standby state STB changes to the active state ACT. FIG. 5 shows potential changes of the standby signal stby, the active signal ack, and the control signal cntn at that time. When the standby signal stby is input, the control signal cntn becomes low and the power switch is turned off, so that the leakage current can be reduced. When the active signal ack is input, the control signal cntn becomes high, the power switch is turned on, and power is supplied to the logic circuit.

  FIG. 6 shows a circuit CNTS for outputting the signal having the waveform shown in FIG. A flip-flop is used to store in the circuit that the STB is in the standby state. At this time, a signal for returning to the active state ACT is prepared. FIG. 7 shows a configuration example of the SRAM circuit SRAM in FIG. The SRAM circuit is connected to the memory cell array MAR and the gates of the peripheral circuits PERI1 and PERI2 for accessing the memory cells, and the MOS transistors s_sw2 and s_sw1 and s_sw2m serving as switches for cutting off the power lines Vss and Vdd of the PERI1 or PERI2. An inverter is included to input an inverted signal of the signal stby for transmitting the standby state. The substrate bias potential can be controlled by connecting the substrate potential of the P-channel MOS transistor included in SRAM_CIR to Vbp and connecting the substrate potential of the N-channel MOS transistor to Vbn. The MAR is a circuit in which SRAM memory cells are arranged on an array. The memory cell is composed of a flip-flop (first and second P-channel load MOS transistors, first and second N-channel drive MOS transistors) formed by connecting the inputs and outputs of a pair of CMOS inverters to each other. And first and second N-channel transfer MOS transistors connected between the two storage nodes of the flip-flop and the bit lines (BL, / BL). A word line WL is connected to the gate electrode of the N channel type transfer MOS transistor. The operating potential of the memory cell is given by Vddma and Vssma. Peripheral circuit PERI1 includes a circuit for controlling word lines WL of memory cells including word driver WDR, row decoder RDEC, and memory controller MCNT. The operating potential of the circuit included in PERI1 is given by Vddper and Vssper. The peripheral circuit PERI2 includes a circuit for controlling a bit line BL of a memory cell including a precharge circuit PRE, a read amplifier / write amplifier RWAMP, which is a read / write control circuit connected to the bit line, and a column decoder CDEC. Yes. The read / write amplifier RWAMP includes an OBUF, which is an output buffer of the sense amplifier, and a control circuit WCNT of the write amplifier. The operating potential of the circuit included in PERI2 is given by Vddamp and Vssamp. In / stby in the figure, a low signal is input to STB during standby. As a result, during standby, the power supply line Vdd input to PERI1 is shut off, and at the same time, the power supply line Vss input to PERI2 is shut off. At the same time, Vbn and Vbp for supplying the substrate potentials of the MOS transistors constituting MAR, PERI1, and PERI2 are controlled so as to increase the absolute value of the threshold voltage of the MOS transistors. Thus, by applying a substrate bias to the SRAM memory cell and applying a substrate bias to the peripheral circuit and providing a switch to the power supply to reduce leakage current, the power consumption of the SRAM during standby can be reduced. Can be reduced.

  In FIG. 7, the peripheral circuit is divided into two and Vss and Vdd are cut off for the following reason. In the standby state, the word line is low, and in the operation state, the word line is low except for the selected word line. Therefore, the circuit that drives the word line can cut off the power supply Vdd that is a high potential, thereby reducing the leakage current, and shortening the time required to return from the standby state, compared to shutting off the power supply Vss that is a low potential. . In other words, when the switch is turned on on the Vdd side, a smaller switch is required than on the switch on the Vss side. On the contrary, since the bit line is normally charged to Vdd in the SRAM, the amplifier or the like is often configured to be stable in the state charged to Vdd. Therefore, when the bit line is charged to Vdd during standby and the power supply Vss of the read amplifier and the write amplifier is shut off by the switch, the leakage current can be reduced, and the return time from the standby state to the active state is shortened. In the circuit that precharges the bit line to Vdd, it is advantageous in terms of leakage current and recovery time to cut off Vss of the circuit that drives the bit line, but naturally in the circuit that precharges the bit line to Vss, Vdd. It is advantageous to cut off the switch on the side, and it is possible to take the configuration.

  The circuit in FIG. 7 assumes the SRAM in the system LSI as shown in FIG. 1, but can be applied not only to the system LSI but also to the memory LSI. Further, FIG. 7 is a diagram for controlling the substrate bias of the SRAM circuit. If the power consumption in the standby state can be sufficiently reduced by suppressing the leakage of the peripheral circuit, the substrate bias is not necessarily set. There is no need to apply it. In particular, if the characteristics of the MOS transistor change in the future, and the leakage current called junction leakage of the MOS transistor increases more than the leakage current called the sub-threshold of the MOS transistor, the method of controlling the substrate potential may not reduce the leakage current. There is sex. In that case, a configuration in which the power supply of the logic circuit in the system LSI and the peripheral circuit of the SRAM is cut off by a switch is considered to be a particularly important technique. FIG. 8 shows a configuration example of the logic circuit OGIC in FIG. The logic circuit LOGIC_CIR is composed of an inverter composed of a P-channel MOS transistor and an N-channel MOS transistor, and logic gates such as NAND and NOR, which are connected in multiple stages. Since no substrate potential is applied to the transistors in the logic circuit, the substrate potential of the P-channel MOS transistor is connected to the high potential side Vdd of the operating potential, and the substrate potential of the N-channel MOS transistor is the low potential of the operating potential. Connected to the side Vssl. FIG. 9 shows a MOS transistor used in a logic circuit or SRAM circuit (CORE) in the LSI, a MOS transistor used in the input / output circuit IO of the LSI, and a switch logic that cuts off the power supply of the logic circuit shown in FIG. The structure of the kind of MOS transistor used for switch S_SW which cuts off the power supply of the MOS transistor used for sw and the peripheral circuit of SRAM shown in FIG. 7 is represented. Although the threshold voltage differs between the P-channel MOS transistor and the N-channel MOS transistor, the absolute value is shown in FIG. Generally, a thick film transistor with a thick insulating film is used for an input / output circuit portion of an LSI, and a thin transistor with a thin insulating film is used for an internal logic circuit or the like. In this figure, an MOS transistor having an insulating film thickness of 6.7 nm is used as an example of a MOS transistor having a thick insulating film, and an MOS transistor having an insulating film thickness of 2.0 nm is used as an example of a MOS transistor having a thin insulating film. In addition, as a thin MOS transistor, a MOS transistor having two or more threshold voltages is often used depending on the amount of impurities. FIG. 9 shows an example in which two types of MOS transistors having a threshold voltage Vth of 0.40 V and 0.25 V are used. A MOS transistor having a lower threshold voltage has a larger current during operation, but also has a larger leakage current during standby. In all combinations, the logic circuit LOGIC_CIR and the SRAM circuit SRAM_CIR excluding the control switch have two types of Vth MOS transistors with a thin gate insulating film, and the IO has a MOS transistor with a thick gate insulating film and a high Vth. Used. In LOGIC_CIR, low threshold transistors are used for the critical path and high threshold transistors are used for the remaining circuits. In SRAM_CIR, a high threshold transistor is used in the memory cell array MAR in order to reduce leakage current and maintain static noise margin (SNB). The peripheral circuit PERI including the precharge circuit, the sense amplifier, the word driver, and the decoder uses a low threshold MOS transistor because high speed is required.

  In the Pattern 1 combination, a thick-film MOS transistor having a high Vth is used for the power switch of the logic circuit, and a thin-film MOS transistor having a high Vth is used for the power switch of the peripheral circuit in the SRAM circuit. A thick film MOS transistor is used for the power switch of the logic circuit to suppress the leakage current of a large-scale circuit. In the SRAM, since the leakage current is suppressed by controlling the substrate bias, the entire leakage current is suppressed because a thin MOS transistor having a somewhat large leakage is used for the power switch. In addition, when the circuit scale of the peripheral circuit included in the SRAM circuit is not large, it is considered that the leakage current of the peripheral circuit is not large, so that the configuration of Pattern 1 is effective. Furthermore, when designing an SRAM circuit as a module that can be easily reused, it is possible to design the SRAM circuit by considering the characteristics of only the thin film MOS transistor. However, the design efficiency is improved. As described above, in the Pattern 1 configuration, when the size of the SRAM circuit itself is not large, when the size of the peripheral circuit in the SRAM circuit is not large, when leakage current can be greatly reduced by controlling the substrate bias, This configuration is effective when considering design efficiency.

  In the pattern 2 combination, a thick MOS transistor having a high Vth is used for both the power switch of the logic circuit and the power switch of the peripheral circuit in the SRAM circuit. As a result, the leakage current of circuits other than the SRAM memory cell in the LSI can be reduced, and the power consumption during standby is reduced as compared with Pattern 1. However, when designing the SRAM circuit, it is necessary to consider the characteristics of the thick film MOS transistor, so that the design efficiency is lowered. The combination of Pattern 2 is an effective combination when the scale of the SRAM circuit is large, when the scale of the peripheral circuit of the SRAM is large, or when the effect of reducing the leakage current by controlling the substrate bias cannot be expected greatly.

  In the pattern 3 combination, a thin film MOS transistor having a high Vth is used for both the power switch of the logic circuit and the power switch of the peripheral circuit in the SRAM circuit. In this case, since a thin-film MOS transistor is used, the effect of reducing the leakage current is reduced as compared with Pattern2. However, since it is not necessary to consider the characteristics of the thick film MOS transistor, the design efficiency is improved. The combination of Pattern 3 is effective when the effect of reducing the leakage current of the LSI is not so great and design efficiency is required.

As described above, in the standby state, the power supply of the logic circuit is cut off by the switch and the substrate bias is applied to the SRAM circuit, thereby reducing the leakage current of the system LSI and reducing the power consumption in the standby state. .
<Example 2>
In this embodiment, a modification of the power switch used in the logic circuit is shown. FIG. 10 shows a circuit block diagram when the power switch mounted only on the power supply Vss of the logic circuit portion in the circuit of FIG. 1 is attached to the power supplies Vdd and Vss. By providing a switch to Vdd and Vss that are two power supplies of the logic circuit to cut off the power supply, an increase in area due to the provision of the power switch increases, but it is possible to more reliably cut off the leakage current during standby. It becomes possible. Although an IO circuit is shown in FIG. 1, it is omitted in FIG. Hereinafter, the IO circuits in the CHIP are also omitted in other drawings.

  FIG. 11 shows the potential of each part of the circuit when the circuit of FIG. 10 is used. This figure is a diagram in which the signal cntp for controlling P1 of the pMOS which is a switch for cutting off the Vdd of the logic portion is added to the potential of FIG. cntp goes low in the active state ACT and goes high in the standby state STB. Therefore, although the internal circuit of the circuit CNTS2 that outputs the control signal in FIG. 7 is not specifically described, it is also possible to take a circuit in which a circuit that outputs a signal of an opposite phase is added to the circuit of FIG. 4 or FIG. is there. 1 and FIG. 10, the circuit in the case where the logic circuit in FIG. 1 is integrated has been described. FIG. 12 shows a block diagram of a circuit when the present invention is applied to an LSI in which a logic circuit is divided into two or more blocks. Although FIG. 12 shows an example in which the logic circuit is divided into two blocks, the same configuration can be applied even when the logic circuit is divided into three or more blocks. The memory-embedded LSI shown in FIG. 12 includes switches N2 and N3 for connecting the ground potential power lines Vssl1 and Vssl2, Vssl1 and Vssl2 of the logic circuits LOGIC1 and LOGIC2, LOGIC1 and LOGIC2, respectively, to the power line Vss of the entire LSI, and a static memory circuit SRAM. The switch control circuit CNTS and the circuit VBBC for controlling the substrate potential of the SRAM. The configuration is the same as that of the circuit of FIG. 1 except that there are a plurality of logic circuits, and the operation is the same as that of the circuit of FIG. By dividing the logic circuit into a plurality of blocks and providing a switch for shutting off the power supply to each block, an optimum switch can be added to each block. For example, an nMOS switch that blocks Vss is added to some logic blocks, a pMOS switch that blocks Vdd is added to another block, or two power supplies of Vdd and Vss are blocked depending on the block. A switch can be provided.

  In the memory-embedded LSI shown in FIG. 13, a power switch is added to each block of each logic circuit, the power switch is controlled by different signals cntn1 and cntn2, and control signals cntn1 and cntn2 are separately transmitted. 12 is different from that shown in FIG. 12 in that the control circuit CNTS3 is controllable. The CNTS3 is a circuit capable of controlling the control signals cntn1 and cntn2 of the power switch, and can be controlled such that the switch N2 is cut off and the switch N3 is turned on depending on the operation state of the circuit. As a result, the logic circuit block that needs to be operated in the standby state is operated, and the logic circuit block that can be stopped and the SRAM circuit are set in the standby state, thereby reducing the leakage current. .

In FIG. 13, as in FIG. 12, it is possible to make a combination in which there are three or more logic blocks, or the Vss side power supply or the Vdd side power supply or both are cut off for each block. In the configuration of FIG. 13, since it is possible to control the supply of power for each block to be in a standby state, that is, a low leakage state, a logic circuit and an SRAM that do not need to operate not only in the standby state but also in the active state It is also possible to minimize the leakage current by controlling the power switch so that the circuit is in a standby state.
FIG. 14 shows an example in which the embodiment of FIG. 13 is applied to a system (microcomputer) equipped with a central processing unit. The system LSI is called a central processing unit CPU, which is a logic circuit block CPU capable of various operations, a logic circuit block DSP dedicated to digital signal operations, a static memory block SRAM circuit, and a bus BUS that connects the blocks and exchanges data. The circuit BSCNT controls the bus and the circuit IO exchanges data with the outside. Since each block exchanges data through the bus in the active state, it can be known whether the block is operating by monitoring the operating state of the bus. For example, when the entire circuit is not operating, if the circuit BSCNT controlling the bus notifies the switch control circuit CNTS3 that all the blocks are in a standby state by a signal stat1, CNTS3 sets cntn1 and cntn2 to each other. The switches N2 and N3 are cut off and the leakage current of the logic circuit can be reduced. At the same time, if VBBC controls Vbn and Vbp, which are the substrate potentials of the SRAM, to reduce the leakage current of the SRAM, the leakage current of the entire circuit can be reduced. Also, for example, when only the CPU is operating and there is no access to the DSP and SRAM via the bus, BSCNT outputs the information via stat1, puts the SRAM substrate potential into the standby state, and shuts off the DSP power switch N3. Thus, it is possible to create a state in which the DSP is in the standby state and only the CPU is in the active state.
<Example 3>
FIG. 15 schematically shows the entire configuration of an LSI in which a logic circuit and an SRAM circuit using the present invention are mounted together. The CHIP, which is an embedded LSI, is input during the standby state, the logic circuit LOGIC, the static memory circuit SRAM, the nMOS transistor N1 serving as a switch between the ground potential line Vss from the outside and the ground potential line Vssl of the logic circuit. A control circuit CNTS that receives a signal stby that is connected to the gate electrode of N1 and outputs a signal cntn that controls N1, and a substrate bias control circuit VBBC that controls the substrate potentials Vbn and Vbp of the SRAM when stby is input. , A circuit CNTV1 for controlling the power supply line Vddm of the SRAM by the stby signal.

  The configuration of FIG. 15 is the same as that of the circuit of FIG. 1 except for CNTV1, and operates in the same manner as FIG. 1 except for CNTV1. When the stby signal is input when the CNTV1 enters the standby state, the power supply voltage of the SRAM is lowered from Vdd to a voltage lower than Vdd that can hold data. Thereby, in the standby state, the substrate potential of the SRAM is controlled, the leakage current is reduced, and the power supply voltage is lowered, so that the leakage current can be further reduced, and the power consumption during standby can be further reduced as compared with the circuit of FIG.

  FIG. 16 shows the potentials at the time of ACT and STB at the time of standby of each part of the circuit of FIG. The voltage of the circuit power supply Vdd indicates a potential in the case of 1.2V. stby, cntn, Vbn, and Vbp are the same as those in FIG. 3, which is the operating potential of FIG. The power supply voltage Vddm of the SRAM is 1.2 V, which is the same as the power supply voltage when active, and is 0.6 V during the standby STB. As a result, the leakage current in the SRAM can be reduced.

The power supply control circuit CNTV1 in FIG. 15 can be realized by the circuit of FIG. 16, for example. CNTV1 includes a step-down circuit PDC and a changeover switch. When the SRAM circuit is in the active state ACT, the power supply line Vddm for supplying the operating potential to the memory cells in the SRAM circuit is connected to the power supply Vdd supplied from the outside by the changeover switch, and the power supply voltage of the SRAM circuit is equal to Vdd. Become. In the standby state STB, the selector switch is switched by the signal stby, and Vddlow, which is lower than Vdd generated by the step-down circuit and is higher than the potential capable of holding the data in the SRAM memory cell, is connected to the power supply Vddm of the SRAM circuit. The power supply voltage of the circuit becomes lower than Vdd. Although the voltage is stepped down on the high potential side in FIG. 15, the power supply control circuit CNTV1 can be connected between Vssm and Vss so that CNTV1 can be a booster circuit. The same effect can be obtained by boosting the low potential side or combining boosting and stepping down.
<Example 4>
FIG. 18 shows a modification of the circuit of FIG. In FIG. 7, the power supply of the memory cell array is Vddma and Vssma, the power supply of the circuit RWAMP including the circuit for driving the bit line is Vddamp and Vssamp, the power of the other circuits is Vddper and Vssper, and the power supply in the SRAM circuit is 3 In the system, a switch composed of an N-channel MOS transistor is connected between the peripheral circuit PERI2 used for bit line control and the low-potential power supply, and the peripheral circuit PERI1 used for word line control and the high-potential power supply. A switch consisting of a P-channel MOS transistor is inserted between the two, but here it is configured so that each power supply can be shut off during standby by inserting switches on the high potential side and low potential side of the three power sources It is. In this circuit, all power supplies include switches composed of MOS transistors, and in standby, the control signal cntmp1 and the control signal cnttmp2 are set to low, the control signal cnttmp3 is set to high, and the control signal cntmn1 and the control signal cntmn3 are set to high. In addition, by setting the control signal cntmn2 to low, the switches P6, P7, N6 and N8 are turned on, and the switches P8 and N7 are cut off, whereby the configuration of FIG. 7 can be realized. P6 and N6 need to be kept conductive even during standby to hold information in the SRAM memory cell. However, when the SRAM circuit described later is divided into blocks, P6 and N6 are set to P6 and N6 in a block that does not need to hold information. Adopting a configuration that cuts off N6 is also effective in reducing power consumption. The Vdd side of a read / write amplifier that is considered to be used in a circuit that precharges the bit line to low by setting cntmp2 high instead of setting the signal cntmn2 applied to the switch that controls Vssamp during standby to low. A circuit that shuts off the power supply can be realized. Thus, in the circuit shown in FIG. 18, several types of circuits can be realized depending on how the control signal is controlled.

FIG. 19 shows a circuit obtained by partially changing the circuit of FIG. The power supply of the column decoder CDEC is connected to Vddper and Vssper. In FIG. 7, the column decoder CDEC cuts off the power supply on the Vss side. However, since the column decoder is arranged near the amplifier, circuit design is easy if the power is cut off with the same switch as the amplifier. This is because it is considered to be. However, if the column decoder uses a common power supply for the word line control circuit and shuts off the power supply on the Vdd side, the design of the power supply arrangement and the like is not complicated, so that the Vdd side can be shut off. it can. Since the column decoder controls the bit line but has many nodes that take a low potential during operation as in the word driver WDR (the number of selection lines is larger than that of non-selection lines), it is the same as the memory controller MNCT that uses switches on the high potential side. It is advantageous to take the operating potentials Vddper and Vssper. For the same reason, although not shown in the figure, it is preferable that the control circuit WCNT of the write amplifier is also connected to Vddper and Vssper. In FIG. 19, switches for the three power sources in FIG. 18 (switches by P-channel MOS transistors provided between Vdd and Vddma, Vddamp and Vddper, respectively, and provided between Vss and Vssma, Vssamp and Vssper, respectively. N-channel MOS transistor switch) and power supply line that does not go through the switch are prepared, but the SRAM circuit is blocked depending on whether it is better to provide a switch that cuts off the low potential side or the high potential side. By doing so, the P-channel MOS transistor connected to Vddamp and the N-channel MOS transistor connected to Vssper can be omitted. In this circuit, unlike FIG. 7, the power source connected to the row decoder RDEC is directly connected to the power sources Vdd and Vss outside the SRAM circuit, not the power source that can be shut off in the SRAM circuit, and the power is supplied to the row decoder during standby. ing. This is to prevent the transfer MOS in the memory cell from becoming conductive due to noise on the word line due to a difference in power supply time when returning from the standby state. This noise is generated because the power supply of the word driver powers on the preceding stage powers up quickly, and a low signal is input to the word driver, and the word driver outputs high. . By supplying power to the row decoder during standby, a low signal is not input to the word driver, and noise is not applied to the word line. In FIG. 19, the power supply for the entire row decoder is directly connected to the power supplies Vdd and Vss supplied from the outside. However, with this circuit configuration, the leakage current of the row decoder cannot be reduced. Therefore, although not shown in particular, the power supply of the entire row decoder is not connected to Vdd and Vss, but the power supplies Vdd and Vss are connected only to the preceding circuit of the word driver, such as a NAND circuit, and the other row decoder circuits. A circuit configuration in which a power source that is cut off by a switch is connected can be considered. With this circuit configuration, the leakage current can be reduced, but the arrangement of the power supply in the row decoder becomes complicated and the design becomes difficult. Therefore, when the scale of the row decoder in the SRAM circuit is relatively large and it is necessary to suppress the leakage current of the row decoder, the power supplies Vdd and Vss supplied from the outside are connected only to the previous circuit of the word driver. The other row decoder circuits are connected to a power supply that can be turned off during standby by a power switch. If the scale of the row decoder is not large and the influence of the leakage current of the row decoder is small, It is considered that this configuration in which all the power supplies of the row decoder are connected to Vdd and Vss is effective. As shown in FIG. 19, by dividing and controlling the power supply of the peripheral circuit of the SRAM according to the function, it becomes possible to reduce the leakage current of the peripheral circuit of the SRAM.
<Example 5>
FIG. 20 shows a configuration diagram in which the substrate bias control is performed not only on the SRAM circuit but also on the logic circuit in the LSI in which the logic circuit and the SRAM circuit of FIG. 1 are mixedly mounted. The CHIP, which is an embedded LSI, includes a logic circuit LOGIC, a static memory circuit SRAM, an nMOS transistor N1 that serves as a switch between the ground potential lines Vssl of the logic circuit, and a substrate potential line Vbnl of the MOS transistors that constitute the logic circuit and the SRAM circuit. , Vbpl, Vbnm, and Vbpm are connected to Vdd, Vss, Vbn, and Vbp, a switch SW1, a control circuit that outputs a signal cntn that controls N1, and a signal cntvbb1 and cntvbb2 that controls switch SW1. CNTS4 and a substrate bias control circuit VBBC2 for generating substrate biases Vbn and Vbp are included.

  The voltage of each part at the time of active and standby becomes the voltage shown in FIG. At the time of standby, the power supply of the logic circuit is cut off, and the substrate potential of the logic circuit is controlled to reduce the leakage current of the logic circuit.

In this circuit, when the power switch of the logic circuit is made of a low-threshold MOS transistor as shown by Pattern 3 in FIG. 9, when there is a leakage current at the power switch, a substrate bias is applied. This is effective because the leakage current of the logic circuit is reduced. In this circuit, the substrate potentials of the logic circuit and the SRAM circuit can be controlled independently. By setting only the SRAM circuit in the standby state and the logic circuit in the active state, leakage current in the SRAM circuit can be reduced when only the logic circuit is operating. It is also possible to reduce the leakage current of the logic circuit by applying a substrate bias to the logic circuit and operating the SRAM circuit. As described above, by providing the logic circuit and the SRAM circuit with a switch that can select whether or not to apply the substrate bias, an operation of reducing the leakage current according to the operation state can be performed. Further, by finely controlling the block that controls the substrate potential, it is possible to change the amount of load that changes the voltage by applying the substrate bias. In other words, if a substrate bias is not applied to an unnecessary portion by providing a switch, the load required to change the potential is reduced, and the time required for the potential change can be shortened.
<Example 6>
FIG. 21 shows a first modification in which the SRAM circuit of FIG. 1 is divided into blocks. In FIG. 24, CHIP, which is an embedded LSI, includes a logic circuit LOGIC, static memory circuits SRAM1 and SRAM2, an nMOS transistor N9 serving as a switch between the power supply Vss and the ground potential line Vssl of the logic circuit, and the power supply Vss and SRAM1. Includes an nMOS transistor N10 that functions as a switch with respect to the ground potential line Vssm1, a control circuit CNTS that outputs a signal cntn for controlling N9 and N10, and a substrate bias control circuit VBBC that generates substrate biases Vbn and Vbp. The SRAM circuits SRAM1 and SRAM2 can have the same configuration as that of the modified example of FIG. 7 and FIG.

  In this circuit, the SRAM circuit of FIG. 1 is divided into two blocks, SRAM1 and SRAM2, and the power supply of the logic circuit and SRAM1 is shut off during standby, and a substrate bias is applied to SRAM2 to reduce the overall leakage current. Reduce power consumption during standby. Therefore, the leakage current of the SRAM 1 circuit can be reduced as compared with the circuit of FIG. However, in this structure, data stored in the SRAM 1 at the time of standby is erased. Therefore, data that needs to be stored at the time of standby needs to be stored in the SRAM 2. In system LSI, several SRAM blocks are mixedly mounted, and there are many possible configurations in which blocks that need to retain data during standby and blocks that do not exist are mixed. By using it, the effect of reducing the leakage current is great.

  FIG. 22 shows combinations of MOS transistors used in each SRAM memory cell circuit when the SRAM circuit is divided into two. In this figure, in the same way as in FIG. 9, the MOS film thickness is 6.7 nm as an example of a thick MOS transistor, and the MOS transistor thickness is 2.0 nm as an example of a thin MOS transistor. Use. Further, as an example in which a thin MOS transistor has two types of threshold voltages, a case where two types of MOS transistors having threshold voltages Vth of 0.40 V and 0.25 V are used is given as an example. MAR1 represents a MOS transistor of the SRAM1 memory cell that can shut off the power supply, and MAR2 represents a MOS transistor of the memory cell of the SRAM2 that does not shut off the power supply. As the logic circuit LOGIC_CIR, as shown in the table of FIG. 9, two kinds of threshold MOS transistors are used. About 10% in the logic circuit uses low threshold MOS transistors, which are assigned to transistors in the critical path path. Although the MOS transistors in the peripheral circuit excluding the SRAM memory cell are not shown, a MOS transistor having the same threshold value as the low threshold value 0.25 V of the logic circuit is used. In either case, a thin film MOS transistor is used. IO represents a MOS transistor used in an input / output circuit. A MOS transistor having a thick film and a high threshold voltage is used in any combination.

  In Pattern 1, a thin film MOS transistor having a high threshold voltage is used for memory cells in all SRAM circuit blocks. In this configuration, the area of the memory cell is reduced, and it is considered that the operation stability of the SRAM is excellent.

  Pattern 2 is a combination in which an SRAM memory cell to which no power switch is added is made of a MOS transistor having a small film thickness and a small leakage current, thereby reducing the leakage current. In this combination, the transistors constituting the memory cell in the SRAM 1 in which the power switch is turned on are made of thin-film MOS transistors, so the area is small and the operation is fast. Furthermore, the leakage current can be suppressed with a power switch. In addition, the leakage current at the time of standby can be reduced by forming the transistors constituting the memory cells in the SRAM 2 without the power switch using thick MOS transistors. However, since the area of the memory cell of the SRAM 2 is considered to be large, the advantage of this circuit is most obtained when it is used in a circuit that does not care much about the circuit area or a circuit that needs to reliably reduce the leakage current. This combination is also effective when the SRAM 2 has a small circuit scale.

  In Pattern 3, the memory cell of SRAM1 is made of a thin film MOS transistor having a low threshold voltage, and the memory cell of SRAM2 is made of a thin film MOS transistor having a high threshold voltage. When the threshold value of the MOS transistor constituting the SRAM memory cell is lowered, the leakage current increases and the power consumption during standby increases, and the operation margin of the SRAM itself disappears and the memory cell itself does not operate. There's a problem. The former problem can be avoided by providing a power switch. Therefore, this combination can be realized only when MOS transistors having such characteristics that the latter problem does not appear remarkably are used.

  Pattern 4 uses a thick-film MOS transistor as the MOS transistor constituting the memory cell of SRAM 2 in the combination of Pattern 3. As a result, the circuit area is larger than that of Pattern 3, but the leakage current can be reduced.

  FIG. 23 shows an application example of FIG. The CHIP, which is an embedded LSI, includes a logic circuit LOGIC, static memory circuits SRAM1 and SRAM2, a bus that transfers data between the logic circuit and the SRAM circuit, a power supply Vss, and a ground potential line Vssl of the logic circuit. NMOS transistor N9 that functions as a switch, nMOS transistor N10 that functions as a switch between power supply Vss and ground potential line Vssm1 of SRAM 1, control circuit CNTS5 that outputs control signals cntn and dtran in the standby state, and substrate bias Vbn And a substrate bias control circuit VBBC for generating Vbp.

  Normally, in the system LSI, data is exchanged between the logic circuit and the SRAM circuit through the bus, so it is considered that the bus also exists in the system LSI circuit of FIG. Therefore, the circuit of FIG. 23 is different from the circuit of FIG. 21 only in the control circuit CNTS5 in the standby state, and the operation of this circuit and the operation of the bus will be described. When the LSI is set to the standby state, the control circuit CNTS5 uses the control signal dtran to control the logic circuit, and the data that needs to be stored in the SRAM 1 during standby is saved to the SRAM 2 via the bus. When the evacuation is completed, the control circuit CNTS5 is informed through the dtran that the evacuation has been completed. As a result, a signal for transition to the standby state is output from the control circuit CNTS5, the power supply of the logic circuit and the SRAM 1 is shut off by the switch, and a substrate bias is applied to the SRAM 2 so as to reduce the leakage current. Conversely, when returning from the standby state to the active state, a signal is output from the control circuit CNTS5, power is supplied to the logic circuit and the SRAM 1, and the standby state substrate bias of the SRAM 2 is switched to the active state bias. . When the power supply voltage of the logic circuit and the SRAM 1 and the substrate potential of the SRAM 2 are stabilized, the circuit for controlling the bus is controlled through the control signal dtran, and the data of the SRAM 1 saved in the SRAM 2 is restored. In this circuit, data that needs to be held during standby can be held, and the leakage current of memory cells corresponding to data that does not need to be held can be reduced. FIG. 24 shows an SRAM circuit according to a second modification in which the SRAM circuit is divided into blocks and a power supply control circuit portion thereof. In FIG. 15, the SRAM circuit is a single step-down circuit, and the high-potential side potential of the SRAM circuit is controlled by CNTV1, but by dividing it, optimal control is performed for each block (SRAM1 is stepped down, but SRAM2 is read out) -It is possible not to step down to perform a write operation. Similar to the case of FIG. 15, the same effect can be obtained by boosting the low potential side or a combination of boosting and stepping down instead of stepping down on the high potential side. The CNTV2 may use the circuit shown in FIG. The step-down voltage needs to be equal to or higher than the minimum voltage that can be stored in the SRAM. FIG. 25 shows an SRAM circuit of a third modification in which the SRAM circuit is divided into blocks and a power supply control circuit portion thereof. Four SRAM blocks SRAM1, SRAM2, SRAM3 and SRAM4, switches P9, P10, P11 and P12 each composed of a P-channel MOS transistor for shutting off the power of each block, and a control circuit CNTS6 for controlling the power switch It is configured. At the time of standby, the power supply of the block that needs to hold data is not cut off, and the power supply of the block that does not need to hold data is cut off. With this circuit configuration, the leakage current of the SRAM circuit can be limited only to the blocks that require data retention. Although an example of a P-channel type MOS transistor has been illustrated, as described above, it is more advantageous to replace the N-channel type transistor in terms of area efficiency. In FIG. 21, a block that does not shut off the power supply is provided and information holding is required, but the information of other blocks that are shut off during standby is transferred. However, according to this configuration, the process of transferring data is performed. There is no need to do it. However, a means for detecting whether or not information holding is required is added, and only the power switch of the block that does not need to hold information is cut off by the means. Therefore, as a control method of the control circuit CNTS6, for example, a block in which necessary data is stored is stored, and control is performed to shut off the power of the block in which no data is stored when transitioning to a standby state. A method is conceivable. In addition, a control method in which a block that shuts off the power supply and a block that does not shut off the power supply are programmed at the time of circuit creation, and the power supply is shut off according to the program. In addition, a control method is also conceivable in which it is programmed which block power is to be shut off during operation, and the power is shut off only for the blocks that need to be shut off. As described above, various power cut-off patterns can be realized by changing the control method of the control circuit CNTS6.

  FIG. 26 shows a switch for connecting CNTV2 of FIG. 24 to one of three power states. The three power states are a state connected to a power source voltage Vdd supplied from the outside, a state connected to a power source having a voltage lower than Vdd capable of holding data in the SRAM, and the power source is shut off. State. When three power supply states can be connected, the power supply of all the blocks is connected to Vdd in the active state, and the power supply of the block that needs to hold data is connected to a power supply having a voltage lower than Vdd in the standby state. Block the power supply of the blocks that do not need to hold data. As a result, the leakage current of a block that needs to hold data can also be reduced. PDC in the figure is a step-down circuit that outputs a voltage that allows the SRAM memory cell to hold data at a voltage lower than the power supply Vdd. In this circuit, the switch is switched according to the value of the input control signal cntp1, and the memory power supply Vddm is switched to Vdd, the circuit in which Vdd is stepped down, or nothing is connected. 25 can reduce the leakage current in the standby state. For example, the power supply of the SRAM block accessed in the active state is connected to Vdd, and the power supply of the block not accessed is lower than Vdd. Connect to the power supply. As a result, it is possible to reduce the leakage current of the unnecessary SRAM block when active. It is also possible to change CNTV2 from a step-down circuit to a step-up circuit and insert it between the power supply on the low potential side of the memory cell. In FIG. 24 and FIG. 25, the SRAM circuit is divided into four blocks. However, the circuit configuration can be applied when there are one or more blocks. Although described as a MOS (Metal-Oxide-Semiconductor) transistor as described above, there is no difference in the effects of the present invention even if it is replaced with a MIS (Metal-Insulated-Semiconductor) transistor that does not use an oxide film.

  CHIP: Chip, LOGIC / LOGIC1, LOGIC2 ... Logic circuit, SRAM / SRAM1 / SRAM2 ... Static memory circuit, POW ... Power supply control system, VssQ ... High potential side power supply line supplied from outside, VddQ ... Low supplied from outside Potential side power supply line, Vss ... Low potential side (ground) potential line of internal circuit, Vdd ... High potential side potential line of internal circuit, stby ... Standby signal, Vbn ... nMOS substrate potential line, Vbp ... pMOS substrate potential line, N1 ~ N10 ... nMOS power switch, P1-P12 ... pMOS power switch, cntn, cntp, cntn1, cntn2, cntmn1, cntmn2, cntmn3, cntp1, cntp2, cnttp3, cntp4, cntmp2, cntmp2, cntmp2, cntmp1, cntmp2, cntmp1, cntmp2, cntmp1, cntmp2, cntmp2, cntmp1, cntmp2, cnt TS / CNTS2 to CNTS5: power switch control circuit, VBBC / VBBC2 ... substrate bias control circuit, Vddl / Vssl / Vssl1 / Vssl2 ... logic circuit power line, IO ... input / output circuit, ack ... active state transition signal, FF ... flip-flop BUS ... Bus, BSCNT ... Bus control circuit, PDC ... Step down circuit, MAR ... Memory cell array, PERI1 / PERI2 ... SRAM peripheral circuit, CORE ... Logic circuit and SRAM circuit, WL ... Word line, BL // BL ... Bit line, WDR ... word driver, RWAMP ... read / write amplifier, PRE ... precharge circuit, CDEC ... column decoder, RDEC ... row decoder, MCNT ... memory control circuit, Vddma / Vssma / Vddamp / Vssamp / Vddper Vssperi: power supply for each memory, OBUF: read amplifier output buffer, cntvbb1, cntvbb2, substrate bias control signal, SW1, changeover switch, Vbpl, Vbnl: logic circuit substrate potential line, Vbpm / Vbnm: SRAM circuit substrate potential line, MEM1 MEM2: SRAM memory cell, BLK1 to BLK2: SRAM block, CNTV1, CNTV2, power supply voltage control circuit, tox: gate insulating film thickness.

Claims (10)

A first power supply line for supplying a first voltage;
A second power supply line for supplying a second voltage lower than the first voltage;
A plurality of static memory cells arranged in an array, a memory cell array having a first power supply node and a second power supply node;
A plurality of word lines connected to corresponding static memory cells;
A plurality of bit lines connected to corresponding static memory cells;
A peripheral circuit including a plurality of word drivers connected to corresponding word lines and a row decoder connected to the plurality of word drivers;
A first switch connected between the first power line and the word driver;
A second switch connected between the second power supply line and the row decoder;
A power supply control circuit connected between the second power supply line and the second power supply node;
In a standby state in which data of the static memory cell is held and no read and write operations are performed on the static memory cell, the second switch supplies the second voltage to the peripheral circuit, and the second switch The first power supply line supplies the first voltage to the peripheral circuit, the first switch cuts off the supply of the first voltage to the plurality of word drivers, and the second power supply line to the plurality of word drivers. The second voltage is supplied, the plurality of word lines are set to the second voltage, and a third voltage between the first voltage and the second voltage is generated from the power supply control circuit. Semiconductor device. The memory cell includes a first inverter coupled between the first memory power supply node and the second memory power supply node, an input terminal of the first inverter connected to an output terminal, and an output of the first inverter A terminal is connected to an input terminal and is connected between a second inverter coupled between the first memory power supply node and the second memory power supply node, and an output terminal of the first inverter and a corresponding bit line. A first access NMOS transistor having a source-drain path and a second access NMOS transistor having a source-drain path connected to the output terminal of the second inverter;
Gate terminals of the first and second access NMOS transistors are connected to corresponding word lines;
2. The semiconductor device according to claim 1, wherein in the standby state, the plurality of word drivers output the signal of the second voltage to the plurality of word lines. The peripheral circuit includes a plurality of precharge circuits connected to the plurality of bit lines,
3. The semiconductor device according to claim 1, wherein the plurality of precharge circuits supply the second potential to the plurality of bit lines in the standby state. In the standby state,
4. The semiconductor device according to claim 1, wherein control is performed so as to increase an absolute value of a threshold voltage of a MOS transistor constituting the static memory cell. 5.   5. The semiconductor device according to claim 1, wherein the first switch is a PMOS transistor, and the second switch is an NMOS transistor. 6. A first power supply line for supplying a first voltage;
A memory cell array having a second power supply line for supplying a second voltage lower than the first voltage, a first power supply node, and a second power supply node, wherein static memory cells are arranged in an array;
A plurality of word lines connected to the corresponding static memory cells;
A plurality of bit lines connected to the corresponding static memory cells;
A plurality of word drivers connected to the corresponding word line;
A row decoder including a preceding circuit of the plurality of word drivers;
A peripheral circuit including a column decoder for selecting the bit line and a plurality of read amplifiers connected to the corresponding bit lines;
A first switch connected between the first power line and the word driver;
A second switch connected between the second power supply line and the peripheral circuit;
A power supply control circuit connected between the second power supply line and the second power supply node;
In a standby state in which data of the static memory cell is held and no read and write operations are performed on the static memory cell, the second switch supplies the second voltage to the peripheral circuit, and the second switch The first power supply line supplies the first voltage to the peripheral circuit, the first switch cuts off the supply of the first voltage to the plurality of word drivers, and the second power supply line to the plurality of word drivers. The plurality of bit lines are set to the first voltage, the plurality of word lines are set to the second voltage, and the power supply control circuit supplies the first voltage and the second voltage. A third voltage is generated between the semiconductor devices. The memory cell includes a first inverter coupled between the first memory power supply node and the second memory power supply node, an input terminal of the first inverter connected to an output terminal, and an output of the first inverter A terminal is connected to an input terminal and is connected between a second inverter coupled between the first memory power supply node and the second memory power supply node, and an output terminal of the first inverter and a corresponding bit line. A first access NMOS transistor having a source-drain path and a second access NMOS transistor having a source-drain path connected to the output terminal of the second inverter;
Gate terminals of the first and second access NMOS transistors are connected to corresponding word lines;
The semiconductor device according to claim 6, wherein the plurality of word drivers output the signal of the second voltage to the plurality of word lines in the standby state. The peripheral circuit includes a plurality of precharge circuits connected to the plurality of bit lines,
8. The semiconductor device according to claim 6, wherein the plurality of precharge circuits supply the first potential to the plurality of bit lines in the standby state. In the standby state,
9. The semiconductor device according to claim 6, wherein control is performed to increase an absolute value of a threshold voltage of a MOS transistor constituting the static memory cell.   The semiconductor device according to claim 6, wherein the first switch is a PMOS transistor, and the second switch is an NMOS transistor.

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