JP2016149596A - Differential circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential circuit containing fewer elements, in which the offset is suppressed and the reduction in response speed is suppressed.SOLUTION: The differential circuit comprises: a first constant-current circuit 5; a second constant-current circuit 6 with the same constant-current value as the first constant-current circuit; a current mirror including a first transistor 1 having the current inflow end connected to the first constant-current circuit, a current outflow end Vm to which a first input voltage is applied, and a gate which is short-circuited with the current inflow end, and a second transistor 2 having a gate connected to the current inflow end of the first transistor and a current outflow end Vp to which a second input voltage is applied; and a current output end Tout connected to a connection point between the second constant-current circuit and the place where the current flows based on the output current of the current mirror.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a differential circuit.

  Conventionally, a differential circuit that outputs a current corresponding to a difference between two input voltages is known. An example of a conventional differential circuit is shown in FIG.

  The conventional differential circuit DF100 shown in FIG. 7 includes transistors 101 to 108 and a constant current circuit 109. The sources of the transistors 101 and 102 which are p-channel MOSFETs (MOS field effect transistors) forming a differential pair are connected to a power supply voltage application terminal via a constant current source 109. The input voltage Vp is applied to the gate of the transistor 101, and the input voltage Vm is applied to the gate of the transistor 102.

  A first current mirror is composed of the transistor 103 which is an n-channel MOSFET whose drain and gate are short-circuited and the transistor 104 which is an n-channel MOSFET, and the drain of the transistor 101 is connected to the drain of the transistor 103. Each source of the transistors 103 and 104 is connected to the ground terminal.

  A transistor 105, which is an n-channel MOSFET whose drain and gate are short-circuited, and a transistor 106, which is an n-channel MOSFET, form a second current mirror, and the drain of the transistor 105 is connected to the drain of the transistor 102. Each source of the transistors 105 and 106 is connected to the ground terminal.

  A third current mirror is composed of the transistor 107, which is a p-channel MOSFET whose drain and gate are short-circuited, and the transistor 108, which is a p-channel MOSFET. The drain of the transistor 106 is connected to the drain of the transistor 107, and the drain of the transistor 108 is connected. The drain of the transistor 104 is connected. Each source of the transistors 107 and 108 is connected to a power supply voltage application terminal. A connection point between the drain of the transistor 108 and the drain of the transistor 104 is connected to the output terminal Tout.

  A drain current flows through each of the transistors 101 and 102 with distribution according to the input voltages Vp and Vm. Then, with the drain current flowing through the transistor 101 as an input, the output current I101 flows through the first current mirror. In addition, the drain current flowing through the transistor 102 is input, and the output current I102 flows through the second current mirror and the third current mirror.

Japanese Patent Laying-Open No. 2009-156835 (FIG. 5)

  Originally, if the input voltages Vp and Vm are the same voltage, the output currents I101 and I102 are balanced, and no current should be output from the output terminal Tout. As a result, the balance between the output currents I101 and I102 may be lost. That is, a current is output from the output terminal Tout, and an offset can occur.

  Accordingly, it is conceivable to suppress the offset by increasing the gain by suppressing the characteristic variation by increasing the gate width of the transistors Vp and Vm and / or shortening the gate length. However, in this case, there is a problem in that the mirror capacity increases and the response speed becomes slow due to an increase in gain.

  Therefore, for example, as shown in FIG. 8, a configuration including a constant current circuit 110, transistors 111 and 112, and resistors 113 and 114 is provided on the front side of the transistors 101 and 102 shown in FIG. It is conceivable to adopt a multi-stage configuration in which a constant current circuit 115, transistors 116 and 117, and resistors 118 and 119 are provided, and the input voltage Vp is applied to the gate of the transistor 116 and the input voltage Vm is applied to the gate of the transistor 117. As a result, the gain of each transistor can be reduced and the mirror capacitance can be reduced, but the overall gain can be increased. However, there is a problem that the number of elements increases.

  Patent Document 1 discloses a conventional example of an overcurrent protection circuit using a differential circuit and discloses a configuration using a bipolar transistor. As described above, the gate size of a MOSFET or the like is disclosed. In Patent Document 1, there is no suggestion about the problem of suppression of characteristic variation due to the setting of, and the associated response speed.

  In view of the above situation, an object of the present invention is to provide a differential circuit capable of suppressing the number of elements while suppressing an offset and suppressing a decrease in response speed.

In order to achieve the above object, a differential circuit according to one embodiment of the present invention includes:
A first constant current circuit;
A second constant current circuit having the same constant current value as the first constant current circuit;
A first transistor having a current inflow end connected to the first constant current circuit, a current outflow end to which a first input voltage is applied, and a gate short-circuited to the current inflow end; and the current inflow end of the first transistor A current mirror including a second transistor having a gate connected to and a current outflow end to which a second input voltage is applied;
A configuration is provided that includes a location where a current based on the output current of the current mirror flows and a current output terminal connected to a connection point between the second constant current circuit (first configuration).

  According to such a configuration, the first input voltage and the second input voltage can be reduced by increasing the gain of the first transistor and the second transistor by suppressing the characteristic variation by increasing the gate width and / or shortening the gate length. The offset of the current output from the current output terminal when the two input voltages are balanced can be suppressed. Even if the gain is increased and the mirror capacitance is increased, the change in the first input voltage or the second input voltage is immediately converted into the change in the output current of the current mirror. Can be suppressed. Furthermore, the number of elements constituting the differential circuit can be suppressed.

  The first configuration further includes a second current mirror in which the current inflow end and the input end of the second transistor are connected and the second constant current circuit and the output end are connected, and the second current mirror includes the second current mirror. The current output terminal may be connected to a connection point between the output terminal and the second constant current circuit (second configuration).

  In the second configuration, the second current mirror includes a first p-channel MOSFET in which a drain and a gate are short-circuited and a source is connected to a power supply voltage application terminal, and the gate and the gate of the first p-channel MOSFET are connected. It is also possible to include a second p-channel MOSFET whose source is connected to the application terminal for the power supply voltage (third configuration).

  In any one of the first to third configurations, an inverter stage including at least one inverter connected to a rear stage side of the current output terminal may be further provided (fourth configuration).

  In any one of the first to fourth configurations, the first transistor is an n-channel MOSFET in which the first input voltage is applied to the source, and the second transistor is in which the second input voltage is applied to the source. N-channel MOSFETs (fifth configuration).

  In any of the first to fifth configurations, the voltage signal for current detection and the reference voltage may be applied as either the first input voltage or the second input voltage, respectively (sixth Constitution).

  In the sixth configuration, the voltage signal for current detection may be a voltage signal based on a current flowing through a synchronous rectification transistor in a synchronous rectification switching power supply device, and the reference voltage may be a ground potential. (Seventh configuration).

  Moreover, the power supply device which concerns on another aspect of this invention is equipped with the differential circuit made into the said 6th or 7th structure (8th structure).

In addition, a power supply device according to another aspect of the present invention includes an output stage that generates a desired output voltage from an input voltage according to on / off control of an upper-stage output transistor and a lower-stage synchronous rectification transistor;
The voltage signal for current detection includes the differential circuit having the seventh configuration, which is a voltage signal at a connection point between the output transistor and the synchronous rectification transistor (a ninth configuration).

  An electronic apparatus according to another aspect of the present invention includes the power supply device having the eighth or ninth configuration.

  According to the differential circuit of the present invention, it is possible to reduce the number of elements while suppressing an offset and suppressing a decrease in response speed.

1 is a circuit diagram of a differential circuit according to an embodiment of the present invention. It is a figure which shows the modification of the differential circuit which concerns on one Embodiment of this invention. 1 is a block diagram illustrating an overall configuration of a switching power supply device according to an embodiment of the present invention. It is a timing chart which shows the switching operation at the time of heavy load. It is a timing chart which shows the backflow interruption | blocking operation | movement at the time of light load. It is an external view of the smart phone which concerns on one Embodiment of this invention. It is a circuit diagram of the differential circuit which concerns on a prior art example. It is a figure which shows the modification of the differential circuit which concerns on a prior art example.

  An embodiment of the present invention will be described below with reference to the drawings. A circuit diagram of a differential circuit according to an embodiment of the present invention is shown in FIG.

  In FIG. 1, the differential circuit DF <b> 1 includes transistors 1 to 4 and constant current circuits 5 and 6. A transistor 1 which is an n-channel MOSFET whose drain and gate are short-circuited and a transistor 2 which is an n-channel MOSFET constitute a first current mirror. The drain of the transistor 1 is connected to a power supply voltage application terminal via a constant current circuit 5. An input voltage Vm is applied to the source of the transistor 1.

  An input voltage Vp is applied to the source of the transistor 2. A transistor 3 that is a p-channel MOSFET whose drain and gate are short-circuited and a transistor 4 that is a p-channel MOSFET constitute a second current mirror. The drain of the transistor 2 is connected to the drain of the transistor 3. A power supply voltage application terminal is connected to each source of the transistors 3 and 4. The drain of the transistor 4 is connected to the ground terminal via the constant current circuit 6. A connection point between the drain of the transistor 4 and the constant current circuit 6 is connected to the output terminal Tout.

  Ideally, when the input voltages Vm and Vp are the same voltage and balanced, a current having the same value as the constant current by the constant current circuit 5 flowing through the transistor 1 flows through the transistor 2. An output current I2 flows through the second current mirror with the flowing current as an input. Since the constant currents flowing through the constant current circuits 5 and 6 are set to the same value, the output current I2 and the current flowing through the constant current circuit 6 are balanced, and no current is output from the output terminal Tout. When the balance between the input voltages Vp and Vm is lost, a current different from the constant current of the constant current circuit 5 flows through the transistor 2 accordingly, so that the balance between the output current I2 and the current flowing through the constant current circuit 6 is balanced. The current collapses and a current is output from the output terminal Tout.

  However, actually, even if the input voltages Vm and Vp are balanced due to the characteristic variation of the transistors 1 and 2, the balance between the output current I2 and the current flowing through the constant current circuit 6 is lost, and the current flows from the output terminal Tout. It can happen to be output. That is, an offset can occur.

  Therefore, the offset can be suppressed by increasing the gain by increasing the gate width of the transistors 1 and 2 and / or shortening the gate length and suppressing characteristic variation. Even if the gain is increased and the mirror capacitance is increased, the input voltage Vp is applied to the source instead of the gate of the transistor 2 in this embodiment. Is immediately converted into a change in drain current and does not cause a decrease in response speed (the same applies to changes in the input voltage Vm). In addition, the number of elements constituting the differential circuit DF1 can be suppressed.

  Further, like the differential circuit DF1 'shown in FIG. 2, an inverter stage IV11 including at least one inverter may be provided on the rear stage side of the output terminal Tout. According to such a configuration, the differential circuit DF1 'can function as a comparator.

<Application example to power supply>
Next, a power supply apparatus will be described as a suitable application example of the differential circuit according to the present embodiment.
<< Switching power supply >>
FIG. 3 is a block diagram showing the overall configuration of the switching power supply apparatus. The switching power supply device 25 of this configuration example is a step-down DC / DC converter that generates an output voltage Vout from an input voltage Vin by a non-linear control method (bottom detection on-time fixed method). The switching power supply device 25 is formed by the semiconductor device 10 and various discrete components (n-channel MOS field effect transistors N1 and N2, a coil L1, a capacitor C1, and resistors R1 and R2) externally attached to the semiconductor device 10. A switch output stage 20.

  The semiconductor device 10 is a main body (so-called power supply control IC) that comprehensively controls the entire operation of the switching power supply device 25. The semiconductor device 10 has external terminals T1 to T7 (upper gate terminal T1, lower gate terminal T2, switch terminal T3, feedback terminal T4, input voltage terminal T5 as means for establishing electrical connection with the outside of the device. , Output voltage terminal T6 and ground terminal T7).

  The external terminal T1 is connected to the gate of the transistor N1. The external terminal T2 is connected to the gate of the transistor N2. The external terminal T3 is connected to the application terminal of the switch voltage Vsw (a connection node between the source of the transistor N1 and the drain of the transistor N2). The external terminal T4 is connected to an application end (a connection node between the resistor R1 and the resistor R2) of the divided voltage Vdiv. The external terminal T5 is connected to the application terminal for the input voltage Vin. The external terminal T6 is connected to the application terminal for the output voltage Vout. The external terminal T7 is connected to the ground terminal.

  Next, the connection relationship of discrete components attached to the semiconductor device 10 will be described. The drain of the transistor N1 is connected to the application terminal for the input voltage Vin. The source of the transistor N2 is connected to the ground terminal. The source of the transistor N1 and the drain of the transistor N2 are both connected to the first end of the coil L1. The second end of the coil L1 and the first end of the capacitor C1 are both connected to the application terminal for the output voltage Vout. The second end of the capacitor C1 is connected to the ground end. The resistors R1 and R2 are connected in series between the application terminal of the output voltage Vout and the ground terminal.

  The transistor N1 is an output transistor that is on / off controlled according to the gate signal G1 input from the external terminal T1. The transistor N2 is a synchronous rectification transistor that is on / off controlled in accordance with the gate signal G2 input from the external terminal T2. As the rectifying element, a diode may be used instead of the transistor N2. The transistors N1 and N2 can also be built in the semiconductor device 10. The coil L1 and the capacitor C1 function as a rectifying / smoothing unit that rectifies and smoothes the rectangular-wave switch voltage Vsw appearing at the external terminal T3 to generate the output voltage Vout. The resistors R1 and R2 function as a divided voltage generation unit that divides the output voltage Vout to generate a divided voltage Vdiv.

  Next, the internal configuration of the semiconductor device 10 will be described. The semiconductor device 10 includes a ripple injection circuit 11, a reference voltage generation circuit 12, a main comparator 13, a one-shot pulse generation circuit 14, an RS flip-flop 15, an on time setting circuit 16, and a gate driver circuit 17. The backflow detection circuit 18 is integrated.

  The ripple injection circuit 11 adds a ripple voltage Vrpl (a pseudo ripple component simulating a coil current IL flowing through the coil L1) to the divided voltage Vdiv to generate a feedback voltage Vfb (= Vdiv + Vrpl). If such a ripple injection technique is introduced, stable switching control can be performed even if the ripple component of the output voltage Vout (and thus the divided voltage Vdiv) is not so large. A ceramic capacitor or the like can be used. However, when the ripple component of the output voltage Vout is sufficiently large, the ripple injection circuit 11 can be omitted.

  The reference voltage generation circuit 12 generates a predetermined reference voltage Vref.

  The main comparator 13 compares the feedback voltage Vfb input to the inverting input terminal (−) and the reference voltage Vref input to the non-inverting input terminal (+) to generate the comparison signal S1. The comparison signal S1 is at a low level when the feedback voltage Vfb is higher than the reference voltage Vref, and is at a high level when the feedback voltage Vfb is lower than the reference voltage Vref.

  The one-shot pulse generation circuit 14 generates a one-shot pulse for the set signal S2 using the rising edge of the comparison signal S1 as a trigger.

  The RS flip-flop 15 sets the output signal S4 to a high level at the rising edge of the set signal S2 input to the set end (S), and the output signal at the rising edge of the reset signal S3 input to the reset end (R). S4 is reset to low level.

  The on-time setting circuit 16 sets the reset signal S3 to one after a predetermined on-time Ton has elapsed after the inverted output signal S4B of the RS flip-flop 15 (the logic inverted signal of the output signal S4) has fallen to a low level. Generate a shot pulse.

  The gate driver circuit 17 generates gate signals G1 and G2 according to the output signal S4 of the RS flip-flop 15, and switches the transistors N1 and N2 in a complementary manner. Note that the term “complementary” used in this specification includes the case where the transistors N1 and N2 are turned on / off completely, as well as the transistors N1 and N2 from the viewpoint of preventing through current. This includes the case where a delay is given to the on / off transition timing (when a simultaneous off period (dead time) is provided).

  The backflow detection circuit 18 monitors the backflow of the coil current IL (coil current IL flowing from the coil L1 to the ground terminal via the transistor N2) and generates a backflow detection signal S5. The backflow detection signal S5 is latched at a high level (a logic level when a backflow is detected) when a backflow of the coil current IL is detected, and a low level (a logic when no backflow is detected) at the rising edge of the gate signal G1 in the next cycle. Level). As a method for monitoring the backflow of the coil current IL, for example, a zero cross point at which the switch voltage Vsw switches from negative to positive during the ON period of the transistor N2 may be detected. When the backflow detection signal S5 is at a high level, the gate driver circuit 17 generates the gate signal G2 so as to forcibly turn off the transistor N2 without depending on the output signal S4.

  The ripple injection circuit 11, the reference voltage generation circuit 12, the main comparator 13, the one-shot pulse generation circuit 14, the RS flip-flop 15, the on-time setting circuit 16, the gate driver circuit 17, and the backflow detection circuit 18 described above are: A non-linear control method for generating the output voltage Vout from the input voltage Vin by performing on / off control of the transistors N1 and N2 according to the comparison result of the feedback voltage Vfb and the reference voltage Vref (in this configuration example, bottom detection on-time) Functions as a switching control circuit.

<< Switching operation >>
FIG. 4 is a timing chart showing the switching operation at the time of heavy load (in the current continuous mode), in which the feedback voltage Vfb, the set signal S2, the reset signal S3, and the output signal S4 are depicted in order from the top.

  When the feedback voltage Vfb decreases to the reference voltage Vref at time t11, the set signal S2 rises to a high level and the output signal S4 changes to a high level. Accordingly, the transistor N1 is turned on, and the feedback voltage Vfb starts to rise.

  Thereafter, when the reset signal S3 rises to a high level at time t12 as the on time Ton elapses, the output signal S4 transitions to a low level. Therefore, the transistor N1 is turned off, and the feedback voltage Vfb starts to fall again.

  The gate driver circuit 17 generates gate signals G1 and G2 in accordance with the output signal S4, and performs on / off control of the transistors N1 and N2 using this. Specifically, when the output signal S4 is at a high level, basically, the gate signal G1 is set to a high level to turn on the transistor N1, and the gate signal G2 is set to a low level to turn off the transistor N2. Is done. Conversely, when the output signal S4 is at a low level, basically, the gate signal G1 is set to a low level to turn off the transistor N1, and the gate signal G2 is set to a high level to turn on the transistor N2.

  Due to the on / off control of the transistors N1 and N2, the switch voltage Vsw having a rectangular waveform appears at the external terminal T3. The switch voltage Vsw is rectified and smoothed by the coil L1 and the capacitor C1, and the output voltage Vout is generated. The output voltage Vout is divided by the resistors R1 and R2, and the divided voltage Vdiv (and thus the feedback voltage Vfb) is generated. With such output feedback control, the switching power supply device 25 generates a desired output voltage Vout from the input voltage Vin with a very simple configuration.

<< Backflow blocking action >>
FIG. 5 is a timing chart showing the reverse current cut-off operation at the time of light load (in the current discontinuous mode). The gate signals G1 and G2, the reverse current detection signal S5, the coil current IL, and the switch voltage Vsw are sequentially shown from the top. It is depicted.

  At times t21 to t22, since the gate signal G1 is at a high level and the gate signal G2 is at a low level, the transistor N1 is turned on and the transistor N2 is turned off. Accordingly, at times t21 to t22, the switch voltage Vsw rises to substantially the input voltage Vin, and the coil current IL increases.

  At time t22, when the gate signal G1 falls to the low level and the gate signal G2 rises to the high level, the transistor N1 is turned off and the transistor N2 is turned on. Therefore, the switch voltage Vsw decreases to a negative voltage (= GND−IL × RN2, where RN2 is the on-resistance value of the transistor N2), and the coil current IL starts to decrease.

  Here, when the output current Iout flowing through the load is sufficiently heavy, the energy stored in the coil L1 is large, so that the coil current IL has a zero value until time t24 when the gate signal G1 is raised to the high level again. The switch voltage Vsw is maintained at a negative voltage while continuing to flow toward the load without falling below. On the other hand, at the time of light load when the output current Iout flowing through the load is small, the energy stored in the coil L1 is small. Therefore, at time t23, the coil current IL falls below the zero value, and a reverse flow of the coil current IL occurs. The polarity of the voltage Vsw switches from negative to positive. In such a state, since the electric charge stored in the capacitor C1 is discarded to the ground terminal, the efficiency at the time of light load is lowered.

  Therefore, the switching power supply device 25 uses the backflow detection circuit 18 to detect backflow of the coil current IL (polarity inversion of the switch voltage Vsw), and during the high level period (time t23 to t24) of the backflow detection signal S5, the transistor N2 Is forcibly turned off. By adopting such a configuration, the reverse flow of the coil current IL can be promptly interrupted, so that it is possible to eliminate a decrease in efficiency at a light load.

  The differential circuit according to the present embodiment can be applied to the backflow detection circuit 18. For example, the ground terminal may be connected to the application terminal of the input voltage Vm in the differential circuit DF1 '(FIG. 2) as a comparator, and the switch voltage Vsw may be applied to the application terminal of the input voltage Vp. For example, in an embodiment in which a normal current detection resistor is connected to the application terminal of the input voltage Vp, a current flowing through the transistor 2 is added as a bias current to a current flowing through the resistor. In the case of the circuit 18, even if a current flows through the transistor 2, the current flowing through the transistor N2 is not affected.

<Example of electronic device>
The power supply device having the differential circuit according to the present embodiment can be applied to various electronic devices. FIG. 6 shows an external view of a smartphone as an example of an electronic device.

  The external appearance of the smartphone X shown in FIG. 6 is an imaging unit X1 mounted on the front and back of the main body, an operation unit X2 (such as various buttons) that accepts user operations, and a display unit X3 that displays characters and video. Have The display unit X3 has a touch panel function for accepting a user's touch operation.

  By mounting the power supply device having the above-described differential circuit on various electronic devices such as a smartphone, it is possible to enjoy the advantages.

  Various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The differential circuit disclosed in the present specification can be used for, for example, a power supply device mounted on various electronic devices.

DF1, DF1 'differential circuit 1, 2 transistor (n-channel MOSFET)
3, 4 transistors (p-channel MOSFET)
5, 6 Constant current circuit IV11 Inverter stage Tout Output terminal 25 Switching power supply device 10 Semiconductor device (power supply control IC)
DESCRIPTION OF SYMBOLS 11 Ripple injection circuit 12 Reference voltage generation circuit 13 Main comparator 14 One shot pulse generation circuit 15 RS flip-flop 16 ON time setting circuit 17 Gate driver circuit 18 Backflow detection circuit 20 Switch output stage N1 Output transistor (n channel MOSFET)
N2 synchronous rectification transistor (n-channel MOSFET)
L1 Coil R1, R2 Resistor C1 Capacitor T1-T7 External terminal

Claims (10)

A first constant current circuit;
A second constant current circuit having the same constant current value as the first constant current circuit;
A first transistor having a current inflow end connected to the first constant current circuit, a current outflow end to which a first input voltage is applied, and a gate short-circuited to the current inflow end; and the current inflow end of the first transistor A current mirror including a second transistor having a gate connected to and a current outflow end to which a second input voltage is applied;
A differential circuit comprising: a current output terminal connected to a connection point between a portion where a current based on an output current of the current mirror flows and a second constant current circuit.   A second current mirror connected between the current inflow end and the input end of the second transistor and connected to the second constant current circuit and the output end; and the output end of the second current mirror and the second constant current circuit; The differential circuit according to claim 1, wherein the current output terminal is connected to a connection point of the differential circuit.   The second current mirror includes a first p-channel MOSFET in which a drain and a gate are short-circuited and a source connected to a power supply voltage application terminal, and the gate and gate of the first p-channel MOSFET are connected and a source applied to the power supply voltage. The differential circuit according to claim 2, further comprising a second p-channel MOSFET connected to the end.   4. The differential circuit according to claim 1, further comprising an inverter stage including at least one inverter connected to a rear stage side of the current output terminal. 5.   The first transistor is an n-channel MOSFET in which a first input voltage is applied to a source, and the second transistor is an n-channel MOSFET in which a second input voltage is applied to a source. The differential circuit according to claim 4.   6. The differential circuit according to claim 1, wherein the voltage signal for detecting current and the reference voltage are applied as either the first input voltage or the second input voltage, respectively. .   The differential signal according to claim 6, wherein the voltage signal for current detection is a voltage signal based on a current flowing through a synchronous rectification transistor in a synchronous rectification switching power supply device, and the reference voltage is a ground potential. circuit.   A power supply device comprising the differential circuit according to claim 6. An output stage that generates a desired output voltage from the input voltage in accordance with on / off control of the upper-stage output transistor and the lower-stage synchronous rectification transistor;
The power supply apparatus comprising: the differential circuit according to claim 7, wherein the voltage signal for current detection is a voltage signal at a connection point between the output transistor and the synchronous rectification transistor.   An electronic device comprising the power supply device according to claim 8 or 9.

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