JP2016019425A - Power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power converter capable of reducing high frequency component included in a voltage output from an inverter 13.SOLUTION: In a period from a point when a first upper arm switch SXp and a second lower arm switch SYn are operated to turn ON to a point when a first lower arm switch SXn and a second upper arm switch SYp are operated to turn ON next time, a first operation processing is made to turn ON a first sub switch Ss1 and a second sub switch Ss2. In a period from a point when the first lower arm switch SXn and the second upper arm switch SYp are operated to turn ON to a point when the first upper arm switch SXp and the second lower arm switch SYn are operated to turn ON next time, a second operation processing is made to turn ON the sub switches Ss1 and Ss2. ON operation switching timing of the sub switches Ss1 and Ss2 is variably set in the first and second operation processing based on the current which flows on respective diodes DXp, DXn, DYp and DYn in a forward direction.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power conversion device.

  2. Description of the Related Art Conventionally, as can be seen, for example, in Patent Document 1 below, a non-contact power supply system that supplies power to an electric vehicle in a non-contact manner from a power supply facility is known. In the non-contact power supply system, the power supply facility side includes an inverter that outputs a rectangular wave voltage while alternately inverting the polarity, and a power transmission side coil to which the output voltage of the inverter is applied. In a non-contact power supply system, on the electric vehicle side, a power receiving side coil that receives power supplied in a non-contact manner from a power transmitting side coil, and an AC voltage output from the power receiving side coil is converted into a DC voltage and supplied to a battery or the like. And a rectifier circuit for

  The inverter is connected in reverse parallel to each of the first upper arm switch and the first lower arm switch connected in series with each other, the second upper arm switch and the second lower arm switch connected in series with each other, and the respective switches. And a diode. The positive potential side of the DC power supply is connected to the high potential side terminals of the first and second upper arm switches. The negative potential side of the DC power supply is connected to the low potential side terminals of the first and second lower arm switches. In addition, an electrical path connecting the first upper arm switch and the first lower arm switch in series is connected to the first end of the power transmission side coil, and the second upper arm switch and the second end of the power transmission side coil are connected to the first end of the power transmission side coil. An electrical path that connects the second lower arm switch in series is connected.

JP 2012-70463 A

  Here, in order to output a rectangular wave voltage while reversing the polarity alternately, the set of the first upper arm switch and the second lower arm switch and the set of the first lower arm switch and the second upper arm switch are: It is turned on alternately. In this case, the slope of the output voltage of the inverter at the time of polarity inversion becomes steep, and the inverter output voltage may contain a high frequency component. If a high-frequency component is included, there is a concern that it may adversely affect EMC (electromagnetic compatibility). Such a problem may occur not only in the non-contact power supply system.

  The main object of the present invention is to provide a power converter that can reduce high-frequency components contained in the voltage output to the coil side.

  Hereinafter, means for solving the above-described problems and the operation and effects thereof will be described.

  The present invention includes a series connection body of a first upper arm switch (SXp) and a first lower arm switch (SXn) connected in parallel to a DC power source (12), and a second upper arm switch connected in parallel to the DC power source. (SYp) and a second lower arm switch (SYn) connected in series to the first upper arm switch, the first lower arm switch, the second upper arm switch, and the second lower arm switch A diode (DXp, DXn, DYp, DYn) connected in parallel and each of the first upper arm switch, the first lower arm switch, the second upper arm switch, and the second lower arm switch are connected in parallel. The first end is connected to the first electric path connecting the capacitors (18a to 18d), the first upper arm switch, and the first lower arm switch in series. And a main coil (15a) having a second end connected to a second electrical path that connects the second upper arm switch and the second lower arm switch in series, and the first electrical path and the second electrical path. A sub reactor (13b; 13c; 13d, 13e) connected to each of the paths, and connected to the sub reactor and turned on, thereby causing a forward current flowing through the diode to flow through the sub reactor and the forward direction. A sub-switch (Ss1, Ss2; Ssα, Ssβ; Ssa to Ssd) provided to reduce a directional current, a set of the first upper arm switch and the second lower arm switch, and the first lower arm Main operating means for alternately turning on a switch and a set of the second upper arm switch, the first upper arm switch and the second lower arm The first switch that turns on the sub switch in the period from the middle of the period when the set of switches is turned on until the middle of the period when the pair of the first lower arm switch and the second upper arm switch is turned on next time. The set of the first upper arm switch and the second lower arm switch is turned on next time in the middle of the operation process and the period during which the set of the first lower arm switch and the second upper arm switch is turned on. Sub-operation means for performing a second operation process for turning on the sub switch in a period until the middle of the period, and the diode in a period in which a set of the first upper arm switch and the second lower arm switch is turned on First setting means for variably setting a first on-operation switching timing of the sub-switch by the first operation processing based on a forward current flowing through Based on a forward current flowing through the diode during a period in which the set of the first lower arm switch and the second upper arm switch is turned on, the second on operation switching timing of the sub switch by the second operation processing is variable. And a second setting means for setting.

  In the above invention, the first upper arm switch and the second lower arm switch are turned on and the first lower arm switch and the second upper arm switch are turned off (hereinafter referred to as the first state). ), A phenomenon may occur in which the phase of the current flowing in the main coil advances from the initially assumed phase (for example, at the time of design) with respect to the rectangular wave voltage applied to the main coil. Specifically, for example, in the first state, a diode (hereinafter referred to as a second lower arm diode), a main coil, and a first upper arm switch connected in reverse parallel to the second lower arm switch from the negative side of the DC power supply A current flows to the positive electrode side of the DC power source through a diode (hereinafter referred to as a first upper arm diode) connected in antiparallel to the DC power source. Here, when a forward current flows through the first upper arm diode and the second lower arm diode, if the sub switch is turned on, the current flowing through the sub reactor increases, and the first upper arm diode and the second lower arm diode increase. The forward current flowing through the arm diode is reduced. When the current flowing through the first upper arm diode and the second lower arm diode decreases to zero, the current flows through the first upper arm switch and the second lower arm switch. After that, the set of the first upper arm switch and the second lower arm switch is switched to the off operation, whereby a capacitor (hereinafter referred to as a first upper arm capacitor) connected in parallel to the first upper arm switch and the second lower arm A charging current flows from the positive electrode side of the DC power supply to a capacitor (hereinafter referred to as a second lower arm capacitor) connected in parallel to the switch.

  Here, the potential at the connection point of the first upper and lower arm switches with respect to the negative side potential of the DC power supply is defined as the first intermediate voltage, and the potential at the connection point of the second upper and lower arm switches with respect to the negative side potential of the DC power supply. Is defined as the second intermediate voltage. The higher the charging current of the first upper arm capacitor and the second lower arm capacitor, the higher the change rate of the first and second intermediate voltages immediately after the first upper arm switch and the second lower arm switch are switched to the OFF operation. Become. By adjusting the charging current to the optimum value based on the relationship between the changing speed and the charging current, the changing speed of the first and second intermediate voltages is set at an allowable level for the high-frequency component contained in the rectangular wave voltage applied to the main coil. Can be as fast as possible. Here, the charging current becomes larger as the ON operation time of the sub switch is longer during the ON operation period of the first upper arm switch and the second lower arm switch. The sub switch ON operation switching timing increases as the forward current of the first upper arm diode and the second lower arm diode during the ON operation period of the first upper arm switch and the second lower arm switch increases. It is necessary to advance the timing for switching off the arm switch and the second lower arm switch. Therefore, in the above invention, the ON setting switching timing of the sub switch in the first state is variably set by the first setting means.

  On the other hand, for example, a state in which the set of the first lower arm switch and the second upper arm switch is turned on and the set of the first upper arm switch and the second lower arm switch is turned off (hereinafter referred to as the second state). ) May also cause a phenomenon in which the phase of the current advances. Specifically, in the second state, from the negative side of the DC power source, the diode is connected in reverse parallel to the first lower arm switch (hereinafter referred to as the first lower arm diode), the main coil, and the second upper arm switch. A current flows to the positive electrode side of the DC power supply via a diode (hereinafter referred to as a second upper arm diode) connected in parallel. Here, when a forward current flows through the first lower arm diode and the second upper arm diode, when the sub switch is turned on, the current flowing through the sub reactor increases, and the first lower arm diode and the second upper arm diode increase. The forward current flowing through the arm diode is reduced. When the current flowing through the first lower arm diode and the second upper arm diode decreases to zero, the current flows through the first lower arm switch and the second upper arm switch. After that, the set of the first lower arm switch and the second upper arm switch is switched to an off operation, whereby a capacitor (hereinafter referred to as a first lower arm capacitor) connected in parallel to the first lower arm switch and the second upper arm A charging current flows from a positive electrode side of a DC power supply to a capacitor (hereinafter referred to as a second upper arm capacitor) connected in parallel to the switch.

  Here, the larger the charging current of the first lower arm capacitor and the second upper arm capacitor, the change in the first and second intermediate voltages immediately after the first lower arm switch and the second upper arm switch are switched to the OFF operation. Increases speed. For this reason, by adjusting the charging current to an optimum value, the changing speed of the first and second intermediate voltages is set to a speed at which the high-frequency component included in the rectangular wave voltage applied to the main coil can be set to an allowable level. Can do. Here, the charging current becomes larger as the ON operation time of the sub switch is longer during the ON operation period of the first lower arm switch and the second upper arm switch. The sub-switch ON operation switching timing is such that the larger the forward current of the first lower arm diode and the second upper arm diode during the ON operation period of the first lower arm switch and the second upper arm switch, the higher the first lower arm switch. It is necessary to advance the timing for switching off the arm switch and the second upper arm switch. Therefore, in the above invention, the ON operation switching timing of the sub switch in the second state is variably set by the second setting means.

  Thus, according to the said invention, the ON operation switching timing of a sub switch can be adjusted appropriately, and the change speed of a 1st, 2nd intermediate voltage can be made into an appropriate speed. Thereby, the high frequency component contained in the voltage output to the main coil side can be reduced suitably.

The lineblock diagram of the non-contact electric supply system concerning a 1st embodiment. The time chart which shows transition of the resonant current which flows into a power transmission side coil. The figure (MODE1) which shows the electric current distribution aspect in the inverter concerning a comparison technique. The figure (MODE2) which shows the electric current distribution aspect in the inverter concerning a comparison technique. The figure (MODE3) which shows the electric current distribution aspect in the inverter concerning a comparison technique. The time chart which shows the generation | occurrence | production aspect of the recovery current concerning a comparison technique. The figure (MODE4) which shows the electric current distribution aspect in the inverter concerning a comparison technique. The figure (MODE5) which shows the electric current distribution aspect in the inverter concerning a comparison technique. The figure (MODE6) which shows the electric current distribution aspect in the inverter concerning a comparison technique. The time chart which shows the effect of a sub switch and a sub reactor. The figure which shows the electric current distribution aspect in an inverter. The figure which shows the electric current distribution aspect in an inverter. The time chart which shows the ON switch switching timing of a sub switch. The time chart which shows the various waveforms at the time of the phase change of a resonance current. The time chart which shows the various waveforms at the time of the amplitude change of a resonance current. The flowchart which shows the procedure of an inverter operation process. The flowchart which shows the procedure of an inverter operation process. The block diagram of the non-contact electric power feeding system concerning 2nd Embodiment. The block diagram of the inverter concerning 3rd Embodiment. The block diagram of the inverter concerning 4th Embodiment. The block diagram of the non-contact electric power feeding system concerning other embodiment.

(First embodiment)
Hereinafter, a first embodiment in which a power conversion device according to the present invention is applied to a non-contact power feeding system will be described with reference to the drawings.

  As shown in FIG. 1, the non-contact power supply system includes a power transmission system PS provided outside (a ground side) of a vehicle that is a moving body, and a power reception system PR provided in the vehicle.

  The power transmission system PS includes a PFC circuit 11 to which an AC voltage output from an AC power supply 10 (system power supply) is input, a DCDC converter 12, an inverter 13, a power transmission side filter circuit 14, and a power transmission pad 15. The PFC circuit 11 improves the power factor of the input voltage and the input current while rectifying the input AC voltage into a DC voltage. The PFC circuit 11 includes, for example, a full-wave rectifier circuit composed of a diode bridge and a non-insulated boost chopper circuit. The DCDC converter 12 converts the DC voltage output from the PFC circuit 11 into a predetermined DC voltage and outputs it. The DCDC converter 12 is, for example, a non-insulated step-down chopper circuit.

  The inverter 13 is a voltage control type inverter. Specifically, the inverter 13 smoothes the input voltage and the series connection body of the first upper arm switch SXp and the first lower arm switch SXn and the series connection body of the second upper arm switch SYp and the second lower arm switch SYn. It is a full bridge inverter provided with the capacitor | condenser 13a to perform. A first upper arm diode DXp is connected in antiparallel to the first upper arm switch SXp, and a first lower arm diode DXn is connected in antiparallel to the first lower arm switch SXn. A second upper arm diode DYp is connected in antiparallel to the second upper arm switch SYp, and a second lower arm diode DYn is connected in antiparallel to the second lower arm switch SYn. In the present embodiment, a voltage control type semiconductor switch is used as each switch SXp, SXn, SYp, SYn, and specifically, an IGBT is used.

  The output terminal on the positive side of the DCDC converter 12 is connected to the collector of the first upper arm switch SXp via the first terminal T 1 of the inverter 13. The collector of the first lower arm switch SXn is connected to the emitter of the first upper arm switch SXp. The output terminal on the negative side of the DCDC converter 12 is connected to the emitter of the first lower arm switch SXn via the second terminal T2 of the inverter 13. The collector of the second upper arm switch SYp is connected to the first terminal T1 of the inverter 13, and the emitter of the second upper arm switch SYp is connected to the collector of the second lower arm switch SYn. The second terminal T2 of the inverter 13 is connected to the emitter of the second lower arm switch SYn.

  The inverter 13 further includes a first sub-switch Ss1, a first sub-diode Ds1, a second sub-switch Ss2, a second sub-diode Ds2, a first protection diode Dp1, a second protection diode Dp2, and a sub-reactor 13b. ing. In this embodiment, voltage control type semiconductor switches are used as the sub switches Ss1 and Ss2, and specifically, IGBTs are used.

  A first sub-diode Ds1 is connected in antiparallel to the first subswitch Ss1, and a second subdiode Ds2 is connected in antiparallel to the second subswitch Ss2. The emitter of the first sub switch Ss1 is connected to the connection point between the first upper arm switch SXp and the first lower arm switch SXn, and the first end of the subreactor 13b is connected to the collector of the first sub switch Ss1. Has been. The collector of the second sub switch Ss2 is connected to the second end of the sub reactor 13b, and the connection point of the second upper arm switch SYp and the second lower arm switch SYn is connected to the emitter of the second sub switch Ss2. Has been. When the first sub switch Ss1 and the second sub switch Ss2 are turned off, current flows in a direction from the emitter side of the first sub switch Ss1 to the emitter side of the second sub switch Ss2, 2 has a function of blocking both current flow in a direction from the emitter side of the sub switch Ss2 to the emitter side of the first sub switch Ss1.

  The connection point between the first sub-switch Ss1 and the sub-reactor 13b is connected to the anode of the first protection diode Dp1, and the cathode of the first protection diode Dp1 is connected to the first terminal T1. The connection point between the second sub-switch Ss2 and the sub-reactor 13b is connected to the anode of the second protection diode Dp2, and the cathode of the second protection diode Dp2 is connected to the first terminal T1. A first terminal of the capacitor 13a is connected to the first terminal T1, and a second terminal T2 is connected to the second terminal of the capacitor 13a.

  A first end of the power transmission pad 15 is connected to a connection point between the first upper arm switch SXp and the first lower arm switch SXn via the power transmission side filter circuit 14, and a power transmission is connected to the second end of the power transmission pad 15. A connection point between the second upper arm switch SYp and the second lower arm switch SYn is connected via the side filter circuit 14. In the present embodiment, a band pass filter is used as the power transmission side filter circuit 14. The power transmission side filter circuit 14 connects a series connection body of the power transmission side first and second reactors 14a and 14b, a series connection body of the power transmission side third and fourth reactors 14d and 14e, and a connection point of each series connection body. Power transmission side capacitor 14c.

  The power transmission pad 15 includes a power transmission side coil 15a, a first resonance capacitor 15b, and a second resonance capacitor 15c. The 1st end of the power transmission pad 15 is connected to the 1st end of the power transmission side coil 15a via the 1st resonant capacitor 15b. The second end of the power transmission pad 15 is connected to the second end of the power transmission side coil 15a via a second resonance capacitor 15c. The power transmission pad 15 constitutes an LC series resonance circuit. The power transmission pad 15 is a circuit for sending electric power to the power reception pad 20 included in the power reception system PR by electromagnetic induction. In the present embodiment, the power transmission side coil 15a corresponds to a “main coil”, and the resonance capacitors 15b and 15c correspond to “power transmission side resonance capacitors”.

  On the other hand, the power receiving system PR includes a power receiving pad 20, a power receiving filter circuit 21, and a rectifier circuit 22. The power receiving pad 20 includes a power receiving side coil 20a, a third resonance capacitor 20b, and a fourth resonance capacitor 20c. The first end of the power receiving pad 20 is connected to the first end of the power receiving side coil 20a via the third resonance capacitor 20b. The second end of the power receiving pad 20 is connected to the second end of the power receiving side coil 20a via a fourth resonance capacitor 20c. The power receiving pad 20 constitutes an LC series resonance circuit. In the present embodiment, each of the resonance capacitors 20b and 20c corresponds to a “power reception side resonance capacitor”.

  A rectifier circuit 22 is connected to the power receiving pad 20 via a power receiving side filter circuit 21. In the present embodiment, a band pass filter is used as the power receiving side filter circuit 21. The power receiving side filter circuit 21 connects a series connection body of the power receiving side first and second reactors 21a and 21b, a series connection body of the power receiving side third and fourth reactors 21d and 21e, and a connection point of each series connection body. Power receiving side capacitor 21c. The rectifier circuit 22 converts the AC voltage output from the power receiving pad 20 into a DC voltage and outputs the DC voltage. As the rectifier circuit 22, for example, a full-wave rectifier circuit configured by a diode bridge or a synchronous rectifier circuit configured by four switching elements (for example, MOSFETs) can be used. The DC voltage output from the rectifier circuit 22 is supplied to the on-vehicle electric load 23 including the on-vehicle battery. In the present embodiment, the battery serves as a power supply source for a rotating machine (motor generator) (not shown) as the in-vehicle main machine.

  The inverter 13 includes first to fourth current sensors 17a to 17d. The first current sensor 17a is provided at a position where the collector current of the first upper arm switch SXp and the forward current of the first upper arm diode DXp can be detected. The second current sensor 17b is provided at a position where the collector current of the first lower arm switch SXn and the forward current of the first lower arm diode DXn can be detected. The third current sensor 17c is provided at a position where the collector current of the second upper arm switch SYp and the forward current of the second upper arm diode DYp can be detected. The fourth current sensor 17d is provided at a position where the collector current of the second lower arm switch SYn and the forward current of the second lower arm diode DYn can be detected.

  The DCDC converter 12 includes an output voltage sensor (not shown) that detects the output voltage. In the present embodiment, the output voltage detected by the output voltage sensor is used as the input voltage VDC of the inverter 13 (potential difference between the first and second terminals T1 and T2). For example, the inverter 13 may be provided with an input voltage sensor that detects the input voltage.

  In the present embodiment, the power transmission system PS further includes a power transmission side control device 16. The power transmission side control device 16 exchanges power between the power transmission side coil 15a and the power reception side coil 20a in a contactless manner. In particular, in the present embodiment, the charging process for charging the vehicle is performed by supplying power from the power transmission side coil 15a to the power reception side coil 20a. The power transmission side control device 16 takes in the detection values of the first to fourth current sensors 17 a to 17 d and the input voltage VDC of the inverter 13 output from the DCDC converter 12. The power transmission side control device 16 operates the PFC circuit 11, the DCDC converter 12, and the inverter 13 by using these detection values or exchanging information with a power reception side control device (not shown) provided in the power reception system PR. .

  The power transmission side control device 16 alternately turns on the set of the first upper arm switch SXp and the second lower arm switch SYn and the set of the first lower arm switch SXn and the second upper arm switch SYp with a dead time interposed therebetween. Manipulate. As a result, a rectangular wave voltage whose polarity is alternately reversed is supplied to the power transmission pad 15. The power transmission side control device 16 operates the DCDC converter 12 so as to control the output voltage of the DCDC converter 12 to the target voltage. The target voltage is variably set to a value capable of realizing highly efficient non-contact power feeding by performing impedance matching between the power transmission side and the power receiving side. Specifically, for example, the target voltage is variably set based on the received power of the power receiving pad 20. Incidentally, in the present embodiment, the power transmission side control device 16 corresponds to “main operation means” and “sub operation means”.

  Here, in the present embodiment, the first snubber capacitor 18a is connected in parallel to the first upper arm switch SXp, and the second snubber capacitor 18b is connected in parallel to the first lower arm switch SXn. A third snubber capacitor 18c is connected in parallel to the second upper arm switch SYp, and a fourth snubber capacitor 18d is connected in parallel to the second lower arm switch SYn. The reason why each of the snubber capacitors 18a to 18d can be installed is that the inverter 13 includes the sub-reactor 13b and the sub-switches Ss1 and Ss2, which are characteristic configurations according to the present embodiment.

  In the present embodiment, the operation method of each of the sub switches Ss1, Ss2 is also characterized. Hereinafter, after describing the sub reactor 13b and the sub switches Ss1 and Ss2, the operation method of the sub switches Ss1 and Ss2 will be described.

<1. Sub reactor 13b and sub switches Ss1, Ss2>
FIG. 2A shows the transition of the resonance current (hereinafter referred to as the primary current Ip) flowing through the power transmission side coil 15a and the applied voltage (hereinafter referred to as the primary side voltage Vp) of the power transmission side coil 15a. b) shows the transition of the operating state of the first upper arm switch SXp and the second lower arm switch SYn, and FIG. 2C shows the transition of the operating state of the first lower arm switch SXn and the second upper arm switch SYp. Indicates. In FIG. 2A, the primary flowing in the direction from the connection point of the first upper arm switch SXp and the first lower arm switch SXn to the connection point of the second upper arm switch SYp and the second lower arm switch SYn. The side current Ip is defined as positive. In FIG. 2A, the first upper arm switch SXp and the first lower arm with respect to the potential on the connection point side of the second upper arm switch SYp and the second lower arm switch SYn among both ends of the power transmission side coil 15a. The primary side voltage Vp when the potential on the connection point side of the arm switch SXn is high is defined as positive. Further, in FIG. 2, illustration of dead time is omitted.

  As shown in the figure, in the present embodiment, the switching period Tsw of each switch SXp, SXn, SYp, SYn and the period of the fundamental current of the primary side current Ip are set to be the same. In such a setting, ideally, the primary side current Ip becomes a positive value when the primary side voltage Vp is positive, and becomes a negative value when the primary side voltage Vp is negative. In this case, the power factor on the power transmission side of the non-contact power feeding system is set to a high level. However, in the non-contact power supply system, the resonance frequency of the resonance circuit of the power transmission pad 15 changes. As this factor, for example, a change in the coupling coefficient between the coils 15a and 20a due to a change in the relative positional relationship between the power transmission pad 15 and the power reception pad 20, a change in transmission / reception power between the power transmission pad 15 and the power reception pad 20, Examples include variations in initial characteristics of components such as a reactor and a capacitor that determine the resonance characteristics of the resonance circuit, and drifts in the resonance characteristics due to temperature changes.

  Due to a change in the resonance frequency of the resonance circuit, a phenomenon that the phase of the primary current Ip advances with respect to the primary voltage Vp may occur. Specifically, in this phenomenon, the period in which the primary side voltage Vp is positive becomes negative in the period after the period in which the primary side voltage Vp is positive is divided into two, and the period in which the primary side voltage Vp is negative is divided into two. This is a phenomenon in which the primary side current Ip becomes positive in a later period.

  Due to the above factors, a phenomenon in which the phase of the primary current Ip is delayed with respect to the primary voltage Vp may occur. More specifically, this phenomenon is achieved by dividing the period in which the primary side current Ip becomes negative and the period in which the primary side voltage Vp becomes negative in the period before the period in which the primary side voltage Vp is positive in 2 minutes. This is a phenomenon in which the primary current Ip becomes positive in the period before the case.

  Here, when a phenomenon occurs in which the phase of the primary current Ip advances, a recovery loss occurs due to the recovery current flowing through the diodes DXp, DXn, DYp, and DYn in the comparative technique. Here, the comparative technique is a configuration in which the sub reactor 13b, the sub switches Ss1, Ss2, the protection diodes Dp1, Dp2, and the snubber capacitors 18a to 18d are removed from the configuration shown in FIG. It is. Hereinafter, occurrence of recovery loss will be described with reference to FIGS. 3 to 5 and 7 to 9, the power transmission side filter circuit 14 and the like are not shown.

  In MODE 1 from time t1 to t2, as shown in FIG. 3, the set of the first upper arm switch SXp and the second lower arm switch SYn is turned on, and the first lower arm switch SXn and the second upper arm switch SYp are turned on. The pair is turned off. In MODE1, a current flows from the first terminal T1 side to the second terminal T2 side via the first upper arm switch SXp, the power transmission side coil 15a, and the second lower arm switch SYn.

  Thereafter, in MODE 2 at times t2 to t31, as shown in FIG. 4, due to the phase advance of the primary side current Ip, the current flows from the second terminal T2 side to the second lower arm diode DYn, the power transmission side coil 15a, And it flows to the first terminal T1 side through the first upper arm diode DXp. Here, at time t3 in the middle of MODE2, the set of the first upper arm switch SXp and the second lower arm switch SYn is switched to the OFF operation, and the set of the first lower arm switch SXn and the second upper arm switch SYp is turned on. Switch to operation. After that, the current flow path shown in FIG. 4 also occurs during the dead time period (time t3 to t31) in which all the switches SXp, SXn, SYp, SYn are turned off. Therefore, in the present embodiment, this dead time period is also included in MODE2.

  Thereafter, in MODE 3 immediately after time t31, as shown in FIG. 5, the anode potential of the first upper arm diode DXp becomes the potential (0) of the second terminal T2, and the cathode potential becomes the potential VDC of the first terminal T1. It becomes. For this reason, a reverse voltage is applied to the first upper arm diode DXp, and a recovery current flows through the first upper arm diode DXp. That is, a current flows from the first terminal T1 side to the second terminal T2 side through the first upper arm diode DXp and the first lower arm switch SXn. A reverse voltage is also applied to the second lower arm diode DYn, and a recovery current flows through the second lower arm diode DYn. That is, a current flows from the first terminal T1 side to the second terminal T2 side via the second upper arm switch SYp and the second lower arm diode DYn. A recovery loss occurs due to the flow of the recovery current.

  Here, the distribution mode of the recovery current will be described in more detail with reference to FIG. 6A shows the transition of the current Idxp flowing through the first upper arm diode DXp, FIG. 6B shows the transition of the current Isxn flowing through the first lower arm switch SXn, and FIG. The transition of the potential at the connection point of the first upper and lower arm switches SXp and SXn (hereinafter referred to as the first intermediate voltage Vx) with respect to the emitter potential of the first lower arm switch SXn is shown. FIG. 6D shows the transition of the operation state of the first upper arm switch SXp, and FIG. 6E shows the transition of the operation state of the first lower arm switch SXn. In FIG. 6, the forward current Idxp flowing through the first upper arm diode DXp is defined as negative, and the connection point of the first upper and lower arm switches SXp, SXn with respect to the emitter potential of the first lower arm switch SXn. The first intermediate voltage Vx when the potential is high is defined as positive.

  As shown in the figure, the forward current flows through the first upper arm diode DXp due to the phase advance of the primary current Ip. Under such circumstances, at time t3, the first upper arm switch SXp is switched to the off operation, and at time t31 when the dead time has elapsed from time t3, the first lower arm switch SXn is switched to the on operation. As a result, the forward current Idxp of the first upper arm diode DXp gradually decreases, and the collector current Isxn flowing through the first lower arm switch SXn gradually increases. Thereafter, a recovery current starts to flow through the first upper arm diode DXp at time t32. At time t33, when the recovery current reaches a peak, the collector current Isxn flowing through the first lower arm switch SXn also peaks. As a result, recovery loss increases. At time t34, the first intermediate voltage Vx is set to 0 by stopping the flow of the recovery current.

  In MODE 4 from time t34 to t4, as shown in FIG. 7, the set of the first upper arm switch SXp and the second lower arm switch SYn is turned off, and the first lower arm switch SXn and the second upper arm switch SYp are turned on. The pair is turned on. In MODE4, a current flows from the first terminal T1 side to the second terminal T2 side via the second upper arm switch SYp, the power transmission side coil 15a, and the first lower arm switch SXn.

  Thereafter, in MODE 5 from time t4 to time t51, as shown in FIG. 8, due to the phase advance of the primary side current Ip, the current flows from the second terminal T2 side to the first lower arm diode DXn, the power transmission side coil 15a, And it flows to the first terminal T1 side through the second upper arm diode DYp. Here, at time t5 in the middle of MODE 5, the set of the first upper arm switch SXp and the second lower arm switch SYn is switched to the on operation, and the set of the first lower arm switch SXn and the second upper arm switch SYp is turned off. Switch to operation. After that, the current flow path shown in FIG. 8 also occurs during the dead time period (time t5 to t51) in which all the switches SXp, SXn, SYp, SYn are turned off. For this reason, in this embodiment, this dead time period is also included in MODE5.

  Thereafter, in MODE 6 immediately after time t51, as shown in FIG. 9, a reverse voltage is applied to the second upper arm diode DYp and the first lower arm diode DXn, and the second upper arm diode DYp and the first lower arm diode DXn are applied. Recovery current will flow through. For this reason, a recovery loss occurs.

  Here, if the snubber capacitors 18a to 18d are connected in parallel to the switches SXp to SYn when the phase advance of the primary current Ip occurs, a large current flows through the switches SXp to SYn, and the reliability of the switches SXp to SYn. May be reduced. Hereinafter, the first upper arm switch SXp will be described as an example. When the snubber capacitors 18a to 18d are connected in parallel to the switches SXp to SYn, in the MODE 5 of FIG. 8, the first current flows from the second terminal T2 side through the first lower arm diode DXn. The snubber capacitor 18a is charged. Thereafter, when the mode shifts from MODE 5 to MODE 6 shown in FIG. 9, the electric charge accumulated in the first snubber capacitor 18a is discharged. In addition to the recovery current of the first lower arm diode DXn, the discharge current of the first snubber capacitor 18a flows to the first upper arm switch SXp, so that the reliability of the first upper arm switch SXp may be reduced. As described above, when the phase advance of the primary current Ip occurs, by installing the snubber capacitors 18a to 18d, a larger current flows through the switches SXp to SYn than when not installed. For this reason, each snubber capacitor 18a-18d cannot be installed. However, each of the snubber capacitors 18a to 18d contributes to reduction of the turn-off loss of each of the switches SXp to SYn when the phase delay of the primary side current Ip occurs. For this reason, when considering the phase lag of the primary current Ip, it is desirable to install the snubber capacitors 18a to 18d.

  Therefore, in the present embodiment, the inverter 13 includes the sub reactor 13b and the sub switches Ss1 and Ss2 operated by the power transmission side control device 16. Hereinafter, this will be described with reference to FIGS.

  FIG. 10A shows the transition of the current Idxp flowing through the first upper arm diode DXp and the current Idyn flowing through the second lower arm diode DYn, and FIG. 10B shows the current Isxn flowing through the first lower arm switch SXn. , Shows the transition of the current Isyp flowing through the second upper arm switch SYp. FIG.10 (c) shows transition of the electric current ICL which flows into the sub reactor 13b. FIGS. 10E and 10F show the transition of the operation state of each of the switches SXp to SYn, and FIG. 10G shows the transition of the operation state of the first and second sub switches Ss1 and Ss2. Note that FIG. 10D corresponds to the previous FIG. In FIG. 10, the current ICL flowing in the direction from the connection point of the first upper arm switch SXp and the first lower arm switch SXn to the connection point of the second upper arm switch SYp and the second lower arm switch SYn is positive. Define.

  The first and second sub switches Ss1, Ss2 are turned on at a time ta before the timing of switching off the first upper arm switch SXp and the second lower arm switch SYn in the period of MODE2. As a result, a part of the forward current flowing in the first upper arm diode DXp and the second lower arm diode DYn starts flowing in the subreactor 13b (see FIG. 11). For this reason, the forward current gradually decreases, and the current ICL flowing through the subreactor 13b gradually increases. Thereby, it is possible to reduce the recovery current at time t3 when the first upper arm switch SXp and the second lower arm switch SYn are subsequently switched off. Thereafter, the first intermediate voltage Vx becomes 0 at time tb, and the first lower arm switch SXn and the second upper arm switch SYp are switched to the on operation at time t31. After that, at time tc, the first and second sub switches Ss1, Ss2 are switched to the off operation, and the current flowing through the subreactor 13b becomes zero at time td.

  Thereafter, the first and second sub-switches Ss1, Ss2 are turned on at a timing before the OFF operation switching timing of the first lower arm switch SXn and the second upper arm switch SYp in the period of MODE5. As a result, part of the forward current flowing in the first lower arm diode DXn and the second upper arm diode DYp starts to flow in the subreactor 13b (see FIG. 12). For this reason, the forward current gradually decreases, and the current ICL flowing through the subreactor 13b gradually increases. Thereby, it is possible to reduce the recovery current at the timing when the first lower arm switch SXn and the second upper arm switch SYp are switched to the OFF operation thereafter. Thereafter, after the first upper arm switch SXp and the second lower arm switch SYn are switched to the on operation, the first and second sub switches Ss1, Ss2 are switched to the off operation.

  As described above, each of the sub-switches Ss1 and Ss2 is turned on so that the forward current flowing through the diode flows through the sub-reactor 13b to reduce the forward current, and then the first upper and lower arm switches SXp , SXn and the second upper and lower arm switches SYp, SYn are provided so as to increase the current flowing through the switch connected in reverse parallel to the diode whose forward current is reduced. By installing the sub reactor 13b and the sub switches Ss1 and Ss2, the recovery current can be reduced. Further, as described above, for example, under the situation where the mode is shifted from MODE5 to MODE6, the discharge of the electric charge accumulated in the first snubber capacitor 18a can be avoided, and the discharge current of the first snubber capacitor 18a is applied to the first upper arm switch SXp. Can be avoided. For this reason, each snubber capacitor 18a-18d can be installed.

<2. Operation method of each sub switch Ss1, Ss2>
In the present embodiment, the ON operation start timing of each of the sub switches Ss1, Ss2 is variably set. This is to reduce the high frequency component included in the output voltage of the inverter 13. In the inverter 13 of the non-contact power feeding system, in order to reduce switching loss, it is required to increase the rate of change of voltage and current to reduce loss. However, increasing the rate of change leads to steep rising and falling slopes of the rectangular wave voltage output from the inverter 13. As a result, a high frequency component is included in the output voltage of the inverter 13. The output voltage including the high frequency component is applied to the power transmission side filter circuit 14. Here, in the present embodiment, the frequency band of the high frequency component is a pass band of the power transmission pad 15 and the power transmission side filter circuit 14 which are resonance circuits. This is because the parasitic capacitance between the windings of the reactor constituting the resonance circuit and the power transmission side filter circuit 14 increases in the frequency band of the high frequency component, so that the resonance circuit and power transmission side filter circuit 14 in the frequency band of the high frequency component are increased. This is because the impedance is excessively low.

  For this reason, the high frequency component contained in the output voltage of the inverter 13 cannot be removed, and there is a concern that the EMC may be adversely affected. In order to cope with such a problem, for example, it is conceivable to separately add a high-frequency filter capable of removing the high-frequency component. However, in this case, the loss in the high frequency filter increases or the physique of the system increases.

  Therefore, in the present embodiment, the rate of decrease in the first intermediate voltage Vx after the set of the first upper arm switch SXp and the second lower arm switch SYn is switched to the off operation, and the emitter potential of the second lower arm switch SYn. The rising speed of the potential of the connection point of the second upper and lower arm switches SYp and SYn (hereinafter referred to as the second intermediate voltage Vy) with respect to the frequency band of the high-frequency component becomes the stop band of the resonance circuit and the power transmission filter circuit 14 Adjust to a speed that is included. Further, the rising speed of the first intermediate voltage Vx and the decreasing speed of the second intermediate voltage Vy after the set of the first lower arm switch SXn and the second upper arm switch SYp is switched to the off operation are set as the frequency of the high frequency component. The speed is adjusted so that the band is included in the stop band of the resonance circuit and the power transmission side filter circuit 14. Such adjustment suppresses the influence of the high-frequency component on the EMC and eliminates the need for a high-frequency filter. As a result, it is possible to reduce the amount of heat generated by reducing the loss in the high frequency filter, reduce the physique of the system, and facilitate the design of the frequency characteristics of the resonance circuit and the power transmission filter circuit 14.

  In the present embodiment, the second intermediate voltage Vy when the potential at the connection point of the second upper and lower arm switches SYp and SYn is higher than the emitter potential of the second lower arm switch SYn is defined as positive. Each sub switch Ss1 when the set of the first upper arm switch SXp and the second lower arm switch SYn is turned on and the set of the first lower arm switch SXn and the second upper arm switch SYp is turned off. , Ss2 on-operation switching timing is referred to as first on-operation switching timing. Further, each sub switch Ss1 when the set of the first upper arm switch SXp and the second lower arm switch SYn is turned off and the set of the first lower arm switch SXn and the second upper arm switch SYp is turned on. , Ss2 on-operation switching timing is referred to as second on-operation switching timing.

  First, the first on-operation switching timing will be described with reference to FIG. Here, FIG. 13A shows the transition of the current that can be detected by the first and fourth current sensors 17a and 17d, and FIG. 13B shows the current that can be detected by the second and third current sensors 17b and 17c. FIGS. 13C to 13G correspond to FIGS. 10C to 10G.

  Description will be made by paying attention to the waveform shown by the solid line in FIG. Before the time t1b under a situation where the first upper arm switch SXp and the second lower arm switch SYn are turned on and the first lower arm switch SXn and the second upper arm switch SYp are turned off, The forward currents Idxp and Idyn flow through the first upper arm diode DXp and the second lower arm diode DYn due to the phase advance of the current. Thereafter, at time t1b, the first and second sub switches Ss1, Ss2 are switched to the on operation. As a result, the current ICL flowing through the subreactor 13b gradually increases, and the forward currents Idxp and Idyn flowing through the first upper arm diode DXp and the second lower arm diode DYn gradually decrease. After the forward currents Idxp and Idyn decrease to zero, the currents Ispp and Isyn flowing through the first upper arm switch SXp and the second lower arm switch SYN are gradually increased.

  Thereafter, at time t2, the set of the first upper arm switch SXp and the second lower arm switch SYn is switched to the off operation. For this reason, the first and fourth snubber capacitors 18a and 18d are charged by the current flowing from the first terminal T1 side. Thereby, the voltage between the terminals of the first and fourth snubber capacitors 18a, 18d gradually increases. At this time, as the inter-terminal voltage of the first snubber capacitor 18a increases, the first intermediate voltage Vx decreases and approaches 0 as shown in FIG. 13 (d). Further, as the inter-terminal voltage of the fourth snubber capacitor 18d increases, the second intermediate voltage Vy increases and approaches the input voltage VDC. The timing after the timing when the first intermediate voltage Vx becomes 0 is adjusted to be the ON operation switching timing of the first lower arm switch SXn, and the timing after the timing when the second intermediate voltage Vy becomes the input voltage VDC is set to the second timing. Adjustment is made so that the timing of switching on the upper arm switch SYp is reached. Thereby, the switch to the ON operation of these switches SXn and SYp can be set to zero voltage switching (ZVS). Here, in FIG. 13, the ideal on-operation switching timing for ZVS is shown at time t3b.

  Here, after the time t2, the decreasing speed of the first intermediate voltage Vx and the increasing speed of the second intermediate voltage Vy are the same as those after the first upper arm switch SXp and the second lower arm switch SYn are switched off. The higher the charging current Ioff of the first and fourth snubber capacitors 18a and 18d, the higher the value. 13 (a), (c), (d), and (f), the transition of each waveform when the charging current Ioff is larger than the ideal value is shown by a one-dot chain line, and the charging current Ioff is ideal. The transition of each waveform when it is smaller than the correct value is indicated by a broken line. In FIG. 13 (f), the ideal ON operation switching timing of each of the sub switches Ss1, Ss2 and the OFF operation switching timing (time t2) of the first upper arm switch SXp and the second lower arm switch SYn are ideal. The time difference is indicated by “Tonb”. When the ideal OFF operation switching timing is set, the ideal time from the time t2 until the first intermediate voltage Vx becomes 0 is indicated by “Tswb”. The ideal time Tswb is, for example, “¼” of the resonance period of the resonance circuit determined by the inductance of the sub-reactor 13b and the capacitances of the snubber capacitors 18a to 18d.

  The first intermediate voltage Vx will be described as an example. When the time difference Tona between the ON operation switching timing (time t1a) of each of the sub switches Ss1 and Ss2 and the time t2 is longer than the ideal time difference Tonb, the first snubber capacitor 18a. The charging current becomes larger than the ideal charging current. As a result, the time Tsw from time t2 to the timing when the first intermediate voltage Vx becomes 0 (time t3a) becomes shorter than the ideal time Tswb. On the other hand, when the time difference Tonc between the ON operation switching timing (time t1c) of each sub switch Ss1, Ss2 and time t2 is shorter than the ideal time difference Tonb, the charging current of the first snubber capacitor 18a is larger than the ideal charging current. Becomes smaller. As a result, the time Tswc from the time t2 to the timing when the first intermediate voltage Vx becomes 0 (time t3c) becomes longer than the ideal time Tswb. This is for the reason explained below.

  In the resonance circuit determined by the inductance of the subreactor 13b and the capacitances of the first and second snubber capacitors 18a and 18b, the minimum current Imin required for soft switching is expressed by the following equation (eq1).

上式（ｅｑ１）では、サブリアクトル１３ｂのインダクタンスを「Ｌｓ」とし、第１，第２スナバコンデンサ１８ａ，１８ｂのそれぞれの静電容量を「Ｃｓｎｂ／２」とした。上式（ｅｑ１）は、最小限の電流Ｉｍｉｎが流れるサブリアクトル１３ｂに蓄積されているエネルギ「１／２×Ｌｓ×Ｉｍｉｎ×Ｉｍｉｎ」が、第１，第２スナバコンデンサ１８ａ，１８ｂの静電容量「Ｃｓｎｂ」を充電するために必要なエネルギ「１／２×Ｃｓｎｂ×ＶＤＣ×ＶＤＣ」になるとの関係から導かれる。第１スナバコンデンサ１８ａの充電電流Ｉｓｎｂが最小限電流Ｉｍｉｎよりも十分大きい場合、先の図１３の時刻ｔ２から第１中間電圧Ｖｘが０となるまでの時間Ｔ０は、下式（ｅｑ２）で表される。

In the above equation (eq1), the inductance of the sub-reactor 13b is “Ls”, and the capacitances of the first and second snubber capacitors 18a and 18b are “Csnb / 2”. The above equation (eq1) indicates that the energy “1/2 × Ls × Imin × Imin” stored in the sub-reactor 13b through which the minimum current Imin flows is the capacitance of the first and second snubber capacitors 18a and 18b. It is derived from the relationship that the energy required to charge “Csnb” becomes “½ × Csnb × VDC × VDC”. When the charging current Isnb of the first snubber capacitor 18a is sufficiently larger than the minimum current Imin, the time T0 from the time t2 in FIG. 13 until the first intermediate voltage Vx becomes 0 is expressed by the following equation (eq2). Is done.

上式（ｅｑ２）は、コンデンサの静電容量Ｃ、端子間電圧Ｖ及び蓄積電荷Ｑの関係「Ｑ＝ＣＶ」から導かれるものである。上式（ｅｑ２）は、スナバコンデンサの充電電流Ｉｓｎｂが大きいほど、上記時間Ｔ０が短くなる（すなわち、第１中間電圧Ｖｘの低下速度が高くなる）ことを示している。このため、充電電流Ｉｓｎｂを最適値に調整することにより、低下速度を適切な速度とすることができる。ここで、充電電流Ｉｓｎｂは、各サブスイッチＳｓ１，Ｓｓ２のオン操作時間が長いほど大きくなる。また、第１上アームスイッチＳＸｐ及び第２下アームスイッチＳＹｎがオン操作されている期間における第１上アームダイオードＤＸｐ及び第２下アームダイオードＤＹｎの順方向電流が大きいほど、各スイッチＳＸｐ，ＳＹｎのオフ操作切替タイミングに対して、第１オン操作切替タイミングを早めることが要求される。上記順方向電流は、電流位相の進み度合いや、１次側電流Ｉｐの振幅が変化することで変化する。

The above equation (eq2) is derived from the relationship “Q = CV” of the capacitance C of the capacitor, the voltage V between terminals, and the accumulated charge Q. The above expression (eq2) indicates that the time T0 is shortened (that is, the rate of decrease in the first intermediate voltage Vx is increased) as the charging current Isnb of the snubber capacitor is increased. For this reason, by adjusting the charging current Isnb to an optimal value, the decrease rate can be set to an appropriate rate. Here, the charging current Isnb increases as the on-operation time of each of the sub switches Ss1, Ss2 increases. Further, the larger the forward current of the first upper arm diode DXp and the second lower arm diode DYn during the period when the first upper arm switch SXp and the second lower arm switch SYn are turned on, the larger the forward current of each switch SXp, SYn. It is required to advance the first on-operation switching timing with respect to the off-operation switching timing. The forward current changes as the degree of advancement of the current phase and the amplitude of the primary current Ip change.

  Next, the second on operation switching timing will be described. This switching timing can also be set by the same method as the first operation switching timing setting method. Specifically, the larger the forward current of the first lower arm diode DXn and the second upper arm diode DYp during the period when the first lower arm switch SXn and the second upper arm switch SYp are turned on, the larger the switches SXn, SYp. It is required to advance the second on-operation switching timing with respect to the off-operation switching timing.

  14 and 15, it will be described that the forward current changes according to the degree of advancement of the current phase and the amplitude of the primary current Ip. 14 and 15, (a) shows transitions of the primary side current Ip and the primary side voltage Vp, and (b) shows the operating states of the first upper arm switch SXp and the second lower arm switch SYn. (C) shows the transition of the operating state of the first lower arm switch SXn and the second upper arm switch SYp.

  As shown in FIG. 14, the primary current Ip at time t1 when the first lower arm switch SXn and the second upper arm switch SYp are switched to the off operation increases as the degree of advancement of the current phase increases. As the primary current Ip increases, the forward current flowing through the first lower arm diode DXn and the second upper arm diode DYp also increases. In this case, in order to adjust the charging currents of the second and third snubber capacitors 18b and 18c to the optimum values that make the rising speed of the first intermediate voltage Vx and the decreasing speed of the second intermediate voltage Vy appropriate speeds, It is required to advance the 2-on operation switching timing. On the other hand, the primary current Ip at time t2 when the first upper arm switch SXp and the second lower arm switch SYn are switched to the off operation also increases as the degree of advancement of the current phase increases. For this reason, in order to adjust the charging current of the first and fourth snubber capacitors 18a and 18d to the optimum values that make the lowering speed of the first intermediate voltage Vx and the rising speed of the second intermediate voltage Vy appropriate speeds, It is required to advance the 1-on operation switching timing.

  Further, as shown in FIG. 15, the primary current Ip at time t1 when the first lower arm switch SXn and the second upper arm switch SYp are switched to the off operation increases as the amplitude of the primary current Ip increases. As a result, the forward current flowing through the first lower arm diode DXn and the second upper arm diode DYp increases. On the other hand, the primary current Ip at time t2 when the first upper arm switch SXp and the second lower arm switch SYn are switched to the off operation also increases as the amplitude of the primary current Ip increases.

  The operation process of the inverter 13 including the setting process of the first on-operation switching timing will be described with reference to FIG. Note that the processing illustrated in FIG. 16 is repeatedly executed by the power transmission side control device 16 at a predetermined cycle, for example.

  In this series of processing, first, in step S10, whether the first upper arm switch SXp and the second lower arm switch SYn are turned on, and the first lower arm switch SXn and the second upper arm switch SYp are turned off. Judge whether or not.

  If an affirmative determination is made in step S10, the process proceeds to step S11 to determine whether it is the first current detection timing. In the present embodiment, the first current detection timing is the charging of the first and third snubber capacitors 18a and 18c from the first reference timing at which the first upper arm switch SXp and the second lower arm switch SYn are switched to the off operation. The timing is set to a time that is longer than the maximum value of the ON operation time of the first and second sub switches Ss1, Ss2 required for adjusting the current to the optimum value. When an affirmative determination is made in step S11, the process proceeds to step S12, and the forward current flowing through the first upper arm diode DXp or the second lower arm diode DYn is detected by the first current sensor 17a or the fourth current sensor 17d. Hereinafter, the current detected by the first current sensor 17a or the fourth current sensor 17d is referred to as a first current value I1.

  In the subsequent step S13, the first specified time ΔTr1 is variably set based on the absolute value of the first current value I1 and the input voltage VDC of the inverter 13. The first specified time ΔTr1 determines the first ON operation switching timing. Specifically, the timing that is the first specified time ΔTr1 backward from the first reference timing is set as the first on-operation switching timing. In the present embodiment, the first specified time ΔTr1 is set longer as the absolute value of the first current value I1 is larger or the input voltage VDC is higher. Here, the reason why the first specified time ΔTr1 is set longer as the input voltage VDC is higher is as follows. In the above equation (eq2), the time T0 becomes longer as the input voltage VDC is higher. When this time T0 becomes longer, the timing at which the first intermediate voltage Vx becomes 0 or the second intermediate voltage Vy becomes the input voltage VDC is the ON operation of the first upper arm switch SXn and the second upper arm switch SYp. The switching timing will be exceeded. As a result, there is a concern that switching to the ON operation of each switch SXn, SYp cannot be made ZVS. In order to deal with such a problem, the input voltage VDC is used to set the first specified time ΔTr1. In the present embodiment, the processing in this step corresponds to “first setting means”.

  In the subsequent step S14, it is determined whether or not it is the first on-operation switching timing based on the first specified time ΔTr1. If an affirmative determination is made in step S14, the process proceeds to step S15, and the first and second sub-switches Ss1, Ss2 are switched to the on operation.

  In a succeeding step S16, it is determined whether or not it is an OFF operation switching timing of the first upper arm switch SXp and the second lower arm switch SYn. If an affirmative determination is made in step S16, the process proceeds to step S17, and the switches SXp and SYn are switched to the off operation. In the subsequent step S18, it is the ON operation switching timing of the first lower arm switch SXn and the second upper arm switch SYp with a dead time between the switching of the first upper arm switch SXp and the second lower arm switch SYn to the OFF operation. Determine whether or not. When an affirmative determination is made in step S18, the process proceeds to step S19, and the switches SXn and SYp are switched to the on operation.

  In a succeeding step S20, it is determined whether or not it is an OFF operation switching timing of the first and second sub switches Ss1, Ss2. When an affirmative determination is made in step S20, the process proceeds to step S21, and the sub switches Ss1, Ss2 are switched to an off operation. If a negative determination is made in step S10 or if the process of step S21 is completed, this series of processes is temporarily terminated.

  The operation process of the inverter 13 including the setting process of the second on-operation switching timing will be described with reference to FIG. The processing illustrated in FIG. 17 is repeatedly executed by the power transmission side control device 16 at a predetermined cycle, for example. In FIG. 17, the same processes as those shown in FIG. 16 are given the same reference numerals for the sake of convenience.

  In this series of processing, first, in step S30, whether the first lower arm switch SXn and the second upper arm switch SYp are turned on, and the first upper arm switch SXp and the second lower arm switch SYn are turned off. Judge whether or not.

  If an affirmative determination is made in step S30, the process proceeds to step S31 to determine whether it is the second current detection timing. In the present embodiment, the second current detection timing is the charging of the second and fourth snubber capacitors 18b and 18d from the second reference timing at which the first lower arm switch SXn and the second upper arm switch SYp are switched to the off operation. The timing is set to a time that is longer than the maximum value of the ON operation time of the first and second sub switches Ss1, Ss2 required for adjusting the current to the optimum value. If an affirmative determination is made in step S31, the process proceeds to step S32, and the forward current flowing through the first lower arm diode DXn or the second upper arm diode DYp is detected by the second current sensor 17b or the third current sensor 17c. Hereinafter, the current detected by the second current sensor 17b or the third current sensor 17c is referred to as a second current value I2.

  In the subsequent step S33, the second specified time ΔTr2 is variably set based on the absolute value of the second current value I2 and the input voltage VDC. The second specified time ΔTr2 determines the second ON operation switching timing. Specifically, a timing that is retroactive to the second specified time ΔTr2 from the second reference timing is set as a second ON operation switching timing. In the present embodiment, the second specified time ΔTr2 is set longer as the absolute value of the second current value I2 is larger or the input voltage VDC is higher. In the present embodiment, the processing in this step corresponds to “second setting means”.

  After the subsequent steps S14 and S15, in step S34, it is determined whether or not it is an OFF operation switching timing of the first lower arm switch SXn and the second upper arm switch SYp. If an affirmative determination is made in step S34, the process proceeds to step S35, and the switches SXn and SYp are switched to an off operation. In the following step S36, it is the on operation switching timing of the first upper arm switch SXp and the second lower arm switch SYn with a dead time between the switching of the first lower arm switch SXn and the second upper arm switch SYp to the off operation. Determine whether or not. When an affirmative determination is made in step S36, the process proceeds to step S37, and the switches SXp and SYn are switched to the on operation. Thereafter, the process proceeds to step S20. If a negative determination is made in step S10 or if the process of step S21 is completed, this series of processes is temporarily terminated.

  According to the embodiment described in detail above, the following effects can be obtained.

  (1) The detected value of the forward current flowing through the diodes DXp and DYn during the period when the set of the first upper arm switch SXp and the second lower arm switch SYn is turned on is large, or the input voltage VDC of the inverter 13 is high. The first ON operation switching timing was advanced with respect to the OFF operation switching timing of the set of the switches SXp and SYn. In addition, as the detected value of the forward current flowing in the diodes DXn and DYp during the period when the set of the first lower arm switch SXn and the second upper arm switch SYp is turned on, or as the input voltage VDC increases, The second ON operation switching timing is advanced with respect to the OFF operation switching timing of the pair of switches SXn and SYp. As a result, the changing speed of the first and second intermediate voltages Vx and Vy can be set to an appropriate speed, and as a result, the high frequency component included in the output voltage of the inverter 13 can be suitably reduced.

  (2) The inverter 13 includes the first protection diode Dp1 and the second protection diode Dp2. If the first sub switch Ss1 is turned off due to a malfunction while a current is flowing through the sub reactor 13b, a surge voltage is applied to both ends of the first sub switch Ss1, and the reliability of the first sub switch Ss1 is improved. There are concerns about a decline. Here, by providing the first protective diode Dp1, the potential at the connection point between the first sub switch Ss1 and the sub reactor 13b can be limited by the potential of the first terminal T1. For this reason, the potential difference between both ends of the first sub switch can be kept below the input voltage VDC of the inverter 13, and a decrease in the reliability of the first sub switch Ss1 can be avoided. The second protective diode Dp2 is for avoiding a decrease in reliability of the second sub switch Ss2. The operation principle of the second protection diode Dp2 is the same as the operation principle of the first protection diode Dp1.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings with a focus on differences from the first embodiment. In the present embodiment, the installation position of the current sensor is changed as shown in FIG. In FIG. 18, the same members as those shown in FIG. 1 are given the same reference numerals for the sake of convenience.

  As illustrated, the inverter 13 includes a fifth current sensor 19a and a sixth current sensor 19b instead of the first to fourth current sensors 17a to 17d. The fifth current sensor 19a is provided at a position where the current flowing through the sub reactor 13b and the sub switches Ss1, Ss2 can be detected. The sixth current sensor 19b is provided at a position where the output current (primary current Ip) of the inverter 13 can be detected.

  Here, in the present embodiment, the first and second current values I1 and I2 used for setting the first and second on-operation switching timing are changed from the detection value of the sixth current sensor 19b to the detection value of the fifth current sensor 19a. Is calculated by subtracting. According to this embodiment described above, the number of current sensors for determining the first and second ON operation switching timings can be reduced.

(Third embodiment)
Hereinafter, the third embodiment will be described with reference to the drawings with a focus on differences from the first embodiment. In this embodiment, as shown in FIG. 19, the connection method of the sub switch and sub reactor provided in the inverter 13 is changed. In FIG. 19, the same members as those shown in FIG. 1 are denoted by the same reference numerals for the sake of convenience.

  As illustrated, the inverter 13 includes a first sub-switch Ssα, a first sub-diode Dsα, a second sub-switch Ssβ, a second sub-diode Dsβ, a first protection diode Dpα, a second protection diode Dpβ, and a sub A reactor 13c is provided. In this embodiment, voltage control type semiconductor switches are used as the sub switches Ssα and Ssβ, and specifically, IGBTs are used.

  A first sub-diode Dsα is connected in antiparallel to the first subswitch Ssα, and a second subdiode Dsβ is connected in antiparallel to the second subswitch Ssβ. The collector of the first sub switch Ssα is connected to the connection point between the first upper arm switch SXp and the first lower arm switch SXn, and the emitter of the second sub switch Ssβ is connected to the emitter of the first sub switch Ssα. Has been. The first end of the sub reactor 13c is connected to the collector of the second sub switch Ssβ. A connection point between the second upper arm switch SYp and the second lower arm switch SYn is connected to the second end of the subreactor 13b. Each of the sub switches Ssα and Ssβ has a function of preventing current from flowing from one to the other of the pair of terminals (collector) of the series connection body of the sub switches Ssα and Ssβ when being turned off. .

  The cathode of the first protection diode Dpα and the anode of the second protection diode Dpβ are connected to the connection point between the second sub switch Ssβ and the subreactor 13c. The second terminal T2 is connected to the anode of the first protection diode Dpα, and the first terminal T1 is connected to the cathode of the second protection diode Dpβ. The first protection diode Dpα is provided to protect the first sub switch Ssα, and the second protection diode Dpβ is provided to protect the second sub switch Ssβ. Specifically, when the sub-switches Ssα and Ssβ are turned off due to malfunction when the current flows through the sub-reactor 13c from the first upper arm switch SXp side to the second lower arm switch SYn side, A surge voltage is applied across the sub switch Ssα. The first protection diode Dpα protects the first sub switch Ssα from this surge voltage. On the other hand, if each sub switch Ssα, Ssβ is turned off due to a malfunction when the current flows through the subreactor 13c from the second lower arm switch SYn side to the first upper arm switch SXp side, A surge voltage is applied across the switch Ssβ. The second protection diode Dpβ protects the second sub switch Ssβ from this surge voltage.

  According to the present embodiment described above, the same effects as those of the first embodiment can be obtained.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to the drawings with a focus on differences from the first embodiment. In the present embodiment, the circuit configuration of the inverter is changed as shown in FIG. In FIG. 20, the same members as those shown in FIG. 1 are given the same reference numerals for the sake of convenience.

  As illustrated, the inverter 13 includes first to fourth sub-switches Ssa to Ssd, and first and second sub-reactors 13d and 13e. In the present embodiment, as each of the sub switches Ssa to Ssd, a voltage control type semiconductor switch in which free wheel diodes are connected in antiparallel is used, and specifically, an IGBT is used. Each of the sub switches Ssa to Ssd is operated by the power transmission side control device 16.

  The collector of the first sub switch Ssa is connected to the emitter of the second sub switch Ssb. A collector of the first upper arm switch SXp is connected to the collector of the second sub switch Ssb, and an emitter of the first lower arm switch SXn is connected to the emitter of the first sub switch Ssa. A connection point of the first upper arm switch SXp and the first lower arm switch SXn is connected to a connection point of the first sub switch Ssa and the second sub switch Ssb via the first sub reactor 13d.

  The collector of the third sub switch Ssc is connected to the emitter of the fourth sub switch Ssd. The collector of the fourth sub switch Ssd is connected to the collector of the second upper arm switch SYp, and the emitter of the third sub switch Ssc is connected to the emitter of the second lower arm switch SYn. A connection point between the third sub switch Ssc and the fourth sub switch Ssd is connected to a connection point between the second upper arm switch SYp and the second lower arm switch SYn via the second sub reactor 13e.

  Subsequently, an operation method of each of the sub switches Ssa to Ssd according to the present embodiment will be described. In the present embodiment, only the first and third sub switches Ssa and Ssc are the sub switches to be operated in steps S14, S15, S20, and S21 of FIG. On the other hand, only the second and fourth sub-switches Ssb and Ssd are the sub-switches to be operated in steps S14, S15, S20, and S21 of FIG.

  According to the embodiment described above, it is possible to obtain an effect according to the effect of the first embodiment.

(Other embodiments)
Each of the above embodiments may be modified as follows.

  The power transmission side filter circuit 14, the power transmission pad 15, the power reception pad 20, and the power reception side filter circuit 21 may be changed as shown in FIG. Specifically, the fifth resonance capacitor 15d is connected in parallel to the power transmission side coil 15a. That is, an LC parallel resonance circuit is configured by the power transmission side coil 15a and the fifth resonance capacitor 15d. The power transmission side filter circuit 14 includes a series connection body of a power transmission side first capacitor 14f and a power transmission side fifth reactor 14g, and a series connection body of a power transmission side second capacitor 14h and a power transmission side sixth reactor 14i. A sixth resonance capacitor 20d is connected in parallel to the power receiving side coil 20a. The power reception side filter circuit 21 includes a series connection body of a power reception side first capacitor 21f and a power reception side fifth reactor 21g, and a series connection body of a power reception side second capacitor 21h and a power reception side sixth reactor 21i. In FIG. 21, the same members as those shown in FIG. 1 are denoted by the same reference numerals.

  In the configuration shown in FIGS. 1 and 19, the protective diodes Dp1 and Dp2 may be removed.

  In the above embodiment, the DCDC converter 12 may be removed.

  In the above embodiment, the switching cycle Tsw of each switch SXp, SXn, SYp, SYn may be set shorter than the cycle of the fundamental current of the primary current Ip.

  -Switch which comprises the inverter 13 is not restricted to IGBT, For example, MOSFET may be sufficient. In this case, the free wheel diode connected in antiparallel to each switch is not limited to an external diode, but may be a body diode of a MOSFET.

  The first lower arm switch SXn after the OFF operation switching timing of the first upper arm switch SXp and the second lower arm switch SYn with respect to steps S11 and S13 in FIG. 16 of the first embodiment. And it is good also as the ON operation switching timing of 2nd upper arm switch SYp. Further, regarding steps S31 and S33 in FIG. 17 of the first embodiment, the second reference timing may be set as the ON operation switching timing of the first upper arm switch SXp and the second lower arm switch SYn.

  -Setting the changing speed of the first and second intermediate voltages Vx and Vy to an appropriate speed is not limited to the case where the phase of the load current of the inverter 13 has advanced. When the value of the snubber capacitor is delayed to the maximum (for example, when the turn-off switching current is maximized and the snubber capacitor is charged earliest), the voltage change rate of the rectangular wave voltage output from the inverter 13 ( (Slope) is set to a value that provides an appropriate voltage change rate. In such a configuration, the on-operation time of the sub switch is controlled to be longer when the phase delay of the current is less than at the time of design or when the delay further decreases and the phase of the current advances. As a result, the voltage change rate can be suitably controlled in the entire region from the current phase delay region to the current phase advance region.

  -In each said embodiment, as a capacitor | condenser connected in parallel with each switch SXp-SYn, between each terminal of each switch SXp-SYn (specifically, between a collector and emitter), each parasitic capacitance (parasitic capacitor), It may be a parasitic capacitance between the terminals of the diodes DXp to DYn connected in reverse parallel to the switch (specifically, between the anode and the cathode).

  -As a coil to which the output voltage of an inverter is applied, it is not restricted to the power transmission side coil which comprises a non-contact electric power feeding system. For example, the coil which comprises a high frequency induction heating apparatus, and the coil which comprises an electromagnetic cooker may be sufficient. Even in this case, if the phenomenon that the phase of the current flowing through the coil advances occurs, the application of the present invention that can reduce the recovery loss is effective.

  13b ... sub reactor, 15a ... power transmission side coil, 18a to 18d ... first to fourth snubber capacitors, SXp, SXn ... first upper and lower arm switches, SYp, SYn ... second upper and lower arm switches, DXp, DXn ... first upper and lower arm diodes, DYp, DYn ... second upper and lower arm diodes, Ss1, Ss2 ... first and second sub-switches.

Claims (7)

A series connection of a first upper arm switch (SXp) and a first lower arm switch (SXn) connected in parallel to the DC power source (12);
A series connection of a second upper arm switch (SYp) and a second lower arm switch (SYn) connected in parallel to the DC power supply;
A diode (DXp, DXn, DYp, DYn) connected in antiparallel to each of the first upper arm switch, the first lower arm switch, the second upper arm switch, and the second lower arm switch;
Capacitors (18a-18d) connected in parallel to each of the first upper arm switch, the first lower arm switch, the second upper arm switch, and the second lower arm switch;
A first end is connected to a first electrical path that connects the first upper arm switch and the first lower arm switch in series, and a second end that connects the second upper arm switch and the second lower arm switch in series. A main coil (15a) having a second end connected to the electrical path;
A subreactor (13b; 13c; 13d, 13e) connected to each of the first electric path and the second electric path;
Sub switches (Ss1, Ss2; Ssα, Ss1, Ss, Ssβ; Ssa to Ssd),
Main operating means for alternately turning on the set of the first upper arm switch and the second lower arm switch and the set of the first lower arm switch and the second upper arm switch;
From the middle of the period when the set of the first upper arm switch and the second lower arm switch is turned on until the middle of the period when the set of the first lower arm switch and the second upper arm switch is turned on next time The first operation process for turning on the sub switch during the period of the first and the first upper arm switch and the first operation from the middle of the period during which the set of the first lower arm switch and the second upper arm switch is turned on. 2 a sub operation means for performing a second operation process for turning on the sub switch in a period until the middle of the period when the set of the lower arm switches is turned on next time;
Based on a forward current flowing through the diode during a period in which the set of the first upper arm switch and the second lower arm switch is turned on, the first on operation switching timing of the sub switch by the first operation processing is variable. First setting means for setting;
Based on a forward current flowing through the diode during a period in which the set of the first lower arm switch and the second upper arm switch is turned on, the second on operation switching timing of the sub switch by the second operation processing is variable. A power conversion device comprising: a second setting unit for setting. The first setting means further uses the voltage between the terminals of the DC power source for variable setting of the ON operation switching timing of the sub switch by the first operation processing,
2. The power converter according to claim 1, wherein the second setting unit further uses a voltage across the terminals of the DC power source for variable setting with the ON operation switching timing of the sub switch by the second operation process. The first setting means increases the forward current flowing through the diode during a period in which the set of the first upper arm switch and the second lower arm switch is turned on, and the first upper arm switch and the second upper arm switch. Advance the on-operation switching timing of the sub switch by the first operation processing with respect to the off-operation switching timing of the lower arm switch set,
The second setting means includes the first lower arm switch and the second lower arm as the forward current flowing through the diode during a period in which the pair of the first lower arm switch and the second upper arm switch is turned on is larger. The power converter according to claim 1, wherein the on-operation switching timing of the sub switch by the second operation processing is advanced with respect to the off-operation switching timing of the set of upper arm switches. A connection point between the first upper arm switch and the first lower arm switch is a first connection point,
A connection point between the second upper arm switch and the second lower arm switch is a second connection point,
The sub-switch includes a first sub-switch (Ss1; Ssα) and a second sub-switch (Ss2; Ssβ),
The first sub switch, the sub reactor (13b; 13c) and the second sub switch are connected in series,
The said 1st electrical path and the said 2nd electrical path are any one of Claims 1-3 connected by the serial connection body of the said 1st subswitch, the said subreactor, and the said 2nd subswitch. Power converter. The sub switch includes a first sub switch (Ssa) and a second sub switch (Ssb) connected in series to each other, and a third sub switch (Ssc) and a fourth sub switch (Ssd) connected in series to each other. ,
The sub reactor includes a first sub reactor (13d) and a second sub reactor (13e),
The series connection of the first sub switch and the second sub switch is connected in parallel to the series connection of the first upper arm switch and the first lower arm switch,
The series connection body of the third sub switch and the fourth sub switch is connected in parallel to the series connection body of the second upper arm switch and the second lower arm switch,
The positive electrode side of the DC power source is connected to the second sub switch side of both ends of the series connection body of the first sub switch and the second sub switch,
A positive electrode side of the DC power source is connected to the fourth sub switch side of both ends of the serial connection body of the third sub switch and the fourth sub switch,
The electric path connecting the first sub switch and the second sub switch in series is connected to the first electric path via the first sub reactor.
The electrical path connecting the third sub switch and the fourth sub switch in series is connected to the second electrical path via the second sub reactor,
The sub operation means sets the operation target of the first operation process as the first sub switch and the third sub switch, and sets the operation target of the second operation process as the second sub switch and the fourth sub switch. The power converter device of any one of Claims 1-3. The main coil constitutes a resonance circuit together with resonance capacitors (15b, 15c; 15d),
The switching period of each of the first upper arm switch and the second lower arm switch group and the first lower arm switch and the second upper arm switch group is a fundamental wave of the current flowing through the main coil. The power converter according to any one of claims 1 to 5, wherein the power converter is set to be the same as the period. It is applied to a non-contact power feeding system that performs non-contact power transfer between a power transmission side coil and a power reception side coil (20a),
The main coil is the power transmission side coil,
The resonant capacitor is a power transmission side resonant capacitor,
The power conversion device according to claim 6, wherein the power reception side coil forms a resonance circuit together with a power reception side resonance capacitor (20 b, 20 c; 20 d).

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