JP2016051726A - Electronic device and method of manufacturing electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic device capable of reducing transmission loss between adjoining semiconductor chips, while reducing the mounting area of the semiconductor chip on a wiring board.SOLUTION: A first semiconductor chip 20 has a first face 23. A second electrode 25 is formed in a part close to one end of the first face 23, in the direction of travel of signal. A second semiconductor chip 30 has a second face 33. A third electrode 34 is formed in a part close to one end of the second face 33, in the direction of travel of signal. The second electrode 25 and third electrode 34 are facing each other, and connected electrically while holding a solder joint 26c therebetween. A signal outputted from the second electrode 25 passes through the solder joint 26c before being inputted to the third electrode 34.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an electronic device and a method for manufacturing the electronic device.

  In Patent Document 1, an upper chip having an I / O circuit for connection to a substrate around, an I / O circuit arranged on the inner side of the upper chip, and an I / O circuit arranged on the inner side. And an optionally connectable auxiliary chip that is substantially directly connected to the upper chip. Patent Document 2 discloses a structure in which a plurality of semiconductor elements are electrically and mechanically connected to an electric wiring board by bumps.

JP 2004-320012 A Japanese Patent Laid-Open No. 5-74985

  In order to reduce the number of processes and reduce the mounting area of a semiconductor chip, electronic devices in which a plurality of flip chip type semiconductor chips are mounted on a substrate are currently used in various devices. In the case of so-called high-frequency signal transmission using such an electronic device in the millimeter wave band, a transmission loss when a signal passes through a transmission line on a substrate, or a conductive member such as solder for connecting the semiconductor chip and the transmission line The transmission loss when the signal passes through becomes large. That is, in the conventional RF connection form, a plurality of flip chip type semiconductor chips are arranged side by side on the main surface of the wiring board. An electrode of one semiconductor chip and a wiring pattern (transmission line) on the wiring board are electrically connected to each other with a conductive member such as solder interposed therebetween, and adjacent to the one semiconductor chip. An electrode and a wiring pattern of another semiconductor chip that fits are electrically connected to each other with a conductive member interposed therebetween. Under such a configuration, a signal output from one semiconductor chip sequentially passes through a conductive member, a wiring pattern, and another conductive member and is input to another semiconductor chip. Therefore, transmission loss occurs in each of the two conductive members and the transmission line through which the signal passes. In addition, since a plurality of semiconductor chips are arranged side by side on the main surface of the wiring substrate, the center interval between adjacent semiconductor chips is not smaller than the interval at which the side surfaces of these semiconductor chips are in contact with each other. This hinders the reduction of the chip mounting area.

  The present invention has been made in view of such problems, and an electronic device capable of reducing transmission loss between adjacent semiconductor chips and reducing the mounting area of the semiconductor chip on the wiring board. And it aims at providing the manufacturing method of an electronic device.

  In order to solve the above-described problem, an electronic device according to the present invention includes a wiring board having a wiring pattern and a concave portion on a main surface, and a frame portion having a concave inside formed on a bottom surface of the concave portion, and a first surface. A flip chip type first semiconductor chip having a first electrode formed on the first surface and connected to the wiring pattern, and a second electrode formed on the first surface; Formed on the second surface, the third surface that is the back surface of the second surface, and the second surface, and is connected to the second electrode directly or with the conductive member joint interposed therebetween A second semiconductor chip disposed in the recess, the second electrode and the third electrode are opposed to each other, and the third surface of the frame portion The solder filled inside is sandwiched between and fixed to the bottom surface of the recess.

  Further, in order to solve the above-described problem, an electronic device manufacturing method according to the present invention includes a step of forming a frame portion having a recessed inside on a bottom surface of a concave portion of a wiring board having a wiring pattern and a concave portion on a main surface; A step of filling the inside of the frame with solder, a second surface, a third surface which is a surface behind the second surface, and a second electrode having a third electrode formed on the second surface. Fixing the third surface of the semiconductor chip to the bottom surface of the recess with the solder interposed therebetween.

  According to the electronic device or the manufacturing method of the electronic device according to the present invention, the transmission loss of the signal transmitted between the first semiconductor chip and the second semiconductor chip is reduced, and the mounting area of the semiconductor chip is reduced. can do.

It is a top view of the electronic apparatus 1 which concerns on this embodiment. It is sectional drawing along the II-II line of FIG. It is sectional drawing along the III-III line of FIG. It is sectional drawing of a 1st semiconductor chip. It is a figure which shows the manufacturing process of an electronic device. It is a figure which shows the manufacturing process of an electronic device. It is a figure which shows the manufacturing process of an electronic device. It is a figure which shows the manufacturing process of an electronic device. It is a figure which shows the manufacturing process of an electronic device. It is a top view of the electronic device which concerns on a comparative example. It is sectional drawing along the XI-XI line of FIG.

[Description of Embodiment of Present Invention]
First, the contents of the embodiment of the present invention will be listed and described. (1) An electronic device according to an embodiment includes a wiring substrate having a wiring pattern and a concave portion on a main surface, and a frame portion having a concave inside formed on a bottom surface of the concave portion, a first surface, and a first surface. A flip chip type first semiconductor chip having a first electrode connected to the wiring pattern and a second electrode formed on the first surface; a second surface; A third surface that is the back surface of the second surface, and a third electrode that is formed on the second surface and is connected to the second electrode directly or with the conductive member joint interposed therebetween And the second semiconductor chip disposed in the recess, the second electrode and the third electrode are opposed to each other, and the third surface is filled inside the frame portion It is fixed to the bottom surface of the recess with the solder sandwiched therebetween.

  According to such a configuration, the signal exchanged between the second electrode and the third electrode only passes through only one conductive member joint during that time. Therefore, compared to the conventional mounting structure, the signal transmitted between the first semiconductor chip and the second semiconductor chip is caused by the loss due to the conductive member joint 1 and the transmission line (wiring pattern). Transmission loss can be reduced by the amount of loss. Further, since the second semiconductor chip is disposed in the recess, the center distance (pitch) between the first and second semiconductor chips can be reduced, and the mounting area of the semiconductor chip can be reduced accordingly. it can. Further, since the frame portion is provided in the concave portion of the wiring substrate and the inside of the frame portion is filled with solder, the second semiconductor chip is accurately fixed by the solder, and the second electrode and the third electrode are fixed. Conductive bonding with the electrode can be reliably performed.

  The frame portion may be made of a resist or polyimide.

  Further, the surface of the frame portion may be coated with a resist or polyimide.

  The second semiconductor chip has a fourth electrode formed on the second surface, and is formed on the fourth surface, the fourth surface, facing the fourth electrode, and electrically You may further provide the flip chip type 3rd semiconductor chip which has the 5th electrode connected.

  (2) According to one embodiment of the present invention, there is provided a method of manufacturing an electronic device, the method comprising: forming a frame portion with a recessed inside on a bottom surface of a recess portion of a wiring board having a wiring pattern and a recess portion on a main surface; A second semiconductor chip having a step of filling with solder, a second surface, a third surface that is the back surface of the second surface, and a third electrode formed on the second surface; And fixing the third surface to the bottom surface of the recess with the solder sandwiched therebetween.

  The frame portion may be formed by applying a resist to the bottom surface of the recess and exposing the resist.

  In addition, a first semiconductor chip having a first surface, a second electrode formed on the first surface, and a first electrode formed on the first surface is connected to the second electrode and the third electrode. The first electrode and the wiring pattern are connected to each other, and the second electrode and the third electrode are connected directly or with the conductive member joint interposed therebetween. And a step of connecting to.

[Details of the embodiment of the present invention]
A specific example of an electronic device according to an embodiment of the present invention will be described below with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to the claim are included. In the following description, the same reference numerals are given to the same elements in the description of the drawings, and redundant descriptions are omitted.

  FIG. 1 is a top view of an electronic device 1 according to this embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. FIG. 3 is a cross-sectional view taken along line III-III in FIG. As shown in FIGS. 1 to 3, the electronic device 1 includes a wiring board 2, a first semiconductor chip 20, a second semiconductor chip 30, a third semiconductor chip 40, a connection chip 50, and solder joints 26 a to 26-. 26c, solder joint portions 46a to 46c, and solder joint portions 56a and 56b. Each of the first semiconductor chip 20 and the third semiconductor chip 40 is a flip chip type semiconductor chip, for example, a monolithic microwave integrated circuit (MMIC). The solder joint portions 26c and 46a are conductive member joint portions in the present embodiment. The solder joint portions 26a to 26c, 46a to 46c, 56a and 56b are, for example, solder balls. 2 and 3, illustration of the internal structure of the first semiconductor chip 20, the second semiconductor chip 30, the third semiconductor chip 40, and the connection chip 50 is omitted.

  The wiring board 2 includes a metal plate 8 and an insulating layer 9 provided on the metal plate 8. The surface of the insulating layer 9 opposite to the metal plate 8 constitutes the main surface 3 of the wiring substrate 2, and the surface of the metal plate 8 opposite to the insulating layer 9 constitutes the back surface 4 of the wiring substrate 2. The wiring board 2 has wiring patterns (RF terminals) 27 a and 47 a, GND patterns 27 b and 47 b, a plurality of terminals 57, and a recess 10 on the main surface 3, and via wirings 28 and 48 inside the insulating layer 9. Have. The GND pattern 27 b is electrically connected to the metal plate 8 via the via wiring 28, and the GND pattern 47 b is electrically connected to the metal plate 8 via the via wiring 48. The recess 10 reaches the metal plate 8 from the insulating layer 9, and the bottom surface 11 is constituted by the metal plate 8. The planar shape of the recess 10 viewed from the thickness direction of the wiring board 2 is, for example, a quadrangle. The bottom surface 11 of the recess 10 is formed with a planar quadrangular frame portion 12 that is recessed inside, and the inside of the frame portion 12 is filled with a solder paste 14. The frame portion 12 is made of, for example, a resist or polyimide. Since resist and polyimide repel molten solder, when the second semiconductor chip 30 overlaps the frame portion 12, the second semiconductor chip 30 is disposed inside the frame portion 12 due to a self-alignment effect. . The material of the frame part 12 may be made of, for example, a resist or polyimide, but the surface of the frame part 12 may be coated with, for example, a resist or polyimide. Each of the plurality of terminals 57 may be a power supply terminal, a ground terminal, or an RF terminal. The material of the insulating layer 9 is, for example, a Teflon (registered trademark) or epoxy resin.

  The first semiconductor chip 20 has a first surface 23. A first electrode 24 is formed on a portion of the first surface 23 near one end in the signal traveling direction, and a second portion of the first surface 23 near the other end in the signal traveling direction is the second. The electrode 25 is formed. The first electrode 24 and the wiring pattern 27a face each other, and are electrically connected to each other with the solder joint portion 26a interposed therebetween. The RF signal output from the wiring pattern 27a passes through the solder joint portion 26a, is input to the first electrode 24, and reaches the inside of the first semiconductor chip 20. An RF signal generated inside the first semiconductor chip 20 based on this RF signal is output from the second electrode 25. In addition, a ground electrode is formed at the central portion of the first surface 23. The ground electrode is electrically connected to the GND pattern 27b with the solder joint portion 26b interposed therebetween. In the present embodiment, a plurality of solder joint portions 26b are arranged side by side. 2 and 4, three solder joints 26b are displayed as an example.

  The second semiconductor chip 30 has a second surface 33 and a third surface 32 that is a surface on the back side of the second surface 33. A third electrode 34 is formed on a portion of the second surface 33 near one end in the signal traveling direction, and a fourth electrode is formed on a portion of the second surface 33 near the other end in the signal traveling direction. 35 is formed. The third surface 32 is fixed to the bottom surface 11 of the recess 10 with the solder paste 14 interposed therebetween. The second electrode 25 and the third electrode 34 are opposed to each other, and are electrically connected to each other with the solder joint portion 26c interposed therebetween. The second electrode 25 and the third electrode 34 may be directly connected, or may be connected with a conductive member other than solder interposed therebetween. The RF signal output from the second electrode 25 passes through the solder joint portion 26 c, is input to the third electrode 34, and reaches the inside of the second semiconductor chip 30. Further, the RF signal generated inside the second semiconductor chip 30 based on this RF signal is output from the fourth electrode 35.

  The third semiconductor chip 40 has a fourth surface 43. A fifth electrode 44 is formed on a portion of the fourth surface 43 near one end in the signal traveling direction, and a sixth electrode is formed on the portion of the fourth surface 43 near the other end in the signal traveling direction. The electrode 45 is formed. The fifth electrode 44 and the fourth electrode 35 are opposed to each other, and are electrically connected to each other with the solder joint 46a interposed therebetween. The sixth electrode 45 and the wiring pattern 47a face each other and are electrically connected to each other with the solder joint portion 46c interposed therebetween. The fifth electrode 44 and the fourth electrode 35 may be directly connected, or may be connected with a conductive member other than solder interposed therebetween. The RF signal output from the fourth electrode 35 passes through the solder joint 46 a, is input to the fifth electrode 44, and reaches the inside of the third semiconductor chip 40. Further, the RF signal generated inside the third semiconductor chip 40 based on this RF signal is output from the sixth electrode 45. The signal output from the sixth electrode 45 is input to the wiring pattern 47a. A ground electrode is formed in the central portion of the fourth surface 43. The ground electrode is electrically connected to the GND pattern 47b with the solder joint 46b interposed therebetween. In the present embodiment, a plurality of solder joints 46b are arranged side by side. In FIG. 2, three solder joints 46b are displayed as an example.

  The connection chip 50 is disposed on the main surface 3 so as to cover a part of the second surface 33 of the second semiconductor chip 30. In the present embodiment, two connection chips 50 are provided, and the two connection chips 50 are arranged side by side in a direction that intersects the traveling direction of the RF signal. One terminal of each connection chip 50 and the ground electrode or the like on the second surface 33 are electrically connected to each other with a solder joint 56a (see FIG. 3) interposed therebetween. The other terminal of each connection chip 50 and the plurality of terminals 57 are electrically connected to each other with the solder joint portion 56b interposed therebetween. One terminal and the other terminal of the connection chip 50 are electrically connected to each other inside the connection chip 50.

  FIG. 4 is a cross-sectional view of the first semiconductor chip 20 and the solder joints 26a to 26c. As shown in FIG. 4, the first semiconductor chip 20 includes a semiconductor substrate 21 and an insulating layer 22. A circuit region 21 a including a transistor is formed inside the semiconductor substrate 21. Inside the insulating layer 22, signal wirings 22a and 22b, via wirings 22c and 22d, a via wiring 22f, and a reference layer 22e are provided. The signal wiring 22a is electrically connected to one terminal of the transistor in the circuit region 21a, and the signal wiring 22b is electrically connected to the other terminal of the transistor in the circuit region 21a. The reference layer 22e is a planar layer provided such that a portion near one end faces the signal wiring 22a, a portion near the other end faces the signal wiring 22b, and a central portion faces the circuit region 21a. It is a conductor layer. The reference layer 22e has a ground potential that is a reference potential. The signal wiring 22a is electrically connected to the solder joint portion 26a through the via wiring 22c. The end of the via wiring 22c on the solder joint portion 26a side constitutes the first electrode 24. The signal wiring 22b is electrically connected to the solder joint portion 26c through the via wiring 22d. The end of the via wiring 22d on the solder joint portion 26c side constitutes the second electrode 25. The reference layer 22e is electrically connected to the solder joint portion 26b through the via wiring 22f. The second semiconductor chip 30 and the third semiconductor chip 40 have the same structure as the first semiconductor chip 20.

  Next, a method for manufacturing the electronic device 1 will be described. 5 to 9 are diagrams showing the manufacturing process of the electronic device 1. 5A to FIG. 7 and FIG. 9 are top views of the electronic device 1 being generated, and FIG. 5B to FIG. 9B are being generated. It is sectional drawing of the electronic device 1 of. First, as shown in FIGS. 5A and 5B, the recess 10 is formed in the main surface 3 of the wiring board 2 having the metal plate 8 and the insulating layer 9. At this time, for example, the recess 10 is formed by cutting. Next, a resist is applied to the bottom surface 11 of the recess 10. Then, the coated resist is processed (exposure / development) to form a frame portion 12 made of resist and having a recess 13 inside. The planar shape and size of the recess 13 are the same as the planar shape and size of the third surface 32 of the second semiconductor chip 30. Next, as shown in FIGS. 6A and 6B, the solder paste 14 is filled inside the frame portion 12. Next, as shown in FIGS. 7A and 7B, the second semiconductor chip 30 is disposed on the solder paste 14 so that the third surface 32 faces the bottom surface 11 of the recess 10. . At this time, the orientation of the second semiconductor chip 30 may be shifted as shown in FIG. However, by continuously performing reflow, the orientation of the second semiconductor chip 30 is automatically corrected along the shape of the recess 13 as shown in FIG. 7A and FIG. Self-aligned). Next, after applying flux to the solder joint portions 26a to 26c of the first semiconductor chip 20 with the solder joint portions 26a to 26c, as shown in FIG. 9A and FIG. The semiconductor chip 20 is arranged over the second semiconductor chip 30 from the periphery of the recess 10 of the wiring board 2. At this time, the first semiconductor chip 20 is connected so that the solder joint portion 26a is connected to the wiring pattern 27a, the solder joint portion 26c is connected to the third electrode 34, and the solder joint portion 26b is connected to the GND pattern 27b. Deploy. Next, the first semiconductor chip 20 is fixed on the wiring substrate 2 and the second semiconductor chip 30 by performing reflow for the second time. The electronic device 1 is completed by performing the above-described steps for the third semiconductor chip 40 in the same manner.

(Function and effect)
FIG. 10 shows an electronic device 70 according to a comparative example. FIG. 11 is a cross-sectional view taken along line XI-XI of the electronic device 70 shown in FIG. As shown in FIGS. 10 and 11, in the electronic device 70 according to the comparative example, unlike the present embodiment, no recess is formed in the wiring board 72, and all the semiconductor chips 80 are arranged on the wiring board 72. Has been placed. As shown in FIGS. 10 and 11, the electronic device 70 includes a wiring board 72, three semiconductor chips 80 </ b> A to 80 </ b> C, and solder joints 86 a to 86 c. The semiconductor chips 80A to 80C have the same structure as the first semiconductor chip 20 (see FIG. 4).

  The wiring board 72 includes a metal plate 78 and an insulating layer 79 provided on the metal plate 78. The surface of the insulating layer 79 opposite to the metal plate 78 constitutes the main surface 73 of the wiring substrate 72, and the surface of the metal plate 78 opposite to the insulating layer 79 constitutes the back surface 74 of the wiring substrate 72. The wiring board 72 has wiring patterns 87 A to 87 D and GND patterns 89 A to 89 C on the main surface 73, and via wirings 88 A to 88 C inside the insulating layer 79. The GND patterns 89A to 89C are electrically connected to the metal plate 78 via the via wirings 88A to 88C, respectively. In the electronic device 70, the wiring patterns 87 </ b> A to 87 </ b> D and the GND patterns 89 </ b> A to 89 </ b> C are alternately arranged on the main surface 73.

  The semiconductor chips 80 </ b> A to 80 </ b> C have a first surface 83. A first electrode 84 is formed on a portion of the first surface 83 near one end in the signal traveling direction, and a second electrode on the first surface 83 is disposed near the other end in the signal traveling direction. The electrode 85 is formed. The first electrode 84 of each of the semiconductor chips 80A to 80C and one end of each of the wiring patterns 87A to 87C are opposed to each other, and are electrically connected to each other with the solder joint 86a interposed therebetween. The second electrode 85 of each of the semiconductor chips 80A to 80C and the other end of each of the wiring patterns 87B to 87D are opposed to each other, and are electrically connected to each other with the solder joint 86c interposed therebetween. . The RF signal output from each of the wiring patterns 87A to 87C is input to the first electrode 84 of each of the semiconductor chips 80A to 80C and reaches the inside of each of the semiconductor chips 80A to 80C. Further, the RF signal generated inside each of the semiconductor chips 80A to 80C based on the RF signal is output from the second electrode 85 and input to the wiring patterns 87B to 87D. In addition, the ground electrode provided in the central portion of the first surface 83 of each of the semiconductor chips 80A to 80C is electrically connected to the GND patterns 89A to 89C with the solder joint portion 86b interposed therebetween.

  In the electronic device 70 according to the comparative example, the RF signal output from the second electrode 85 of the semiconductor chip 80A or 80B passes through the solder joint 86c, the wiring pattern 87B or 87C, and the solder joint 86a, respectively. , Input to the first electrode 84 of the semiconductor chip 80B or 80C. Therefore, in the electronic device 70, transmission loss occurs in each of the solder joint portion 86c, the wiring pattern 87B or 87C, and the solder joint portion 86a through which the RF signal passes. Further, the distance between adjacent semiconductor chips (for example, semiconductor chips 80A and 80B) cannot be made smaller than the distance at which their side surfaces contact each other, which hinders the reduction of the mounting area of the semiconductor chips 80A to 80C.

  On the other hand, according to the electronic apparatus 1 according to the present embodiment, the RF signal output from the second electrode 25 passes through the solder joint portion 26 c and is input to the third electrode 34. The RF signal output from the fourth electrode 35 passes through the solder joint 46 a and is input to the fifth electrode 44. Therefore, when the RF signal is transmitted between the semiconductor chips, it passes only through one solder joint, and compared with the electronic device 70 according to the comparative example, the loss due to one solder joint and the wiring pattern Transmission loss can be reduced by the amount of loss at one location. In addition, since the second semiconductor chip 30 is disposed in the recess 10, the center interval (pitch) between the first semiconductor chip 20, the third semiconductor chip 40 and the second semiconductor chip 30 can be reduced. Thus, the mounting area of the semiconductor chip can be reduced accordingly. Therefore, a compact mounting of the semiconductor chip is possible.

  As a method for fixing the second semiconductor chip 30 to the bottom surface 11 of the recess 10, a method in which the frame portion 12 is not formed can be considered. That is, the third surface 32 of the second semiconductor chip 30 having the solder barrier structure electrode is fixed to the bottom surface 11 of the recess 10 without forming the frame portion 12, and then the first with the solder joint portion. A method in which a flux is applied to a solder joint provided on the first surface 23 of the semiconductor chip 20, the first semiconductor chip 20 is disposed on the wiring pattern 27a and the second semiconductor chip 30, and solder reflow is performed. is there. At this time, the gap is fixed with an underfill material or the like as necessary. However, according to such a process, when the second semiconductor chip 30 is fixed, a technique for fixing the second semiconductor chip 30 with high accuracy in the vertical direction and the horizontal direction is required. In this regard, according to the electronic device 1 or the method for manufacturing the electronic device 1 according to the present embodiment, the solder paste 14 is filled inside the frame portion 12 provided in the concave portion 10 of the wiring board 2, so that the vertical direction and The second semiconductor chip 30 can be fixed with high precision in the horizontal direction.

  The electronic device and the method for manufacturing the electronic device according to the present invention are not limited to the above-described embodiments, and various other modifications are possible. For example, the first and second semiconductor chips illustrated in the above embodiment have circuit regions including transistors, but the first and second semiconductor chips of the present invention have various circuits other than this. Can do.

DESCRIPTION OF SYMBOLS 1 ... Electronic device, 2 ... Wiring board, 10 ... Recessed part, 12 ... Frame part, 14 ... Solder paste, 20 ... 1st semiconductor chip, 25 ... 2nd electrode, 26c ... Solder junction part, 30 ... 2nd Semiconductor chip 34 ... third electrode 35 ... fourth electrode 40 ... third semiconductor chip 44 ... fifth electrode 46a ... solder joint.

Claims (7)

A wiring board having a wiring pattern and a concave portion on the main surface, and a frame portion with a concave inside formed on the bottom surface of the concave portion;
A flip chip type having a first surface, a first electrode formed on the first surface and connected to the wiring pattern, and a second electrode formed on the first surface A first semiconductor chip;
Formed on the second surface, the third surface that is the back surface of the second surface, and the second surface, with the second electrode directly or with a conductive member joint interposed therebetween A second semiconductor chip having a third electrode connected and disposed in the recess,
The second electrode and the third electrode are opposed to each other, and the third surface is fixed to the bottom surface of the recess with a solder filled inside the frame portion interposed therebetween. An electronic device.   The electronic device according to claim 1, wherein the frame portion is made of resist or polyimide.   The electronic device according to claim 1, wherein a surface of the frame portion is coated with a resist or polyimide. The second semiconductor chip has a fourth electrode formed on the second surface,
A flip chip type third semiconductor chip having a fourth surface, a fifth electrode formed on the fourth surface, facing the fourth electrode, and electrically connected; The electronic device according to claim 1. A step of forming a frame portion having a concave inside on the bottom surface of the recess of the wiring board having a wiring pattern and a recess on a main surface;
Filling the inside of the frame with solder;
A second surface, a third surface that is the back surface of the second surface, and the third surface of the second semiconductor chip having a third electrode formed on the second surface; And a step of fixing the solder to the bottom surface of the recess, with the solder interposed therebetween.   The method of manufacturing an electronic device according to claim 5, wherein the frame portion is formed by applying a resist to a bottom surface of the concave portion and exposing the resist. A first semiconductor chip having a first surface, a second electrode formed on the first surface, and a first electrode formed on the first surface; The third electrode is disposed so as to face each other, the first electrode and the wiring pattern are connected to each other, and the second electrode and the third electrode are directly or electrically conductive member joined portion. The method for manufacturing an electronic device according to claim 5, further comprising a step of connecting each other with a gap therebetween.

Images