JP2015230922A - Manufacturing method of chip resistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a chip resistor which improves sulfur resistance and also improves resistance value precision.SOLUTION: An aggregate substrate 10 is divided into a number of chip regions S1 and sub regions S2 by primary dividing grooves 11 and secondary dividing grooves 12 extending in a lattice shape. A pair of front electrodes 3 which confront each other while interposing a predetermined interval therebetween, a resistor 6 spread over the pair of front electrodes 3, a first insulation layer 7 covering the resistor 6 and the like are formed in the chip region S1. The front electrode 3 connected with the resistor 6 is formed from an electrode material of high specific resistance containing Pd or the like with sulfur resistance, an extending portion 3a is formed by projecting the front electrode 3 to the sub region S2 neighboring to the chip region S1 over the primary dividing groove 11. An auxiliary electrode 14 of low specific resistance containing Ag as a main component is formed on the extending portion 3a, a probe is brought into contact with paired auxiliary electrodes 14, and a resistance value of the resistor 6 is measured.

Description

  The present invention relates to a method of manufacturing a surface mount type chip resistor.

  The chip resistor is disposed to face the rectangular parallelepiped insulating substrate, a pair of front electrodes opposed to the surface of the insulating substrate with a predetermined interval, and the back surface of the insulating substrate with a predetermined interval. A pair of back electrodes, an end face electrode that bridges the front electrode and the back electrode, a resistor that bridges the pair of front electrodes, and a first insulating layer and a second insulating layer that cover the resistor. It is configured.

  In general, when manufacturing such a chip resistor, after forming a large number of electrodes, resistors, insulating layers, etc. on a large aggregate substrate at once, the aggregate substrate is divided into a grid pattern. A plurality of chip resistors are taken along a line (for example, a dividing groove). In the manufacturing process of such a chip resistor, a large number of resistors are printed and formed in a predetermined arrangement on one side of the collective substrate, but due to the influence of positional deviation and bleeding during printing, temperature unevenness in the firing furnace, etc. Since it is difficult to avoid slight variations in the size and film thickness of each resistor, a resistance value adjustment operation is performed in which trimming grooves are formed in each resistor in the state of the aggregate substrate and set to a desired resistance value. .

  In this resistance value adjustment operation, a probe is brought into contact with a pair of surface electrodes that are bridged by a resistor, and the resistance value is measured, and the resistor is irradiated with laser light to form a trimming groove. Since the resistance value increases as the trimming groove is lengthened, when the resistance value of the resistor to be trimmed reaches the target resistance value, the irradiation of laser light is stopped and the resistance value is reached. The adjustment work is finished.

  Here, if the contact position of the probe with respect to the surface electrode varies, the distance of the surface electrode from the contact position of the probe to the resistor fluctuates, so that the specific resistance of the surface electrode greatly affects the resistance value accuracy of the resistor. Thus, when the surface electrode is formed of a silver-based material mainly composed of silver having a low specific resistance, the resistance value can be accurately measured regardless of variations in the contact position of the probe. However, when a surface electrode made of a silver-based material is used in an environment where a large amount of sulfur gas exists, silver and sulfide gas react to generate silver sulfide, causing problems such as poor conduction and disconnection. is there.

  As a countermeasure against such a problem, Patent Document 1 discloses that the surface electrode is changed to an electrode material (for example, Ag—Pd—Au) containing sulfide-resistant palladium or the like, thereby progressing the sulfidation of the surface electrode. A chip resistor that suppresses the above is disclosed. Further, in Patent Document 2, a surface electrode has a two-layer structure of a lower electrode layer and an upper electrode layer, a lower electrode layer as a lower layer is formed of a silver-based material, and a silver-based material containing palladium as an upper upper electrode layer. A chip resistor is disclosed that is formed of a material to suppress sulfidation of the lower electrode layer at the upper electrode layer.

JP 2008-300607 A JP 2002-64003 A

  However, when the surface electrode is formed of an electrode material containing sulfide-resistant palladium or the like as in the conventional example disclosed in Patent Document 1, the specific resistance of the surface electrode is increased. As the contact position of the electrode fluctuates, the measured value of the resistor varies, making it difficult to measure the resistance value with high accuracy. Further, as in the conventional example disclosed in Patent Document 2, when the front electrode has a two-layer structure of an Ag-based lower electrode layer and an Ag / Pd upper electrode layer, the surface electrode is represented by a silver-based material of the lower electrode layer. Although the specific resistance of the electrode is reduced, there is a problem that the silver of the lower electrode layer diffuses into the resistor during firing of the electrode material, resulting in a chip resistor with poor TCR characteristics. Moreover, since the silver of the lower electrode layer diffuses not only in the resistor but also in the upper electrode layer when the electrode material is baked, it is necessary to use more expensive palladium having sulfur resistance in the upper electrode layer. There is also a problem that the product cost rises accordingly.

  The present invention has been made in view of the above-described prior art, and an object of the present invention is to provide a method of manufacturing a chip resistor that has excellent resistance to sulfidation and high resistance value accuracy.

  In order to achieve the above object, a method for manufacturing a chip resistor according to the present invention provides a collective substrate having a plurality of chip regions partitioned by a grid-like dividing line, and a predetermined region is provided in the chip region of the collective substrate. A step of forming a pair of front electrodes facing each other with a gap, a step of forming a resistor straddling the pair of surface electrodes, a step of forming an insulating protective layer covering the upper surface of the resistor, A step of adjusting a resistance value by forming a trimming groove in a part of the resistor and the protective layer, and the surface electrode is made of an electrode material containing silver as a main component and containing at least palladium. The auxiliary electrode made of an electrode material containing silver as a main component is provided on the surface electrode of the extended portion and extends to the outside of the chip region beyond the dividing line, and the auxiliary electrode forming a pair is probed The And to measure the resistance value of the resistor by touch.

  In the manufacturing method of the chip resistor according to the present invention, the surface electrode connected to the resistor is made of an electrode material having a high specific resistance containing palladium or the like having resistance to sulfidation. Since the auxiliary electrode consisting mainly of silver and having a low specific resistance is formed on the protruding part that protrudes outward, even if the contact position of the probe with respect to the auxiliary electrode varies, the variation is the accuracy of resistance measurement. The resistance value can be measured stably. In addition, the portion where the auxiliary electrode is formed does not exist in the chip region that is the product, and the portion that is the product is a surface electrode containing palladium or the like having excellent sulfidation resistance. There is no risk of silver diffusing into the resistor to deteriorate the TCR characteristics, or silver at the auxiliary electrode diffusing into the surface electrode to deteriorate the sulfidation characteristics. can do.

  In the method of manufacturing a chip resistor according to the present invention, the surface electrode connected to the resistor is made of an electrode material containing sulfur-resistant palladium or the like, and protrudes outward from the chip region beyond the dividing line of the surface electrode. An auxiliary electrode mainly composed of silver and having a low specific resistance is formed on the extending portion to partially form a two-layer structure, and a probe is brought into contact with the auxiliary electrode to measure the resistance value of the resistor. Therefore, stable resistance value measurement can be performed regardless of variations in the contact position of the probe, and deterioration of TCR characteristics and sulfuration resistance characteristics can be prevented.

It is sectional drawing of the chip resistor which concerns on the example embodiment of this invention. It is a top view of the collective board used in the manufacture process of this chip resistor. FIG. 3 is a process view in plan view showing a state where a surface electrode is formed on the collective substrate of FIG. 2. It is process drawing of planar view which shows the state which formed the auxiliary electrode in the surface electrode of FIG. It is process drawing of planar view which shows the state in which the resistor was formed in this aggregate substrate. It is process drawing of planar view which shows the state which formed the trimming groove | channel in the resistor of FIG. It is process drawing of the cross sectional view which shows the contact state of the probe used at the time of formation of this trimming groove | channel.

  Hereinafter, embodiments of the invention will be described with reference to the drawings. As shown in FIG. 1, a chip resistor 1 according to an embodiment of the present invention includes a rectangular parallelepiped insulating substrate 2 and an insulating substrate 2. A pair of front electrodes 3 provided at both ends in the longitudinal direction on the upper surface of the substrate, a pair of back electrodes 4 provided at both ends in the longitudinal direction on the lower surface of the insulating substrate 2, and provided on the side surfaces of the insulating substrate 2. And a pair of end face electrodes 5 that bridge the corresponding front electrode 3 and back electrode 4 and a resistance that is provided on the upper surface of the insulating substrate 2 and bridges the front electrodes 3 on both sides in the longitudinal direction. Body 6, first insulating layer 7 covering resistor 6, second insulating layer 8 covering first insulating layer 7, plating layer 9 covering front electrode 3, back electrode 4 and end surface electrode 5, It is mainly composed by.

  The insulating substrate 2 is made of ceramics or the like, and the insulating substrate 2 is divided into individual pieces by dividing a large-sized collective substrate (see FIG. 2) described later along vertical and horizontal dividing grooves.

  The front electrode 3 is located immediately below the boundary portion between the second insulating layer 8 and the plating layer 9 and is affected by the sulfur gas entering from the boundary portion, and therefore has resistance to sulfur with Ag (silver) as a main component. It consists of an electrode material containing 15 to 25 wt% Pd (palladium) and 1 to 20 wt% Au (gold). On the other hand, the back electrode 4 is an electrode on the mounting side and is not affected by the sulfide gas. Therefore, the back electrode 4 is made of an Ag-based electrode material that does not contain Pd or Au, or an Ag-Pd-based electrode material that has a low Pd content. Become.

  The front electrode 3, the end face electrode 5, and the back electrode 4 are formed at both ends in the longitudinal direction of the insulating substrate 2 as base electrode layers that are substantially U-shaped, and a plating layer 9 is attached to the base electrode layer. Thus, the electrode part of the chip resistor 1 is formed. The front electrode 3 and the back electrode 4 are collectively formed on the collective substrate, while the end face electrode 5 is formed on a split surface of a strip-shaped substrate obtained by primarily dividing the collective substrate. The plating layer 9 includes two or more layers including an innermost Ni plating layer that is in close contact with the base electrode layer and an outermost solder plating layer (Sn / Pb plating layer or Sn plating layer) exposed on the outer surface. It has a laminated structure.

  The resistor 6 is made of ruthenium oxide or the like, and the resistance value of the chip resistor 1 is adjusted by forming a trimming groove in the resistor 6 and the first insulating layer 7 as will be described in detail later.

  The first insulating layer 7 and the second insulating layer 8 constitute a protective layer having a two-layer structure, of which the first insulating layer 7 is an undercoat layer that covers the resistor 6 before the trimming groove is formed. The layer 8 is an overcoat layer that covers the first insulating layer 7 after the trimming grooves are formed.

  Next, a manufacturing method of the chip resistor 1 configured as described above will be described with reference to FIGS.

  First, as shown in FIG. 2, a collective substrate 10 is prepared in which primary divided grooves 11 and secondary divided grooves 12 extending in a lattice shape in the vertical and horizontal directions are formed. By these primary division grooves 11 and secondary division grooves 12, the front and back surfaces of the collective substrate 10 are partitioned into a large number of chip areas S1 and sub areas S2. Each chip region S1 corresponds to a planar shape (upper surface or lower surface) of one chip resistor 1, and each sub-region S2 is a portion that is discarded after the aggregate substrate 10 is primarily divided along the primary division grooves 11. . Chip regions S1 and sub-regions S2 are alternately arranged on the front and back surfaces of the collective substrate 10 along the extending direction of the secondary dividing grooves 12, and the rows of the chip regions S1 and the sub-regions S2 are arranged in the primary dividing grooves 11. Many are arranged along the extending direction.

  Then, an electrode paste is screen-printed at a position crossing the primary dividing groove 11 on the surface of the collective substrate 10 and baked to form an electrode pattern 13 having a predetermined size as shown in FIG. This electrode paste is mainly composed of Ag (silver), Pd (palladium) is contained in an amount of 15 to 25 wt%, Au (gold) is contained in an amount of 1 to 20 wt%, and the balance is Ag—Pd—Au composed of a metal component of Ag. Of the electrode pattern 13 formed using such an electrode paste, a portion existing in the chip region S1 corresponds to the front electrode 3, and a portion existing in the sub-region S2 becomes an extended portion 3a. ing. That is, by forming the electrode pattern 13, the surface electrode 3 is formed at both ends in the longitudinal direction of the chip region S1, and the surface electrode 3 extends beyond the primary dividing groove 11 to project into the sub region S2. It is part 3a.

  Although not shown, a plurality of pairs of back electrodes 4 are formed on the back surface of the collective substrate 10 so as to straddle the primary dividing grooves 11 before and after the electrode pattern 13 forming step. Since the back electrode 4 is an electrode on the mounting side, the back electrode 4 is formed by screen-printing and baking an Ag-based paste or an Ag-Pd paste having a low Pd content.

  As a next step, on the extended portion 3a existing in the sub-region S2, by printing and baking Ag-Pd paste having a low content of Ag-based paste or Pd, as shown in FIG. An auxiliary electrode 14 having a low specific resistance is formed on the extended portion 3 a of the electrode pattern 13.

  As a next step, a resistor paste containing ruthenium oxide or the like is screen printed on the surface of the collective substrate 10 and baked, so that both end portions in the longitudinal direction in the chip region S1 are surface electrodes as shown in FIG. 3 is formed in a lump. In this step, the surface electrodes 3 paired in each chip region S1 are bridged by the resistor 6.

  As a next step, the first insulating layer 7 that covers the resistor 6 in the chip region S1 as shown in FIG. 6 is obtained by screen-printing and baking a glass paste in a region that covers each resistor 6 individually. Are collectively formed.

  As a next step, in order to adjust the resistance value of each resistor 6, a number of resistors 6 covered by the first insulating layer 7 are sequentially irradiated with laser light to form trimming grooves 15. To do. At that time, as shown in FIG. 7, the probes 16 are brought into contact with the auxiliary electrodes 14 in the pair of sub-regions S2 facing each other with the chip region S1 interposed therebetween, and the resistor 6 to be trimmed is connected via these probes 16. Measure the resistance value.

  Here, the surface electrode 3 connected to the resistor 6 is made of an electrode material having a high specific resistance containing Pd or the like having sulfur resistance, but protrudes beyond the primary division groove 11 of the surface electrode 3 to the sub-region S2. Since the auxiliary electrode 14 mainly composed of Ag and having a low specific resistance is formed on the extending portion 3a, even if the contact position of the probe 16 with respect to the auxiliary electrode 14 varies, the variation is not measured in the resistance value measurement. The accuracy is hardly affected, and stable resistance measurement can be performed.

  Although not shown in the drawings, as the next step, primary division is performed by screen printing an epoxy resin paste so as to cover the first insulating layer 7, the resistor 6, the trimming groove 15, and the like, followed by heat curing. A second insulating layer 8 extending in a strip shape along the extending direction of the groove 11 is formed. The first insulating layer 7 described above is for preventing the vicinity of the trimming groove 15 of the resistor 6 from being damaged by the heat of the laser beam, and the second insulating layer 8 protects the resistor 6 from the external environment. Is to do.

  The process so far is batch processing for the collective substrate 10. In the next process, the collective substrate 10 is primarily divided into strips along the primary division grooves 11, so that the longitudinal direction of the chip region S1 is defined as the width dimension. A strip-shaped substrate (not shown) is obtained. In this step, since the electrode pattern 13 is divided into the surface electrode 3 and the extended portion 3a by the primary dividing groove 11, the strip-shaped substrate has the surface electrode 3 having excellent resistance to sulfidation and a high specific resistance remaining. The sub-region S2 in which the 13 extended portions 3a and the auxiliary electrode 14 remain is discarded as a discarded substrate.

  Then, in the next step, Ni / Cr or the like is sputtered onto the split surface of the strip-shaped substrate, thereby forming the end face electrode 5 that bridges the front electrode 3 and the back electrode 4. Thereafter, the strip-shaped substrate is secondarily divided along the second divided grooves 12 to obtain individual pieces (chip alone) having the same size as the chip resistor 1.

  Finally, Ni plating or solder plating is applied to the base electrode layer (the front electrode 3, the back electrode 4, and the end face electrode 5) of each single chip to form a plating layer 9 having a laminated structure that covers the base electrode layer. Thereby, the chip resistor 1 as shown in FIG. 1 is completed.

  As described above, in the method for manufacturing the chip resistor 1 according to this embodiment, the surface electrode 3 connected to the resistor 6 includes an electrode material having a high specific resistance containing Pd (palladium) having sulfur resistance. The surface electrode 3 is projected beyond the primary dividing groove 11 to a sub-region S2 adjacent to the chip region S1 to form an extended portion 3a, and Ag (silver) is a main component on the extended portion 3a. Since the auxiliary electrode 14 having a low specific resistance is formed, even if the contact position of the probe 16 with respect to the auxiliary electrode 14 varies, the variation hardly affects the accuracy of the resistance value measurement and is stable. Resistance value measurement can be performed. In addition, the sub-region S2 of the collective substrate 10 on which the auxiliary electrode 14 is formed is a portion that is discarded instead of being a product, and what is formed in the chip region S1 that is a product is Pd or the like having excellent resistance to sulfidation. Since the surface electrode 3 is contained, the silver of the auxiliary electrode 14 diffuses into the resistor 6 to deteriorate the TCR characteristic, or the silver of the auxiliary electrode 14 diffuses into the surface electrode 3 to deteriorate the sulfurization characteristic. There is no fear that the chip resistor 1 is excellent in sulfuration resistance.

  In the above embodiment, the grid-like dividing grooves 11 and 12 are engraved on the collective substrate 10 in advance to divide the chip area S1 and the sub-areas S2, but the grid-like grid line set as a virtual line is used. The chip area S1 and the sub area S2 may be partitioned by a dividing line, and the collective substrate 10 may be cut by dicing, laser light, or the like along the dividing line.

DESCRIPTION OF SYMBOLS 1 Chip resistor 2 Insulating substrate 3 Front electrode 3a Extension part 4 Back electrode 5 End surface electrode 6 Resistor 7 1st insulating layer 8 2nd insulating layer 9 Plating layer 10 Aggregate substrate 11 Primary divided groove 12 Secondary divided groove 13 Electrode pattern 14 Auxiliary electrode 15 Trimming groove 16 Probe S1 Tip area S2 Sub area

Claims (1)

Preparing an aggregate substrate having a plurality of chip regions partitioned by a grid-like dividing line, and forming a pair of front electrodes facing each other at a predetermined interval in the chip region of the aggregate substrate; Forming a resistor straddling the surface electrode, forming an insulating protective layer covering the upper surface of the resistor, and forming a trimming groove in a part of the resistor and the protective layer to provide a resistance value And a process of adjusting
The surface electrode is made of an electrode material containing silver as a main component and containing at least palladium. The surface electrode extends beyond the dividing line to the outside of the chip region, and on the surface electrode of the extended portion. Provide an auxiliary electrode made of an electrode material mainly composed of silver,
A chip resistor manufacturing method, wherein a probe is brought into contact with the pair of auxiliary electrodes to measure a resistance value of the resistor.