JP2015115928A - Delay locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay locked loop circuit capable of appropriately setting a DC operation point of a voltage control delay line under all frequency conditions and all PVT conditions of an input clock.SOLUTION: A delay locked loop circuit comprising a voltage control delay line for outputting, according to control voltage, an output clock which is in phase synchronization with an input clock and is delayed from the input clock by time corresponding to one period comprises: a load connection unit which connects output loads whose magnitude are the same with corresponding output clocks respectively or does not connect the output loads with corresponding output clocks respectively; and a connection control unit which outputs a connection control signal in an active state, when the control voltage is larger than preset reference voltage after a lapse of time equal to or larger than time corresponding to lock time. The load connection unit connects the output loads with the corresponding output clocks respectively, when the connection control signal is in the active state.

Description

  The present invention relates to a delay-locked loop circuit (DLL) that includes a voltage-controlled delay line that is phase-synchronized with an input clock in accordance with a control voltage and outputs an output clock delayed by a time corresponding to one period with respect to the input clock Circuit).

As a typical DLL circuit, there is a configuration disclosed in Non-Patent Document 1.
FIG. 4 is a block diagram illustrating an example of the configuration of the DLL circuit disclosed in Non-Patent Document 1. The DLL circuit 10 shown in FIG. 1 includes a phase comparator (PD) 12, a charge pump (CP) 14, a loop filter (LF) 16, and a voltage control delay line (VCDL) 18.

  In the DLL circuit 10, the phase comparator 12 detects the phase difference between the input clock CLKIN and the feedback clock FBCLK output from the voltage control delay line 18, and the up signal ( U) and a down signal (D) are output.

As a result, when the phase of the feedback clock FBCLK is earlier than the phase of the input clock CLKIN, the capacitive element constituting the loop filter 16 is discharged by the charge pump 14 according to the down signal, and the control voltage VCONT is lowered.
On the other hand, when the phase of the feedback clock FBCLK is later than the phase of the input clock CLKIN, the above-described capacitive element is charged up by the charge pump 16 according to the up signal, and the control voltage VCONT is raised.

  Subsequently, an output clock CLKOUT delayed by a delay time corresponding to the control voltage VCONT is output from the voltage control delay line 18 with respect to the input clock CLKIN. The output clock CLKOUT has a shorter delay time when the control voltage VCONT decreases, and a longer delay time when the control voltage VCONT increases. The output clock CLKOUT is fed back to the phase comparator 12 as the feedback clock FBCLK.

  Thereafter, in the same manner, the phase difference between the input clock CLKIN and the feedback clock FBCLK whose delay time has been changed is detected, and the control voltage VCONT changes accordingly and the delay time of the feedback clock FBCLK is changed. By being repeatedly performed, the phase between the input clock CLKIN and the feedback clock FBCLK is locked. As a result, the voltage control delay line 18 outputs an output clock CLKOUT that is phase-synchronized with the input clock CLKIN and delayed by a time corresponding to one period with respect to the input clock.

  Next, the voltage control delay line 18 will be described.

  FIG. 5 is a circuit diagram illustrating an example of the configuration of the voltage control delay line illustrated in FIG. The voltage control delay line 18 shown in FIG. 1 includes a plurality of stages of delay cells (differential inverters) 22 connected in series, a replica circuit 24 of the delay cells 22, and an amplifier 26.

  The delay cell 22 in the first stage has inputs of four PMOS (P-type MOS transistors) 28, 30, 32, and 34 serving as load resistors, and an input clock CLKIN_P and an inverted input clock CLKIN_N (hereinafter collectively referred to as an input clock CLKIN). Are composed of two NMOSs (N-type MOS transistors) 36 and 38 and an NMOS 40 serving as a tail current source.

The two PMOSs 28 and 30 are connected in parallel between the power supply VDD and the internal node A. Similarly, the two PMOSs 32 and 34 are connected in parallel between the power supply VDD and the internal node B. . The gate of the PMOS 28 is connected to the drain of the PMOS 28, and the gate of the PMOS 34 is connected to the drain of the PMOS 34. A control voltage VCONT is input to the gates of the PMOSs 30 and 32.
The NMOS 36 is connected between the internal node A and the internal node C, and the input clock CLKIN_P is input to its gate. Similarly, the NMOS 38 is connected between the internal node B and the internal node C, and the inverted input clock CLKIN_N is input to its gate.
The NMOS 40 is connected between the internal node C and the ground GND, and the output signal of the amplifier 26 is input to its gate.
The output clock CLKOUT_P_1 is output from the internal node A, and the inverted output clock CLKOUT_N_1 is output from the internal node B.

  Instead of the input clock CLKIN_P and the inverted input clock CLKIN_N of the first-stage delay cell 22, the second-stage delay cell 22 has an output clock CLKOUT_P_1 and an inverted output clock CLKOUT_N_1 (hereinafter collectively referred to as an output clock CLKOUT). Except that the output clock CLKOUT_P_2 and the inverted output clock CLKOUT_N_2 are output instead of the output clock CLKOUT_P_1 and the inverted output clock CLKOUT_N_1, and the delay cell 22 of the first stage (previous stage) has the same configuration. . The same applies to the delay cells 22 in the third and subsequent stages.

  The replica circuit 24 includes two PMOSs 42 and 44 corresponding to the two PMOSs 28 and 30 as load resistors, an NMOS 46 corresponding to the NMOS 36 for inputting the input clock CLKIN_P, and an NMOS 48 corresponding to the NMOS 40 as the tail current source. ing.

The two PMOSs 42 and 44 are connected in parallel between the power supply VDD and the internal node A ′ corresponding to the internal node A. The gate of the PMOS 42 is connected to the drain of the PMOS 42, and the control voltage VCONT is input to the gate of the PMOS 44.
The NMOS 46 is connected between the internal node A ′ and an internal node C ′ corresponding to the internal node C, and its gate is connected to the power supply VDD.
The NMOS 48 is connected between the internal node C ′ and the ground GND, and the output signal of the amplifier 26 is input to its gate.

  The control voltage VCONT is input to the input terminal + of the amplifier 26, and the signal of the internal node A 'is input to the input terminal-.

  In the voltage control delay line 18, the amplifier 26 outputs an output signal for controlling the amount of current flowing through the NMOS 48 so that the control voltage VCONT is equal to the voltage of the signal at the internal node A ′.

The two PMOSs 42 and 44 of the replica circuit 24 change in load resistance (ON resistance) according to the control voltage VCONT.
In the replica circuit 24, the ON state of the NMOS 48 is controlled according to the output signal of the amplifier 26, and the two PMOSs 42 and 44 of the load resistance, the NMOS 46 of the ON state, and the NMOS 48 whose ON state is controlled are supplied from the power supply VDD. The amount of current flowing through the ground GND changes, and the voltage of the signal at the internal node A ′ is controlled to be a voltage corresponding to the control voltage VCONT.

  The delay cell 22 has the same configuration as that of the replica circuit 24, and the output signal of the amplifier 26 input to the gate of the NMOS 48 of the replica circuit 24 is input to the gate of the NMOS 40. Therefore, the delay cell 22 operates in the same manner as the replica circuit 24 and is controlled so that the signal of the internal node on the drain side of the NMOS of the two NMOSs 36 and 38 becomes the control voltage VCONT.

In the delay cell 22 at the first stage, when the input clock CLKIN_P changes from L (low level) to H (high level), that is, when the inverted input clock CLKIN_N changes from H to L, the NMOS 36 changes from the OFF state to the ON state, and the NMOS 38 changes from the ON state. The output clock CLKOUT_P_1 changes from H to L, and the inverted output clock CLKOUT_N_1 changes from L to H.
On the other hand, when the input clock CLKIN_P changes from H to L, that is, when the inverted input clock CLKIN_N changes from L to H, the above operation is reversed.
At this time, the output clock CLKOUT_P_1 and the inverted output clock CLKOUT_N_1 are changed with respect to the input clock CLKIN_P and the inverted input clock CLKIN_N according to the control voltage VCONT, the load resistances of the PMOSs 28, 30, 32, and 34, and the output clocks CLKOUT_P_1 and Delayed by a delay time t corresponding to the output load of the inverted output clock CLKOUT_N_1.

The delay cells 22 after the second stage operate similarly. Therefore, the output clock CLKOUT output from the second-stage delay cell 22 is delayed by the delay time t with respect to the output clock CLKOUT of the first-stage delay cell 22. That is, the output clock CLKOUT_P_2 and the inverted output clock CLKOUT_N_2 are delayed by the delay time 2t with respect to the input clock CLKIN. The same applies to the output clock CLKOUT output from the delay cells 22 in the third and subsequent stages.
As a result, the output clock CLKOUT delayed from the input clock CLKIN by a time corresponding to the delay time t × the number of stages of the delay cells 22, that is, a time corresponding to one period, is output from the voltage control delay line 18. The

For example, the output clock CLKOUT output from the delay cell 22 at the final stage is fed back to the phase comparator 12 as the feedback clock FBCLK.
As a result, when the control voltage VCONT increases, the load resistance of the PMOSs 28, 30, 32, and 34 increases, so that the delay time t increases. Conversely, when the control voltage VCONT decreases, the PMOSs 28, 30, 32, and 34 Since the load resistance is reduced, the delay time t is shortened.

  In the conventional DLL circuit 10, the delay time of the output clock CLKOUT relative to the input clock CLKIN, that is, the control voltage VCONT, depending on the PVT (P: manufacturing process, V: power supply voltage, T: temperature) conditions, the frequency of the input clock CLKIN, and the like. There is a problem that changes greatly.

  FIG. 6 is a graph showing an example of the relationship between the control voltage and the delay time of the output clock per delay cell when the voltage control delay line shown in FIG. 5 has a 14-stage delay cell configuration. The horizontal axis of this graph represents the control voltage VCONT, and the vertical axis represents the delay time of the output clock CLKOUT.

  In the graph of the figure, for example, the curve of the condition of ss_-40 indicates that the manufacturing process is “ss” and the temperature is “−40 ° C.”. The same applies to the other curves. The process condition “ss” indicates that the manufacturing process of NMOS (N-type MOS transistor) and PMOS (P-type MOS transistor) is slow and slow. The process condition “ff” indicates that the NMOS and PMOS manufacturing processes are fast and fast. The same applies to other process conditions.

Further, in the graph of the figure, a horizontal line representing Spec_160M indicates that a delay time corresponding to one cycle of the input clock CLKIN when the frequency is 160 MHz is formed in the voltage control delay line 18 having a 14-stage delay cell configuration. In this case, the delay time required per delay cell is expressed. In other words, the horizontal line representing Spec_160M and the curve of each condition intersect with each other under the condition of each curve. When the frequency of the input clock CLKIN is 160 MHz, the output clock CLKOUT is compared with the input clock CLKIN. 1 represents the control voltage VCONT when delayed by a time corresponding to one period. The same applies to Spec — 14.2M.
In the graph of the figure, the value of the X coordinate of each curve in the region sandwiched between the Spec — 14.2M straight line and the Spec — 160M straight line is a value that can be taken by the control voltage VCONT. In the case of the graph in the figure, the control voltage VCONT can take a value in the range of about 0.4V ≦ control voltage VCONT ≦ about 1.08V.

Thus, if the amplitude of the control voltage VCONT when the PVT condition or the frequency of the input clock is changed is large, it is difficult to ensure the DC operating point of the delay cell 22.
For example, in the graph of FIG. 6, under the condition of ff_125 where the control voltage VCONT is the largest, the control voltage VCONT is 1.08 V at the maximum, but the power supply voltage is 1.2 V. Therefore, in this control voltage VCONT, The load resistors PMOS 28, 30, 32, and 34 constituting the delay cell 22 operate in the subthreshold region. In this case, the amount of current flowing through the PMOSs 28, 30, 32, 34 fluctuates exponentially due to manufacturing variations and power supply noise, resulting in jitter deterioration and delay times of the delay cells 22 constituting the voltage control delay line 18. Therefore, it becomes a big problem when the output of each delay cell 22 is taken out and used as a multiphase clock. This makes it impossible to obtain an output clock CLKOUT having an accurate delay time.

On the other hand, in order to avoid the control voltage VCONT rising to 1.08 V under the condition of ff_125, for example, it is conceivable to connect a load capacitor to the output of each delay cell.
However, when a load capacitor is connected to the output of the delay cell 22, for example, in the condition of ss_-40 where the control voltage VCONT is the smallest in the graph of FIG. The NMOS 40, which is the tail current source of the delay cell 22 that must be operated at, falls into the linear region.

FIGS. 7A and 7B are graphs showing examples of the relationship between the control voltage and the delay time of one stage of the delay cell when a load capacitor is connected to the output of the delay cell.
The graph of FIG. 5A shows that when the voltage control delay line 18 has a 14-stage configuration of the delay cells 22, the condition of ff_125, the power supply voltage of 1.2V, and 14.2 MHz to 160 MHz for each stage of the delay cell 22 is shown. This represents the relationship between the control voltage VCONT and the delay time of the output clock CLKOUT when operating with the input clock CLKIN having a frequency in the range and changing the value of the load capacitance connected to the output of the delay cell 22.

As shown in the graph of FIG. 11A, it can be seen that, under the condition of ff_125, the control voltage VCONT is greatly reduced as the value of the load capacitance connected to the output of the delay cell 22 is increased.
On the other hand, FIG. 6B shows that the DLL circuit 10 is connected to the output of the delay cell 22 with the condition of ss_-40, the power supply voltage of 1.2V, the input clock having the frequency in the range of 14.2 MHz to 160 MHz. Represents the relationship between the control voltage VCONT and the delay time of the output clock CLKOUT when the load capacitance value to be operated is changed.
As shown in the graph of FIG. 7B, in the case of the condition of ss_−40, as the value of the load capacitance connected to the output of the delay cell 22 is increased, the control voltage VCONT decreases too much and the tail current source is turned on. The DC operating points of the NMOS 48 and the NMOS 40 constituting the configuration are out of the saturation region.

  As described above, the DC operating point of the delay cell 22 cannot be appropriately set under all frequency conditions and all PVT conditions of the input clock CLKIN simply by connecting a load capacitor to the output of the delay cell 22.

  Moreover, there exists patent document 1 as a prior art document relevant to this invention.

Japanese Patent Application Laid-Open No. 2004-133867 describes a method for changing a delay amount in a pre-driver section of a delay monitor circuit for monitoring a delay amount of a compensation clock that is output from a variable delay cell constituting a DLL circuit and delays a system clock. A configuration is described in which a plurality of capacitors and a plurality of switches for connecting the capacitors and the compensation clock are provided, and the on / off state of the switches is controlled as needed by a control signal to change the delay amount by connecting or disconnecting the capacitors. Yes.
However, in the configuration of Patent Document 1, there is a problem that a complicated control signal input from the outside of the DLL circuit is required to switch the connection of a plurality of capacitors.

JP 2003-188705 A

John G. Maneatis, Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques, IEEE JOURNAL OF SOLID-STATE CIRCUITS, NOVEMBER 1996, VOL. 31, NO. 11

  An object of the present invention is to provide a delay locked loop circuit that can solve the problems of the prior art and can appropriately set the DC operating point of the voltage controlled delay line under all frequency conditions and all PVT conditions of the input clock. There is to do.

In order to achieve the above object, according to the present invention, a voltage control delay that outputs an output clock that is phase-synchronized with an input clock in accordance with a control voltage and is delayed by a time corresponding to one period with respect to the input clock. A delay locked loop circuit comprising a line,
Each output load of the same size is connected to a corresponding output clock, or each load load is not connected to each corresponding output clock; and
A connection control unit that controls to output an active connection control signal when the control voltage is greater than a preset reference voltage after a time equal to or greater than a lock time has elapsed. Prepared,
The load connection unit provides a delay locked loop circuit that connects each output load to the corresponding output clock when the connection control signal is in an active state. is there.

  Here, when the control voltage is larger than the preset reference voltage, the connection control unit controls the connection control signal in the active state to be output only once. preferable.

In addition, the connection control unit
A reference voltage generating circuit for generating the reference voltage;
A comparison circuit that outputs a comparison result comparing the control voltage and the reference voltage;
A counter that outputs a holding signal after counting a time equal to or longer than the time corresponding to the lock time;
It is preferable to include a comparison result holding circuit that holds the comparison result and outputs the comparison result as the connection control signal in synchronization with the holding signal.

  Preferably, the reference voltage generation circuit generates (power supply voltage—threshold voltage of MOS when the manufacturing process of NMOS and PMOS swings first and first) as the reference voltage.

  The reference voltage generation circuit preferably generates a voltage corresponding to a control voltage when the manufacturing process is typical and the temperature is normal temperature, as the reference voltage.

The load connecting portion is
As each output load, each load capacity of the same capacity value,
Each of the load capacitors connected between the load capacitors and the corresponding output clocks, and turned on when the connection control signal is in an active state to connect the load capacitors to the corresponding output clocks. And a switch.

In the present invention, in the DLL circuit manufactured under the condition that the control voltage is larger than the preset reference voltage, each output load is connected to the corresponding output clock, and the control voltage is lowered.
On the other hand, in the DLL circuit manufactured under the condition that the control voltage is smaller than the reference voltage, each output load is not connected to the corresponding output clock, and the control voltage is not unnecessarily lowered.
Thus, according to the present invention, the range that the control voltage can take can be narrowed, so that it is easy to secure the DC operating point margin of the voltage control delay line, and the frequency range of the input clock can be expanded.
Further, in the present invention, after the reset is released, the holding signal is limited to change only once, thereby preventing the connection state of the output load from being switched unintentionally during the normal operation of the DLL circuit. it can.

It is a block diagram of one Embodiment showing the structure of the DLL circuit of this invention. FIG. 2 is a circuit diagram illustrating an example of a configuration of a voltage control delay line, a load connection unit, and a connection control unit illustrated in FIG. (A) and (B) are timing charts of examples showing the operation of the DLL circuit shown in FIG. It is a block diagram of an example showing the structure of the DLL circuit disclosed by the nonpatent literature 1. FIG. 5 is an exemplary circuit diagram illustrating a configuration of a voltage control delay line illustrated in FIG. 4. 6 is a graph illustrating an example of a relationship between a control voltage and a delay time of an output clock per stage of delay cells illustrated in FIG. 5. (A) and (B) are graphs showing examples of the relationship between the control voltage and the delay time of one stage of the delay cell when a load capacitor is connected to the output of the delay cell.

  Hereinafter, a delay locked loop circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a block diagram of an embodiment showing a configuration of a DLL circuit of the present invention. The DLL circuit 50 according to the present embodiment shown in the figure further includes a load connection unit 52 and a connection control unit 54 in the conventional DLL circuit 10 shown in FIG.
That is, the DLL circuit 50 includes a phase comparator (PD) 12, a charge pump (CP) 14, a loop filter (LF) 16, a voltage control delay line (VCDL) 18, a load connection unit 52, and connection control. Part 54.
In the DLL circuit 50 of the present embodiment, the same components as those in the conventional DLL circuit 10 are denoted by the same reference numerals, and repeated description thereof is omitted.

The load connection unit 52 connects each output load of the same size to the corresponding output clock CLKOUT or connects each output load to the corresponding output clock CLKOUT in accordance with a connection control signal described later. It is something that does not.
When the connection control signal is in an active state, the load connection unit 52 connects each output load to the corresponding output clock CLKOUT.

When the control voltage VCONT is greater than the preset reference voltage VREF after a time equal to or greater than the time corresponding to the lock time of the DLL circuit 50 has elapsed, the connection control unit 54 sends an active connection control signal. It controls to output.
The connection control unit 54 of the present embodiment performs control so that the connection control signal in the active state is output only once when the control voltage VCONT is higher than the preset reference voltage VREF.

Here, the purpose of connecting the output load to the output clock CLKOUT is possible even if the load resistors PMOS 28, 30, 32, and 34 are prevented from falling into the subthreshold region or even if they operate in the subthreshold region. As much as possible, the gate-source voltage Vgs can be increased.
In the case of the example shown in FIG. 6, the control voltage VCONT does not increase so much in the manufacturing processes other than ff, so it is sufficient to pay attention to the control voltage VCONT of the manufacturing process at the time of ff.

Therefore, it is conceivable to set the reference voltage VREF = (power supply voltage−PMOS threshold voltage Vth when the manufacturing process fluctuates to ff).
In this case, for example, if the threshold voltage Vth of the PMOS 28, 30, 32, and 34 is 0.3V when the power supply voltage is 1.2V and the manufacturing process is ff, the reference voltage VREF = 1.2V−0.3V. = 0.9V.
Alternatively, the reference voltage VREF may be set to a standard condition, that is, a voltage corresponding to the control voltage VCONT when the manufacturing process is typical and the temperature is normal temperature.

  The reference voltage VREF may be set anywhere within the range that the control voltage VCONT can take as long as the minimum value that the control voltage VCONT can take is not lowered.

Next, FIG. 2 is a circuit diagram illustrating an example of the configuration of the voltage control delay line, the load connection unit, and the connection control unit illustrated in FIG.
As shown in the figure, the load connection unit 52 of the present embodiment has, as each output load, each load capacitance 56 having the same capacitance value, and between each load capacitance 56 and the corresponding output clock CLKOUT. Each switch 58 is connected and is turned on when the connection control signal Tgate_N and the inverted connection control signal Tgate_P are in the active state of H and L, and connects each load capacitor 56 to the corresponding output clock CLKOUT. ing.
The capacitance value of the load capacitor 56 can be determined according to the layout area, how much the control voltage VCONT is to be reduced, and the like.

The load connection unit 52 corresponding to the delay cell 22 in the first stage includes two capacitive elements 60 and 62 as a load capacitor 56, and two transfer gates 64 and 66 as a switch 58.
The transfer gate 64 and the capacitive element 60 are connected in series between the output clock CLKOUT_P_1 and the ground GND. Similarly, the transfer gate 66 and the capacitive element 62 are connected in series between the inverted output clock CLKOUT_N_1 and the ground GND.
A connection control signal Tgate_N and an inverted connection control signal Tgate_P are input to the gates of the PMOS and NMOS constituting the transfer gates 64 and 66, respectively.
The same applies to the load connection units 52 corresponding to the delay cells 22 in the second and subsequent stages.

  Subsequently, the connection control unit 54 of this embodiment includes a reference voltage generation circuit 68, a comparison circuit 70, a counter 72, a comparison result holding circuit 74, and an inverter 76.

  The reference voltage generation circuit 68 generates a predetermined reference voltage VREF set in advance. The reference voltage generation circuit 68 according to the present embodiment divides the voltage between the power supply VDD and the ground GND by a plurality of resistance elements connected in series between the power supply VDD and the ground GND to obtain the reference voltage VREF. Occur.

  The comparison circuit 70 outputs a comparison result obtained by comparing the control voltage VCONT and the reference voltage VREF.

The counter 72 outputs a holding signal Count_out after counting a time equal to or greater than the time corresponding to the lock time in synchronization with the divided clock DIVCLK obtained by dividing the input clock CLKIN.
Since the lock time can be calculated by, for example, simulation or the like, the counter 72 that counts a time equal to or greater than the time corresponding to the lock time can be configured according to the divided clock DIVCLK and the lock time.
Although the input clock CLKIN may be used instead of the divided clock DIVCLK, the circuit scale of the counter 72 can be reduced by using the divided clock DIVCLK.

The comparison result holding circuit 74 holds the comparison result in synchronization with the holding signal Count_out and outputs it as a connection control signal Tgate_N.
The inverter 76 outputs an inverted connection control signal Tgate_P obtained by inverting the connection control signal Tgate_N.

  Hereinafter, the operation of the DLL circuit 50 will be described.

Although not shown, in the connection control unit 54, the counter 72 and the comparison result holding circuit 74 are reset by, for example, a power-on reset or the like.
As a result, the holding signal Count_out is initialized to L, the connection control signal Tgate_N is initialized to L, that is, the inverted connection control signal Tgate_P is initialized to H. Further, all the transfer gates 64 and 66 (switch 58) of the load connection unit 52 are turned off.

After the reset is released, the counter 72 counts a time equal to or greater than the time corresponding to the lock time in synchronization with the divided clock DIVCLK, and then outputs a holding signal Count_out that changes only once from L to H.
On the other hand, the comparison circuit 70 compares the control voltage VCONT after the DLL circuit 50 is locked with the reference voltage VREF, and outputs the comparison result. The comparison circuit 70 of this embodiment outputs H as a comparison result when the control voltage VCONT is larger than the reference voltage VREF.

  Subsequently, the comparison result holding circuit 74 holds the comparison result in synchronization with the rise of the holding signal Count_out, and outputs it as a connection control signal Tgate_N. Further, the inverter 76 inverts the connection control signal Tgate_N and outputs it as an inverted connection control signal Tgate_P.

When the control voltage VCONT is higher than the reference voltage VREF, the connection control signal Tgate_N is H, the inverted connection control signal Tgate_P is L, and all the transfer gates 64 and 66 are turned on in the load connection unit 52. Accordingly, each capacitive element 60 is connected to the corresponding output clock CLKOUT_P, and each capacitive element 62 is connected to the corresponding inverted output clock CLKOUT_N.
When the capacitive elements 60 and 62 are connected to the output clock CLKOUT, the delay time of the output clock CLKOUT changes. The output clock CLKOUT whose delay time has changed is fed back to the phase comparator 12 as the feedback clock FBCLK, and is changed in the direction in which the control voltage VCONT is lowered. Then, the delay time of the output clock CLKOUT is changed again according to the changed control voltage VCONT.

  On the other hand, when the control voltage VCONT is equal to or lower than the reference voltage VREF, the connection control signal Tgate_N is L, that is, the inverted connection control signal Tgate_P is H, and in the load connection unit 52, all the transfer gates 64 and 66 are turned off. Accordingly, each capacitive element 60 is not connected to the corresponding output clock CLKOUT_P, and each capacitive element 62 is not connected to the corresponding inverted output clock CLKOUT_N.

For example, when the power supply voltage is 1.2 V, when the reference voltage VREF is set to 0.9 V, the maximum control voltage VCONT is about 1.08 V under the condition of ff_125 in which the control voltage VCONT becomes the largest in FIG. In the case of the curve, the control voltage VCONT is larger than the reference voltage VREF, and the comparison result is H. As a result, as shown in FIG. 3A, the connection control signal Tgate_N becomes H, the inverted connection control signal Tgate_P becomes L, and each load capacitor 56 is connected to the corresponding output clock CLKOUT.
FIG. 3 shows changes in the control voltage VCONT when the load capacitor 56 is connected to the output clock CLKOUT and when it is not connected so that the comparison is easy.
As a result, in the DLL circuit manufactured under the condition that the control voltage VCONT is larger than the preset reference voltage VREF, the control voltage VCONT is lowered, and the load resistors PMOS 28, 30, 32, and 34 fall into the subthreshold region. Even when the operation is performed in the subthreshold region, the gate-source voltage Vgs can be increased as much as possible.

  In the simulation conducted by the present inventor, the load resistors PMOS 28, 30, 32, and 34 operate in the subthreshold region even after the load capacitor 56 is connected to the output clock CLKOUT. The voltage Vgs between them was improved in the direction of increasing 80 mV. In the subthreshold region, the current value of the MOS changes with an exponential function of (Vgs−Vth). Therefore, even if the gate-source voltage Vgs is improved by 80 mV, the variation in the threshold voltage Vth and the power supply noise are greatly increased. Become stronger.

On the other hand, for example, in the case of a curve where the control voltage VCONT is about 0.4 V which is the minimum under the condition of ss_−40 where the control voltage VCONT is the smallest, the control voltage VCONT is smaller than the reference voltage VREF, and the comparison result is L. As a result, as shown in FIG. 3B, the connection control signal Tgate_N remains L and the inverted connection control signal Tgate_P remains H, and each load capacitor 56 is not connected to the corresponding output clock CLKOUT.
Thereby, in the DLL circuit manufactured under the condition that the control voltage VCONT is smaller than the reference voltage VREF, the control voltage VCONT is not unnecessarily lowered.

  As described above, since the range of values that the control voltage VCONT can take can be narrowed by switching connection / disconnection of the load capacitor 56 to / from the output clock CLKOUT, a DC operating point margin of the voltage control delay line 18 is ensured. And the frequency range of the input clock can be expanded.

In the case of the present embodiment, the holding signal Count_out changes only once from L to H after reset is released or does not change, so that the connection state (connected or non-connected) of the capacitive element is fixed.
As described above, after the reset is released, the holding signal Count_out is limited to change only once from L to H, so that the connection state of the capacitive element is switched unintentionally during the normal operation of the DLL circuit 50. Can be prevented.

  The specific configurations of the DLL circuit 50, the voltage control delay line 18, the load connection unit 52, and the connection control unit 54 are not limited at all, and various configurations that perform the same function can be used.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

10, 50 DLL circuit 12 Phase comparator (PD)
14 Charge pump (CP)
16 Loop filter (LF)
18 Voltage Control Delay Line (VCDL)
22 Delay cell (differential inverter)
24 replica circuit 26 amplifier 28, 30, 32, 34, 42, 44 PMOS (P-type MOS transistor)
36, 38, 40, 46, 48 NMOS (N-type MOS transistor)
52 Load connection unit 54 Connection control unit 56 Load capacity 58 Switch 60, 62 Capacitance element 64, 66 Transfer gate 68 Reference voltage generation circuit 70 Comparison circuit 72 Counter 74 Comparison result holding circuit 76 Inverter

Claims (6)

A delay-locked loop circuit comprising a voltage-controlled delay line that is phase-synchronized with an input clock according to a control voltage and outputs an output clock delayed by a time corresponding to one period with respect to the input clock;
Each output load of the same size is connected to a corresponding output clock, or each load load is not connected to each corresponding output clock; and
A connection control unit that controls to output an active connection control signal when the control voltage is greater than a preset reference voltage after a time equal to or greater than a lock time has elapsed. Prepared,
The delay locked loop circuit, wherein the load connection unit is configured to connect each output load to the corresponding output clock when the connection control signal is in an active state.   The connection control unit controls the active connection control signal to be output only once when the control voltage is higher than the preset reference voltage. Delay-locked loop circuit. The connection control unit
A reference voltage generating circuit for generating the reference voltage;
A comparison circuit that outputs a comparison result comparing the control voltage and the reference voltage;
A counter that outputs a holding signal after counting a time equal to or longer than the time corresponding to the lock time;
The delay locked loop circuit according to claim 1, further comprising a comparison result holding circuit that holds the comparison result and outputs the comparison result as the connection control signal in synchronization with the holding signal.   4. The delay synchronization according to claim 3, wherein the reference voltage generation circuit generates (power supply voltage—threshold voltage of MOS when the manufacturing process of NMOS and PMOS swings first and first) as the reference voltage. 5. Loop circuit.   4. The delay locked loop circuit according to claim 3, wherein the reference voltage generation circuit generates a voltage corresponding to a control voltage when the manufacturing process is typical and the temperature is normal temperature, as the reference voltage. The load connection part is:
As each output load, each load capacity of the same capacity value,
Each of the load capacitors connected between the load capacitors and the corresponding output clocks, and turned on when the connection control signal is in an active state to connect the load capacitors to the corresponding output clocks. The delay locked loop circuit according to claim 1, further comprising a switch.

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