JP2015197863A - Image processor and control method thereof, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for preventing circuit information showing an operation state of a circuit from being lost by reconfiguration in an image processor for performing image processing by the circuit capable of dynamic partial reconfiguration.SOLUTION: An image processor 100 includes a dynamic reconfiguration part 131 as a reconfigurable circuit capable of dynamically reconfiguring a portion of a circuit configuration. In the dynamic reconfiguration part 131, dynamic partial reconfiguration configures an image processing part 132 for performing image processing, and a register part for storing a register value (circuit information) for image processing, showing an operation state of the image processing part 132. A CPU 101 stores the register value stored in the register part 133 in an SRAM 134 provided outside the dynamic reconfiguration part 131 after being reconfigured in a circuit configuration which can execute first image processing by a configuration controller 130 and before being reconfigured in a circuit configuration which can execute second image processing to be executed next.

Description

  The present invention relates to an image processing apparatus, a control method therefor, and a program.

  Reconfigurable circuits such as PLD (Programmable Logic Device) and FPGA (Field Programmable Gate Array) capable of changing the configuration of the logic circuit are well known. In general, when a logic circuit of a PLD or FPGA is changed, circuit configuration information (circuit configuration data) stored in a nonvolatile memory such as a ROM is converted into a configuration memory that is a volatile memory inside the PLD or FPGA at the time of startup. Realized by writing to Since the information in the configuration memory is cleared when the power is turned off, it is necessary to write the circuit configuration information stored in the ROM again in the configuration memory when the power is turned on. In this way, a method of configuring a PLD or FPGA logic circuit only once while power is supplied is called static reconfiguration. On the other hand, an FPGA or the like that can dynamically change the configuration of a logic circuit while the logic circuit is operating has been developed, and such a method of dynamically changing a logic circuit is called dynamic reconfiguration.

  Some FPGAs can rewrite only the circuit configuration of a specific area, not the circuit configuration of the entire FPGA chip, and such rewriting is called partial reconfiguration. In particular, changing other circuit configurations without stopping the operation of the circuit in operation is called dynamic partial reconfiguration. In dynamic partial reconfiguration, it is possible to partially reconfigure the FPGA logic circuit by rewriting only a partial area of the configuration memory instead of rewriting the entire configuration memory at the time of dynamic reconfiguration. it can. By using such dynamic partial reconfiguration, for example, a plurality of logic circuits can be switched and mounted in a certain area of the FPGA in a time division manner. As a result, with a small amount of hardware resources, various functions can be flexibly realized while maintaining high-speed computing performance by hardware.

  An image processing apparatus such as an MFP (Multi Function Printer) executes image processing selected from a plurality of executable processes (copy job, print job, SEND job, etc.) in response to a request from the user. In such an image processing apparatus, errors such as image defects and hang-ups may occur. In order to analyze and debug such an error, in general, various software parameters handled by application software that executes various functions and driver software that performs register settings for image processing hardware can be analyzed. In addition, register values such as image processing parameters and status inside the circuit held in the image processing hardware can be stored in an external nonvolatile memory by software and used for error analysis.

  For example, in Patent Document 1, accompanying information (version information, update date, etc.) of configuration data for reconfiguration of a reconfigurable core (circuit) such as an FPGA is stored in a storage unit outside the reconfigurable core. A reconfigurable circuit device has been proposed. As a result, the accompanying information can be read from the external device, and information related to the circuit configured in the reconfigurable core can be known from the outside.

JP 2009-123146 A

  However, in order to execute multiple image processing in a time division manner, when a plurality of logic circuits are switched and implemented in a time division manner with respect to a circuit capable of dynamic partial reconfiguration, a new circuit is created by the reconfiguration. When implemented, at least part of the information about the circuit before reconfiguration is lost. Specifically, in Patent Document 1, it is possible to obtain circuit information indicating the hardware configuration of the circuit by storing accompanying information of configuration data in a storage unit outside the reconfigurable circuit. On the other hand, circuit information indicating the operation state of the circuit, such as parameters (register values) used in image processing and circuit status, is lost due to circuit reconfiguration. As a result, such circuit information cannot be used for error analysis and debugging. Thus, when circuit information indicating the operation state of the circuit is lost due to reconfiguration of the reconfigurable circuit, such circuit information can be used for error analysis and debugging when an error occurs. It becomes impossible.

  The present invention has been made in view of the above problems. An object of the present invention is to provide a technique for preventing circuit information indicating an operation state of a circuit from being lost due to reconfiguration in an image processing apparatus that performs image processing using a circuit capable of dynamic partial reconfiguration.

  The present invention can be realized as an image processing apparatus, for example. An image processing apparatus according to an aspect of the present invention is a reconfigurable circuit capable of dynamically reconfiguring a part of a circuit configuration, an image processing unit that performs image processing, and an operation state of the image processing unit The reconfigurable circuit and the reconfigurable circuit configured to include a register unit that holds circuit information for the image processing are reconfigured to a circuit configuration that can execute image processing necessary for a job. And a second image processing to be executed next after the reconfigurable circuit is reconfigured to a circuit configuration capable of executing the first image processing by the reconfiguring means. Control means for controlling to store the circuit information held in the register unit in a storage means provided outside the reconfigurable circuit before being reconfigured into an executable circuit configuration. It is characterized by that.

  An image processing apparatus according to another aspect of the present invention is a reconfigurable circuit capable of dynamically reconfiguring a part of a circuit configuration, an image processing unit that performs image processing, and an operation of the image processing unit The reconfigurable circuit configured to include a register unit that holds circuit information for the image processing that indicates a state, and the image processing unit to a circuit configuration that can perform image processing required for a job The circuit information for the first image processing is held in the register unit after the image processing unit is reconfigured to a reconfiguration unit for reconfiguration and a circuit configuration capable of executing the first image processing. In addition, the image processing unit includes a control unit that controls the reconstruction unit so that the image processing unit is reconfigured in a circuit configuration capable of executing the second image processing to be executed next.

  According to the present invention, in an image processing apparatus that performs image processing using a circuit capable of dynamic partial reconfiguration, it is possible to prevent circuit information indicating the operation state of the circuit from being lost due to reconfiguration.

1 is a diagram illustrating a configuration example of an image processing apparatus (first and third embodiments). FIG. 4 is a diagram illustrating an example of configuration data stored in a ROM, an example of the order of image processing executed by each job that can be executed by the image forming apparatus, and an example of corresponding configuration data. FIG. 10 is a diagram illustrating an example of a reconfiguration procedure of a dynamic reconfiguration unit when the image processing apparatus executes a copy job (first to third embodiments). The flowchart which shows the procedure of the reconstruction control of a dynamic reconstruction part (1st Embodiment). FIG. 2 is a diagram illustrating a configuration example of an image processing apparatus (second embodiment). 9 is a flowchart illustrating a procedure of reconfiguration control of a dynamic reconfiguration unit (second embodiment). , The flowchart which shows the procedure of the reconstruction control of a dynamic reconfiguration | reconstruction part (modification of 2nd Embodiment). FIG. 10 is a diagram illustrating an example of a reconfiguration procedure of a dynamic reconfiguration unit when an image processing apparatus executes a copy job (third embodiment). 10 is a flowchart illustrating a procedure of reconfiguration control of a dynamic reconfiguration unit (third embodiment). The flowchart which shows the procedure of the reconstruction control of a dynamic reconfiguration | reconstruction part (modification of 3rd Embodiment).

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. The following embodiments do not limit the invention according to the claims, and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention.

<Configuration of image processing apparatus>
FIG. 1 is a block diagram illustrating a configuration example of an image processing apparatus 100 according to the first embodiment. In the present embodiment, an example in which the image processing apparatus 100 is a multifunction peripheral (multifunctional processing apparatus) having a scanner unit and a printer unit will be described.

  The image processing apparatus 100 includes an operation unit 103 for a user using the image processing apparatus 100 to perform various operations, a scanner unit 109 that reads image information of a document, and a printer that prints an image on a sheet based on image data. Part 107. The scanner unit 109 includes a CPU (not shown) that controls the scanner unit 109, an illumination lamp for reading a document, a scanning mirror (all not shown), and the like. The printer unit 107 includes a CPU (not shown) that controls the printer unit 107, a photosensitive drum and a fixing device (none of which are shown), and the like for image formation (printing) and fixing.

  The image processing apparatus 100 includes an FPGA 140 including a dynamic reconfiguration unit as a controller that controls the image processing apparatus 100. In this example, the FPGA 140 includes a CPU 101 that comprehensively controls the operation of the image processing apparatus 100. The CPU 101 executes a program for controlling the FPGA 140, the configuration controller 130 for controlling reconfiguration, and the like. Note that the FPGA 140 includes the CPU 101 is merely an example, and the CPU may be provided outside the FPGA 140.

  The image processing apparatus 100 includes a ROM 104 and a RAM 111. The ROM 104 stores a boot program executed by the CPU 101 and circuit configuration data (configuration data) for configuring (configuring) the dynamic reconfiguration unit 131. The RAM 111 is a system work memory for the CPU 101 to operate, and is also an image memory for temporarily storing image data. The CPU 101 can store the duplicated data of the circuit configuration data stored in the ROM 104 in the RAM 111 and can read out the circuit configuration data from the RAM 111 at high speed.

  The FPGA 140 includes a CPU 101, a network interface (network I / F) 102, a printer I / F 106, a scanner I / F 108, a memory controller 110, a ROM I / F 112, an operation unit I / F 113, a USB I / F 115, a FAX I / F 116, A configuration controller 130, a dynamic reconfiguration unit 131, an SRAM 134, a system bus 120, and an image bus 121 are provided. The CPU 101, the network I / F 102, the ROM I / F 112, the operation unit I / F 113, the USB I / F 115, the FAX I / F 116, the configuration controller 130, and the image processing unit 132 and the register unit 133 of the dynamic reconfiguration unit 131 are They are connected to each other via a system bus 120. In addition, the image processing unit 132, the scanner I / F 108, and the printer I / F 106 of the dynamic reconfiguration unit 131 are connected to each other via the image bus 121. The image bus 121 is used to transfer image data to be processed. Note that the memory controller 110 is connected to both the system bus 120 and the image bus 121.

  The dynamic reconfiguration unit 131 is a reconfigurable circuit that can dynamically reconfigure (rewrite) a circuit configuration (configuration) and rewrite a part of the circuit configuration. That is, while a part of the circuit of the dynamic reconfiguration unit 131 is operating, another circuit can be reconfigured in another part that does not overlap with the part occupied by the circuit. The configuration controller 130 controls the circuit configuration (configuration) of the dynamic reconfiguration unit 131 and reconfigures the dynamic reconfiguration unit 131 according to control by the CPU 101. In the present embodiment, the configuration controller 130 is an example of a reconfiguration unit that reconfigures the dynamic reconfiguration unit 131 (reconfigurable circuit) into a circuit configuration that can execute image processing required for a job.

  The dynamic reconfiguration unit 131 includes an image processing unit 132 and a register unit 133 by dynamic partial reconfiguration. The image processing unit 132 can partially reconfigure a logic circuit for performing various types of image processing, and performs image processing using the reconfigured circuit configuration. The register unit 133 holds parameters (register values) for image processing by the image processing unit 132. The parameter held by the register unit 133 is used by the image processing unit 132 during execution of image processing by the image processing unit 132, and corresponds to circuit information indicating the operation state of the image processing unit 132. In this embodiment, the number of image processing units and register units configured in the dynamic reconfiguration unit 131 is one, but the number of image processing units and register units is limited to one. It is not a thing. The SRAM 134 is a non-volatile memory that is provided outside the dynamic reconfiguration unit 131 and stores parameters (register values) held by the register unit 133 of the dynamic reconfiguration unit 131.

  The CPU 101 comprehensively controls the operation of the image processing apparatus 100. Further, the CPU 101 communicates (transmits / receives) with a general-purpose computer (not shown) on the network via the network I / F 102. The ROM I / F 112 controls access to the ROM 104 (data writing to the ROM 104 and data reading from the ROM 104). Further, the CPU 101 performs parameter setting for the register unit 133 configured in the dynamic reconfiguration unit 131 via the system bus 120.

  The CPU 101 communicates (transmits / receives) with a general-purpose computer (not shown) connected to the image processing apparatus 100 via the USB I / F 115. The CPU 101 is connected to the public line network via the FAX I / F 116 and communicates (transmits / receives) with other image processing apparatuses or facsimile apparatuses (not shown). The FAX I / F 116 includes a CI detection circuit (not shown) that detects a CI (Call Indicator) signal that is a call signal from the public network.

  The operation unit I / F 113 functions as an interface between the system bus 120 and the operation unit 103. The scanner I / F 108 receives image data from the scanner unit 109. The printer I / F 106 outputs image data to the printer unit 107. The memory controller 110 controls data writing to the RAM 111 and data reading from the RAM 111. The memory controller 110 is connected to the system bus 120 and the image bus 121. The memory controller 110 exclusively switches the access to the RAM 111 from the bus master connected to the image bus 121 and the access to the RAM 111 from the bus master connected to the system bus 120.

<Example of dynamic reconfiguration unit reconfiguration>
Next, an example of reconfiguration of the dynamic reconfiguration unit 131 in the image processing apparatus 100 according to the present embodiment will be described with reference to FIGS. 2 and 3.
FIG. 2A is a diagram illustrating an example of circuit configuration data (configuration data) stored in the ROM 104. As shown in FIG. 2A, the ROM 104 includes a plurality of configuration data (hereinafter referred to as “configuration data”) for reconfiguring some of the circuits (the image processing unit 132 and the register unit 133) of the dynamic reconstruction unit 131. Abbreviated as “configuration data”). Each configuration data is data for mounting in the dynamic reconfiguration unit 131 a logic circuit that realizes a specific image processing function (that can execute image processing).

  The image processing unit 132 and the register unit 133 of the dynamic reconfiguration unit 131 are reconfigured into a logic circuit that realizes a specific image processing function by reconfiguration using each configuration data. For example, by reconfiguration using the configuration data 1, the image processing unit 132 and the register unit 133 perform image processing A (filter processing), and a register unit in which register values for the image processing A are stored. Reconfigured to A. The image processing apparatus 100 can realize various image processing functions by reconfiguring the dynamic reconfiguration unit 131 using configuration data stored in the ROM 104.

  The image processing apparatus 100 can realize a series of image processing functions by reconfiguring the logic circuit for realizing a series of image processing functions necessary for each job in the dynamic reconfiguration unit 131 in time division. It is. FIG. 2B shows image processing functions required for each job (that is, image processing executed in each job) and execution order for each job that can be executed by the image processing apparatus 100, and each image processing function. It is a figure which shows an example with the config data corresponding to. In the present embodiment, copy jobs, print jobs, and SEND jobs are shown as examples of jobs that can be executed by the image processing apparatus 100. The “reconfiguration number” in FIG. 2B indicates the reconfiguration of the dynamic reconfiguration unit 131 using the configuration data corresponding to the image processing function required when the image processing apparatus 100 executes each job. Represents the execution order.

  For example, as shown in FIG. 2B, an image processing function for a copy job can be realized by sequentially executing four image processes A to D. The image processing A is a table conversion process, a filter process, or the like that corrects characteristic variations caused by device characteristics of an image obtained by the scanner unit 109. Image processing B is image area separation processing for performing attribute determination of a character portion or a photograph portion of a document image. Image processing C is color conversion processing for converting RGB data into CMYK data. The image processing D is halftone processing for performing N-value conversion by comparing input image data with a predetermined threshold value.

  When executing a copy job, the image processing apparatus 100 reads the configuration data 1 to 4 corresponding to the image processings A to D from the ROM 104 in time division order and uses them for reconfiguration of the dynamic reconfiguration unit 131. Accordingly, the image processing unit 132 sequentially performs the image processing A to D in a time division manner while being reconfigured in order by the circuits (image processing units A to D) that execute the image processing A to D.

  Further, as shown in FIG. 2B, an image processing function for a print job can be realized by executing the image processing E after executing the image processing C and D. The image processing E is a registration correction process for correcting a registration error when the printer image output of the printer unit 107 is scanned. When executing the print job, the image processing apparatus 100 sequentially reads the configuration data 1 to 4 corresponding to the image processing C to E from the ROM 104 in a time division manner and uses the configuration data 1 to 4 for reconfiguration of the dynamic reconfiguration unit 131. .

  Further, as shown in FIG. 2B, an image processing function for a SEND job can be realized by executing image processing F after executing image processing A and B. The image processing F is a high-resolution compression process for converting scanned image data into a format suitable for network transfer. When executing the SEND job, the image processing apparatus 100 reads the configuration data 1, 2, and 6 corresponding to the image processes A, B, and F from the ROM 104 in a time-sharing manner in order, and reconfigures the dynamic reconfiguration unit 131. Used for configuration.

  Next, FIG. 3 is a diagram illustrating an example of a reconfiguration procedure of the dynamic reconfiguration unit 131 when the image processing apparatus 100 executes a copy job. When the execution of a job is started, the image processing apparatus 100 according to the present embodiment reads necessary configuration data from the ROM 104 in an order determined according to the type of job, sequentially reconfigures the dynamic reconfiguration unit 131, and performs reconfiguration. The configured dynamic reconfiguration unit 131 is caused to execute image processing.

  When the execution of the copy job is instructed via the operation unit 103, the image processing apparatus 100 first sets the reconstruction number to “1” and uses the configuration data 1 as shown in FIG. The dynamic reconfiguration unit 131 is reconfigured. As a result, the image processing unit 132 and the register unit 133 constitute the image processing unit A that executes the image processing A and the register unit A that stores the register values for the image processing A.

  When the execution of the image processing A is completed, the image processing apparatus 100 next sets the reconfiguration number to “2” and reconfigures the dynamic reconfiguration unit 131 using the configuration data 2. Thus, the image processing unit 132 and the register unit 133 are configured with an image processing unit B that executes the image processing B and a register unit B that stores the register values for the image processing B.

  When the execution of the image processing B is completed, the image processing apparatus 100 next sets the reconstruction number to “3” and reconfigures the dynamic reconfiguration unit 131 using the configuration data 3. Thus, the image processing unit 132 and the register unit 133 are configured with an image processing unit C that executes the image processing C and a register unit C that stores register values for the image processing C.

  When the execution of the image processing C is completed, the image processing apparatus 100 next sets the reconfiguration number to “4” and reconfigures the dynamic reconfiguration unit 131 using the configuration data 4. Accordingly, the image processing unit 132 and the register unit 133 are configured with the image processing unit C that executes the image processing D and the register unit D that stores the register values for the image processing D.

  As described above, in the image processing apparatus 100 according to this embodiment, each of the logic circuits for realizing a series of image processing functions necessary for a job is reconfigured in time division in the dynamic reconfiguration unit 131. An image processing function for a job can be realized. The jobs illustrated in FIGS. 2 and 3 are merely examples, and the jobs that can be executed by the image processing apparatus 100 are not limited to those illustrated in FIGS. Further, the unit of image processing is not limited to that shown in FIGS. 2 and 3, and the image processing included in each job can be divided into finer processing.

  As shown in FIG. 3, after completion of specific image processing using the dynamic reconfiguration 131, the dynamic reconfiguration unit 131 is reconfigured to a circuit configuration capable of executing image processing to be executed next. The image processing necessary for the job can be sequentially executed by the dynamic reconfiguration unit 131. However, when the dynamic reconfiguration unit 131 is reconfigured to obtain a circuit configuration corresponding to the next image processing, not only the image processing unit 132 but also the register unit 133 is reconfigured. As a result, as described above, the register value indicating the operation state of the image processing unit 132 held in the register unit 133 is lost.

  In the present embodiment, in the image processing apparatus 100, in order to avoid losing the register value (circuit information) held in the register unit 133 due to the reconfiguration of the dynamic reconfiguration unit 131, the following control is performed. Run. After the dynamic reconfiguration unit 131 is reconfigured to a circuit configuration capable of executing the first image processing, the CPU 101 is reconfigured to a circuit configuration capable of executing the second image processing to be executed next. Before registering, the register unit 133 performs control to save the register value to another storage device. Specifically, the CPU 101 performs control for storing the register value held in the register unit 133 in the SRAM 134 provided outside the dynamic reconfiguration unit 131. Thereby, it is possible to prevent the register value (circuit information) held in the register unit 133 from being lost due to the reconfiguration of the dynamic reconfiguration unit 131.

<Reconfiguration control of dynamic reconfiguration unit>
FIG. 4 is a flowchart illustrating a procedure of reconfiguration control of the dynamic reconfiguration unit 131 when the image processing apparatus 100 according to the present embodiment executes a job using the dynamic reconfiguration unit 131. Each process shown in the flowchart of FIG. 4A is realized by the CPU 101 reading out a control program stored in advance in the ROM 104 or the like to the RAM 111 and executing it. Each process shown in the flowchart of FIG. 4B is executed by the configuration controller 130, and each process shown in the flowchart of FIG. 4C is executed by the image processing unit 132.

  When the image processing apparatus 100 is activated from the power stop state or returned from the sleep state, the CPU 101 starts the process of S101. In step S <b> 101, the CPU 101 determines whether a job execution request has occurred based on information received from the operation unit 103, information received via the network I / F 102, and the like. When an execution request is generated (“YES” in S101), the CPU 101 advances the process to S102. In step S102, the CPU 101 determines the type of job specified by the execution request. For example, the CPU 101 determines which one of a copy job, a print job, and a SEND job is the designated job.

  In step S103, the CPU 101 starts execution of the designated job and advances the process to step S104. Here, according to the job type determined in S102, the CPU 101, as shown in FIG. 2B, the necessary image processing execution order and the dynamic reconfiguration unit corresponding to the image processing. The use order of configuration data for reconfiguration 131 is determined. As described above, during execution of a designated job, reconfiguration of the dynamic reconfiguration unit 131 is repeatedly executed using a plurality of configuration data corresponding to a plurality of image processing required for the job in order. The The CPU 101 manages the number of reconfigurations of the dynamic reconfiguration unit 131 using the reconfiguration number N (N is an integer). The CPU 101 sets N = 1 and starts job execution. In this way, the CPU 101 reconfigures a plurality of circuit configurations corresponding to a plurality of image processes (including the first and second image processes) necessary for the job in a time division manner in the dynamic reconfiguration unit 131. Thus, the job can be executed while controlling the configuration controller 130.

  In step S <b> 104, the CPU 101 transmits a reconfiguration instruction indicating that the reconfiguration corresponding to the reconfiguration number N for the dynamic reconfiguration unit 131 should be executed to the configuration controller 130 via the system bus 120. . Note that the CPU 101 includes information relating to configuration data corresponding to the reconstruction number N shown in FIG. 2B as information relating to the reconstruction corresponding to the reconstruction number N in the reconstruction instruction. Thereafter, in S105, the CPU 101 waits until a reconfiguration completion notification is received from the configuration controller 130. When the reconfiguration completion notification is received, the CPU 101 proceeds to S106.

(Processing of the configuration controller 130)
When receiving a reconfiguration instruction from the CPU 101, the configuration controller 130 reconfigures the dynamic reconfiguration unit 131 according to the procedure shown in FIG. First, in S121, the configuration controller 130 waits until a reconfiguration instruction from the CPU 101 is received. When receiving the reconfiguration instruction (“YES” in S121), the configuration controller 130 advances the process to S122.

  In S122, the configuration controller 130 reads configuration data from the ROM 104 in accordance with a reconfiguration instruction from the CPU 101. Further, the configuration controller 130 reconfigures the circuit configuration of the region (image processing unit 132 and register unit 133) to be reconfigured by the dynamic reconfiguration unit 131 using the read configuration data. In this way, the configuration controller 130 reconfigures the target area of the dynamic reconfiguration unit 131. As a result, the dynamic reconfiguration unit 131 is reconfigured using the configuration data corresponding to the reconfiguration number N.

  Thereafter, when the reconfiguration of the target area of the dynamic reconfiguration unit 131 is completed (“YES” in S123), the configuration controller 130 advances the process to S124. In S124, the configuration controller 130 transmits a notification (reconfiguration completion notification) indicating that the reconfiguration according to the reconfiguration instruction is completed to the CPU 101 via the system bus 120, and returns the process to S121. Thereafter, the configuration controller 130 enters a standby state in S121 until a reconfiguration instruction is received from the CPU 101 again.

  Returning again to the flowchart of FIG. 4A, when the CPU 101 receives a reconfiguration completion notification from the configuration controller 130 in S105 (“YES” in S105), the process proceeds to S106. In S <b> 106, the CPU 101 sets a register value necessary for executing image processing corresponding to the reconstruction number N to the register unit 133 reconfigured in the dynamic reconfiguration unit 131 via the system bus 120. .

  Further, in S107, the CPU 101 reconfigures the dynamic reconfiguration unit 131 via the system bus 120 with an instruction indicating that the image processing (first image processing) corresponding to the reconfiguration number N should be started. To the image processing unit 132. As a result, the image processing unit 132 starts executing image processing on the image data transferred from the RAM 111.

(Processing of the image processing unit 132)
When receiving an image processing start instruction from the CPU 101, the image processing unit 132 executes image processing according to the procedure shown in FIG. First, in step S131, the image processing unit 132 stands by until an image processing start instruction is received from the CPU 101. When the image processing unit 132 receives an instruction to start image processing (“YES” in S131), the process proceeds to S132. In S132, the image processing unit 132 starts image processing on the image data transferred from the RAM 111 in accordance with the start instruction.

  Thereafter, when the image processing unit 132 completes the image processing in accordance with the instruction from the CPU 101 (“YES” in S133), the process proceeds to S134. In S134, the image processing unit 132 transmits a notification (image processing completion notification) indicating that the image processing is completed to the CPU 101 via the system bus 120, and returns the processing to S131. Thereafter, the image processing unit 132 enters a standby state in S131 until an instruction to start image processing is received from the CPU 101 again.

  Returning to the flowchart of FIG. 4A again, the CPU 101 receives the image processing completion notification from the image processing unit 132 (“YES” in S108), and advances the processing to S109. In S109, the CPU 101 determines whether or not the next reconfiguration (reconfiguration number N + 1) for the dynamic reconfiguration unit 131 should be executed. Here, with respect to the plurality of configuration data whose use order has been determined in S103, there remains configuration data to be used for the reconfiguration of the dynamic reconfiguration unit 131 (that is, execution with respect to the plurality of image processes whose execution order has been determined). It is determined whether image processing to be performed remains. When the CPU 101 does not execute the next reconfiguration (reconfiguration number N + 1) for the dynamic reconfiguration unit 131 (“NO” in S109), the CPU 101 ends the job execution and executes the next reconfiguration (S109). "YES"), the process proceeds to S110.

  In S110, the CPU 101 transfers the image processing register value corresponding to the reconstruction number N set in the register unit 133 to the SRAM 134 and stores it. As described above, the CPU 101 registers the register unit 133 before instructing the configuration controller 130 that the dynamic reconfiguration unit 131 should be reconfigured to have a circuit configuration corresponding to the next image processing (second image processing). Are stored in the SRAM 134. Thus, before the next reconfiguration of the dynamic reconfiguration unit 131 is performed, the register value (circuit information) held in the register unit 133 is saved, and the circuit information is erased by the reconfiguration of the register unit 133. Can be prevented.

  Thereafter, in S111, the CPU 101 increments the reconstruction number N (increases by 1 from N to N + 1), and returns the process to S104. As a result, the CPU 101 reconfigures the dynamic reconfiguration unit 131 for the image processing (second image processing) to be executed next corresponding to the next reconfiguration number N + 1 for the dynamic reconfiguration unit 131. Initiate configuration control.

  As described above, in the present embodiment, the register value (circuit information) held by the register unit 133 is stored in the SRAM 134 before the next reconfiguration of the dynamic reconfiguration unit 131 is performed, It is possible to prevent the circuit information from disappearing with the reconfiguration. As a result, the circuit information stored in the SRAM 134 after execution of reconfiguration by the dynamic reconfiguration unit 131 can be used for error analysis, error debugging, and the like when an error occurs in the image processing apparatus 100. It becomes possible. As a result, it is possible to improve the quality of a device including a reconfigurable circuit such as an FPGA using such information.

  If the image processing unit 132 is operating normally and no error has occurred (that is, if error debugging is not required), the CPU 101 skips the processing of S110 and transfers the register value to the SRAM 134. And it is not necessary to store. Thereby, when the image processing apparatus 100 is operating normally, the time required for job execution can be reduced by the time required for the processing of S110. Note that when debugging of an error that occurs in a specific image process is necessary, the CPU 101 can transfer and store only the register value (circuit information) used in the specific image process in the SRAM 134.

  Further, at an arbitrary timing after the execution of the job is completed, the reconfiguration using the configuration data corresponding to the reconfiguration number M (M is an integer) is executed again, and the register value stored in the SRAM 134 in S110 is stored in the register unit 133. It is also possible to write back to In this case, the register value written back to the register unit 133 is a register value for image processing corresponding to the reconstruction number M. Thereby, for example, when an error occurs in the reconfigured dynamic reconfiguration unit 131 corresponding to the reconfiguration number M, the circuit configuration and circuit state of the dynamic reconfiguration unit 131 when the error occurs are reproduced. Can be used for error analysis and debugging.

[Second Embodiment]
In the first embodiment, during execution of a job, the CPU 101 stores register values held in the register unit 133 before reconfiguring the dynamic reconfiguration unit 131 in a circuit corresponding to image processing to be executed next. (Circuit information) is stored in the SRAM 134. In the second embodiment, an example will be described in which the register value (circuit information) held in the register unit 133 is automatically saved without being processed by the CPU 101 in order to reduce the processing load on the CPU 101. . For simplification of description, description of the same configuration and control as in the first embodiment is omitted.

<Configuration of image processing apparatus>
FIG. 5 is a block diagram illustrating a configuration example of the image processing apparatus 100 according to the second embodiment. As shown in FIG. 5, unlike the first embodiment, the image processing apparatus 100 according to the present embodiment further includes a register storage control unit 500 connected to the system bus 120 in the FPGA 140. .

  The register storage control unit 500 stores the register value (circuit information) held in the register unit 133 of the dynamic reconfiguration unit 131 in the SRAM 134 in accordance with an instruction from the CPU 101. Such processing is performed in accordance with the reconfiguration timing of the dynamic reconfiguration unit 131 by the configuration controller 130, as will be described later.

<Reconfiguration control of dynamic reconfiguration unit>
FIG. 6 is a flowchart illustrating a procedure of reconfiguration control of the dynamic reconfiguration unit 131 when the image processing apparatus 100 according to the present embodiment executes a job using the dynamic reconfiguration unit 131. Each process shown in the flowchart of FIG. 6A is realized by the CPU 101 reading out a control program stored in advance in the ROM 104 or the like to the RAM 111 and executing it. The processing executed by the configuration controller 130 and the image processing unit 132 is the same as that in the first embodiment (FIGS. 4B and 4C). Each process shown in the flowchart of FIG. 6B is executed by the register storage control unit 500.

  First, S101 to S109 are the same as those in the first embodiment. If the CPU 101 executes the next reconfiguration (reconfiguration number N + 1) for the dynamic reconfiguration unit 131 in S109 (“YES” in S109), the process proceeds to S201.

  In S <b> 201, the CPU 101 sends an instruction (storage start instruction) indicating that the image processing register value corresponding to the reconstruction number N held in the register unit 133 should be stored in the SRAM 134 via the system bus 120. To the register storage control unit 500. As described above, the CPU 101 instructs to start storing before instructing the configuration controller 130 that the dynamic reconfiguration unit 131 should be reconfigured to a circuit configuration corresponding to the next image processing (second image processing). Is transmitted to the register storage control unit 500. Thereby, the register storage control unit 500 stores the register value set for the register unit 133 for image processing corresponding to the reconstruction number N, which is executed by the image processing unit 132, in the SRAM 134.

  Thereafter, in S202, the CPU 101 waits until receiving a notification (storage completion notification) indicating that the storage of the register value in the SRAM 134 is completed from the register storage control unit 500. By this storage completion notification, the CPU 101 is informed that the next reconfiguration (reconfiguration number N + 1) can be started. When the CPU 101 receives the storage completion notification from the register storage control unit 500 (“YES” in S202), the CPU 101 advances the process to S111, increments the reconstruction number N (increases by 1 from N to N + 1), and performs the process. Return to S104. As a result, the CPU 101 starts control related to the reconfiguration corresponding to the next reconfiguration number N + 1 for the dynamic reconfiguration unit 131.

(Processing of the register storage control unit 500)
When receiving a storage start instruction from the CPU 101, the register storage control unit 500 executes processing according to the procedure shown in FIG. First, in S241, the register storage control unit 500 stands by until a storage start instruction is received from the CPU 101. When the register storage control unit 500 receives the storage start instruction (“YES” in S241), the process proceeds to S242.

  In S <b> 242, the register storage control unit 500 reads out the image processing register value corresponding to the reconstruction number N from the register unit 133 and stores it in the SRAM 134. Further, when storing of the register value in the SRAM 134 is completed (“YES” in S243), the register storage control unit 500 transmits a storage completion notification to the CPU 101 via the system bus 120 in S244, and returns the process to S241. . Thereafter, the register storage control unit 500 enters a standby state in S241 until it receives a register value storage start instruction from the CPU 101 again.

  As described above, in this embodiment, the register storage control unit 500 automatically saves the register value held in the register unit 133 in the SRAM 134 when receiving the notification from the CPU 101. As a result, during the execution of the job, the register value (which is held by the register unit 133 before reconfiguring the dynamic reconfiguration unit 131 in the circuit corresponding to the image processing to be executed next while reducing the load on the CPU 101). Circuit information) can be automatically saved.

<Modification>
As a modification of the above-described second embodiment, processing when an error occurs in the image processing unit 132 can be added as follows.
FIG. 7 is a flowchart illustrating a procedure of reconfiguration control of the dynamic reconfiguration unit 131 when the image processing apparatus 100 according to the present modification executes a job using the dynamic reconfiguration unit 131. Each process shown in the flowchart of FIG. 7 is realized by the CPU 101 reading out a control program stored in advance in the ROM 104 or the like to the RAM 111 and executing it. The processing executed by the configuration controller 130 is the same as that in the first embodiment (FIG. 4B).

  As shown in FIG. 7, the present modification is different from FIG. 6 in that if the CPU 101 does not receive an image processing completion notification from the image processing unit 132 in S108 (“NO” in S108), the process proceeds to S109. Is different. In this case, the CPU 101 determines whether or not a notification indicating that an image processing error has occurred has been received from the image processing unit 132 in S109. When the CPU 101 receives the notification from the image processing unit 132 (“YES” in S109), the CPU 101 ends the execution of the job, and when the notification is not received (“NO” in S109), the process returns to S108. Continue job execution.

(Processing of the image processing unit 132)
In the present modification, when the image processing unit 132 receives an instruction to start image processing from the CPU 101 (S107), the image processing unit 132 executes image processing according to the procedure illustrated in FIG. This modification example is similar to FIG. 4C in that the process proceeds to S231 when the image processing unit 132 has not completed image processing in accordance with the instruction from the CPU 101 in S133 (“NO” in S133). Is different. In this case, in step S231, the image processing unit 132 determines whether an error has occurred during execution of the image processing. If no error has occurred (“NO” in S231), the image processing unit 132 returns the process to S133, and if an error has occurred (“YES” in S231), the image processing unit 132 advances the process to S232. In step S232, the image processing unit 132 transmits a notification indicating that an image processing error has occurred (image processing error notification) to the CPU 101 and the register storage control unit 500 via the system bus 120, and ends the processing. Do

(Processing of the register storage control unit 500)
In the present modification, the register storage control unit 500 executes processing according to the procedure shown in FIG. This modification is different from FIG. 6B in that the register storage control unit 500 advances the process to S245 when the register value storage start instruction is not received from the CPU 101 (“NO” in S241). ing. In this case, the register storage control unit 500 determines whether a notification indicating that an image processing error has occurred has been received from the image processing unit 132. If the notification is not received from the image processing unit 132 (“NO” in S245), the register storage control unit 500 returns the process to S241, and if the notification is received (“YES” in S245). ), The process proceeds to S242.

  When an error occurs in the image processing unit 132, in S242, the register storage control unit 500 reads out the register value held in the register unit 133 at the time of occurrence of the error from the register unit 133 and stores it in the SRAM 134. Further, when storing of the register value in the SRAM 134 is completed (“YES” in S243), the register storage control unit 500 transmits a storage completion notification to the CPU 101 via the system bus 120 in S244, and returns the process to S241. . Thereafter, the register storage control unit 500 enters a standby state in S241 until it receives a register value storage start instruction from the CPU 101 again.

  As described above, in this modification, when an error occurs in the image processing unit 132, the register storage control unit 500 is automatically held in the register unit 133 in response to a notification from the image processing unit 132. The register value (circuit information) is stored in the SRAM 134. As a result, circuit information held by the register unit 133 is automatically saved while reducing the load on the CPU 101 not only during a normal operation in which no error has occurred in the image processing unit 132 but also when an error occurs. It is possible.

  In the present embodiment and this modification, the register storage control unit 500 may be configured inside the dynamic reconfiguration unit 131. In this case, the register storage control unit 500 can be realized with a configuration suitable for the image processing unit 132 and the register unit 133 that can have various circuit configurations according to the job to be executed and the content of the image processing.

[Third Embodiment]
In the first and second embodiments, the register value (circuit information) held in the register unit 133 is stored in the SRAM 134, thereby preventing the circuit information from being lost due to the reconfiguration of the dynamic reconfiguration unit 131. It is out. In the third embodiment, when the logic circuit for realizing a series of image processing functions necessary for each job is reconfigured in the dynamic reconfiguration unit 131 in order by time division, the image processing unit 132 is partially configured. An example in which circuit information is continuously held in the register unit 133 will be described. For simplification of description, description of the same configuration and control as in the first embodiment is omitted.

<Example of dynamic reconfiguration unit reconfiguration>
FIG. 9 is a diagram illustrating an example of a reconfiguration procedure of the dynamic reconfiguration unit 131 when the image processing apparatus 100 executes a copy job. The difference from the first and second embodiments (FIG. 3) is that only the image processing unit 132 of the dynamic reconfiguration unit 131 is to be reconfigured by configuration data, and the register unit 133 is not reconfigured. .

  When the execution of a job is started, the image processing apparatus 100 according to the present embodiment reads out necessary configuration data from the ROM 104 in an order determined according to the type of job, and only the image processing unit 132 of the dynamic reconfiguration unit 131 is read. Reconstruct sequentially. The register unit 133 is configured in advance in the dynamic reconfiguration unit 131 so as to have a storage capacity capable of storing all of the register values used for a series of image processing executed in every job that can be executed by the image processing apparatus 100. Has been.

  In this embodiment, when the execution of a copy job is instructed via the operation unit 103, the image processing apparatus 100 first sets the reconstruction number to “1” as shown in FIG. The image processing unit 132 of the dynamic reconstruction unit 131 is reconfigured using the data 1. Thus, the image processing unit 132 includes the image processing unit A that executes the image processing A. Further, the register unit 133 stores a register value for image processing A. Thereby, the register unit 133 functions as the register unit A.

  When the execution of the image processing A is completed, the image processing apparatus 100 next sets the reconstruction number to “2” and reconfigures the image processing unit 132 of the dynamic reconstruction unit 131 using the configuration data 2. Thereby, the image processing unit 132 includes the image processing unit B that executes the image processing B. Further, the register value for image processing B is newly stored in the register unit 133 while the register value for image processing A is held. As a result, the register unit 133 functions as the register units A and B.

  When the execution of the image processing B is completed, the image processing apparatus 100 next sets the reconstruction number to “3” and reconfigures the image processing unit 132 of the dynamic reconstruction unit 131 using the configuration data 2. Thereby, the image processing unit 132 includes an image processing unit C that executes the image processing C. Further, the register value for image processing C is newly stored in the register unit 133 while the register values for image processing A and B are held. Thereby, the register unit 133 functions as the register units A, B, and C.

  When the execution of the image processing C is completed, the image processing apparatus 100 next sets the reconstruction number to “4” and reconfigures the image processing unit 132 of the dynamic reconstruction unit 131 using the configuration data 2. As a result, the image processing unit 132 includes the image processing unit D that executes the image processing D. Furthermore, the register unit 133 newly stores the register values for the image processing D while holding the register values for the image processing A, B, and C. Thereby, the register unit 133 functions as the register units A, B, C, and D.

  As described above, in the image processing apparatus 100 according to the present embodiment, dynamic reconfiguration is performed in a state where register values (circuit information) for realizing a series of image processing functions necessary for each job are held in the register unit 133. Unit 131 is reconfigured in order by time division. This prevents the circuit information held in the register unit 133 from being lost due to the reconfiguration of the dynamic reconfiguration unit 131 for executing the next image processing, and for each job. An image processing function can be realized.

<Reconfiguration control of dynamic reconfiguration unit>
FIG. 10 is a flowchart illustrating a procedure of reconfiguration control of the dynamic reconfiguration unit 131 when the image processing apparatus 100 according to the present embodiment executes a job using the dynamic reconfiguration unit 131. Each process shown in the flowchart of FIG. 10 is realized by the CPU 101 reading out a control program stored in advance in the ROM 104 or the like to the RAM 111 and executing it. The processing executed by the configuration controller 130 and the image processing unit 132 is the same as that in the first embodiment (FIGS. 4B and 4C).

  First, S101 to S103 are the same as those in the first embodiment. After S103, in S301, the CPU 101 sends a reconfiguration instruction indicating that the reconfiguration corresponding to the reconfiguration number N for the dynamic reconfiguration unit 131 should be executed to the configuration controller 130 via the system bus 120. Send to. At this time, the CPU 101 includes information on the configuration data corresponding to the reconstruction number N shown in FIG. 2B as information on the reconstruction corresponding to the reconstruction number N in the reconstruction instruction, and only the image processing unit 132. Is specified as the area to be reconfigured.

  Thereby, in S122, the configuration controller 130 reads the configuration data from the ROM 104 in accordance with the reconfiguration instruction from the CPU 101, and reconfigures the circuit of only the image processing unit 132 designated as the reconfiguration target area. On the other hand, the configuration controller 130 does not reconfigure the circuit of the register unit 133 that is not designated as an area to be reconfigured. Thereafter, in S105, the CPU 101 waits until a reconfiguration completion notification is received from the configuration controller 130. When the reconfiguration completion notification is received, the CPU 101 proceeds to S106. In S106, the CPU 101 newly sets a register value necessary for executing the image processing corresponding to the reconstruction number N to the register unit 133 via the system bus 120, and advances the processing to S107.

  S107 to S109 are the same as those in the first embodiment. In the present embodiment, when the CPU 101 executes the next reconfiguration (reconfiguration number N + 1) for the dynamic reconfiguration unit 131 (“YES” in S109), the process proceeds to S302. In S302, the CPU 101 does not transfer and store the image processing register value corresponding to the reconstruction number N to the SRAM 134 as in the first embodiment, but stores the register value of the register unit 133 as it is. 133. In this embodiment, only the image processing unit 132 is reconfigured by the reconfiguration instruction in S104, the register unit 133 is not reconfigured, and the register value disappears by the reconfiguration of the register unit 133. Because there is no. As described above, the CPU 101 has the image processing unit 132 in a circuit configuration capable of executing image processing to be executed next while the register value for image processing corresponding to the reconstruction number N is held in the register unit 133. The configuration controller 130 is controlled so as to be reconfigured.

  After that, in S111, the CPU 101 increments the reconstruction number N (increment by 1 from N to N + 1) and returns the process to S104, as in the first embodiment. As a result, the CPU 101 starts control related to the reconfiguration corresponding to the next reconfiguration number N + 1 for the dynamic reconfiguration unit 131.

  As described above, in this embodiment, only the image processing unit 132 is partially reconfigured without performing reconfiguration of the register unit 133 in the dynamic reconfiguration unit 131 during execution of a job. Accordingly, the register value (circuit information) is continuously held in the register unit 133 before the next reconfiguration of the dynamic reconfiguration unit 131 is performed during the execution of the job. As a result, as in the first and second embodiments, it is possible to prevent the circuit information from disappearing along with the reconfiguration of the dynamic reconfiguration unit 131. In addition, after executing the reconfiguration of the dynamic reconfiguration unit 131, the circuit information held in the register unit 133 is used for error analysis and error debugging when an error occurs in the image processing apparatus 100. It becomes possible to do.

<Modification>
As a modification of the above-described second embodiment, processing when an error occurs in the image processing unit 132 can be added as follows.
FIG. 11 is a flowchart illustrating a procedure of reconfiguration control of the dynamic reconfiguration unit 131 when the image processing apparatus 100 according to the present modification executes a job using the dynamic reconfiguration unit 131. Each process shown in the flowchart of FIG. 11 is realized by the CPU 101 reading a control program stored in advance in the ROM 104 or the like into the RAM 111 and executing it. The processing executed by the configuration controller 130 and the image processing unit 132 is the same as that in the first embodiment (FIGS. 4B and 4C).

  First, S101 to S103 are the same as those in the first embodiment. When the processing of S103 is completed, in S311, the CPU 101 issues a reconfiguration instruction indicating that the register unit 133 of the dynamic reconfiguration unit 131 should be reconfigured according to the contents of the designated job. The data is transmitted to the configuration controller 130 via 120. Specifically, the CPU 101 causes the configuration controller 130 to reconfigure the register unit 133 so as to have a storage capacity capable of storing all register values for image processing necessary for the job being executed. For example, in the case of a copy job, the register unit 133 is reconfigured as a circuit having a storage capacity capable of storing register values for image processing A, B, C, and D.

  Thereafter, when the CPU 101 receives a reconfiguration completion notification for the register unit 133 from the configuration controller 130, the process proceeds to S301. The processes after S301 are the same as those in the embodiment shown in FIG.

  As described above, in the embodiment illustrated in FIG. 10, the register unit 133 is not reconfigured after the job execution is started. For this reason, the register unit 133 needs to be configured in advance so as to have a storage capacity capable of simultaneously storing register values for all image processing necessary for each job executable by the image processing apparatus 100. is there. For example, as shown in FIG. 2A, when configuration data corresponding to image processing A to X is stored in the ROM 104, a register having a storage capacity capable of storing a register value used for the image processing A to X The part 133 needs to be prepared.

  On the other hand, in the modification shown in FIG. 11, every time the job is executed, the CPU 101 has a configuration controller so that it has a storage capacity capable of simultaneously storing register values for all image processing necessary for the job. 130 causes the register unit 133 to be reconfigured. For example, as shown in FIG. 2B, the register unit 133 has a storage capacity capable of storing register values used for image processing A to D in the case of a copy job and image processing C to E in the case of a print job. Is reconstructed. Therefore, in this modification, a register unit that holds register values (circuit information) for error analysis and error debugging when an error occurs in the image processing apparatus 100, as compared with the embodiment shown in FIG. The storage capacity of 133 can be minimized.

[Other Embodiments]
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.

100: Image processing device, 131: Dynamic reconfiguration unit, 132: Image processing unit, 133: Register unit, 134: SRAM, 101: CPU, 104: ROM, 111: RAM, 140: FPGA

Claims (13)

A reconfigurable circuit capable of dynamically reconfiguring a part of a circuit configuration, which holds an image processing unit that performs image processing, and circuit information for the image processing that indicates an operation state of the image processing unit The reconfigurable circuit configured with a register unit to
Reconfiguring means for reconfiguring the reconfigurable circuit into a circuit configuration capable of executing image processing required for a job;
After the reconfigurable circuit is reconfigured to a circuit configuration capable of executing the first image processing, the reconfigurable circuit is reconfigured to a circuit configuration capable of executing the second image processing to be executed next. Control means for controlling to store the circuit information held in the register unit in a storage means provided outside the reconfigurable circuit before being configured. apparatus. The control means controls the reconfiguration means so that a plurality of circuit configurations corresponding to a plurality of image processes including the first and second image processes are reconfigured in the reconfigurable circuit in a time division manner. The image processing apparatus according to claim 1, wherein the job that requires the plurality of image processing is executed. The control means determines that the reconfigurable circuit should be reconfigured to a circuit configuration corresponding to the second image processing after the execution of the first image processing using the reconfigurable circuit. The image processing apparatus according to claim 1, wherein the circuit information stored in the register unit is stored in the storage unit before instructing the configuration unit. If no error has occurred in the image processing unit during the execution of the first image processing using the reconfigurable circuit, the control means stores the circuit information held in the register unit. 4. The reconfiguration unit is instructed to reconfigure the reconfigurable circuit in a circuit configuration corresponding to the second image processing without storing in the storage unit. 5. Image processing apparatus. A storage control unit for storing the circuit information held in the register unit in the storage unit;
The control means determines that the reconfigurable circuit should be reconfigured to a circuit configuration corresponding to the second image processing after the execution of the first image processing using the reconfigurable circuit. 3. The storage control unit is instructed to store the circuit information held in the register unit in the storage unit before instructing the configuration unit. The image processing apparatus described. 6. The storage control unit according to claim 5, further comprising: automatically storing the circuit information held in the register unit in the storage unit when an error occurs in the image processing unit. Image processing device. A reconfigurable circuit capable of dynamically reconfiguring a part of a circuit configuration, which holds an image processing unit that performs image processing, and circuit information for the image processing that indicates an operation state of the image processing unit The reconfigurable circuit configured with a register unit to
Reconfiguring means for reconfiguring the image processing unit into a circuit configuration capable of executing image processing required for a job;
After the image processing unit is reconfigured in a circuit configuration capable of executing the first image processing, the circuit information for the first image processing is executed next while being held in the register unit. An image processing apparatus comprising: a control unit that controls the reconfiguration unit so that the image processing unit is reconfigured to have a circuit configuration capable of executing the second power image processing.   The register unit is configured in advance so as to have a storage capacity capable of simultaneously storing the circuit information for all image processing required for each job executable by the image processing apparatus. Item 8. The image processing device according to Item 7.   When the execution of the job is started, the control means has the storage capacity capable of simultaneously storing the circuit information for all image processing required for the job by the reconfiguration means by the register. The image processing apparatus according to claim 7, wherein the unit is reconfigured. The control unit is configured to store the circuit information for the second image processing in the register after the image processing unit is reconfigured to a circuit configuration capable of executing the second image processing by the reconfiguration unit. The image processing apparatus according to claim 7, wherein the image processing apparatus is set in a section. A reconfigurable circuit capable of dynamically reconfiguring a part of a circuit configuration, which holds an image processing unit that performs image processing, and circuit information for the image processing that indicates an operation state of the image processing unit And a register unit configured to control an image processing apparatus including the reconfigurable circuit,
A reconfiguration step of reconfiguring the reconfigurable circuit into a circuit configuration capable of performing image processing required for a job;
In the reconfiguration step, the reconfigurable circuit is reconfigured to a circuit configuration capable of executing the first image processing, and then reconfigured to a circuit configuration capable of executing the second image processing to be executed next. An image processing apparatus comprising: a control step of controlling the circuit information held in the register unit to be stored in a storage unit provided outside the reconfigurable circuit before being configured. Control method. A reconfigurable circuit capable of dynamically reconfiguring a part of a circuit configuration, which holds an image processing unit that performs image processing, and circuit information for the image processing that indicates an operation state of the image processing unit And a register unit configured to control an image processing apparatus including the reconfigurable circuit,
A reconfiguration step of reconfiguring the image processing unit into a circuit configuration capable of executing image processing required for a job;
After the image processing unit is reconfigured in a circuit configuration capable of executing the first image processing, the circuit information for the first image processing is executed next while being held in the register unit. And a control step of controlling the image processing unit to be reconfigured in a circuit configuration capable of executing power second image processing.   The program for functioning a computer as each means of the image processing apparatus of any one of Claim 1 to 10.

Images