JP2015170653A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to inhibit a void from extending and achieve good electrical conduction between an upper layer and a lower layer by a through hole via.SOLUTION: In a semiconductor device, a cross sectional area of a through hole via 4a, 7a is made larger at an intermediate position in a thickness direction of a silicon chip 4, 7 than on a surface side and on a rear face side. A spherical or oval void 4d, 7d is formed at the intermediate position in the thickness direction. This makes it possible to reduce stress applied to a tip position of the void 4d, 7d which is located on the surface side or the rear face side of the silicon chip 4, 7, and the void 4d, 7d is less likely to extend in a height direction of the void 4d, 7d, that is, the thickness direction of the silicon chip 4, 7. Accordingly, the void 4d, 7d can be prevented from passing through the through hole via 4a, 7a in a vertical direction, and electrical conduction can be prevented from being broken caused by an increase in wiring resistance and the occurrence of disconnection.

Description

  The present invention relates to a semiconductor device in which an upper layer and a lower layer are electrically connected by a through-hole via in which a conductor is embedded.

  Conventionally, there is a semiconductor device in which an upper layer and a lower layer are electrically connected by a through-hole via in which a conductor is embedded in the through-hole. For example, a metal such as copper having high conductivity is used as the conductor, and a through hole via is configured by embedding a metal in a through hole formed in a base material such as a silicon substrate.

  However, when a metal such as copper having a high conductivity is completely embedded in the through hole, the metal has a larger coefficient of thermal expansion than the base material. The metal protrudes from the surface, or the metal enters inside from the surface of the substrate due to heat shrinkage. Since there is no margin for thermal expansion and contraction due to temperature changes, the conductor peels off from the contact area with the inner wall surface of the through-hole and the electrode due to stress, and electrical conduction between the upper layer and the lower layer due to the through-hole via cannot be obtained. End up.

  For this reason, Patent Document 1 proposes a structure in which stress is relieved by forming voids in the conductor rather than completely filling the through hole with the conductor. With such a structure, it is possible to take a margin for thermal expansion and thermal contraction due to temperature change, and it is possible to suppress the conductor from peeling off from the inner wall surface of the through hole.

Japanese Patent Laid-Open No. 03-174727

  However, since the void of the structure described in Patent Document 1 is a linear shape extending in the height direction of the through hole at the center of the cylindrical through hole, stress is easily concentrated on both ends of the void. May progress and penetrate the top and bottom of the through-hole via. And since the direction of void growth is not constant, there arises a problem that the wiring resistance increases depending on the direction of progress, or disconnection occurs and electrical conduction cannot be achieved. Further, if the void penetrates the upper and lower sides of the through-hole via during the manufacturing process, there is a problem that a material formed on the upper layer in a subsequent process, for example, a resist in the photo process, enters the void.

  In view of the above points, the present invention provides a semiconductor device that can suppress the progress of voids in a structure in which a void is formed in a through-hole via and can satisfactorily establish electrical conduction between an upper layer and a lower layer by the through-hole via. The purpose is to provide.

  In order to achieve the above object, according to the first aspect of the present invention, the semiconductor device has a front surface and a back surface, and is formed of a semiconductor substrate. Through holes (4b, 7b) are formed from the front surface to the back surface. A through-hole via (4a, 7a) is formed by embedding conductors (4c, 7c) in the through-hole, and a semiconductor chip (4, 7), and the through-hole via has a middle-thickness shape in which the cross-sectional area of the through-hole via is larger than that on the front surface side and the back surface side at an intermediate position in the thickness direction on the way from the front surface to the back surface of the semiconductor chip. The voids (4d, 7d) are formed in the conductor at the portion where the cross-sectional area is enlarged.

  As described above, the cross-sectional area of the through-hole via is larger than that of the front surface side and the back surface side at an intermediate position in the thickness direction of the semiconductor chip. A void is formed at an intermediate position in the thickness direction. In such a configuration, the end portions on the front surface side and the back surface side of the semiconductor chip in the void are rounded, and the stress applied to the tip position on the front surface side and the back surface side of the semiconductor chip in the void can be relieved. It becomes possible, and it becomes difficult for the void to progress in the height direction, that is, the thickness direction of the semiconductor chip. As a result, the void can be prevented from penetrating up and down the through-hole via, and it is possible to suppress an increase in wiring resistance or disconnection resulting in failure to achieve electrical conduction.

  Therefore, in a structure in which a void is intentionally formed in a through-hole via where stress is not easily concentrated, the progress of the void can be suppressed and the electrical conduction between the upper layer and the lower layer by the through-hole via can be satisfactorily taken. It becomes possible to set it as an apparatus.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

It is a figure showing the section composition of the semiconductor device concerning a 1st embodiment of the present invention. It is the figure which expanded the vicinity of the through-hole via of the semiconductor device shown in FIG. FIG. 2 is a cross-sectional view showing a through hole via formation process in the semiconductor device shown in FIG. 1.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described. In the present embodiment, a semiconductor device in which silicon chips are arranged in multiple layers to form a three-dimensional module will be described as an example.

  As shown in FIG. 1, the semiconductor device 1 according to the present embodiment is configured by mounting a plurality of silicon chips 3 to 8 on an interposer 2.

  A wiring pattern (not shown) is formed on the interposer 2, and the stacked silicon chips 3 to 5 and the stacked silicon chips 6 to 8 are joined to the interposer 2 by flip chip mounting or the like. As a result, the semiconductor device 1 is configured as a module having a three-dimensional structure. For example, the interposer 2 is composed of a multilayer wiring board or the like, and pads connected to the wiring pattern are formed at positions different from the silicon chips 3 to 8 on the front surface side where the silicon chips 3 to 8 are mounted, or on the back surface. The pad can be electrically connected to the outside.

  The silicon chips 3 and 5 are formed with semiconductor elements, wiring layers, pad portions, and the like (not shown), and are electrically connected to each other by, for example, flip chip mounting through through-hole vias 4a formed in the silicon chip 4. ing. That is, the silicon chip 3 disposed in the upper layer of the through-hole via 4a and the silicon chip 5 disposed in the lower layer are electrically connected through the through-hole via 4a. Then, by mounting the silicon chips 3 to 5 on the interposer 2, the semiconductor elements and the like formed on the silicon chips 3 to 5 and the wiring pattern formed on the interposer 2 are electrically connected.

  Similarly, semiconductor elements, wiring layers, pad portions, and the like (not shown) are formed on the silicon chips 6 and 8, and are electrically connected to each other by, for example, flip-chip mounting via through-hole vias 7a formed on the silicon chip 7. It is connected to the. That is, the silicon chip 6 disposed in the upper layer of the through-hole via 7a and the silicon chip 8 disposed in the lower layer are electrically connected via the through-hole via 7a. Then, by mounting the silicon chips 6 to 8 on the interposer 2, the semiconductor elements and the like formed on the silicon chips 6 to 8 and the wiring pattern formed on the interposer 2 are electrically connected.

  In the semiconductor device 1 configured as described above, the structure of the through-hole vias 4a and 7a is as follows so that the upper layer and the lower layer can be electrically connected through the through-hole vias 4a and 7a.

  Specifically, as shown in FIG. 2, the through-hole vias 4a and 7a are configured by embedding conductors 4c and 7c, for example, metal such as copper, in the through-holes 4b and 7b. In the case of the present embodiment, the through-hole vias 4a and 7a have a cross-sectional area (opening diameter) at an intermediate position in the thickness direction that is halfway from the front surface to the back surface compared to the front surface side and the back surface side of the silicon chips 4 and 7. It is an enlarged middle fat shape. In the through hole vias 4a and 7a, voids 4d and 7d are provided in the conductors 4c and 7c at an intermediate position in the thickness direction where the cross-sectional area is increased. The voids 4d and 7d are configured by being filled with vacuum or air.

  More specifically, as the through-hole vias 4a and 7a progress from the front surface side to the back surface side of the silicon chips 4 and 7, the cross-sectional area gradually increases from the state in which the cross-sectional area becomes substantially constant. It has a reverse taper shape with inclined wall surfaces. Further, the through-hole vias 4a and 7a have a tapered shape in which the inner wall surfaces are inclined so that the cross-sectional area becomes substantially constant again when proceeding further to the back side of the silicon chips 4 and 7, and then gradually reduced. . Then, when the through-hole vias 4a and 7a further proceed to the back surface side of the silicon chips 4 and 7, the cross-sectional area again becomes substantially constant, and then reaches the back surfaces of the silicon chips 4 and 7. Of these, the inner wall surface has a rounded shape at the portion where the cross-sectional area of the through-hole vias 4a and 7a changes from expansion to reduction.

  The voids 4d and 7d are formed inside the through-hole vias 4a and 7a configured as described above. Specifically, the through-holes 4b and 7b are completely filled with the conductors 4c and 7c on the front surface side and the back surface side of the silicon chips 4 and 7, but the inner wall surface at the intermediate position in the thickness direction of the silicon chips 4 and 7 The conductors 4c and 7c are formed by a predetermined thickness. For this reason, voids 4d and 7d are formed at the intermediate positions in the thickness direction of the silicon chips 4 and 7. The shapes of the voids 4d and 7d are such that the end portions on the front surface side and the back surface side of the silicon chips 4 and 7 are rounded, such as a spherical shape or an elliptical shape. The diameters of the voids 4d and 7d are smaller than the diameters of the through-hole vias 4a and 7a, so that the conductivity between the front surface side and the back surface side of the silicon chips 4 and 7 can be maintained. .

  As described above, the semiconductor device 1 according to the present embodiment is configured. In the semiconductor device 1 configured as described above, the cross-sectional areas of the through-hole vias 4a and 7a are larger than those on the front surface side and the back surface side at intermediate positions in the thickness direction of the silicon chips 4 and 7. Then, spherical or elliptical voids 4d and 7d are formed at an intermediate position in the thickness direction. Thus, the tips of the voids 4b and 7b are rounded.

  Accordingly, it is possible to relieve the stress applied to the tip positions on the front and back sides of the silicon chips 4 and 7 in the voids 4d and 7d, and the voids 4d and 7d are in the height direction, that is, the silicon chips 4 and 7 It becomes difficult to progress in the thickness direction. As a result, the voids 4d and 7d can be prevented from penetrating the through-hole vias 4a and 7a in the vertical direction, and it is possible to suppress an increase in wiring resistance or disconnection resulting in failure of electrical conduction. .

  Therefore, in the structure in which the voids 4d and 7d are formed in the through-hole vias 4a and 7a, the progress of the voids 4d and 7d can be suppressed, and the electrical conduction between the upper layer and the lower layer by the through-hole vias 4a and 7a can be favorably taken. It is possible to obtain a semiconductor device capable of satisfying the requirements.

  Note that the voids 4d and 7d are not limited to one in the through-hole vias 4a and 7a, but may be divided into a plurality. The voids 4d and 7d are preferably not included in the through-hole vias 4a and 7a that are not included in the portion where the cross-sectional area of the front surface side or the lower surface side of the silicon chips 4 and 7 is the smallest, and the cross-sectional area is enlarged. It is good to be in a state where it is located only within the area. By doing in this way, the dimension of the voids 4d and 7d in the thickness direction of the silicon chips 4 and 7 can be reduced, and the voids 4d and 7d can be further prevented from being tapered. Thereby, it can suppress more that the voids 4d and 7d will be in the state which penetrated the front and back of the silicon chips 4 and 7 like the case where it becomes a tapered shape.

  Subsequently, a method for manufacturing the semiconductor device 1 according to the present embodiment will be described. Since the manufacturing method of the semiconductor device 1 is the same as the conventional method except for the steps of forming the through-hole vias 4a and 7a, the through-hole via 4a and 7a will be mainly described.

  First, silicon chips 3 to 8 are prepared. The silicon chips 3, 5, 6, and 8 can be created by performing a device forming process on a normal silicon substrate. The silicon chips 4 and 7 are produced by the following method, for example.

  As shown in FIGS. 3A to 3E, a silicon substrate 10 is prepared, a mask material 11 such as a resist or an oxide film is disposed thereon, and the mask material 11 is opened at a position where the through-hole via 4a is formed. Let Then, the through hole 12 is formed by etching the silicon substrate 10 at the location where the mask material 11 is opened. At this time, when etching is performed, the through hole 12 is formed by performing a so-called Bosch process in which etching is performed step by step while covering the side wall of the through hole 12 with a protective film.

First, as shown in FIG. 3A, the through hole 12 is formed vertically from the surface of the silicon substrate 10 to a predetermined depth. For example, while etching is performed using SF ₆ as an etching gas, not only a side wall protective film such as C ₄ F ₈ is used to protect the side wall of the through hole 12 formed thereby, but the etching gas is, for example, He. By switching to a mixed gas of O _2, a strong protective film 13 is formed on the inner wall surface of the through hole 12. When a mixed gas of He and O ₂ is used, the protective film 13 made of SiO ₂ can be formed by the reaction between silicon and oxygen constituting the silicon substrate 10. Etching of the through hole 12 is advanced while the inner wall surface is protected by the protective film 13 by alternately repeating the introduction of the etching gas and the gas for forming the protective film 13.

In this case, increasing the proportion of O ₂ in the mixed gas of He and O _2, for example, when the ratio of O ₂ in the mixed gas to 40%, because it can further increase the protective film 13, forming the middle of the through hole 12 Is removed preferentially over the side walls. Thereby, the through hole 12 can be formed perpendicular to the surface of the silicon substrate 10.

Next, as shown in FIG. 3B, when the through hole 12 is further deepened from a predetermined depth, etching is performed under the condition that the cross-sectional area of the through hole 12 gradually increases. Specifically, as in FIG. 3A, the sidewall of the through hole 12 is protected by the protective film 13 while the bottom of the through hole 12 is etched. That is, while performing etching using, for example, SF ₆ as an etching gas, not only the sidewall protective film such as C ₄ F ₈ is used as the etching gas, but also the inner wall surface of the through hole 12 by switching to a mixed gas of He and O ₂ , for example. A protective film 13 is formed on the etching gas, but Cl _{2 serving} as an etching accelerating gas is added to the etching gas so that lateral etching is superior to the side wall protection by the protective film 13 in a portion where etching is newly performed. To do. As a result, a portion where etching is newly advanced, that is, a portion where the protective film 13 is thin, also proceeds in the lateral direction etching, and becomes an inversely tapered shape in which the inner wall surface is inclined so that the cross-sectional area of the through hole 12 is gradually enlarged. .

  Note that, by the lateral etching at this time, the surface side of the silicon substrate 10 in the through hole 12 is also slightly etched in the lateral direction, and has a slightly reverse tapered shape with respect to the surface of the silicon substrate 10.

  Further, as shown in FIG. 3C, the etching is further advanced from the reverse tapered portion. At this time, the silicon substrate 10 is etched again so that the cross-sectional areas of the through holes 12 are the same. For example, etching for forming the through hole 12 is performed under the same etching conditions as in the step shown in FIG.

Subsequently, as shown in FIG. 3D, when the through hole 12 is further deepened, etching is performed under the condition that the cross-sectional area of the through hole 12 gradually decreases. Specifically, as in FIG. 3A, the etching of the through hole 12 is advanced by adjusting the mixing ratio when the protective film 13 protects the side wall of the through hole 12. That is, while performing etching using, for example, SF ₆ as an etching gas, not only the sidewall protective film such as C ₄ F ₈ is used as the etching gas, but also the inner wall surface of the through hole 12 by switching to a mixed gas of He and O ₂ , for example. A protective film 13 is formed.

In this case, lowering the proportion of O ₂ in the mixed gas of He and O _2, for example, the proportion of O ₂ in the mixed gas when the 20% or less, can be thinner protective film 13. For this reason, the protective film 13 on the side wall surface is also thinned before the bottom of the through-hole 12 being formed is sufficiently removed, so that the next protective film 13 is formed in a shorter time. It will be switched. For this reason, the next protective film 13 is formed before the cross-sectional area of the bottom of the through hole 12 becomes large, so that the cross-sectional area of the through hole 12 can be gradually reduced.

  Finally, as shown in FIG. 3C, etching is further advanced from the tapered portion. At this time, the silicon substrate 10 is etched again so that the cross-sectional areas of the through holes 12 are the same. For example, etching for forming the through hole 12 is performed under the same etching conditions as in the step shown in FIG.

  In this way, as it proceeds from the front surface side to the back surface side of the silicon substrate 10, the cross-sectional area becomes an inversely tapered shape in which the inner wall surface is inclined so that the cross-sectional area gradually increases from the state where it is substantially constant, Further, when proceeding to the back surface side, the through-hole 12 having a substantially constant cross-sectional area is formed again after the cross-sectional area has changed from enlargement to reduction.

  Thereafter, although not shown, the through hole 12 is filled with the conductor 14 by performing copper plating or the like. As a result, the conductor 14 is formed with a predetermined film thickness on the inner wall surface of the through hole 12, and a void is formed in the conductor 14 in the portion of the through hole 12 where the cross-sectional area is large. If the process for forming the conductor 14 at this time is performed in a vacuum (or a reduced-pressure atmosphere close to vacuum), the void is constituted by a vacuum, and if performed in the atmosphere, the void is filled with the atmosphere.

  As described above, a structure in which a void is formed in the conductor 14 while the through hole 12 is filled with the conductor 14 is configured. Then, by dividing the silicon substrate 10 into chips, the silicon chips 4 and 7 shown in FIG. 1 can be formed. Then, the silicon chips 4 and 7 thus formed are stacked on the interposer 2 together with the other silicon chips 3 and 5 and the silicon chips 6 and 8, and bonded by flip chip mounting or the like, so that the semiconductor of this embodiment The device is completed.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, in the above embodiment, as the through-hole vias 4a and 7a have a structure in which the cross-sectional area is gradually enlarged from the surface side to the back side as the silicon chips 4 and 7 progress from the front side to the back side. An example is given of a shape that has become almost constant again and then gradually reduced and then becomes almost constant. However, this is merely an example, and it is sufficient that the cross-sectional area is enlarged at an intermediate position in the thickness direction in the middle from the front surface to the back surface of the silicon chips 4 and 7.

  In the above embodiment, an example of a semiconductor device to which a through-hole via is applied has been described as an example. Specifically, the case where a silicon substrate is used as a semiconductor substrate on which through-hole vias are formed is given as an example. However, this is merely an example, and the present invention can be applied to the case where the through-hole via is formed using another semiconductor material, for example, a compound semiconductor such as silicon carbide.

  In the above embodiment, an example is shown in which one void 4d, 7d is formed in each through-hole via 4a, 7a. However, the void 4d, 7d may be formed in a plurality of parts. Also in this case, if each of the voids 4d is formed in the middle-thick shape in which the cross-sectional area of the through-holes 4b and 7b is enlarged at the middle position in the thickness direction of the silicon chips 4 and 7 as in the through-hole vias 4a and 7a. , 7d can be made the same shape as the above embodiment.

  In the above-described embodiment, the voids 4d and 7d are filled with vacuum or air. However, the configuration is such that the conductors 4c and 7c are extruded by the material constituting the voids 4d and 7d. This is because it can be avoided. That is, if the voids 4d and 7d are filled with a material having a larger thermal expansion coefficient than the conductors 4c and 7c, the conductors 4c and 7c are expanded from the inside during thermal expansion. Thereby, the stress generated between the inner wall surfaces of the through holes 4b and 7b is increased, and the conductors 4c and 7c may be peeled off from the inner wall surfaces of the through holes 4b and 7b. For this reason, it is preferable that the voids 4d and 7d are made of a material whose vacuum or thermal expansion coefficient is smaller than that of the conductors 4c and 7c.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Interposer 3-8 Silicon chip 4a, 7a Through-hole via 4b, 7b, 12 Through-hole 4c, 7c, 14 Conductor 4d, 7d Void 10 Silicon substrate 11 Mask material 13 Protective film

Claims (5)

It has a front surface and a back surface, is composed of a semiconductor substrate, and through holes (4b, 7b) are formed from the front surface to the back surface, and conductors (4c, 7c) are embedded in the through holes. Through-hole vias (4a, 7a) are formed, and there are semiconductor chips (4, 7) that electrically connect the front surface side and the back surface side through the through-hole vias,
The through-hole via has a middle-thick shape in which the cross-sectional area of the through-hole via is larger than that of the front surface side and the back surface side at an intermediate position in the thickness direction that is halfway from the front surface to the back surface of the semiconductor chip. The semiconductor device is characterized in that voids (4d, 7d) are formed in the conductor at a portion where the cross-sectional area is enlarged.   2. The semiconductor device according to claim 1, wherein the void has a shape in which end portions on a front surface side and a back surface side of the semiconductor chip are rounded.   The semiconductor device according to claim 1, wherein the void is filled with a material having a vacuum or a thermal expansion coefficient smaller than that of the conductor.   The said void is located only in the part by which the cross-sectional area was expanded rather than the said surface side and the said back surface side among the said through-hole vias, The Claim 1 characterized by the above-mentioned. Semiconductor device.   4. The void according to claim 1, wherein the void has a size smaller than a diameter of the through-hole via, and conductivity between the front surface side and the back surface side of the through-hole via is maintained. The semiconductor device according to any one of the above.

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