JP2015073147A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide, by an easy method, a semiconductor device which allows a gate pulse current to flow through gate resistance of an intended resistance value while inhibiting oscillation of a switching element.SOLUTION: A semiconductor device comprises: a switching element having a gate terminal; gate resistance connected to the gate terminal; and an impedance reduction part connected to the gate resistance. Impedance of the impedance reduction part against an oscillating frequency of an oscillating circuit formed inside the switching element is smaller than impedance of the gate resistance against the oscillating frequency, and flow of an oscillating current of the oscillating circuit through the impedance reduction part causes an absolute value of the impedance against the oscillating frequency on the side from the gate terminal to the gate resistance to be smaller than an absolute value of impedance against the oscillating frequency on the side from the gate terminal to the switching element.

Description

  The present invention relates to a semiconductor device used, for example, for switching a large current.

  An oscillation circuit may be formed inside a switching element such as an IGBT. Patent Document 1 discloses a technique for suppressing oscillation of a switching element. This technique suppresses oscillation without impairing the switching speed of the switching element by increasing the resistance value of the gate electrode of the switching element “as it is closer to the gate pad”. That is, since the oscillation is likely to occur in a portion where the resistance value of the gate electrode is small, the resistance value in that portion is increased.

JP 2012-23234 A

  It is preferable to provide a semiconductor device in which the gate pulse current of the switching element flows through the gate resistance having a desired resistance value while suppressing the oscillation of the switching element by an easy method. However, in the technique disclosed in Patent Document 1, as the resistance value of the gate resistance is partially increased, it is necessary to redesign a chip for forming a switching element. Therefore, there was a problem that cost and time were required.

  The present invention has been made to solve the above-described problems, and provides an easy method for a semiconductor device in which a gate pulse current flows through a gate resistance having a desired resistance value while suppressing oscillation of a switching element. For the purpose.

  A semiconductor device according to the present invention includes a switching element having a gate terminal, a gate resistance connected to the gate terminal, and an impedance reduction unit connected to the gate resistance, and is formed inside the switching element. The impedance of the impedance reduction unit with respect to the oscillation frequency of the oscillation circuit is smaller than the impedance of the gate resistance with respect to the oscillation frequency, and the oscillation current of the oscillation circuit flows through the impedance reduction unit, so that the gate terminal The absolute value of the impedance with respect to the oscillation frequency on the resistance side is smaller than the absolute value of the impedance with respect to the oscillation frequency on the switching element side from the gate terminal.

  Another semiconductor device according to the present invention includes a switching element having a gate terminal, a gate signal line connected to the gate terminal, a capacitor connected in series to the gate signal line, and both terminals of the capacitor. A gate resistor connected in parallel with the capacitor by a drawn signal line, and the impedance of the capacitor with respect to the oscillation frequency of the oscillation circuit formed inside the switching element is the gate with respect to the oscillation frequency. When the oscillation current of the oscillation circuit is smaller than the impedance of the resistor and flows through the capacitor, the absolute value of the impedance with respect to the oscillation frequency from the gate terminal to the gate resistance side becomes the oscillation from the gate terminal to the switching element side. Characterized by being smaller than the absolute value of impedance with respect to frequency

  According to the present invention, since the impedance reduction unit that allows the oscillation current to flow and does not flow the gate pulse current is provided, the gate pulse current can flow to the gate resistance having a desired resistance value while suppressing the oscillation of the switching element.

1 is a circuit diagram of a semiconductor device according to a first embodiment of the present invention. It is a test circuit diagram. It is a figure which shows a gate voltage waveform and a gate current waveform. It is a figure which shows a gate voltage waveform and a gate current waveform. It is the figure which expanded the gate current waveform of 6 microsecond vicinity of FIG. It is a figure which shows a gate voltage waveform and a gate current waveform. It is a figure which shows a gate voltage waveform and a gate current waveform. It is a test circuit diagram of a semiconductor device concerning a modification. It is a circuit diagram of the semiconductor device which concerns on Embodiment 2 of this invention. It is a test circuit diagram. It is a figure which shows a gate voltage waveform and a gate current waveform. It is a figure which shows a gate voltage waveform and a gate current waveform. It is a circuit diagram of the semiconductor device which concerns on Embodiment 3 of this invention. It is a test circuit diagram. It is a circuit diagram of the semiconductor device which concerns on Embodiment 4 of this invention. It is a test circuit diagram. FIG. 10 is a circuit diagram of a semiconductor device according to a fifth embodiment of the present invention. It is a test circuit diagram. It is a graph which shows the frequency dependence of the impedance of a capacitor. It is a top view which shows the structure on the base plate of a semiconductor device. It is a figure which shows a gate voltage waveform and a gate current waveform. It is a circuit diagram of the semiconductor device which concerns on Embodiment 6 of this invention. It is a circuit diagram of the semiconductor device which concerns on Embodiment 7 of this invention. It is a circuit diagram of the semiconductor device which concerns on Embodiment 8 of this invention.

  A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram of a semiconductor device 10 according to the first embodiment of the present invention. The semiconductor device 10 has a switching element 12 formed of an IGBT chip. The switching element 12 has a gate terminal 12a. A gate resistor 14 is connected to the gate terminal 12a. More specifically, the gate resistor 14 is connected in series to the gate signal line connected to the gate terminal 12a. The gate resistor 14 includes a balance resistor 14a and an external gate resistor 14b connected in series. The balance resistor 14a and the switching element 12 constitute a semiconductor module by being accommodated in one housing. For example, the balance resistor 14a and the switching element 12 are fixed to a base plate in the housing.

  On the other hand, the external gate resistor 14b is provided outside the semiconductor module. The resistance value of the balance resistor 14a is 12Ω. The resistance value of the external gate resistor 14b is 20Ω. An impedance reduction unit 16 is connected in parallel to the external gate resistor 14b which is a part of the gate resistor 14.

  The impedance reduction unit 16 includes a capacitor 16a and an inductance 16b. Therefore, the impedance reduction unit 16 constitutes an LC series resonance circuit. The electric capacity of the capacitor 16a is 2 nF. The value of the inductance 16b is 9.93 nH. The resonance frequency of the impedance reduction unit 16 (hereinafter simply referred to as the resonance frequency refers to the resonance frequency of the impedance reduction unit 16) is 35.7 MHz. The impedance reducing unit 16 functions as a band pass filter whose impedance becomes 0 with respect to the resonance frequency.

  FIG. 2 is a test circuit diagram for switching the switching element 12 in a short circuit state (arm short circuit state). This test circuit is a circuit that intentionally creates a situation where oscillation occurs in the switching element 12 of the semiconductor device 10 and tests whether oscillation can be suppressed under that situation. The collector of the switching element 12 is connected to the DC voltage power supply 20 by wiring. An inductance 22 is generated by the wiring. Further, a load inductance 24 is generated on the collector side of the switching element 12. However, since the switching element 12 is in a short-circuited state, the inductance 24 has a very small value of about 3.2 nH, for example.

  The resistance of the gate wiring in the switching element 12 is a gate wiring resistance 26. The inductance of the gate wiring in the switching element 12 is a gate wiring inductance 28. The electrostatic capacity between the gate wiring and the emitter wiring in the switching element 12 is the electrostatic capacity 30. This capacitance 30 can cause the switching element 12 to oscillate (Hartley oscillation). Note that the gate wiring resistor 26, the gate wiring inductance 28, and the electrostatic capacitance 30 exist in the switching element 12.

  In order to supply a gate pulse current (gate voltage) to the switching element 12 via the gate resistor 14, a gate power supply 40 is connected to the external gate resistor 14b. The gate power supply 40 outputs a gate pulse current having a frequency of about 1 MHz (hereinafter referred to as a switching frequency). Note that the output impedance of the gate power supply 40 can be regarded as zero.

  The operation of this test circuit will be described. When an ON signal is applied from the gate power supply 40 to the switching element 12 in a short circuit state, an oscillation circuit having an oscillation frequency of about 35.7 MHz is formed inside the switching element 12. This oscillation circuit is considered to be composed of a gate wiring inductance 28, a capacitance 30, and a capacitance between the gate and emitter of the switching element 12.

  Let Zp be the absolute value of the impedance with respect to the oscillation frequency from the gate terminal 12a to the gate resistor 14 side. Further, the absolute value of the impedance with respect to the oscillation frequency on the switching element 12 side from the gate terminal 12a is Zc. Since the resonance frequency of the impedance reduction unit 16 (LC series resonance circuit) is 35.7 MHz and the oscillation frequency of the oscillation circuit is 35.7 MHz, both are equal. Therefore, since the impedance of the impedance reduction unit 16 with respect to the oscillation frequency is 0, Zp is 12Ω, which is the impedance of the balance resistor 14a.

  Zc is slightly larger than 12Ω but smaller than 20Ω. Thereby, since Zp becomes smaller than Zc, the oscillation current in the switching element 12 can be suppressed by flowing an oscillation current to the gate power supply 40 side. As described above, the oscillation current of the oscillation circuit flows through the impedance reduction unit 16 so that Zp <Zc. If the impedance reduction unit 16 is not provided, Zp is 32Ω and Zc is 12 to 20Ω, so that Zp <Zc cannot be established.

  FIG. 3 is a diagram showing a gate voltage waveform and a gate current waveform when an ON signal is applied to a short-circuited switching element in the test circuit of FIG. It can be seen from the gate voltage waveform and the gate current waveform that the oscillation of the switching element 12 is suppressed.

  On the other hand, the impedance of the impedance reduction unit 16 (LC series resonance circuit) with respect to the switching frequency is a very large value of, for example, 100Ω or more. Therefore, the absolute value of the impedance of the impedance reduction unit 16 with respect to the switching frequency is larger than the absolute value (20Ω) of the impedance of the gate resistance (external gate resistance 14b) with respect to the switching frequency.

  Therefore, since the gate pulse current transmitted from the gate power supply 40 does not flow through the impedance reduction unit 16 but flows through the external gate resistor 14b, the impedance reduction unit 16 does not affect the switching of the switching element 12. That is, both the external gate resistor 14b and the balance resistor 14a can be used as the gate resistor. As described above, according to the semiconductor device according to the first embodiment of the present invention, the gate pulse current having a desired resistance value can be obtained while suppressing the oscillation of the switching element 12 only by providing the impedance reduction unit 16. Can be shed.

  FIG. 4 shows a gate voltage waveform and a gate current waveform when an ON signal is applied to the short-circuited switching element 12 in the circuit in which the impedance reduction unit 16 is removed from the test circuit of FIG. In this case, the resistance value of the gate resistance is 32Ω. Oscillation is observed in the gate voltage waveform and the date current waveform. Such oscillation may generate electromagnetic waves, which may degrade the gate drive circuit or cause malfunction. Comparing the waveforms of FIG. 4 and FIG. 3, the switching waveform of FIG. 3 is almost the same as the switching waveform of FIG. 4, and oscillation can be suppressed in the case of FIG.

  FIG. 5 is an enlarged view in which the gate current waveform in the vicinity of 6 μs in FIG. 4 is enlarged. It can be seen that the oscillation waveform is a sine wave. It can also be seen that the oscillation frequency is 35.7 MHz. In the first embodiment of the present invention, a resonance frequency that matches the oscillation frequency thus determined is set.

  FIG. 6 shows a gate voltage waveform and a gate current waveform when the external gate resistance is set to 5Ω for the circuit in which the impedance reduction unit 16 is removed from the test circuit of FIG. In this case, the resistance value of the gate resistor is 17Ω by adding the resistance value of 5Ω of the external gate resistor and the resistance value of 12Ω of the balance resistor 14a. Oscillation is observed in the gate voltage waveform and the date current waveform.

  FIG. 7 shows a gate voltage waveform and a gate current waveform when the external gate resistance is set to 1Ω for the circuit in which the impedance reduction unit 16 is removed from the test circuit of FIG. In this case, the resistance value of the gate resistor is 13Ω, which is the sum of the resistance value of 1Ω of the external gate resistor and the resistance value of 12Ω of the balance resistor 14a. No oscillation is seen in the gate voltage waveform and the date current waveform.

  4 and 6 are compared. The gate voltage rises faster as the gate resistance decreases. Also, the smaller the gate resistance, the smaller the oscillation amplitude. Therefore, it is considered that the oscillation circuit of the switching element is not excited by the rising component of the gate voltage, but is excited and amplified by noise due to thermal vibration of the atoms of the switching element 12. Data supporting this idea was also obtained in the simulation.

  4, 6, and 7, it can be seen that by decreasing the resistance value of the external gate resistor, the oscillation current flowing to the gate power supply 40 side increases as Zp is decreased, thereby suppressing the oscillation. This idea is theoretically consistent with the fact that oscillation can be suppressed by increasing the resistance value of the gate wiring inside the switching element (inside the chip).

  Therefore, in a circuit without the impedance reduction unit 16, the oscillation of the switching element 12 can be suppressed by reducing the resistance value of the gate resistor 14 so that Zp <Zc. However, if the resistance value of the gate resistor 14 is made too small, there is a problem that the rise of the gate voltage is accelerated. Therefore, in the first embodiment of the present invention, the impedance reduction unit 16 is provided in which only the oscillation current flows to the gate power supply 40 side and the gate pulse current does not flow. Thereby, since the gate pulse current flows through the gate resistance having a desired resistance value, it is possible to eliminate the adverse effects such as the rise of the gate voltage being accelerated.

  In short, the semiconductor device 10 according to the first embodiment of the present invention simultaneously obtains an oscillation suppression effect that suppresses oscillation of the switching element and a gate resistance maintenance effect that can increase the resistance value of the gate resistance to a desired value. It is.

  The oscillation suppression effect can be obtained by making Zp smaller than Zc. In the semiconductor device 10 according to the first embodiment of the present invention, in order to satisfy this condition, the resonance frequency of the impedance reduction unit 16 is matched with the oscillation frequency, and Zp is reduced to 12Ω. Thus, it is ideal that the impedance of the impedance reduction unit 16 with respect to the oscillation frequency is as low as possible. However, if the impedance of the impedance reduction unit 16 with respect to the oscillation frequency is made smaller than the impedance with respect to the oscillation frequency of the gate resistor (external gate resistor 14b) connected in parallel to the impedance reduction unit 16, Zp can be lowered. Thereby, Zp can be made smaller than Zc.

  By the way, the oscillation frequency f is expressed by the following equation.

  When the inductance of the impedance reduction unit 16 is L and the capacitance is C, the effect of sufficiently reducing Zp can be obtained if the range is (1/2) LoCo <LC <2LoCo.

  The impedance of the impedance reduction unit 16 with respect to the oscillation frequency is preferably less than 0.15 times the impedance of the gate resistor (external gate resistor 14b) connected in parallel with the impedance reduction unit 16 with respect to the oscillation frequency.

  The effect of maintaining the gate resistance can be obtained when the gate pulse current having the switching frequency flows through the gate resistor 14 without flowing through the impedance reducing unit 16. In order to satisfy this condition, the impedance reducing unit 16 has a very high impedance with respect to the switching frequency.

  The impedance of the impedance reduction unit 16 with respect to the switching frequency is preferably larger than 10 times the impedance with respect to the switching frequency of the gate resistor (external gate resistor 14b) connected in parallel with the impedance reduction unit 16.

  The semiconductor device 10 according to the first embodiment of the present invention can be variously modified. Although the balance resistor 14a and the external gate resistor 14b are used as the gate resistor 14, only one of them may be used as the gate resistor. That is, since the above effect can be obtained by providing the impedance reduction unit 16 in parallel with the gate resistance, it does not matter whether there is a gate resistance in which the impedance reduction unit is not connected in parallel.

  In addition, values such as the resistance value described above can be appropriately changed within a range where the effects of the present invention can be obtained. The switching element 12 is not limited to an IGBT chip, and an element that can form an oscillation circuit similarly to the IGBT chip may be used. For example, a chip on which a MOSFET is formed can be used.

  The switching element 12 is often formed of silicon, but may be formed of a wide band gap semiconductor having a band gap larger than that of silicon. Examples of the wide band gap semiconductor include silicon carbide, gallium nitride-based materials, and diamond.

  FIG. 8 is a test circuit diagram of the semiconductor device according to the modification of the first embodiment of the present invention. One end of the impedance reduction unit 16 of this semiconductor device is grounded. Since the impedance of the gate power supply 40 is zero, the effect of the present invention can be obtained even if one end of the impedance reducing unit 16 is connected to the gate resistor 14 and the other end is grounded. These modifications can also be applied to semiconductor devices according to the following embodiments.

Embodiment 2. FIG.
Since the semiconductor device according to the second embodiment of the present invention has much in common with the semiconductor device of the first embodiment, the description will focus on differences from the semiconductor device of the first embodiment. The same applies to the third and fourth embodiments.

  FIG. 9 is a circuit diagram of a semiconductor device according to Embodiment 2 of the present invention. The impedance reduction unit 50 is connected in parallel to the balance resistor 14a. The impedance reduction unit 50 is formed of an LC series resonance circuit including a capacitor 50a and an inductance 50b. The resonance frequency of the impedance reduction unit 50 is equal to the oscillation frequency. The resistance value of the external gate resistor 14b is 12Ω. The resistance value of the balance resistor 14a is 20Ω. Therefore, Zp is 12Ω equal to the resistance value of the external gate resistor 14b.

  FIG. 10 is a test circuit diagram for switching the short-circuited switching element. This test circuit is a circuit that intentionally creates a situation in which oscillation occurs in the switching element 12 of the semiconductor device of FIG. 9 and tests whether oscillation can be suppressed under that situation.

  FIG. 11 is a diagram showing a gate voltage waveform and a gate current waveform when an ON signal is applied to a short-circuited switching element in the test circuit of FIG. It can be seen that the oscillation can be suppressed.

  Since the balance resistor 14a is formed on the base plate of the semiconductor module, the impedance reduction unit 16 connected in parallel with the balance resistor 14a can also be formed into a pattern by patterning the base plate. Therefore, it is possible to form the impedance reduction unit 16 having a precise resonance frequency.

  FIG. 12 is a diagram showing a gate voltage waveform and a gate current waveform when the resistance value of the balance resistor is 12Ω and the resistance value of the external gate resistor is 20Ω in the test circuit of FIG. In this case, Zp is 20Ω. It can be seen from FIG. 12 that oscillation is not suppressed. Oscillation could be suppressed when Zp was 12Ω, and oscillation could not be suppressed when Zp was 20Ω. Therefore, it is considered that Zc is larger than 12Ω and smaller than 20Ω.

Embodiment 3 FIG.
FIG. 13 is a circuit diagram of the semiconductor device according to the third embodiment of the present invention. As the impedance reduction unit, the impedance reduction unit 50 connected in parallel to the balance resistor 14a and the impedance reduction unit 16 connected in parallel to the external gate resistor 14b are provided. The impedance reduction unit 50 in FIG. 13 is referred to as a first LC series resonance circuit. The impedance reduction unit 16 in FIG. 13 is referred to as a second LC series resonance circuit.

  The resonance frequency of the first LC series resonance circuit and the second LC series resonance circuit is the same as the oscillation frequency. Therefore, Zp can be set to zero. FIG. 14 is a test circuit diagram for intentionally creating a situation where oscillation occurs in the switching element 12 of the semiconductor device of FIG. 13 and testing whether oscillation can be suppressed under that situation. Since Zp can be set to 0 as described above, oscillation can be suppressed. Further, since the resistance values of the external gate resistor 14b and the balance resistor 14a do not contribute to Zp, they can be set to arbitrary values without considering Zp reduction.

Embodiment 4 FIG.
FIG. 15 is a circuit diagram of a semiconductor device according to Embodiment 4 of the present invention. The impedance reducing unit 60 includes an LC series resonance circuit connected in parallel to the gate resistor 14 (the external gate resistor 14b and the balance resistor 14a). The LC series resonance circuit has a capacitor 60a and an inductance 60b.

  The resonance frequency of the impedance reduction unit 60 is the same as the oscillation frequency. Therefore, Zp can be set to zero. FIG. 16 is a test circuit diagram for intentionally creating a situation where oscillation occurs in the switching element 12 of the semiconductor device of FIG. 15 and testing whether oscillation can be suppressed under that situation. Since Zp can be set to 0 as described above, oscillation can be suppressed. Further, since the resistance values of the external gate resistor 14b and the balance resistor 14a do not contribute to Zp, they can be set to arbitrary values without considering Zp reduction.

  The semiconductor device of the fourth embodiment and the semiconductor device of the third embodiment have the same effect. However, since only one LC series resonance circuit is required in the semiconductor device of the fourth embodiment, the number of components can be reduced compared to the semiconductor device of the third embodiment that requires two LC series resonance circuits.

  In the semiconductor devices of the first to fourth embodiments, care must be taken not to adversely affect the Hartley oscillation by providing the impedance reduction unit that is a resonance circuit. Since the oscillation waveform may not be a perfect sine wave, sufficient care is required in selecting the resonance frequency of the impedance reduction unit. Further, there may be two or more oscillation frequencies in the switching element. In this case, a resonance circuit having the same resonance frequency as the oscillation frequency may be prepared for each oscillation frequency, and these resonance circuits may be connected in parallel to the gate resistor.

Embodiment 5
Since the semiconductor device according to the fifth embodiment of the present invention has much in common with the semiconductor device of the second embodiment, the description will focus on differences from the semiconductor device of the second embodiment. FIG. 17 is a circuit diagram of the semiconductor device 100 according to the fifth embodiment of the present invention. A gate signal line 101 is connected to the gate terminal 12a. A capacitor 102 is connected in series to the gate signal line 101. The electric capacity of the capacitor 102 is 2 nF. The gate signal line 101a connects the capacitor 102 and the gate terminal 12a. The gate signal line 101b connects the capacitor 102 and the external gate resistor 14b.

  The capacitor 102 functions as an impedance reduction unit. Lead signal lines 104 and 106 are led from both terminals of the capacitor 102, respectively. A gate resistor (balance resistor 108) is connected to the lead signal lines 104 and 106. As a result, the balance resistor 108 is connected in parallel to the capacitor 102. The resistance value of the balance resistor 108 is 20Ω. In addition, an inductance 110 is generated by the lead signal lines 104 and 106. The resistance value of the external gate resistor 14b connected in series to the gate signal line 101 is 12Ω.

  FIG. 18 is a test circuit diagram for intentionally creating a situation where oscillation occurs in the switching element 12 of the semiconductor device of FIG. 17 and testing whether oscillation can be suppressed under that situation. FIG. 19 is a graph showing the frequency dependence of the impedance of the capacitor 102. The impedance of the capacitor 102 is (1 / (Cω)). FIG. 19 also shows the frequency dependence of Lω + 1 / (Cω) for reference. The impedance of the capacitor 102 with respect to the oscillation frequency (35.7 MHz) is as low as about 2Ω.

  Therefore, the impedance (2Ω) of the capacitor 102 with respect to the oscillation frequency is smaller than the impedance (20Ω) of the gate resistance (balance resistor 108) with respect to the oscillation frequency. Further, the absolute value of the impedance (12Ω) from the gate terminal 12a to the oscillation frequency on the gate resistance side is smaller than the absolute value of the impedance (greater than 12Ω) from the gate terminal 12a to the oscillation frequency on the switching element 12 side. That is, the oscillation current of the oscillation circuit flows through the capacitor 102, so that Zp <Zc.

  On the other hand, the impedance of the capacitor 102 with respect to the switching frequency (1 MHz or less) is a sufficiently high value of 100Ω or more. Therefore, the gate pulse current flows through the balance resistor 108 instead of the capacitor 102. As described above, the oscillation suppressing effect and the gate resistance maintaining effect can be obtained at the same time.

  The semiconductor device 100 is characterized in that the impedance reduction unit is formed only by the capacitor 102. FIG. 20 is a plan view showing a configuration on the base plate of the semiconductor device 100. An insulating metallized substrate 122 and a ceramic substrate 124 are formed on the base plate 120. The insulating metallized substrate 122 includes a ceramic pattern and a metal pattern formed on both main surfaces of the ceramic substrate. The switching element 12 is fixed to the insulating metallized substrate 122.

  Gate signal lines 101 a and 101 b are formed on the ceramic substrate 124. One end of the gate signal line 101a is connected to the gate terminal of the switching element 12 by a wire. A connection terminal 126 extending outside the base plate 120 is formed on the gate signal line 101b.

  The capacitor 102 is a chip capacitor that connects the gate signal line 101a and the gate signal line 101b. Lead signal lines 104 and 106 extending from both terminals of the capacitor 102 are connected to gate signal lines 101a and 101b, respectively. The lead signal lines 104 and 106 extend in the Y positive direction from both ends of the capacitor 102. The balance resistor 108 connects the extraction signal line 104 and the extraction signal line 106.

  By the way, in order to determine the resonance frequency of the impedance reduction part of Embodiment 1-4, it is necessary to calculate the inductance and electric capacity of an impedance reduction part beforehand. However, since it is difficult to calculate the inductance, it is preferable to eliminate the inductance from the impedance reduction unit or reduce the inductance.

  The semiconductor device according to the fifth embodiment of the present invention has a reduced inductance. That is, the balance resistor 108 connected by the lead signal lines 104 and 106 is connected to the inductance 110 by the lead signal lines 104 and 106, but the inductance 102 is not connected to the capacitor 102 that does not pass through the lead signal line (or sufficiently small). ). As described above, the resonance frequency can be easily calculated by using the impedance reduction unit that has only the capacitor 102 and can be regarded as having zero inductance.

  Since the short-circuit oscillation is a high frequency phenomenon, the capacitor 102 is a small component having a small electric capacity. As shown in FIG. 20, the small capacitor 102 can be easily mounted on the base plate 120. Further, the capacitor 102 and the balance resistor 108 can be collectively mounted on the base plate 120.

  If the impedance of the capacitor 102 with respect to the switching frequency is larger than the impedance with respect to the switching frequency of the gate resistor (balance resistor 108) connected in parallel with the capacitor 102, the gate pulse current can flow through the balance resistor 108. However, in order to obtain a sufficient gate resistance maintaining effect, the impedance of the capacitor 102 with respect to the switching frequency is preferably greater than 10 times the impedance of the gate resistance (balance resistor 108) with respect to the switching frequency.

である。
そして、キャパシタ１０２のスイッチング周波数に対するインピーダンスは、
１／Ｃω＝２０８．３Ω
となる。
他方、バランス抵抗１０８の抵抗値は２０Ωである。そして、スイッチング周波数（１ＭＨｚ程度）では引出信号線１０４、１０６のインピーダンスは無視できるほど小さい。よって、スイッチング周波数に対するキャパシタ１０２のインピーダンス（２０８．３Ω）は、ゲート抵抗（バランス抵抗１０８）のスイッチング周波数に対するインピーダンス（２０Ω）の１０倍より大きい。この場合、ゲートパルス電流は、キャパシタ１０２には流れず、引出信号線１０４、１０６とバランス抵抗１０８に流れる。従って、キャパシタ１０２はゲートパルス電流に全く影響を与えない。 Actually, the impedance with respect to the switching frequency of the capacitor 102 is calculated.
Capacitance C of capacitor 102: 3 nF
Inductance Lc of the lead signal lines 104 and 106: 20 nH
Gate voltage rise time Ts: 1 μs
Gate voltage rising frequency: f
Gate voltage rise period: T
Angular frequency of gate voltage rise: ω
Then,

It is.
And the impedance with respect to the switching frequency of the capacitor 102 is
1 / Cω = 208.3Ω
It becomes.
On the other hand, the resistance value of the balance resistor 108 is 20Ω. At the switching frequency (about 1 MHz), the impedances of the lead signal lines 104 and 106 are negligibly small. Therefore, the impedance (208.3Ω) of the capacitor 102 with respect to the switching frequency is larger than 10 times the impedance (20Ω) with respect to the switching frequency of the gate resistance (balance resistor 108). In this case, the gate pulse current does not flow through the capacitor 102 but flows through the extraction signal lines 104 and 106 and the balance resistor 108. Therefore, the capacitor 102 has no influence on the gate pulse current.

  If the impedance of the capacitor 102 with respect to the oscillation frequency is smaller than the impedance with respect to the oscillation frequency of the gate resistor (balance resistor 108) connected in parallel with the capacitor 102, the Zp reduction effect by providing the capacitor 102 can be obtained. However, in order to obtain a sufficient oscillation suppression effect, the impedance of the capacitor 102 with respect to the oscillation frequency is preferably less than 0.15 times the impedance of the gate resistance (balance resistor 108) with respect to the oscillation frequency.

である。従ってキャパシタ１０２の発振周波数に対するインピーダンスは、

となる。
発振周波数に対するキャパシタ１０２のインピーダンス（１．４９Ω）は、発振周波数に対するバランス抵抗１０８のインピーダンス（２０Ω）の０．１５倍未満となっている。この場合、発振電流はバランス抵抗１０８を流れず、キャパシタ１０２に流れる。 Actually, the impedance with respect to the oscillation frequency of the capacitor 102 is calculated.
Since the oscillation frequency fo is 35.7 MHz, the angular frequency ωo of oscillation is

It is. Therefore, the impedance of the capacitor 102 with respect to the oscillation frequency is

It becomes.
The impedance (1.49Ω) of the capacitor 102 with respect to the oscillation frequency is less than 0.15 times the impedance (20Ω) of the balance resistor 108 with respect to the oscillation frequency. In this case, the oscillation current does not flow through the balance resistor 108 but flows through the capacitor 102.

  In this case, Zp is 1.49 by adding 1.49 and 12 (the resistance value of the external gate resistor 14b) to 13.49. FIG. 21 is a diagram showing a gate voltage waveform and a gate current waveform when an ON signal is applied to a short-circuited switching element in the test circuit of FIG. It can be seen that the oscillation can be suppressed.

  Further, comparing FIG. 21 showing the gate voltage waveform when the impedance reduction unit is not provided with FIG. 21, it can be seen that the rise of the gate voltage is almost the same, so that the provision of the capacitor 102 does not affect the switching speed.

  The following sixth to eighth embodiments will be described focusing on differences from the fifth embodiment. Further, the description of the test circuit diagram is omitted for the sixth to eighth embodiments.

Embodiment 6 FIG.
FIG. 22 is a circuit diagram of a semiconductor device according to the sixth embodiment of the present invention. This semiconductor device includes a capacitor 150 that functions as an impedance reduction unit. A gate resistor (external gate resistor 156) is connected in parallel with the capacitor 150 by lead-out signal lines 152 and 154 drawn from both terminals of the capacitor 150. Further, the lead signal lines 152 and 154 generate an inductance 158. Since the external gate resistor 156 is outside the semiconductor module, the capacitor 150 is also provided outside the semiconductor module. Therefore, the degree of freedom in design can be ensured as compared with the case where the capacitor is accommodated in the semiconductor module.

Embodiment 7 FIG.
FIG. 23 is a circuit diagram of a semiconductor device according to Embodiment 7 of the present invention. This semiconductor device has a first capacitor 160 to which an external gate resistor 156 is connected in parallel and a second capacitor 162 to which a balance resistor 108 is connected in parallel as capacitors that function as an impedance reduction unit. . First capacitor 160 has the same function as capacitor 102 of the fifth embodiment. Second capacitor 162 has the same function as capacitor 150 of the sixth embodiment. Therefore, Zp can be greatly reduced to increase the oscillation suppression effect.

Embodiment 8 FIG.
FIG. 24 is a circuit diagram of a semiconductor device according to the eighth embodiment of the present invention. This semiconductor device includes a capacitor 200 that functions as an impedance reduction unit. A gate resistor (external gate resistor 206 and balance resistor 208) is connected in parallel with the capacitor 200 by lead-out signal lines 202 and 204 drawn from both terminals of the capacitor 200. Further, an inductance 210 is generated by the lead signal lines 202 and 204. Since this semiconductor device requires only one capacitor, the number of components can be reduced as compared with the semiconductor device of the seventh embodiment. Note that the features of the semiconductor devices in the above embodiments may be combined as appropriate.

  DESCRIPTION OF SYMBOLS 10 Semiconductor device, 12 Switching element, 12a Gate terminal, 14 Gate resistance, 14a Balance resistance, 14b External gate resistance, 16 Impedance reduction part, 16a Capacitor, 16b Inductance, 20 DC voltage power supply, 22,24 Inductance, 26 Gate wiring Resistance, 28 Gate wiring inductance, 30 Capacitance, 40 Gate power supply, 50, 60 Impedance reduction unit, 50a, 60a capacitor, 50b, 60b Inductance, 100 Semiconductor device, 101 Gate signal line, 102 Capacitor, 104, 106 Extraction signal Wire, 108 balance resistor, 110 inductance, 120 base plate, 122 insulating metallized substrate, 124 ceramic substrate, 126 connection terminal, 50,160,162,200 capacitor, 152,154,202,204 lead signal lines

Claims (18)

A switching element having a gate terminal;
A gate resistor connected to the gate terminal;
An impedance reduction unit connected to the gate resistor,
The impedance of the impedance reduction unit with respect to the oscillation frequency of the oscillation circuit formed inside the switching element is smaller than the impedance of the gate resistor with respect to the oscillation frequency,
When the oscillation current of the oscillation circuit flows through the impedance reduction unit, the absolute value of the impedance with respect to the oscillation frequency from the gate terminal to the gate resistance side is the impedance of the impedance with respect to the oscillation frequency from the gate terminal to the switching element side. A semiconductor device characterized by being smaller than an absolute value. The gate resistor has an external gate resistor,
The semiconductor device according to claim 1, wherein the impedance reduction unit includes an LC series resonance circuit connected in parallel to the external gate resistor. The gate resistor has a balance resistor,
The semiconductor device according to claim 1, wherein the impedance reduction unit includes an LC series resonance circuit connected in parallel to the balance resistor. The gate resistor has a balance resistor and an external gate resistor connected in series,
The semiconductor device according to claim 1, wherein the impedance reduction unit includes an LC series resonance circuit connected in parallel to the gate resistor.   5. The semiconductor device according to claim 2, wherein a resonance frequency of the LC series resonance circuit is the same as the oscillation frequency. 6. The gate resistor has a balance resistor and an external gate resistor connected in series,
The impedance reduction unit includes a first LC series resonance circuit connected in parallel to the balance resistor and a second LC series resonance circuit connected in parallel to the external gate resistor. The semiconductor device described.   The semiconductor device according to claim 6, wherein a resonance frequency of the first LC series resonance circuit and the second LC series resonance circuit is the same as the oscillation frequency.   The semiconductor device according to claim 1, wherein the impedance reduction unit includes an LC series resonance circuit having one end connected to the gate resistance and the other end grounded.   The absolute value of the impedance of the impedance reduction unit with respect to the switching frequency of the switching element is larger than the absolute value of the impedance of the gate resistance with respect to the switching frequency. Semiconductor device. A switching element having a gate terminal;
A gate signal line connected to the gate terminal;
A capacitor connected in series to the gate signal line;
A gate resistor connected in parallel with the capacitor by a lead-out signal line drawn from both terminals of the capacitor;
The impedance of the capacitor with respect to the oscillation frequency of the oscillation circuit formed inside the switching element is smaller than the impedance of the gate resistor with respect to the oscillation frequency,
When the oscillation current of the oscillation circuit flows through the capacitor, the absolute value of the impedance with respect to the oscillation frequency from the gate terminal to the gate resistance side is the absolute value of the impedance with respect to the oscillation frequency from the gate terminal to the switching element side. A semiconductor device characterized by being smaller.   The semiconductor device according to claim 10, wherein the gate resistance is a balance resistance.   The semiconductor device according to claim 10, wherein the gate resistance is an external gate resistance.   The semiconductor device according to claim 10, wherein the gate resistor has a balance resistor and an external resistor connected in series. The gate resistor has a balance resistor and an external gate resistor connected in series,
The semiconductor device according to claim 10, wherein the capacitor includes a first capacitor to which the external gate resistor is connected in parallel and a second capacitor to which the balance resistor is connected in parallel.   The semiconductor device according to claim 10, wherein an impedance of the capacitor with respect to a switching frequency of the switching element is greater than 10 times an impedance of the gate resistor with respect to the switching frequency.   16. The semiconductor device according to claim 10, wherein an impedance of the capacitor with respect to the oscillation frequency is less than 0.15 times an impedance of the gate resistance with respect to the oscillation frequency.   The semiconductor device according to claim 1, wherein the switching element is formed of a wide band gap semiconductor.   The semiconductor device according to claim 17, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

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