JP2014197944A - Gate driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that causes power loss or increased heat generation at a switching element because a gate driver placed between the switching element and a PWM control unit of an inverter bridge circuit will produce an invalid or ineffective pulse if its output is applied to a gate of the switching element as it is.SOLUTION: A gate driver A is placed between a PWM control unit 40 and a switching element Q, and a signal transfer element 50 built in it relays a PWM control signal S1 from the PWM control unit 40 and transfers it to a gate of the switching element. Furthermore, a pulse passage control unit 60 provided in series with the signal transfer element 50 detects the pulse width Tp and pulse voltage Vp of the PWM control signal, permits passage of a pulse P2 of the PWM control signal only if the detected pulse width Tp is equal to or more than a pulse width specified value Tpth and the detected pulse voltage Vp is equal to or more than a pulse voltage specified value Vpth, and blocks passage of the pulse P2 otherwise.

Description

  The present invention is interposed between a switching element and a PWM (pulse width modulation) control unit in an inverter bridge circuit or the like of a power conditioner, and relays a PWM control signal from the PWM control unit to the gate of the switching element. It relates to a gate driver for transmission.

  FIG. 8 is a circuit diagram showing a schematic configuration of an inverter in a conventional power conditioner. This type of inverter 100 includes a converter unit 10 that boosts a generated DC voltage, and an inverter unit 20 that converts the DC voltage boosted by the converter unit 10 into an AC voltage synchronized with a commercial power system. .

  In FIG. 8, 10 is a converter unit that receives and boosts a direct-current voltage (DC) and converts it to a larger direct-current output, 20 is an inverter unit that converts direct-current generated by the converter unit 10 into alternating current (AC), and 30. Is a low-pass filter that performs waveform shaping by cutting unnecessary harmonic components contained in the AC output from the inverter unit 20, and 40 is a PWM represented by a microcomputer (microcomputer) that controls the converter unit 10 and the inverter unit 20. The control unit 50 is an electric insulation type signal transmission such as a photocoupler or an electromagnetic relay for electrically insulating the PWM control signals S1 and S2 from the PWM control unit 40 to the switching element Q of the converter unit 10 and the inverter unit 20. An element A is a gate driver including a plurality of signal transmission elements 50.

  As constituent elements of the converter unit 10, L1 is a choke coil of the converter unit 10, Q11 and Q12 are voltage-driven switching elements using a power semiconductor such as an IGBT (insulated gate bipolar transistor) connected in a half bridge type, D11 and D12 Are freewheeling diodes connected in antiparallel to switching elements Q11 and Q12, respectively.

  As constituent elements of the inverter unit 20, Q21, Q22, Q23, and Q24 are voltage-driven switching elements such as IGBTs connected in a full bridge type, and D21, D22, D23, and D24 are switching elements Q21, Q22, Q23, and Q24. Are free-wheeling diodes connected in reverse parallel to each other.

  The low-pass filter 30 on the output stage side of the inverter unit 20 includes a pair of reactors L2 and L3 and an interphase capacitor C1.

  It is from the secondary side of the inverter 100 to the primary side that the electrically insulating signal transmission element 50 is interposed between the output port of the PWM control signal S1 in the PWM control unit 40 and the gate of each switching element Q. This is to avoid disturbance due to power regression in the signal transmission.

  In the converter unit 10, the two switching elements Q11 and Q12 are alternately turned on / off by the PWM control signal S2 from the gate driver A, thereby adjusting the electromagnetic energy accumulated in the choke coil L1 to increase the voltage. .

  When the lower arm switching element Q12 is turned on while the upper arm switching element Q11 is turned off, a current from a DC power supply (storage battery) (not shown) flows along the path of the choke coil L1 → switching element Q12, and electromagnetic energy is applied to the choke coil L1. Is accumulated. Next, when the switching element Q12 of the lower arm is turned off, the energy stored in the choke coil L1 is released, and the current flows into the inverter unit 20 through the freewheeling diode D11 in antiparallel with the switching element Q11. . By alternately repeating the above operation, the voltage of the DC power supply is boosted and supplied to the inverter unit 20.

  In the inverter unit 20, the first pair of switching elements Q 21 and Q 24 and the same second pair of switching elements Q 23 and Q 22 in the diagonal positions of the upper arm and the lower arm, respectively, are connected to the PWM control signal. The on / off control is alternately performed by S2. The first pair of switching elements Q21 and Q24 are ON / OFF controlled simultaneously, and the second pair of switching elements Q23 and Q22 are ON / OFF controlled simultaneously. The off operation (on operation) of the first pair of switching elements Q21 and Q24 and the on operation (off operation) of the second pair of switching elements Q23 and Q22 are performed in synchronization with each other.

  (1) When both of the first pair of switching elements Q21 and Q24 are turned on (at this time, the second pair of switching elements Q23 and Q22 are in the off state), the current from the converter unit 10 is switched from the switching element Q21 to the low-pass It flows through the path of the reactor L2 → the load (not shown) connected to the AC end of the filter 30 → the reactor L3 → the switching element Q24. Thus, a positive half-wave alternating current is obtained.

  (2) Next, when both of the second pair of switching elements Q23 and Q22 are turned on (at this time, the first pair of switching elements Q21 and Q24 are in an off state), the current from the converter unit 10 is changed to the switching element Q23. → Reactor L3 → Load connected to AC terminal (not shown) → Reactor L2 → Flow through switching element Q22. Thus, a negative half-wave alternating current is obtained.

  By alternately repeating the operations (1) and (2) above, a full-wave alternating current is output to the next stage of the low-pass filter 30.

  The PWM control signal S1 output from the PWM control unit 40 drives the light emitting element (light emitting diode) on the secondary side of the photocoupler that is the electrically insulating signal transmission element 50, and the optical signal from the light emitting element is the primary side. The PWM control signal S2 is transmitted to the light receiving element in an electrically insulated state. The PWM control signal S2 output from the light receiving element is applied to the gate of each switching element Q to control the switching element Q on / off.

  The power conditioner includes a power flow operation for supplying power to the DC power source (storage battery) from the commercial power system through the inverter unit 20 to the converter unit 10, and a path from the DC power source (storage battery) to the converter unit 10 to the inverter unit 20. It has two main modes: reverse power flow operation that supplies power to the commercial power system. Here, since it deviates from the gist of the invention, further detailed explanation is omitted.

  FIG. 9 is a waveform diagram for explaining the operation of the gate driver in the conventional power conditioner. FIG. 9B shows a schematic waveform of the PWM control signal S1 output from the PWM control unit 40 to the switching element Q. 9A is a waveform diagram corresponding to the timing of FIG. 9B. The PWM control signal S2 output from the electrically insulated signal transmission element 50 based on the PWM control signal S1 of FIG. The sine wave output waveform from the inverter part 20 when being applied to the gate is shown. FIG. 9C shows a detailed waveform of the pulse P1 of the PWM control signal S1 in a period T1 corresponding to a quarter cycle of FIG. This is a PWM control signal S1 output from the PWM control unit 40 toward the electrically insulating signal transmission element 50.

  The PWM control signal S1 output from the PWM control unit 40 for on / off control of the switching element Q is a pulsed rectangular wave, and in the case of an equivalent sine wave (approximate sine wave unequal width) PWM method, This is a pulse waveform in which the pulse width (time width of the “H” level section) changes in time series. In the period corresponding to a half cycle of a sine wave, the center side is wide, the both end sides are narrow, and the pulse width gradually decreases from the center to both ends. In the case of this method, there is an advantage that the AC waveform generated by the DC-AC conversion in the inverter unit is equivalently a highly accurate sine wave. In addition, performance is superior in noise / vibration, efficiency, and torque pulsation as compared to the rectangular wave PWM method in which a repetitive pattern has a constant pulse width.

JP 2009-124824 A JP 2012-34490 A Japanese Patent No. 4417005

  The above-described equivalent sine wave PWM type gate driver has a problem of power loss in the switching element. Hereinafter, this problem will be described.

  FIG. 9D is a waveform diagram corresponding to the timing of FIG. 9C, and is a waveform of the pulse P2 of the PWM control signal S2 output from the electrically insulating signal transmission element 50 to the switching element Q.

  As shown in the figure, the pulse width of the PWM control signal S1 becomes considerably small in the vicinity of the zero cross point of the sine wave of the AC voltage output from the inverter unit 20. In the electrically insulating signal transmission element 50, when a PWM control signal S1 having a small pulse width is input to the light emitting element, the light transmitting element 50 outputs the light signal from the light emitting element to the light receiving element. In the pulse P2, the peak value (voltage amplitude) decreases. FIG. 9D shows the state.

  As shown in FIGS. 9C and 9D, the pulse width (time width) of each pulse P1 of the PWM control signal S1 is considerably small near the zero cross point of the sine wave. Therefore, the pulse voltage of each pulse P2 of the PWM control signal S2 output from the electrically insulated signal transmission element 50 in response to this may become zero, that is, no output. Alternatively, the pulse voltage may be lower than the conduction threshold level Vth of the voltage-driven switching element Q.

  As an example, for the first input pulse P11, the output pulse P21 has its pulse voltage significantly reduced to zero, and for the second input pulse P12, the output pulse P22 has its pulse voltage decreased. It becomes less than the conduction threshold level Vth, and the third output pulse P23 has a pulse voltage that is greater than the conduction threshold level Vth, but is considerably reduced with respect to the original input pulse P13.

  Even if a pulse having a pulse voltage lower than the conduction threshold level Vth is applied to the gate of the switching element Q, the switching element Q does not perform an inversion operation. Further, although the pulse voltage exceeds the conduction threshold level Vth, even if it is applied to the gate of the switching element Q, the inversion operation of the switching element Q is performed even if it is applied to the gate of the switching element Q. Is unstable or does not reverse.

  That is, an invalid pulse or an invalid pulse is applied to the gate of the switching element Q, and repeatedly applying such a pulse causes an increase in power loss in the switching element. In addition, a problem of heat generation of the switching element is caused.

  In an inverter that is a power conversion device such as a power conditioner, it is important to improve the conversion efficiency. Under such circumstances, a slight decrease in conversion efficiency is a major problem in energy saving.

  Further, even when the pulse width is equal to or greater than the pulse width specified value, the pulse voltage may be lower than the conduction threshold level of the switching element when passing through the electrically insulating signal transmission element. In fact, none of the conventional technologies can cope with this point of view.

  The present invention was created in view of such circumstances, and the power loss of the voltage-driven switching element that occurs during the period when the pulse width of the PWM control signal is small is reduced, and the load of an inverter or the like is reduced. The object is to make it possible to suppress a reduction in the power efficiency of the apparatus.

  Note that the signal transmission element is not necessarily an insulating signal transmission element. The reason is as follows. In other words, when transmitting a pulse for inverting the switching element to the gate of the switching element, the signal transmission element is not necessarily electrically insulated as a measure for reducing the power loss caused by the application of the invalid or invalid pulse. This is because it is not necessary to assume that it is a type.

  In the present invention, it is assumed that each pulse of the PWM control signal output from the signal transmission element toward the switching element is abnormal such that the pulse waveform interferes with the inversion operation of the switching element. In this case, the problem of power loss of the voltage-driven switching element is to be solved by controlling the output of the abnormal pulse.

  The gate driver according to the present invention is interposed between the PWM control unit and the switching element, and relays the PWM control signal from the PWM control unit and transmits it to the gate of the switching element. A signal transmission element is inserted between the input terminal for the PWM control signal from the PWM controller and the output terminal to the gate of the switching element.

  In such a gate driver, in the present invention, a pulse passage control unit is inserted in series with the signal transmission element. The pulse passage control unit detects the pulse width and pulse voltage of the PWM control signal, and only when the detected pulse width is equal to or greater than the pulse width specified value and the detected pulse voltage is equal to or greater than the specified pulse voltage value. The PWM control signal is allowed to pass a pulse, and otherwise it is configured to block the passage of the pulse.

  In the gate driver of the present invention configured as described above, not only the pulse voltage but also the pulse width is checked in the pulse passage control unit, and the pulse of the PWM control signal has a logical product of two elements of the pulse voltage determination and the pulse width determination. Since it is determined whether the waveform is normal or abnormal, it is not necessary to apply a pulse to the switching element gate that is wasted in the inversion operation.

  According to the present invention, the pulse passing control unit is interposed in the signal transmission path of the PWM control signal via the signal transmission element from the PWM control unit to the switching element, and the logical product of two elements of the pulse voltage determination and the pulse width determination Is configured to determine whether the pulse waveform of the PWM control signal is normal or abnormal. Since passage is allowed only for pulses that satisfy both pulse voltage and pulse width, it is not necessary to apply a pulse that is wasted in the inversion operation to the gate of the switching element. As a result, the power loss of the voltage-driven switching element can be reduced, the heat generation of the switching element can be suppressed, and the power efficiency of a load device such as an inverter can be improved.

1 is a schematic configuration diagram of a power conditioner to which a gate driver according to an embodiment of the present invention is applied. Configuration diagram of a gate driver according to an embodiment of the present invention Operational explanatory diagram of the gate driver according to the embodiment of the present invention Configuration diagram of a gate driver according to an embodiment of the present invention Configuration diagram of a gate driver according to an embodiment of the present invention 1 is a circuit configuration diagram of a gate driver according to an embodiment of the present invention. Waveform diagram for explaining the operation of the gate driver of the embodiment according to the present invention The circuit diagram which shows the schematic structure of the inverter in the power conditioner of a prior art Waveform diagram explaining the operation of the gate driver in a conventional power conditioner

  Hereinafter, the gate driver according to the embodiment of the present invention will be described. A gate driver according to the present invention is mainly interposed between a switching element and a PWM control unit in a bridge circuit for power conversion in an inverter unit in an inverter such as a power conditioner or for DC boosting in a converter unit. .

  For each of a plurality of switching elements constituting a bridge circuit of an inverter in a power conditioner or the like (which is composed of a converter for boosting DC and an inverter for DC-AC conversion) A PWM control signal including a pulse train for on / off control is output from the PWM control unit. The role of the gate driver is to relay the PWM control signal by relaying feedback between the PWM control unit and the switching element. The PWM control unit is on the secondary side, and it is necessary to electrically insulate the secondary side from the primary side for feedback control with respect to the bridge circuit on the primary side. The gate driver is provided with an electrically insulating signal transmission element. This signal transmission element is inserted between the input terminal of the PWM control signal from the PWM control unit and the output terminal to the gate of the switching element. A photocoupler comprising a light-emitting element (light-emitting diode) and a light-receiving element (phototransistor) is a suitable example of an electrically insulating signal transmission element, but is not necessarily limited thereto, and an electromagnetic relay, an insulating transformer, etc. It may be. The bridge circuit may be a full bridge circuit or a half bridge circuit. The switching element is a voltage-driven type, and a power semiconductor IGBT (insulated gate bipolar transistor) is a preferred example, but is not necessarily limited thereto, and may be a MOSFET or the like.

  The gate driver includes a pulse passage control unit as a new component in addition to the electric insulation type signal transmission element. This pulse passage control unit is inserted in series with an electrically insulating signal transmission element. The pulse passage control unit detects the pulse width and pulse voltage of the input PWM control signal, determines the pulse width whether the detected pulse width is equal to or greater than the pulse width specified value, and the detected pulse voltage is the pulse voltage specified. The pulse voltage is determined to determine whether the value is greater than or equal to the value. If the detected pulse width is not less than the specified value in the pulse width determination and the detected pulse voltage is not less than the specified value in the pulse voltage determination, the pulse of the PWM control signal is allowed to pass only in that case, In other cases, it has a function of blocking the passage of pulses.

  The pulse passing control unit interposed in the signal transmission path of the PWM control signal between the input terminal and the output terminal of the gate driver has a pulse width and a pulse voltage for the pulse of the PWM control signal that is going to pass therethrough. Is detected. Then, the detection pulse width is compared with a prescribed pulse width value, and the detected pulse voltage is compared with a prescribed pulse voltage value.

  (1) When the detected pulse width is equal to or greater than the pulse width specified value and the detected pulse voltage is equal to or greater than the specified pulse voltage value, the pulse passing control unit passes the pulse of the PWM control signal and the gate of the switching element. To send to.

  (2) Even if the detection pulse width is equal to or greater than the pulse width specified value, if the detected pulse voltage is less than the pulse voltage specified value, the pulse passage control unit blocks the passage of the pulse of the PWM control signal.

  (3) Even if the detected pulse voltage is equal to or higher than the specified pulse voltage value, if the detected pulse width is less than the specified pulse width value, the pulse passage control unit blocks the passage of the pulse of the PWM control signal.

  (4) When the detected pulse width is less than the pulse width specified value and the detected pulse voltage is less than the specified pulse voltage value, this is included in the above (2) or (3), and naturally the pulse passes. The control unit blocks the passage of the PWM control signal pulse.

  Even if it is assumed that the pulse width of the PWM control signal is equal to or greater than the pulse width specified value and the pulse voltage is equal to or greater than the pulse voltage specified value, the pulse passes through the pulse passing control unit and then the gate of the switching element. The voltage amplitude is attenuated before reaching the value, and the pulse voltage may fall below the specified pulse voltage value. Therefore, in the present invention, in order to avoid this inconvenience, the pulse pass control unit also checks the pulse voltage, and if the detected pulse voltage is equal to or higher than the pulse voltage specified value, the pulse is allowed to pass. The passage of pulses is blocked because there is a possibility that the inversion operation of the switching element may be hindered.

  On the other hand, even if the pulse voltage of the PWM control signal is equal to or higher than the pulse voltage specified value, the pulse undergoes pulse width attenuation after passing through the pulse passage control unit and before reaching the gate of the switching element. May be less than the specified pulse width, or may be disturbed by the influence of disturbance noise or the like. Therefore, in the present invention, in order to avoid this inconvenience, not only the pulse voltage but also the pulse width is checked in the pulse passage control unit, and if the detected pulse width is equal to or larger than the pulse width specified value, the passage of the pulse is permitted. If it is less than the value, it is assumed that there is a possibility that the inversion operation of the switching element may be hindered, and the passage of pulses is blocked.

  Since it is determined that the pulse waveform of the PWM control signal is normal or abnormal by the logical product of the above two factors of the pulse voltage determination and the pulse width determination, the pulse application that is wasted in the inversion operation is applied to the gate of the switching element. Does not occur. As a result, it is possible to reduce the power loss of the voltage-driven switching element, and it is possible to suppress a decrease in power efficiency of a load device such as an inverter.

  A gate driver according to a preferred embodiment of the present invention will be described below with reference to the drawings.

  FIG. 1A shows an overall schematic configuration of the power conditioner. In FIG. 1, 1 is a DC power supply unit (storage battery), 2 is a grid connection protection device, 3 is an external power system (commercial AC power supply), 100 is an inverter, 10 is a converter unit, 20 is an inverter unit, and 30 is a low-pass filter. , 40 is a PWM control unit configured as a part of the function of the microcomputer, and A is a gate driver. For example, the voltage waveform is monitored between the low-pass filter 30 and the grid connection protection device 2, and the waveform is stabilized by feedback control from the PWM control unit 40 via the gate driver A.

  FIG. 1B shows a schematic configuration of the gate driver A, 50 is an electrically insulated signal transmission element, and 60 is a pulse passage control unit.

  FIG. 2 is a configuration diagram of the gate driver A showing a more detailed configuration of the pulse passage control unit. 2A and 2B show two different modes. 61 is a pulse voltage determination unit in the pulse passage control unit 60, 62 is a pulse width determination unit in the pulse passage control unit 60, 63 is an input terminal of the gate driver A, 64 is an output terminal, and 65 is an input terminal 63 to an output terminal 64. It is a signal transmission path to reach.

  2A and 2B, the pulse passage control unit 60 includes a pulse voltage determination unit 61 and a pulse width determination unit 62. The pulse voltage determination unit 61 and the pulse width determination unit 62 are inserted in series in the signal transmission path 65.

  In the case of (a) in FIG. 2, the pulse voltage determination unit 61 is positioned in front of the pulse width determination unit 62.

  In the case of (b) of FIG. 2, the pulse width determination unit 62 is positioned upstream of the pulse voltage determination unit 61, contrary to the above.

  The detailed operation of the gate driver A in the case of FIG. 2A is as follows. This will be described with reference to FIG.

  The pulse voltage determination unit 61 in the pulse passage control unit 60 detects the pulse voltage Vp of the pulse P2 of the PWM control signal S2 input from the electrically insulating signal transmission element 50, and the detected pulse voltage Vp is the pulse voltage regulation. A pulse voltage determination is made as to whether or not the value is Vpth or more. If the detected pulse voltage Vp is equal to or higher than the pulse voltage specified value Vpth, the pulse P2 is passed as it is and output to the pulse width determination unit 62.

  The pulse width determination unit 62 in the pulse passage control unit 60 detects the pulse width Tp of the pulse P2 of the PWM control signal S2 input from the pulse voltage determination unit 61, and the detected pulse width Tp is equal to or greater than the pulse width specified value Tpth. The pulse width is determined as to whether or not. If the detected pulse width Tp is equal to or greater than the pulse width specified value Tpth, the pulse P2 is passed as it is and output to the output terminal 64.

  A specific example will be described as follows.

  As shown in FIG. 3A, for the pulse P2 of the PWM control signal S2, if the pulse voltage Vp is equal to or higher than the pulse voltage specified value Vpth, the pulse voltage determination unit 61 passes the pulse P2 (in the upper stage). (See Figure (a)).

  However, if the pulse voltage Vp is less than the pulse voltage specified value Vpth, the pulse voltage determination unit 61 blocks the pulse P2 (see the lower diagram (b)).

  Since the pulse voltage Vp is equal to or higher than the pulse voltage specified value Vpth, the pulse P2 that has passed through the pulse voltage determination unit 61 and is input to the pulse width determination unit 62 is subjected to pulse width determination here. If the pulse width Tp is equal to or greater than the pulse width specified value Tpth, the pulse width determination unit 62 passes the pulse P2 (see FIG. 3C).

  However, if the pulse width Tp is less than the pulse width specified value Tpth, the pulse width determination unit 62 blocks the pulse P2 (see FIG. 4D).

  The detailed operation of the gate driver A in the case of FIG. 2B is as follows. This will be described with reference to FIG.

  The pulse width determination unit 62 in the pulse passage control unit 60 detects the pulse width Tp of the pulse P2 of the PWM control signal S2 input from the electrically insulating signal transmission element 50, and the detected pulse width Tp is the pulse width defining. A pulse width determination is made as to whether the value is equal to or greater than the value Tpth. If the detected pulse width Tp is equal to or greater than the pulse width specified value Tpth, the pulse P2 is passed as it is and output to the pulse voltage determination unit 61.

  The pulse voltage determination unit 61 in the pulse passage control unit 60 detects the pulse voltage Vp of the pulse P2 of the PWM control signal S2 input from the pulse width determination unit 62, and the detected pulse voltage Vp is equal to or higher than the pulse voltage specified value Vpth. The pulse voltage is determined as to whether If the detected pulse voltage Vp is equal to or higher than the pulse voltage specified value Vpth, the pulse P2 is passed as it is and output to the output terminal 64.

  A specific example will be described as follows.

  As shown in FIG. 3B, if the pulse width Tp of the pulse P2 of the PWM control signal S2 is equal to or greater than the pulse width specified value Tpth, the pulse width determination unit 62 passes the pulse P2 (in the upper stage). (See Figure (a)).

  However, if the pulse width Tp is less than the pulse width specified value Tpth, the pulse width determination unit 62 blocks the pulse P2 (see the lower diagram (b)).

  Since the pulse width Tp is equal to or greater than the pulse width specified value Tpth, the pulse P2 that has passed through the pulse width determination unit 62 and is input to the pulse voltage determination unit 61 is subjected to pulse voltage determination here. If the pulse voltage Vp is equal to or higher than the pulse voltage specified value Vpth, the pulse voltage determination unit 61 passes the pulse P2 (see FIG. 3C).

  However, if the pulse voltage Vp is the pulse voltage specified value Vpth, the pulse voltage determination unit 61 cuts off the pulse P2 (see FIG. 4D).

  FIG. 4 shows another embodiment. In the case of FIG. 4, the pulse passage control unit 60 includes a pulse voltage determination unit 61, a pulse width determination unit 62, and a gate unit 66. The gate unit 66 is inserted in series in the signal transmission path 65, and the pulse voltage determination unit 61 and the pulse width determination unit 62 are branched from the signal transmission path 65 between the electrically insulating signal transmission element 50 and the gate unit 66. ing.

  In the case of FIG. 4, the pulse voltage determination unit 61 and the pulse width determination unit 62 have a parallel relationship, not a pre-stage / rear-stage relationship. When the output from the electrically insulating signal transmission element 50 is input to the gate unit 66, the gate unit 66 controls passage allowance / blocking by the logical product of the output of the pulse voltage determination unit 61 and the output of the pulse width determination unit 62. To do.

  The detailed operation of the gate driver A in the case of FIG. 4 is as follows. The pulse P2 of the PWM control signal S2 from the electrically insulating signal transmission element 50 is branched by the signal transmission path 65 and input to the pulse voltage determination unit 61 and the pulse width determination unit 62, where the pulse voltage determination and the pulse are respectively performed. Receive width judgment. The determination signals S61 and S62 are input to the gate unit 66. The gate unit 66 controls passage / cut-off of the pulse P2 from the signal transmission element 50 with the logical product of the two determination signals S61 and S62. That is, if both the determination signal S61 from the pulse voltage determination unit 61 and the determination signal S62 from the pulse voltage determination unit 61 are in an asserted (valid) state, the gate unit 66 passes the pulse P2. In other cases, the pulse P2 is cut off.

  A preferred embodiment of the present invention is shown in FIG. As shown in FIG. 5, in the pulse passage control unit 60, the pulse voltage determination unit 61 is inserted in the subsequent stage of the electric insulation type signal transmission element 50, whereas the pulse width determination unit 62 is an electric insulation type. The signal transmission element 50 is inserted in the previous stage. The pulse voltage determination unit 61 determines the pulse P2 input from the signal transmission element 50 as in FIG. 2, but the pulse width determination unit 62 determines the determination target in FIG. Differently, the pulse P1 of the PWM control signal S1 from the PWM control unit 40 before being input to the signal transmission element 50. In this embodiment, the pulse voltage Vp tends to decrease before and after the passage of the electric insulation type signal transmission element 50, whereas the pulse width Tp is before and after the passage of the electric insulation type signal transmission element 50. This is based on the knowledge that there is almost no change.

  Although illustration is omitted, the concept of the configuration of FIG. 5 may be applied to the configuration of FIG. That is, in FIG. 4, the position of the pulse width determination unit 62 is changed and moved to the previous stage of the electrically insulating signal transmission element 50.

  In the above, a plurality of modes have been described. In any case, a pulse passage control unit is included in the signal transmission path 65 of the PWM control signal via the electrically isolated signal transmission element 50 from the PWM control unit 40 to the switching element Q. 60 is configured to determine normality / abnormality of the pulse waveform of the PWM control signal with a logical product of two elements of pulse voltage determination and pulse width determination. Since the pulse passage control unit 60 allows passage only for a pulse whose pulse voltage and pulse width satisfy both conditions, it is not necessary to apply a pulse that is wasted on the inversion operation to the gate of the switching element Q. . As a result, the power loss of the voltage-driven switching element Q can be reduced, the heat generation of the switching element Q can be suppressed, and the power conversion efficiency of the inverter 100 can be improved.

  The bridge circuit may be a bridge circuit in a DC-AC conversion inverter section in an inverter, or a bridge circuit in a DC boost converter section (DC-DC converter) in the inverter. May be targeted. The bridge circuit may be a full bridge circuit or a half bridge circuit.

  Hereinafter, embodiments of a gate driver according to the present invention will be described in detail with reference to the drawings. In the present embodiment, the configuration of FIG. 8 used in the description of the prior art is followed. However, in this embodiment, the configuration of the gate driver A is different from that of the prior art.

  FIG. 6 is a schematic circuit diagram showing the configuration of the gate driver of the embodiment according to the present invention. As shown in FIG. 6, the gate driver A interposed between the microcomputer (My computer) as the PWM control unit 40 and the gate of each switching element Q in the inverter unit 20 is an electrically isolated signal transmission element 50. A photocoupler 51, an operational amplifier 52 for amplification, a pulse voltage determination unit 61, a pulse width determination unit 62, and a buffer 53 for amplification and waveform shaping. The photocoupler 51 is composed of a light emitting diode 51a and a phototransistor 51b that are opposed to each other with a space therebetween. The buffer 53 is a complementary (complementary) connection of the NPN transistor Q1 and the PNP transistor Q2. As the switching element Q, a power semiconductor IGBT (insulated gate bipolar transistor) is used.

  FIG. 7 is an operation waveform diagram of the gate driver of this embodiment. Since (a), (b), and (c) of FIG. 7 have the same contents as (a), (b), and (c) of FIG. 9 in the case of the prior art, description thereof is omitted. In the case of the present embodiment, as shown in FIG. 7D, the pulse passage control unit 60 has a pulse width in the vicinity of the zero-cross point of the AC voltage sine wave in which the pulse width of the PWM control signal S1 is considerably reduced. The passage of pulses having a pulse width Tp smaller than the prescribed pulse width value Tpth and pulses having a pulse voltage Vp lower than the prescribed pulse voltage value Vpth (P21, P22, P23) is blocked.

  In the case of the prior art, these pulses P21, P22, P23 are passed through and applied to the gate of the switching element Q despite being ineffective for the inversion operation of the switching element Q. Was invited. On the other hand, in the case of the present embodiment, the inconvenience is avoided. As a result, it is possible to reduce the power loss of the voltage-driven switching element Q, and it is possible to suppress a decrease in power conversion efficiency of the inverter.

  A transformer type can also be used as the electrically insulating signal transmission element 50. It can also be applied to a gate driver without an insulating function.

  In the gate driver interposed between the switching element and the PWM control unit in the inverter bridge circuit such as a power conditioner, the present invention outputs invalid or ineffective pulses when output as it is and applied to the gate of the switching element. Even in such a case, it is useful as a technique for blocking the passage of such a pulse and solving the problem of power loss and heat generation in the switching element.

40 PWM controller (microcomputer)
50 Electrically insulated signal transmission elements (photocouplers)
60 Pulse Pass Control Unit 61 Pulse Voltage Judgment Unit 62 Pulse Width Judgment Unit 63 Input Terminal 64 Output Terminal 65 Signal Transmission Path 66 Gate Unit 100 Inverter (Load Device)
A Gate driver Q11, Q12 Switching element (IGBT)
Q21, Q22, Q23, Q24 Switching element (IGBT)
S1 PWM control signal output from the PWM control unit S2 PWM control signal that has passed through the electrical isolation type signal transmission element S61, S62 Determination signal P1 Pulse of the PWM control signal output from the PWM control unit P2 Electrical isolation type signal transmission Pulse of PWM control signal that has passed through the element Vp Pulse voltage Vpth Pulse voltage specified value Tp Pulse width Vpth Pulse voltage specified value

Claims (6)

A gate driver interposed between the PWM control unit and the switching element to relay the PWM control signal from the PWM control unit to the gate of the switching element;
A signal transmission element inserted between an input terminal of a PWM control signal from the PWM control unit and an output terminal to the gate of the switching element;
When inserted in series in the signal transmission element to detect the pulse width and pulse voltage of the PWM control signal, and when the detected pulse width is equal to or greater than the specified pulse width and the detected pulse voltage is equal to or greater than the specified pulse voltage A gate driver comprising a pulse passage control unit that allows passage of pulses of the PWM control signal as long as possible, and blocks passage of pulses in other cases.   The gate driver according to claim 1, wherein the signal transmission element is an electrically insulating signal transmission element that transmits a PWM control signal from the PWM control unit to a gate of the switching element in an electrically insulated state.   The pulse passage control unit detects a pulse voltage of a PWM control signal input from the signal transmission element, performs a pulse voltage determination whether the detected pulse voltage is equal to or higher than a pulse voltage specified value, and outputs a pulse voltage specified value. If it is above, the passage of the PWM control signal is allowed, and if it is less than the pulse voltage specified value, the pulse voltage determination unit for blocking the passage of the PWM control signal, and the PWM control signal input from the signal transmission element Detects the pulse width and determines whether the detected pulse width is equal to or greater than the pulse width specified value. If the detected pulse width is equal to or greater than the pulse width specified value, the PWM control signal is allowed to pass. The gate driver according to claim 1, further comprising: a pulse width determination unit that blocks passage of the PWM control signal.   4. The gate driver according to claim 2, wherein the pulse passage control unit is such that the pulse voltage determination unit is subsequent to the signal transmission element, and the pulse width determination unit is subsequent to the pulse voltage determination unit.   4. The gate driver according to claim 2, wherein the pulse passage control unit includes the pulse width determination unit at a subsequent stage of the signal transmission element and the pulse voltage determination unit at a subsequent stage of the pulse width determination unit.   The pulse passage control unit includes a gate unit that switches between allowing and blocking the passage of the PWM control signal from the signal transmission element, and a detected pulse voltage of the PWM control signal from the signal transmission element is equal to or higher than a specified pulse voltage value. A pulse voltage determination unit that performs a pulse voltage determination and sends the determination signal to the gate unit, and a pulse width determination as to whether the detected pulse width of the PWM control signal from the signal transmission element is equal to or greater than a pulse width specified value And a pulse width determination unit that transmits the determination signal to the gate unit, and the gate unit has a logical product of the determination signal from the pulse voltage determination unit and the determination signal from the pulse width determination unit. The gate driver according to claim 2, wherein the gate driver is configured to allow passage of the PWM control signal.

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