JP2014157906A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method and a semiconductor device, which can avoid decrease in intensity of a connection part such as a micro bump by side etching and a Cu pillar.SOLUTION: A semiconductor device manufacturing method comprises: first forming an electrode 12 and an insulation film 13 on a semiconductor substrate 11; subsequently forming a conductive layer 15 on the insulation film 13 of the semiconductor substrate 11; forming on the conductive layer 15, a resist film having an opening at a part corresponding to the electrode 12; and subsequently forming a metal plating layer 18 on an inner side of the opening of the resist film by electrolytic plating. In this plating process, a plating solution enters between the resist film around the resist opening and the conductive layer to form a flange. The semiconductor device manufacturing method comprises: removing the resist film; subsequently forming an oxide film 15a by oxidizing a surface of the conductive layer 15 at an exposed part; and subsequently removing the oxide film 15a and the conductive layer 15 under the oxide film 15a by etching.

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  In recent years, higher density and higher performance of semiconductor devices have been promoted, and accordingly, a stack type semiconductor device in which a plurality of semiconductor chips are stacked is also increasing. In a stack type semiconductor device, micro bumps and Cu pillars smaller than conventional bumps are used for bonding between chips.

  In the present application, a bump having a UBM (Under Bump Metal) diameter of 85 μm or more is called a normal bump, and a bump smaller than that is called a micro bump. At present, the UBM diameter of micro bumps and Cu pillars is about 30 μm.

JP 2009-302340 A

  It is an object of the present invention to provide a method for manufacturing a semiconductor device and a semiconductor device capable of avoiding a decrease in the strength of connection portions such as micro bumps and Cu pillars due to side etching.

  According to one aspect of the disclosed technology, a step of forming an electrode on a semiconductor substrate, a step of forming an insulating film on a portion corresponding to the electrode on the semiconductor substrate, and the semiconductor A step of forming a conductive layer on the insulating film of the substrate; a step of forming a resist film on the conductive layer with an opening corresponding to the electrode; and an electrolytic plating method to form the resist. A metal plating layer is formed on the conductive layer inside the opening of the film, and the same metal as the metal plating layer is formed between the resist film and the conductive layer around the opening of the resist film. Forming a flange portion, removing the resist film to expose the conductive layer, and oxidizing the surface of the conductive layer exposed by removing the resist film to form an oxide film Process A method of manufacturing a semiconductor device and a step of removing by etching the oxide layer and the conductive layer thereunder are provided.

  According to another aspect of the disclosed technology, a semiconductor substrate, an electrode formed above the semiconductor substrate, a conductive layer formed on the electrode, and a metal plating layer covering the conductive layer And a semiconductor device formed on the metal plating layer and having a metal layer having a smaller diameter than the metal plating layer.

  According to the method for manufacturing a semiconductor device according to the above aspect, the conductive layer is larger than the metal layer by the amount of the flange portion. As a result, a semiconductor device having a high strength of the connection portion can be obtained.

FIG. 1 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a schematic view showing a collar portion formed by the plating solution entering the gap between the resist film and the conductive layer. FIG. 7 is a schematic view showing a plasma ashing apparatus used for oxidizing the conductive layer. FIG. 8 is a view showing a state where a semiconductor device is completed by stacking (stacking) semiconductor chips formed by the method according to the first embodiment on other semiconductor chips. FIG. 9 is a view showing a state where a semiconductor device is completed by mounting a semiconductor chip formed by the method according to the first embodiment on a package substrate. FIG. 10 is a diagram showing a problem when the conductive layer is etched without oxidizing the surface of the conductive layer. FIG. 11 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 13 is a cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 14 is a cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 15 is a cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 16 is a view showing a state where a semiconductor device is completed by stacking (stacking) semiconductor chips formed by the method according to the second embodiment on other semiconductor chips. FIG. 17 is a view showing a state where a semiconductor device is completed by mounting a semiconductor chip formed by the method according to the second embodiment on a package substrate.

  As described above, in the stack type semiconductor device, micro bumps and Cu pillars smaller than normal bumps are used. For the formation of these micro bumps and Cu pillars, a film forming process, a photolithography process, and an etching process are used, but when the UBM is side-etched in the etching process, the originally small UBM diameter is further reduced, Strength will fall remarkably. This impairs the reliability of the semiconductor device.

  In the following embodiments, a method for manufacturing a semiconductor device capable of avoiding a decrease in strength of connection portions such as micro bumps and Cu pillars due to side etching will be described.

(First embodiment)
1 to 5 are cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. Here, a method for manufacturing a semiconductor device provided with a Cu pillar in the connection portion is described.

  First, an element such as a transistor is formed on a semiconductor substrate (wafer) by a known method, and an insulating layer and a wiring layer are formed thereon. Reference numeral 11 in FIG. 1A denotes a semiconductor substrate on which an element, an insulating layer, and a wiring layer are formed.

  An electrode 12 is formed at a predetermined position on the semiconductor substrate 11 by using a metal such as Al (aluminum). The diameter of the electrode 12 is about 50 μm to 100 μm, for example, and the thickness of the electrode 12 is about several μm, for example.

  Next, an insulating material such as silicon oxide or silicon nitride is deposited on the entire upper surface of the semiconductor substrate 11 by a CVD (Chemical Vapor Deposition) method or the like to form a passivation film 13.

  Thereafter, a portion corresponding to the electrode 12 in the passivation film 13 is removed by using a photolithography method to expose the surface of the electrode 12.

  Next, as shown in FIG. 1B, a barrier layer 14 and a conductive layer 15 to be UBM are formed on the entire upper surface of the semiconductor substrate 11. In this embodiment, Ti (titanium) is deposited to a thickness of about 100 μm by sputtering to form the barrier layer 14, and Cu (copper) is deposited to a thickness of about 250 μm thereon to form the conductive layer 15. However, the material and thickness of the barrier layer 14 and the conductive layer 15 may be changed as appropriate.

  Next, as shown in FIG. 1C, a photoresist is applied on the conductive layer 15 to a thickness of, for example, 40 μm to 80 μm to form a resist film 16. The thickness of the resist film 16 is appropriately set according to the thickness of a Cu pillar 19 and a solder layer 20 described later.

  Next, after drying the resist film 16, as shown in FIG. 2A, a portion of the resist film 16 above the electrode 12 is selected using an exposure mask 17 provided with a predetermined pattern. Exposure.

  Thereafter, development processing is performed to form an opening 16a in which a portion of the conductive layer 15 above the electrode 12 is exposed, as shown in FIG. The diameter of the opening 16a is, for example, about 25 μm to 35 μm.

  Next, the resist film 16 is ashed using an ashing device as shown in FIG. This ashing is performed in order to ensure the wettability of the resist film 16 and facilitate the penetration of the plating solution into the opening 16a during the electrolytic plating performed in the process described later.

  Next, as shown in FIG. 3A, Ni (nickel) plating is performed using the conductive layer 15 as an electrode to form a Ni plating layer 18 on the conductive layer 15 in the opening 16a. The thickness of the Ni plating layer 18 is, for example, about 5 μm to 10 μm.

  At this time, at the inner edge portion of the opening 16a, the plating solution enters a slight gap between the resist film 16 and the conductive layer 15, and the plating metal (Ni) is deposited on the conductive layer 15. FIG. As schematically shown, a flange 18a is formed. The width a of the flange portion 18a is, for example, about 2 μm to 3 μm.

  In the present embodiment, as described above, it is important that the plating solution enters the interface between the conductive layer 15 and the resist film 16 to form the flange portion 18a. The extent to which the plating solution enters the interface between the conductive layer 15 and the resist film 16 is related to the degree of adhesion between the conductive layer 15 and the resist film 16.

  When a general photoresist that is commercially available (for example, a photoresist PMER P-LA900 PM manufactured by Tokyo Ohka Kogyo Co., Ltd.) is used, a plating solution is present at the interface between the conductive layer 15 and the resist film 16 at the edge of the opening 16a. Slightly entering, the flange 18a is inevitably formed.

  In the present embodiment, the conductive layer 15 is made of Cu, and the plating layer 18 is made of Ni. However, the conductive layer 15 and the plating layer 18 may be formed of a metal selected from Cu, Ni, Au, Ag, Cr, and Sn, or an alloy containing the metal as a main component.

  Next, as shown in FIG. 3B, Cu is deposited on the Ni plating layer 18 to a thickness of, for example, 30 μm to 60 μm by electrolytic plating to form a Cu pillar 19. The diameter of the Cu pillar 19 is the same as the diameter of the opening 16 a and is smaller than the diameter of the plating layer 18.

  Further, as shown in FIG. 3C, solder is electroplated on the Cu pillar 19 to a thickness of, for example, 10 μm to 15 μm to form a solder layer 20.

  Next, the resist film 16 is removed using a resist stripper as shown in FIG. After removing the resist film 16, the Ni plating layer 18 (including the flange portion 18 a) remains on the conductive layer 15.

Next, as shown in FIG. 4B, the surface of the exposed portion of the conductive layer 15 is oxidized to form an oxide layer 15a. Specifically, as schematically shown in FIG. 7, the semiconductor substrate 11 is disposed in the chamber 31 of the plasma ashing apparatus 30. Then, while supplying, for example, a mixed gas of oxygen (O ₂ ) and CF ₄ into the chamber 31, the inside of the chamber 31 is evacuated by a vacuum pump (not shown) to maintain the inside of the chamber 31 at a constant pressure. . A high frequency voltage is applied from a high frequency (RF) power source 33 between the upper electrode 32a and the lower electrode 32b. As a result, plasma is generated in the chamber 31, the surface of the conductive layer 15 formed of Cu is oxidized (plasma ashing), and the oxide layer 15a is formed.

In this case, the thickness of the oxide layer 15a is determined by the ashing time. The conductive layer 15 may be oxidized to about half of its thickness direction. If more oxidation is attempted, the ashing time becomes longer and the throughput decreases. As in this embodiment, the addition of CF ₄ to O ₂ gas increases the ashing rate when Cu is oxidized.

  The ashing when oxidizing the conductive layer 15 may be isotropic ashing or anisotropic ashing.

  Next, as shown in FIG. 4C, the oxide layer 15a and the underlying conductive layer 15 are etched until the barrier layer 14 is exposed. For etching the conductive layer 15 and the oxide layer 15a, for example, perhydroacetic acid (a mixture of hydrogen peroxide, acetic acid, and pure water) or perhydrosulfuric acid (hydrogen peroxide, sulfuric acid, and pure water) is used as an etchant. Can be used.

  In this embodiment, since the surface of the conductive layer 15 is oxidized, the conductive layer 15 can be etched away in a short time. After the etching is completed, the conductive layer 15 remains under the Ni plating layer 18 (including the flange 18a).

  In a general semiconductor device manufacturing process, even if a flange is formed at the edge portion inside the resist opening in the plating process, the flange is easily dropped in the subsequent etching process or the like. However, in the present embodiment, in order to leave the flange portion 18a, as described above, the conductive layer 15 is oxidized (ashed) before the etching process to shorten the etching time.

  As described above, after the conductive layer 15 and the oxide layer 15a are etched to expose the barrier layer 14, the barrier layer 14 is etched until the passivation film 13 is exposed as shown in FIG. For the etching of the barrier layer 14 made of Ti, for example, an alkaline titanium etching solution (for example, a solution obtained by mixing pure water and potassium hydroxide in hydrogen peroxide solution) can be used.

  Next, as shown in FIG. 5B, the solder layer 20 is reflowed at a low temperature of about 230 ° C. to 240 ° C., for example, to smooth the surface of the solder layer 20. In the present embodiment, since the thickness of the solder layer 20 is as thin as 10 μm to 15 μm as described above, the amount of lateral protrusion from the Cu pillar 19 of the solder layer 20 after reflow is small. Therefore, it can be applied to a narrow pitch semiconductor device.

  Next, the semiconductor substrate 11 is cut by a dicing apparatus and separated into individual semiconductor chips. Then, the semiconductor chip is mounted on another semiconductor chip or a package substrate to complete the semiconductor device.

  FIG. 8 is a view showing a state in which the semiconductor device is completed by stacking (stacking) the semiconductor chip formed by the above-described method on another semiconductor chip.

  A semiconductor device 40 illustrated in FIG. 8 includes a package substrate 41, a semiconductor chip 44, and a semiconductor chip 45.

  A logic circuit is formed on the semiconductor chip 44, and the semiconductor chip 44 is mounted on the package substrate 41. A normal bump 42 connected to an electrode formed on a circuit board (not shown) is formed on the lower surface side of the package substrate 41, and an electrode 43 is formed on the upper surface side. The electrode 44 and the electrode formed on the periphery of the upper surface of the semiconductor chip 44 are electrically connected by a metal thin wire (bonding wire) 47.

  For example, a DRAM (Dynamic Random Access Memory) is formed in the semiconductor chip 45 and is connected to the electrode of the semiconductor chip 44 through the Cu pillar 19 formed by the method described in the above-described embodiment.

  FIG. 9 is a diagram showing a state where the semiconductor chip is completed by mounting the semiconductor chip formed by the above-described method on the package substrate.

  A semiconductor device 50 shown in FIG. 9 includes a package substrate 51 and a semiconductor chip 55.

  A normal bump 52 is formed on the lower side of the package substrate 51. Further, an electrode 53 is formed on the upper side of the package substrate 51.

  The semiconductor chip 55 is connected to the electrode 53 of the package substrate 51 via the Cu pillar 19 formed by the method described in the above embodiment.

  In the present embodiment, as described above, the etching time of the conductive layer 15 is shortened by oxidizing the surface of the conductive layer 15 before etching the conductive layer 15. Thereby, at the end of etching, the flange portion 18a, and the conductive layer 15 and the barrier layer 14 below the flange portion 18a remain.

  And since the conductive layer 15 and the barrier layer 14 remain below the flange portion 18a, the reduction of the UBM diameter is avoided, and the strength of the Cu pillar 19 is increased. As a result, the reliability of the semiconductor device is improved.

  If the conductive layer 15 is etched without oxidizing the surface of the conductive layer 15, the etching time becomes long and the collar portion 18a is removed. Therefore, for example, as shown in FIG. 10, the diameter of the conductive layer 15 is reduced, and the barrier layer 14 is further side-etched. Thereby, the intensity | strength of Cu pillar 19 reduces and the reliability of a semiconductor device will fall.

(Second Embodiment)
11 to 15 are cross-sectional views showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps. Here, a manufacturing method of a semiconductor device provided with a micro bump in the connection portion is described.

  First, an element such as a transistor is formed on a semiconductor substrate (wafer) by a known method, and an insulating layer and a wiring layer are formed thereon. Reference numeral 61 in FIG. 11A denotes a semiconductor substrate on which an element, an insulating layer, and a wiring layer are formed.

  An electrode 62 is formed at a predetermined position on the semiconductor substrate 61 by using a metal such as Al.

  Next, a passivation film 63 is formed by depositing an insulating material such as silicon oxide or silicon nitride on the entire upper surface of the semiconductor substrate 61 by a CVD method or the like.

  Thereafter, a portion of the passivation film 63 corresponding to the electrode 62 is removed by using a photolithography method to expose the surface of the electrode 62.

  Next, as illustrated in FIG. 11B, a barrier layer 64 and a conductive layer 65 to be UBM are formed on the entire upper surface of the semiconductor substrate 61. In this embodiment, Ti (titanium) is deposited to a thickness of about 100 μm by sputtering to form the barrier layer 64, and Cu (copper) is deposited to a thickness of about 250 μm thereon to form the conductive layer 65.

  Next, as shown in FIG. 11C, a photoresist is applied on the conductive layer 65 to a thickness of, for example, 10 μm to 20 μm to form a resist film 66. The thickness of the resist film 66 is appropriately set according to the thickness of a solder layer 69 described later.

  Next, after drying the resist film 66, as shown in FIG. 12A, a portion of the resist film 66 above the electrode 62 is selected using an exposure mask 67 provided with a predetermined pattern. Exposure.

  Thereafter, development processing is performed to form an opening 66a in which a portion of the conductive layer 65 above the electrode 62 is exposed, as shown in FIG. The diameter of the opening 66a is, for example, about 25 μm to 35 μm.

  Next, using an ashing apparatus, the resist film 66 is ashed as shown in FIG.

  Next, as shown in FIG. 13A, Ni (nickel) plating is performed using the conductive layer 65 as an electrode to form a Ni plating layer 68 on the conductive layer 65 in the opening 66a. The thickness of the Ni plating layer 68 is, for example, about 5 μm.

  At this time, at the inner edge portion of the opening 66a, the plating solution enters a slight gap between the resist film 66 and the conductive layer 65, and the plating metal (Ni) is deposited on the conductive layer 65, so that the flange 68a. Is formed.

  Next, as shown in FIG. 13 (b), a solder layer 69 is formed by electroplating solder on the Ni plating layer 68 to a thickness of 10 μm to 15 μm, for example. In this embodiment, as shown in FIG. 13B, Ni plating is performed until the solder layer 69 slightly protrudes outside the opening 66a.

  Next, using a resist stripper, the resist film 66 is removed as shown in FIG. After removing the resist film 66, the Ni plating layer 68 (including the flange portion 68a) remains on the conductive layer 65.

  Next, using the plasma ashing apparatus illustrated in FIG. 7, the surface of the exposed portion of the conductive layer 65 is oxidized as shown in FIG. 14A to form an oxide layer 65a.

  Next, as shown in FIG. 14B, the oxide layer 65a and the underlying conductive layer 65 are etched until the barrier layer 64 is exposed. For etching the conductive layer 65 and the oxide layer 65a, for example, perhydroacetic acid (a mixture of hydrogen peroxide, acetic acid, and pure water) or perhydrosulfuric acid (hydrogen peroxide, sulfuric acid, and pure water) is used as an etchant. Can be used.

  In this embodiment, since the surface of the conductive layer 65 is oxidized, the conductive layer 65 can be removed by etching in a short time. After the etching is completed, the conductive layer 65 remains under the Ni plating layer 68 (including the flange portion 68a).

  Next, as shown in FIG. 14C, the barrier layer 64 is etched until the passivation film 63 is exposed. For the etching of the barrier layer 64 made of Ti, for example, an alkaline titanium etching solution (for example, a solution obtained by mixing pure water and potassium hydroxide in hydrogen peroxide solution) can be used.

  Next, as shown in FIG. 15, the solder layer 69 is reflowed at a low temperature of about 230 ° C. to 240 ° C., for example, to form spherical microbumps 70 having a smooth surface made of solder. In this embodiment, since the thickness of the solder layer 69 is as thin as about 10 μm to 15 μm as described above, the amount of protrusion of the micro bumps 70 formed from the solder layer 69 in the lateral direction is small. Therefore, it can be applied to a narrow pitch semiconductor device.

  Next, the semiconductor substrate 61 is cut by a dicing apparatus and separated into individual semiconductor chips. Then, the semiconductor chip is mounted on another semiconductor chip or a package substrate to complete the semiconductor device.

  FIG. 16 is a diagram showing a state in which the semiconductor device is completed by stacking (stacking) the semiconductor chip formed by the above-described method on another semiconductor chip.

  A semiconductor device 80 illustrated in FIG. 16 includes a package substrate 81, a semiconductor chip 84, and a semiconductor chip 85.

  A logic circuit is formed on the semiconductor chip 84, and the semiconductor chip 84 is mounted on the package substrate 81. A normal bump 82 connected to an electrode formed on a circuit board (not shown) is formed on the lower surface side of the package substrate 81, and an electrode 83 is formed on the upper surface side. The electrode 84 and the electrode formed on the periphery of the upper surface of the semiconductor chip 84 are electrically connected by a metal thin wire (bonding wire) 87.

  For example, a DRAM is formed in the semiconductor chip 85 and is connected to the electrode of the semiconductor chip 84 via the micro bumps 70 formed by the method described in the above-described embodiment.

  FIG. 17 is a view showing a state where a semiconductor device is completed by mounting the semiconductor chip formed by the above-described method on a package substrate.

  A semiconductor device 90 illustrated in FIG. 17 includes a package substrate 91 and a semiconductor chip 95.

  A normal bump 92 is formed on the lower side of the package substrate 91. An electrode 93 is formed on the upper side of the package substrate 91.

  The semiconductor chip 95 is connected to the electrode 93 of the package substrate 91 through the micro bumps 70 formed by the method described in the above embodiment.

  Also in this embodiment, the etching time of the conductive layer 65 is shortened by oxidizing the surface of the conductive layer 65 before the conductive layer 65 is etched, as in the first embodiment. As a result, when the etching is finished, the flange 68a, and the conductive layer 65 and the barrier layer 64 below the flange 68a remain.

  Then, the conductive layer 65 and the barrier layer 64 remain below the flange portion 68a, so that the UBM diameter is prevented from being reduced and the strength of the microbump 70 is increased. As a result, the reliability of the semiconductor device is improved.

  The following additional notes are disclosed with respect to the above embodiments.

(Appendix 1) forming an electrode on a semiconductor substrate;
Forming an insulating film provided with an opening in a portion corresponding to the electrode on the semiconductor substrate;
Forming a conductive layer on the insulating film of the semiconductor substrate;
Forming a resist film having an opening in a portion corresponding to the electrode on the conductive layer;
A metal plating layer is formed on the conductive layer inside the opening of the resist film by an electrolytic plating method, and the resist film and the conductive layer around the opening of the resist film are interposed between the resist film and the conductive layer. Forming a flange made of the same metal as the metal plating layer;
Removing the resist film to expose the conductive layer;
Oxidizing the surface of the conductive layer exposed by removing the resist film to form an oxide film;
And a step of removing the oxide film and the conductive layer therebelow by etching.

  (Appendix 2) The semiconductor device according to Appendix 1, further comprising a step of forming a barrier layer on the insulating film between the step of forming the insulating film and the step of forming the conductive layer. Production method.

  (Additional remark 3) The manufacturing method of the semiconductor device of Additional remark 1 or 2 characterized by forming the said conductive layer with copper.

  (Additional remark 4) The said metal plating layer is formed with nickel, The manufacturing method of the semiconductor device of any one of Additional remark 1 thru | or 3 characterized by the above-mentioned.

(Supplementary note 5) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 4, wherein the step of forming the oxide film is performed in an oxygen atmosphere containing CF ₄ .

  (Additional remark 6) It has the process of plating a metal layer on the said metal plating layer between the process of forming the said metal plating layer, and the process of removing the said resist film, The additional remark 1 thru | or 5 characterized by the above-mentioned A manufacturing method of a semiconductor device given in any 1 paragraph.

  (Additional remark 7) The manufacturing method of the semiconductor device of Additional remark 6 characterized by forming the said metal layer with copper.

  (Additional remark 8) The manufacturing method of the semiconductor device of Additional remark 6 characterized by forming the said metal layer with a solder.

(Appendix 9) a semiconductor substrate;
An electrode formed above the semiconductor substrate;
A conductive layer formed on the electrode;
A metal plating layer covering the conductive layer;
A semiconductor device comprising: a metal layer formed on the metal plating layer and having a smaller diameter than the metal plating layer.

  (Supplementary note 10) The semiconductor device according to supplementary note 9, wherein the conductive layer is made of copper and the metal plating layer is made of nickel.

  (Supplementary note 11) The semiconductor device according to Supplementary note 9 or 10, wherein the metal layer is a Cu pillar formed of copper.

  (Supplementary note 12) The semiconductor device according to Supplementary note 9 or 10, wherein the metal layer is a micro bump formed of solder.

  DESCRIPTION OF SYMBOLS 11, 61 ... Semiconductor substrate, 12, 62 ... Electrode, 13, 63 ... Passivation film, 14, 64 ... Barrier layer, 15, 65 ... Conductive layer, 15a, 65a ... Oxidation layer, 16, 66 ... Resist film, 17, 67 ... Exposure mask, 18, 68 ... Plating layer, 18a, 68a ... Hut, 19 ... Cu pillar, 20, 69 ... Solder layer, 30 ... Plasma ashing device, 31 ... Chamber, 32a ... Upper electrode, 32b ... Lower electrode 33, high frequency power supply, 40, 50.80, 90 ... semiconductor device, 41, 51, 81, 91 ... package substrate, 42, 52, 82, 92 ... normal bump, 43, 53, 83, 93 ... electrode, 44 , 45, 55, 84, 85, 95... Semiconductor chip, 47, 87... Fine metal wire, 70.

Claims (6)

Forming an electrode on a semiconductor substrate;
Forming an insulating film provided with an opening in a portion corresponding to the electrode on the semiconductor substrate;
Forming a conductive layer on the insulating film of the semiconductor substrate;
Forming a resist film having an opening in a portion corresponding to the electrode on the conductive layer;
A metal plating layer is formed on the conductive layer inside the opening of the resist film by an electrolytic plating method, and the resist film and the conductive layer around the opening of the resist film are interposed between the resist film and the conductive layer. Forming a flange made of the same metal as the metal plating layer;
Removing the resist film to expose the conductive layer;
Oxidizing the surface of the conductive layer exposed by removing the resist film to form an oxide film;
And a step of removing the oxide film and the conductive layer therebelow by etching.   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a barrier layer on the insulating film between the step of forming the insulating film and the step of forming the conductive layer.   The method of manufacturing a semiconductor device according to claim 1, wherein the conductive layer is formed of copper.   The method of manufacturing a semiconductor device according to claim 1, wherein the metal plating layer is formed of nickel.   5. The method according to claim 1, further comprising a step of plating a metal layer on the metal plating layer between the step of forming the metal plating layer and the step of removing the resist film. A method for manufacturing the semiconductor device according to the item. A semiconductor substrate;
An electrode formed above the semiconductor substrate;
A conductive layer formed on the electrode;
A metal plating layer covering the conductive layer;
A semiconductor device comprising: a metal layer formed on the metal plating layer and having a smaller diameter than the metal plating layer.

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