JP2014150654A - Gate Drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate drive circuit that has a small-sized pulse transformer and includes a circuit for preventing malfunction.SOLUTION: A diode 7 is connected between a secondary-side terminal of a pulse transformer 2 and a gate of a MOS FET 1, and as first switch means for discharging between the gate and a source of the MOS FET 1 and turning off the MOS FET 1, a PNP transistor 8 is connected between the gate and the source of the MOS FET 1. Further, a capacitance 11 is connected between a control input terminal of the PNP transistor 8 and the source of the MOS FET 1. Moreover, as second switch means for charging the capacitance 11 by a positive input voltage, turning off the PNP transistor 8, discharging the capacitance 11 by a negative input voltage, and turning on the PNP transistor 8, an NPN transistor 9 and a diode 10 are connected between the other end of the secondary-side terminal of the pulse transformer 2 and the control input terminal of the PNP transistor 8.

Description

  The present invention relates to a gate drive circuit for a capacitive switch element used in a switching power supply or the like.

  A plurality of capacitive switching elements such as MOS FETs and IGBTs are used as switching elements for switching power supplies and AC inverters. As these gate drive circuits, a circuit insulated from the control circuit by a pulse transformer as shown in FIG. 7 is used.

  The operation is as follows. When the switch 5 is turned on by a control signal from the control circuit, a voltage substantially equal to the DC power supply voltage (Vcc) is applied to the primary side of the pulse transformer 2. If the winding ratio of the pulse transformer 2 is 1: 1, a voltage of Vcc is also generated in the secondary winding. The gate-source capacitance of the MOS FET 1 is charged through the resistor 3, the gate-source VGS is also a voltage substantially equal to Vcc, and the MOS FET 1 is turned on. This is shown in FIG.

  In addition to the gate-source capacitance charging current, an exciting current shown in FIG. 8 flows in the primary winding of the pulse transformer 2. Thereafter, when the switch 5 is turned off, the primary winding voltage of the pulse transformer 2 becomes a reverse polarity voltage given by the pulse transformer reset circuit 4, and the voltage applied to the gate of the MOS FET 1 is discharged and turned off. At this time, the excitation current flowing in the pulse transformer 2 starts to decrease and eventually becomes 0A.

The exciting current I that flows when the switch 5 is on can be expressed as Equation 1.
I = (Vcc x Ton) / L
Where Ton is the ON time of the switch 1 and L is the inductance of the primary winding of the pulse transformer.

  As is clear from Equation 1, the excitation current is proportional to the applied voltage, that is, the power supply voltage Vcc, and the on time Ton. Therefore, there is a problem that a large excitation current flows when the on-time is long. In order to avoid this, a large-sized pulse transformer with a large inductance is required.

  As a solution to this problem, Patent Document 1 proposes a method of adding constant voltage means and capacity. This conventional technique will be described with reference to FIGS. As shown in FIG. 9, in the gate drive circuit, a constant voltage diode 12 as a constant voltage means is connected between the secondary terminal of the pulse transformer 2 and the gate of the MOS FET 1, and a capacitance is connected between the gate and source of the MOS FET 1. 11 is connected.

  The operation is as follows. When a positive voltage Vp is applied from the pulse voltage source 6 to the primary winding of the pulse transformer 2, a positive Vp is also generated in the secondary winding of the pulse transformer 2, and the capacitance is passed through the constant voltage diode 12. 11 and MOS FET1 gate-source capacitance is charged and MOS FET1 is turned on. VGS at this time is Vp1 obtained by subtracting the forward voltage of the constant voltage diode 12 from Vp.

  Thereafter, when the primary side voltage of the pulse transformer 2 is set to 0V, the gate-source voltage of the MOS FET 1 is maintained at Vp by the action of the constant voltage diode 12. The voltage application period of the pulse transformer 2 can be made shorter than the ON period of the MOS FET 1, and an increase in excitation current can be suppressed.

  To turn off MOS FET1, apply negative Vn. As a result, the constant voltage diode 12 becomes conductive, and the gate-source voltage of the MOS FET 1 is discharged and turned off.

  However, the method proposed in Patent Document 1 has the following problems. Consider the case where a voltage is applied between the gate and source of MOS FET 1 due to some path, such as drain-to-gate leakage current or drain-side noise components caused by drain-to-gate capacitance, while MOS FET 1 is off. . In the circuit shown in FIG. 7, the voltage is immediately discharged. However, in the method proposed in Patent Document 1, the voltage is maintained by the action of the constant voltage means, and the MOS FET 1 is erroneously turned on.

JP 2010-279225 A

  The present invention has been made in view of such problems, and an object of the present invention is to provide a circuit for preventing erroneous turn-on while enabling the use of a small pulse transformer by suppressing an increase in excitation current. Another object is to provide a gate driving circuit.

  In order to solve the above-described problems, the present invention charges a switch-element gate-source capacitance with a positive input voltage to turn on the switch element, and a negative input voltage causes the switch-element gate-source capacitance to turn on. A switch element gate drive circuit in which one end of an input terminal is connected to a switch element source terminal to discharge the capacitance and turn off the switch element, and is connected between the other end of the input terminal and the gate of the switch element A diode that charges between the gate and the source of the switch element by a positive input voltage, a first switch means that turns off the switch element by discharging between the gate and the source of the switch element, and the first A capacitor connected between the switch means control input terminal and the switch element source; the other end of the input terminal; and the first switch means control. Connected between input terminals, the capacitor is charged by a positive input voltage, the first switch means is turned off, the capacitor is discharged by a negative input voltage, and the first switch means is turned on. And a second switch means.

  According to a second aspect of the present invention, in the gate drive circuit according to the first aspect of the present invention, a resistor connected in parallel to the capacitor is provided.

  According to a third aspect of the present invention, in the gate drive circuit according to the first aspect, the input terminal is a terminal of a secondary winding of the pulse transformer, and the circuit including the primary winding of the pulse transformer is: A series circuit composed of a first switch and a second switch connected to both ends of the DC power supply, and a primary side winding and a second capacitor of the pulse transformer connected to both ends of the first switch And a clamp element connected in parallel to the primary winding of the pulse transformer, and when the first switch is off and the second switch is on, the pulse A positive drive voltage is applied to the primary winding of the transformer and the second capacitor to generate a positive input voltage between the input terminals, the first switch is turned on, and the second switch is turned off. The second capacity Characterized in that for generating a negative input voltage between the pulse transformer of the negative drive voltage is applied to the primary winding the input terminal by the voltage.

  The present invention has an effect of preventing erroneous turn-on while enabling the use of a small-sized pulse transformer by suppressing an increase in excitation current.

1 is a circuit diagram of a gate drive circuit according to Embodiment 1 of the present invention. FIG. FIG. 3 is a voltage / current waveform diagram on the gate drive circuit according to the first embodiment of the invention. FIG. 6 is a circuit diagram of a gate drive circuit according to Embodiment 2 of the present invention. FIG. 6 is a circuit diagram of a gate drive circuit according to Example 3 of the invention. It is a circuit diagram of the gate drive circuit based on Example 4 of this invention. It is a voltage waveform diagram on the gate drive circuit which concerns on Example 4 of this invention. It is a circuit diagram of the gate drive circuit explaining a prior art. It is a wave form diagram of the said gate drive circuit. It is a circuit diagram of the gate drive circuit explaining a prior art. It is a wave form diagram of the said gate drive circuit.

[Example 1]
FIG. 1 shows a circuit diagram of a gate drive circuit according to Embodiment 1 of the present invention, and FIG. 2 shows voltage / current waveform diagrams on the gate drive circuit. A diode 7 is connected between the secondary terminal of the pulse transformer 2 and the gate of the MOS FET 1, and the PNP transistor 8 is used as the first switch means to turn off the MOS FET 1 by discharging between the gate and source of the MOS FET 1. Connected between the gate and source of FET1. A capacitor 11 is connected between the control input terminal of the PNP transistor 8 and the source of the MOS FET 1. Further, the capacitor 11 is charged by a positive input voltage, the PNP transistor 8 is turned off, the capacitor 11 is discharged by a negative input voltage, and the NPN transistor 9 is used as a second switching means for turning on the PNP transistor 8. And a diode 10 are connected between the secondary terminal of the pulse transformer 2 and the control input terminal of the PNP transistor 8.

  When a positive drive voltage Vp is applied to the primary winding of the pulse transformer 2, a positive Vp is also generated in the secondary winding of the pulse transformer 2, and the gate-source capacitance of the MOS FET 1 is charged through the diode 7 and VGS is charged. Rises and MOS FET1 turns on. At this time, VGS becomes Vp1 obtained by subtracting the forward voltage of the diode 7 from Vp.

  At the same time, the capacitor 11 is charged through the diode 10. At this time, the transistor 8 is turned off because the base and emitter, which are control input terminals, have the same potential. Transistor 9 is similarly off because its base is reverse-biased with respect to the emitter.

  After VGS rises sufficiently, when the primary winding voltage of pulse transformer 2 is set to 0V, V1 also becomes 0V. However, since the transistor 9 remains off, the transistor 8 also remains off. Further, the VGS is kept on without being discharged by the action of the diode 7.

  When a negative drive voltage Vn is applied to the primary winding of the pulse transformer 2, negative Vn is also generated in the secondary winding of the pulse transformer 2, and the transistor 9 is turned on. Then, the capacitor 10 is discharged and the transistor 8 is turned on, the gate-source capacitance of the MOS FET 1 is discharged, VGS falls, and the MOS FET 1 is turned off.

  After VGS has dropped sufficiently, the primary winding voltage of the pulse transformer 2 is set to 0 V, and the on / off cycle is completed.

  As is apparent from FIG. 2, even when the MOS FET 1 ON period is long, the period during which the drive voltage is applied to the pulse transformer 2 can be short, so that the excitation current can be suppressed to a low value. In addition, even after the negative drive voltage Vn is applied, the MOS FET 1 remains off even if the primary winding voltage of the pulse transformer 2 is set to 0 V. However, this is caused through the drain-gate leakage current and the drain-gate capacitance When a voltage is applied between the gate and source of MOS FET 1 due to noise components on the drain side, the base current of transistor 8 flows through capacitor 11, and the current multiplied by the DC current amplification factor is the transistor 8 emitter-collector. Therefore, the rise of the gate-source voltage VGS of the MOS FET 1 is suppressed. As a result, erroneous turn-on of the MOS FET 1 can be prevented.

[Example 2]
FIG. 3 shows a circuit diagram of a gate drive circuit according to the second embodiment of the present invention. In the second embodiment, a resistor 13 is connected in parallel with the capacitor 11 with respect to the first embodiment. As described above, the leakage current between the drain and gate and the current due to the drain-side noise component caused by the drain-gate capacitance flow through the capacitor 11, but if the insulation resistance between the capacitor 11 terminals is high, the capacitance 11 is gradually charged, and MOS FET1 may turn on. In order to prevent this, in the present invention, a resistor 13 is added and the capacitor 11 is discharged. It should be noted that the value of the resistor 13 needs to be selected so that the gate-source voltage VGS is not greatly reduced during the MOS FET 1 ON period and the loss of the MOS FET 1 is not increased.

[Example 3]
FIG. 4 shows a circuit diagram of a gate drive circuit according to Embodiment 3 of the present invention. The third embodiment uses an N-channel MOS FET 14 instead of the NPN transistor 9 and the diode 10 as the second switch means with respect to the first embodiment.

[Example 4]
FIG. 5 shows a circuit diagram of a gate drive circuit according to Embodiment 4 of the present invention, and FIG. 6 shows a voltage waveform diagram on the gate drive circuit. The fourth embodiment includes a DC power supply 18 that supplies a MOS FET1 gate drive voltage, a clamp element 4, a capacitor 15, and switches 16 and 17 as a primary circuit of the pulse transformer 2. A clamp element 4 is connected between the primary terminals of the pulse transformer 2, and a capacitor 15 is connected between the primary terminal of the pulse transformer 2 to which the anode of the clamp element 4 is connected and one end of the DC power supply 18. Switches 16 and 17 are connected to the primary side terminal of the pulse transformer 2 to which the cathode of the clamp element 4 is connected, and the other ends of the switches 16 and 17 are connected to both ends of the DC power source 18, respectively. The capacitor 15 may be connected between the switch 16 and the primary terminal of the pulse transformer 2 to which the cathode of the clamp element 4 is connected.

  The operation is as follows. When the switch 16 is turned on and the switch 17 is turned off, the positive drive voltage Vcc is applied to the series circuit of the primary winding of the pulse transformer 2 and the capacitor 15. As a result, the MOS FET gate-source voltage VGS rises, and the capacitor 15 is also charged by the current flowing through the primary winding of the pulse transformer 2. VGS rises to Vcc1, which is a value obtained by subtracting the forward voltage of the diode 7 from the voltage obtained by dividing Vcc by the capacitance between the gate and source of the MOS FET 1 and the capacitance 15. This is shown in FIG.

  In order to make the voltage distributed to VGS sufficiently larger than the on-voltage of MOS FET 1, the capacitance of capacitor 15 needs to be sufficiently larger than the capacitance between the gate and source of MOS FET 1.

  If the switch 16 continues to be in the ON state even after VGS rises, the capacitor 15 continues to be charged by the exciting current, so the voltage VC of the capacitor 15 rises, and the primary winding voltage V1 of the pulse transformer 2 starts to decrease. However, VGS is maintained by the action of the diode 7 and the like.

  After a predetermined time has elapsed, the switch 16 is turned off. A negative voltage limited by the clamp element 4 is generated in each winding of the pulse transformer 2. This voltage needs to be lower than the ON voltage (approximately 0.6 V) of the transistor 9 as the switch means. This is because the transistors 9 and 8 are turned on and VGS is discharged. As an example, by using a Schottky diode as the clamp element, the voltage applied to the transistor 9 is about 0.2 V, which satisfies this requirement. Note that the voltage of the capacitor 15 is maintained as Vn1, which is a value charged by the exciting current.

  Next, when the switch 17 is turned on, the voltage VC of the capacitor 15 is applied to the primary winding of the pulse transformer 2 as a negative drive voltage -Vn1. Transistors 9 and 8 are turned on, and MOS FET 1 is turned off.

  As shown in FIG. 6, also in the fourth embodiment, the period during which the drive voltage is applied to the pulse transformer 2 with respect to the ON period of the MOS FET 1 can be shortened, so that the excitation current can be suppressed to a low value.

  In the circuit proposed in Patent Document 1 shown in FIG. 9, it is necessary to apply a negative drive voltage that is substantially the same voltage as the positive drive voltage V1 in order to turn on the constant voltage diode 12 when the MOS FET 1 is turned off. . On the other hand, in the gate drive circuit of the present invention, it is only necessary to apply a negative voltage sufficient to turn on the transistor 9 as the switch means, so that the primary circuit of the pulse transformer can be simplified.

  The present invention can be applied to a gate drive circuit of a capacitive switch element used for a switching power supply, an AC inverter, or the like.

1 MOS FET
2 Pulse transformer 3 Resistance 4 Clamp element 5 Switch 6 Pulse voltage source 7 Diode 8 Transistor 9 Transistor 10 Diode 11 Capacitance 12 Constant voltage diode 13 Resistance 14 MOS FET
15 capacity 16 switch 17 switch 18 DC power supply

Claims (3)

The switch element is turned on by charging the gate-source capacitance of the switch element with a positive input voltage, and the switch element is turned off by discharging the gate-source capacity of the switch element with a negative input voltage. A switch element gate drive circuit in which one end of the terminal is connected to the switch element source terminal,
A diode connected between the other end of the input terminal and the gate of the switch element, and charging between the gate and source of the switch element by a positive input voltage;
A transistor that discharges between the gate and source of the switch element to turn off the switch element;
A capacitor connected between the base of the transistor and the source of the switch element;
Connected between the other end of the input terminal and the base of the transistor, the capacitor is charged by a positive input voltage, the transistor is turned off, and the capacitor is discharged by a negative input voltage. Switch means to turn on;
A gate drive circuit comprising:   The gate drive circuit according to claim 1, further comprising a resistor connected in parallel to the capacitor. The input terminal is a terminal of a secondary winding of a pulse transformer,
The circuit including the primary winding of the pulse transformer is:
A series circuit composed of a first switch and a second switch connected to both ends of the DC power supply;
A series circuit composed of a primary winding and a second capacitor of the pulse transformer connected to both ends of the first switch;
A clamp element connected in parallel to the primary winding of the pulse transformer;
With
When the first switch is off and the second switch is on, a positive drive voltage is applied to the primary winding of the pulse transformer and the second capacitor, and a positive input is applied between the input terminals. When the first switch is on and the second switch is off, a negative driving voltage is applied to the primary winding of the pulse transformer by the voltage of the second capacitor when the first switch is on and the second switch is off. The gate drive circuit according to claim 1, wherein a negative input voltage is generated between the input terminals.

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