JP2014016631A - Semiconductor device, module, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure of a semiconductor device which achieves low power consumption even with increase in area, and a method of fabricating the same.SOLUTION: A thin film transistor of a pixel used for a screen is fabricated. In the thin-film transistor, source wiring and a gate electrode are fabricated on an identical plane. In addition, wiring for connecting the source wiring and thin-film transistor and wiring for connecting a pixel electrode and the thin-film transistor are fabricated in an identical process.

Description

The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof. For example, the present invention relates to a device represented by a liquid crystal display device (mounted with a liquid crystal module) and an electronic device mounted with such a device as a component.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.

Conventionally, a liquid crystal display device is known as an image display device. Active matrix liquid crystal display devices are often used because high-definition images can be obtained compared to passive liquid crystal display devices. In an active matrix liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. Specifically, by applying a voltage between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, optical modulation of the liquid crystal layer disposed between the pixel electrode and the counter electrode is performed. The optical modulation is recognized by the observer as a display pattern.

Applications of such active matrix liquid crystal display devices are expanding, and demands for higher definition, higher aperture ratio, and higher reliability are increasing as the screen size increases. At the same time, demands for improved productivity and lower costs are increasing.

Conventionally, when a TFT is manufactured using aluminum as the gate wiring material of the TFT,
Due to the formation of protrusions such as hillocks and whiskers and the diffusion of aluminum atoms into the channel formation region due to the heat treatment, the TFT malfunctioned and the TFT characteristics deteriorated. Therefore, when using a metal material that can withstand heat treatment, typically a metal element having a high melting point, problems such as increased wiring resistance occur when the screen size is increased, resulting in increased power consumption. And so on.

Accordingly, an object of the present invention is to provide a structure of a semiconductor device that realizes low power consumption even when the screen is enlarged and a manufacturing method thereof.

In the present invention, the surface of the source wiring of the pixel portion is plated to reduce the resistance of the wiring. Note that in the present invention, the source wiring of the pixel portion is manufactured in a different process from the source wiring of the driver circuit portion. Similarly, the electrode of the terminal portion is plated to reduce the resistance.

In the present invention, it is desirable that the wiring before plating is formed of the same material as the gate electrode, and the surface of the wiring is plated to form the source wiring. Further, it is desirable to use a material film having a lower electrical resistance than the gate electrode as the material film to be plated. Therefore, the source wiring of the pixel portion becomes a low resistance wiring by the plating process.

The structure of the invention disclosed in this specification includes a TFT including a semiconductor layer formed over an insulating surface, an insulating film formed over the semiconductor layer, and a gate electrode formed over the insulating film. A pixel comprising a first n-channel TFT having a source wiring that surrounds a wiring made of the same material as the gate electrode and whose surface is covered with a material film having a lower resistance than the gate electrode And a drive circuit comprising a circuit comprising a second n-channel TFT and a p-channel TFT, and a material film whose surface is lower in resistance than the gate electrode so as to surround a wiring made of the same material as the gate electrode And a terminal portion covered with the semiconductor device.

In the above structure, the low-resistance material film is a material film containing Cu, Al, Au, Ag, or an alloy thereof as a main component.

A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film, comprising: A pixel unit including a first n-channel TFT having a source line formed thereon, a drive circuit including a circuit including a second n-channel TFT and a p-channel TFT, a plated terminal unit, A semiconductor device characterized by comprising:

In the above configuration, the surface of the terminal portion and the surface of the source wiring of the pixel portion are Cu, Al
It is characterized by being covered with a thin film made of a material mainly composed of Au, Ag, or an alloy thereof.

Further, in the above structure, the source wiring of the terminal portion and the pixel portion is plated at the same time or separately. The plated source wiring is obtained by plating a wiring made of the same material as that of the gate electrode. Further, the plated source wiring is formed by a printing method and is made of a material having a lower resistance than the gate electrode.

In the above structure, the second n-channel TFT and the p-channel TFT
Thus, a CMOS circuit is formed.

In the above structure, the first n-channel TFT includes a gate electrode and a channel formation region overlapping the gate electrode, and the width of the channel formation region and the width of the gate electrode are the same. It is characterized by. Alternatively, in the above structure, the first n-channel TFT includes a gate electrode having a tapered portion, a channel formation region overlapping with the gate electrode, and an impurity region partially overlapping with the gate electrode. In that case, a triple gate structure having three channel formation regions is preferable.

In the above structure, the n-channel TFT of the driver circuit includes a gate electrode having a tapered portion, a channel formation region overlapping with the gate electrode, and an impurity region partially overlapping with the gate electrode.

In the above structure, the impurity concentration in the impurity region of the n-channel TFT includes a region having a concentration gradient in the range of at least 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ³ . As the distance increases, the impurity concentration increases.

The structure of the present invention relating to a manufacturing method for obtaining each of the above structures is a method for manufacturing a semiconductor device including a driver circuit, a pixel portion, and a terminal portion over an insulating surface, and a semiconductor layer is formed over the insulating surface. A step of forming a first insulating film on the semiconductor layer, a step of forming a first gate electrode, a source wiring of a pixel portion, and an electrode of a terminal portion on the first insulating film, An n-type first impurity region is formed by adding an impurity element imparting n-type to the semiconductor layer using the first gate electrode as a mask; and the first gate electrode is etched and tapered.
Forming an n-type second impurity region by adding an impurity element imparting n-type conductivity to the semiconductor layer through the tapered portion of the first gate electrode; An impurity element imparting p-type is added to the semiconductor layer through the taper portion of the gate electrode 1 and p
Forming an impurity region of a mold, plating a surface of the source wiring of the pixel portion and the terminal portion, forming a second insulating film covering the source wiring of the pixel portion and the terminal portion, and Forming a gate wiring and a source wiring of a driving circuit over the second insulating film.

Further, the structure of the present invention relating to another manufacturing method is a manufacturing method of a semiconductor device including a driver circuit, a pixel portion, and a terminal portion on an insulating surface, and a step of forming a semiconductor layer on the insulating surface;
Forming a first insulating film on the semiconductor layer; forming a first gate electrode on the first insulating film; a source wiring of a pixel portion; and an electrode of a terminal portion; and the first gate. Forming an n-type first impurity region by adding an impurity element imparting n-type to the semiconductor layer using an electrode as a mask; and forming a tapered portion by etching the first gate electrode; A step of forming an n-type second impurity region by adding an impurity element imparting n-type to the semiconductor layer through the tapered portion of the first gate electrode; and a taper of the first gate electrode A step of adding a p-type impurity region by adding an impurity element imparting p-type to the semiconductor layer through the − portion, plating a surface of the source wiring of the pixel portion, A step of plating the surface; and the pixel Forming a second insulating film covering the source wiring and the terminal portion, and forming a gate wiring and a source wiring of a driving circuit on the second insulating film. .

In the above structure, the source wiring of the pixel portion and the terminal portion are Cu, Al, A
It is characterized by being made of a material mainly composed of u, Ag, or an alloy thereof.

In the above structure, in the step of plating, the source wiring of the pixel portion is connected by wiring so as to have the same potential.
The wiring connected to have the same potential may be divided by a laser beam after the plating process, or may be divided simultaneously with the substrate after the plating process.

In a semiconductor device represented by an active matrix liquid crystal display device according to the present invention,
Good display can be realized even when the area of the pixel portion is increased and the screen is enlarged. Since the resistance of the source wiring of the pixel portion is greatly reduced, the present invention can be applied to, for example, a large screen with a diagonal of 40 inches or a diagonal of 50 inches.

10A and 10B illustrate a manufacturing process of an AM-LCD. 10A and 10B illustrate a manufacturing process of an AM-LCD. 10A and 10B illustrate a manufacturing process of an AM-LCD. FIG. 6 is a top view of a pixel. FIG. 6 is a top view of a pixel. FIG. 9 is a diagram showing a cross-sectional structure of an active matrix liquid crystal display device. The figure which shows a terminal part. The figure which shows a terminal part. The figure which shows the external appearance of a liquid crystal module. The figure which shows a top view. The figure which shows the cross section of a pixel part. The figure which shows the cross section of a pixel part. The figure which shows a terminal part. The figure which shows the example of bottom gate type TFT. The figure which shows the cross section of a pixel part. The figure which shows the mask 146. FIG. FIG. 6 is a top view of a pixel. FIG. 14 illustrates an example of an electronic device. FIG. 14 illustrates an example of an electronic device.

  Embodiments of the present invention will be described below.

First, a base insulating film is formed over a substrate, and then a semiconductor layer having a desired shape is formed by a first photolithography process.

Next, an insulating film (including a gate insulating film) is formed to cover the semiconductor layer. A first conductive film and a second conductive film are stacked over the insulating film. These stacked films are subjected to a first etching process by a second photolithography process, and a gate electrode including the first conductive layer and the second conductive layer, a source wiring of the pixel portion, and an electrode of the terminal portion are formed. Form. In the present invention, after the gate electrode is formed first, the gate wiring is formed on the interlayer insulating film.

Next, while leaving the resist mask formed in the second photolithography process as it is, an impurity element imparting n-type (phosphorus or the like) is added to the semiconductor to form an n-type impurity region (high concentration) in a self-aligning manner. ).

Next, while the resist mask formed in the second photolithography step is left as it is, a second etching process is performed by changing etching conditions, and a first conductive layer (first width) having a tapered portion is formed. A second conductive layer (second width) is formed. The first width is the second
The electrode formed of the first conductive layer and the second conductive layer here is n-channel type TF.
It becomes a T gate electrode (first gate electrode).

Next, after removing the resist mask, an impurity element imparting n-type conductivity is added to the semiconductor layer through the tapered portion of the first conductive layer using the second conductive layer as a mask. here,
A channel formation region is formed below the second conductive layer, and an impurity region (low concentration) in which the impurity concentration gradually increases as the distance from the channel formation region is increased is formed below the first conductive layer.

Thereafter, the tapered portion is selectively removed in order to reduce the off current of the TFT in the pixel portion.
Only the tapered portion of the gate electrode of the pixel portion may be removed by performing dry etching with the mask shown in FIG. In particular, it is not necessary to selectively remove the tapered portion,
If not removed, it is desirable to reduce the off-current as a triple gate structure as shown in FIG.

Next, a mask is formed by a third photolithography method so as to cover a region where an n-channel TFT is to be formed, and a third doping process is performed. In this third doping process,
A p-type impurity region (high concentration) is formed by adding an impurity element (boron) imparting p-type to the semiconductor.

Next, after the impurity element added to each semiconductor layer is activated, a plating process (electrolytic plating method) is performed to form a metal film on the surface of the source wiring in the pixel portion and the surface of the electrode in the terminal portion.
The plating method is a method in which a direct current is passed through an aqueous solution containing metal ions to be formed by plating to form a metal film on the cathode surface. As the metal to be plated, a material having a lower resistance than the gate electrode, such as copper, silver, gold, chromium, iron, nickel, platinum, or an alloy thereof can be used. Since copper has a very low electric resistance, it is optimal for a metal film covering the surface of the source wiring of the present invention. Thus, in the present invention, since the source wiring of the pixel portion is covered with a low-resistance metal material, it can be driven at a sufficiently high speed even if the area of the pixel portion is increased.

Further, the thickness of the metal film formed in the plating method can be appropriately set by the practitioner by controlling the current density and time.

  In the present invention, the metal film formed on the surface is also referred to as source wiring.

Next, an interlayer insulating film is formed, and a transparent conductive film is formed. Next, the transparent conductive film is patterned by a fourth photolithography method to form a pixel electrode. Next, a contact hole is formed by a fifth photolithography process. Here, a contact hole reaching the impurity region, a contact hole reaching the gate electrode, and a contact hole reaching the source wiring are formed.

Next, a conductive film made of a low-resistance metal material is formed, and an electrode that connects the gate wiring, the source wiring, and the impurity region, and an electrode that connects the pixel electrode and the impurity region are formed by a sixth photolithography process. . In the present invention, the gate wiring is electrically connected to the first gate electrode or the second gate electrode through a contact hole provided in the interlayer insulating film. The source wiring is electrically connected to the impurity region (source region) through a contact hole provided in the interlayer insulating film. An electrode connected to the pixel electrode is electrically connected to the impurity region (drain region) through a contact hole provided in the interlayer insulating film.

Thus, a total of six photolithography steps, that is, the pixel TFT (with six masks)
An element substrate including a pixel portion having an n-channel TFT) and a driver circuit having a CMOS circuit can be formed. Note that although an example in which a transmissive display device is manufactured is shown here, a reflective display device can also be manufactured by using a highly reflective material for a pixel electrode. In the case of manufacturing a reflective display device, since the reflective electrode can be formed at the same time as the gate wiring, the element substrate can be formed with five masks.

Although an example in which the source wiring of the pixel portion and the electrode of the terminal portion are formed simultaneously with the gate electrode is shown here, they may be formed separately. For example, after an impurity element is added to each semiconductor layer, an insulating film that protects the gate electrode is formed, the impurity element added to each semiconductor layer is activated, and a low resistance is formed on the insulating film by a photolithography process. You may form simultaneously the source wiring of the pixel part which consists of metal materials (typically material which has aluminum, silver, and copper as a main component), and the electrode of a terminal part. The source wiring of the pixel portion and the electrode of the terminal portion thus obtained are plated. In order to reduce the number of masks, the source wiring of the pixel portion may be formed by a printing method.

The present invention having the above-described configuration will be described in more detail with the following examples.

Here, a method for simultaneously manufacturing a pixel portion (n-channel TFT) and TFTs (n-channel TFT and p-channel TFT) constituting a CMOS circuit of a driver circuit provided around the pixel portion on the same substrate is shown. It demonstrates using FIGS. 1-10.

First, in this embodiment, a substrate 100 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is used. The substrate 100 is not particularly limited as long as it has translucency, and a quartz substrate may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.

Next, a base film 101 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 100. Although a two-layer structure is used as the base film 101 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 101, a silicon oxynitride film 101a formed by using a plasma CVD method and using SiH ₄ , NH ₃ , and N ₂ O as a reaction gas is 10 to 200 nm (preferably 50 to
100 nm). In this embodiment, a silicon oxynitride film 101a having a film thickness of 50 nm (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) is formed. Next, the base film 1
As the second layer of 01, a silicon oxynitride film 101b formed using SiH ₄ and N ₂ O as a reaction gas by a plasma CVD method is 50 to 200 nm (preferably 100 to 150 nm).
). In this embodiment, the silicon oxynitride film 101b having a thickness of 100 nm is used.
(Composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) was formed.

Next, semiconductor layers 102 to 105 are formed over the base film. The semiconductor layers 102 to 105 are
After a semiconductor film having an amorphous structure is formed by a known means (sputtering method, LPCVD method, plasma CVD method, etc.), a known crystallization treatment (laser crystallization method, thermal crystallization method, nickel, etc.) A crystalline semiconductor film obtained by performing a thermal crystallization method using the above catalyst is formed into a desired shape by patterning. The thickness of the semiconductor layers 102 to 105 is 25 to 80 n.
It is formed with a thickness of m (preferably 30 to 60 nm). There is no limitation on the material of the crystalline semiconductor film, but it is preferably formed of silicon or a silicon germanium alloy. In this example, a 55 nm amorphous silicon film was formed by plasma CVD, and then a solution containing nickel was held on the amorphous silicon film. This amorphous silicon film is dehydrogenated (50
(0 ° C., 1 hour), thermal crystallization (550 ° C., 4 hours) was performed, and laser annealing treatment for improving crystallization was further performed to form a crystalline silicon film. Then, the crystalline silicon film is subjected to patterning processing using a photolithography method, so that the semiconductor layer 1
02-105 were formed.

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser can be used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. Crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 400 mJ / cm ² (typically 200 to 300 mJ / cm ^2). ). If a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1.
10 kHz, and the laser energy density is 300 to 600 mJ / cm ² (typically 350
˜500 mJ / cm ² ). Then, when the laser beam condensed linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, the superposition ratio (overlap ratio) of the linear laser light at this time is 80 to 98%. Good.

Next, a gate insulating film 106 that covers the semiconductor layers 102 to 105 is formed. The gate insulating film 106 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by plasma CVD or sputtering. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 115 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as illustrated in FIG. 1A, a first conductive film 107 a with a thickness of 20 to 100 nm and a second conductive film 107 b with a thickness of 100 to 400 nm are stacked over the gate insulating film 106. In this embodiment, a first conductive film 107a made of a TaN film with a thickness of 30 nm and a film thickness of 37
A second conductive film 107b made of a 0 nm W film was stacked. The TaN film was formed by sputtering, and was sputtered in a nitrogen-containing atmosphere using a Ta target. In addition, W film is W
It formed by the sputtering method using the target of. In addition, tungsten hexafluoride (WF ₆ )
It can also be formed by a thermal CVD method using In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in the W film, the crystallization is hindered and the resistance is increased. Therefore, in this embodiment, sufficient consideration is given so that impurities are not mixed from the gas phase during film formation by sputtering using a target of high purity W (purity 99.9999% or 99.99%). By forming a W film, a resistivity of 9 to 20 μΩcm could be realized.

In this embodiment, the first conductive film 107a is TaN and the second conductive film 107b is W. However, there is no particular limitation, and all of them are Ta, W, Ti, Mo, Al, Cu, Cr, Nd. You may form with the element selected from these, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. In addition, the first conductive film is formed of a tantalum (Ta) film, and the second conductive film is formed of W.
A combination in which the first conductive film is formed of a titanium nitride (TiN) film, a second conductive film is formed of a W film, the first conductive film is formed of a tantalum nitride (TaN) film, The first conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is combined with an Al film.
The conductive film may be a combination of Cu films.

Next, resist masks 108a to 112a are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used as the first etching condition, CF ₄ , Cl ₂ and O ₂ are used as etching gases, and the respective gas flow ratios are 25. / 25/1
Etching was performed by generating a plasma by generating 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa at a pressure of 0 (sccm). The etching gas is C
Chlorine gas such as l ₂ , BCl ₃ , SiCl ₄ , CCl ₄ or the like or CF ₄ , SF ₆ , N
A fluorine-based gas represented by F ₃ or the like, or O ₂ can be used as appropriate. Here, dry etching equipment (Model E645- □ IC using ICP manufactured by Matsushita Electric Industrial Co., Ltd.)
P) was used. 150W RF (13.56MHz) power is also applied to the substrate side (sample stage).
A substantially negative self-bias voltage is applied. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered. The etching rate for W under the first etching conditions is 200.39 nm / min, and the etching rate for TaN is 80.
. The selection ratio of W to TaN is about 2.5. Further, the taper angle of W is about 26 ° under this first etching condition.

Thereafter, the masks 108a to 112a made of resist are changed to the second etching conditions without removing them, CF ₄ and Cl ₂ are used as etching gases, and the respective gas flow ratios are set to 30/3.
Etching is performed for about 30 seconds by generating 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa and generating a plasma. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching condition is 58.97 nm.
/ Min, the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.

In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of the tapered portion may be 15 to 45 °.

In this manner, the first shape conductive layers 113 to 117 (the first conductive layers 113a to 117a and the second conductive layers 113b to 113b) formed of the first conductive layer and the second conductive layer by the first etching process.
117b). (FIG. 1B) The width of the first conductive layer in the channel length direction here corresponds to the first width shown in the above embodiment mode.
Although not shown, the first shape conductive layers 113 to 1 in the insulating film 106 to be a gate insulating film.
A region not covered with 17 is etched by about 10 to 20 nm to form a thinned region.

Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the semiconductor layer. (FIG. 1C) The doping process may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is a dose of 1 × 10 ¹³
˜5 × 10 ¹⁵ / cm ² and acceleration voltage is 60 to 100 keV. In this embodiment, the dose is set to 1.5 × 10 ¹⁵ / cm ² and the acceleration voltage is set to 80 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 113 to 116 serve as a mask for the impurity element imparting n-type, and n-type impurity regions (high concentration) 118 to 121 are self-aligned.
Is formed. An impurity element imparting n-type conductivity is added to the impurity regions 118 to 121 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

Next, a second etching process is performed without removing the resist mask.
Here, SF ₆ , Cl _2, and O ₂ are used as etching gases, and the respective gas flow ratios are 2
4/12/24 (sccm) at a pressure of 1.3 Pa, a 700 W RF (1
3.56 MHz) Electric power was applied to generate plasma, and etching was performed for 25 seconds. 10 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The etching rate for W in the second etching process is 227.3 nm / m.
The etching rate for in and TaN is 32.1 nm / min.
Is 7.1, and the etching rate for SiON, which is the insulating film 106, is 33. As shown in FIG.
The selection ratio of W to TaN is 6.83. Thus, when SF ₆ is used as the etching gas, the selectivity with respect to the insulating film 106 is high, so that film loss can be suppressed.

By this second etching process, the taper angle of the second conductive layer (W) became 70 °.
The second conductive layers 122b to 126b are formed by the second etching process. On the other hand, the first conductive layer is hardly etched, and the first conductive layers 122a to 126a are formed. Further, the masks 108a to 112a made of resist are deformed into masks 108b to 112b made of resist by the second etching process. (FIG. 1D) Although not shown, the width of the first conductive layer actually retreats by about 0.15 μm compared to before the second etching process, that is, the entire line width recedes by about 0.3 μm. . Further, the width of the second conductive layer in the channel length direction here corresponds to the second width shown in the embodiment mode.

Note that the electrode formed of the first conductive layer 122a and the second conductive layer 122b serves as a gate electrode of an n-channel TFT of a CMOS circuit formed in a later step, and the first conductive layer 12
The electrode formed of 5a and the second conductive layer 125b serves as one electrode of a storage capacitor formed in a later step.

In the second etching process, CF ₄ , Cl ₂ and O ₂ can be used as an etching gas. In that case, each gas flow rate ratio is 25/25/10 (sc
cm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. 20W RF on the substrate side (sample stage)
(13.56MHz) Apply power and apply a substantially negative self-bias voltage. When CF ₄ , Cl ₂ and O ₂ are used, the etching rate with respect to W is 124.62 nm / min, the etching rate with respect to TaN is 20.67 nm / min, and the selection ratio of W with respect to TaN is 6
. 05. Therefore, the W film is selectively etched. In this case, the insulating film 10
6, a region not covered with the first shape conductive layers 122 to 126 is etched by about 50 nm to form a thinned region.

Next, after removing the resist mask, a second doping process is performed to obtain FIG.
The state of A) is obtained. Doping is performed using the second conductive layers 122b to 125b as masks against the impurity element so that the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer. In this embodiment, P (phosphorus) is used as the impurity element, the doping conditions are a dose of 1.5 × 10 ¹⁴ / cm ² , an acceleration voltage of 90 keV, and an ion current density of 0.5.
Plasma doping was performed with μA / cm ² , phosphine (PH ₃ ) 5% hydrogen dilution gas, and a gas flow rate of 30 sccm.
In this manner, impurity regions (low concentration) 127 to 136 overlapping with the first conductive layer are formed in a self-aligning manner. The concentration of phosphorus (P) added to the impurity regions 127 to 136 is 1 × 10 ¹⁷ to
It is 1 × 10 ¹⁹ / cm ³ and has a concentration gradient according to the film thickness of the tapered portion in the first conductive layer. Note that in the semiconductor layer overlapping the tapered portion of the first conductive layer, the impurity concentration (P concentration) gradually decreases from the end of the tapered portion in the first conductive layer toward the inside. That is, a concentration distribution is formed by this second doping process. Further, an impurity element is further added to the impurity regions (high concentration) 118 to 121, so that the impurity regions (high concentration) 1
37 to 145 are formed.

In the present embodiment, the width of the taper portion (width in the channel length direction) is preferably at least 0.5 μm, and the limit is 1.5 μm to 2 μm. Accordingly, the width in the channel length direction of the impurity region having a concentration gradient (low concentration), which depends on the film thickness, is also 1.5 μm to 2 μm.
Is the limit. Here, the impurity region (high concentration) and the impurity region (low concentration) are illustrated as being separate, but actually there is no clear boundary and a region having a concentration gradient is formed. Similarly, there is no clear boundary between the channel formation region and the impurity region (low concentration).

Next, a third etching process is performed with the portions other than the pixel portion covered with the mask 146 later.
As the mask 146, a metal plate, a glass plate, a ceramic plate, or a ceramic glass plate may be used. A top view of the mask 146 is shown in FIG. In this third etching process,
The tapered portion of the first conductive layer in the region not overlapping with the mask 146 is selectively dry etched so that there is no region overlapping with the impurity region of the semiconductor layer. The third etching process is performed using an ICP etching apparatus using Cl ₃ having a high selectivity to W as an etching gas. In this embodiment, the gas flow ratio of Cl ₃ is 80 (sccm), and 350 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma and perform etching for 30 seconds. went. 50 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. By the third etching, the first conductive layers 124c and 126c are formed. (Fig. 2 (B))

In this embodiment, an example in which the third etching process is performed has been described. However, if the third etching process is not necessary, it is not particularly necessary.

Next, a mask 147 made of resist formed by a third photolithography method is used to cover a semiconductor layer that will later become an active layer of the n-channel TFT, and a third doping process is performed. By this third doping treatment, a p-type impurity in which an impurity element imparting a conductivity type (p-type) opposite to the one conductivity type (n-type) is added to a semiconductor layer that becomes an active layer of a p-channel TFT. Regions (high concentration impurity region and low concentration impurity region) 148 to 150 are formed. Note that, since doping is performed through the tapered portion, the p-type low-concentration impurity region has the same concentration gradient as the n-type low-concentration impurity region. (FIG. 2C) The first conductive layer is used as a mask against the impurity element, and an impurity element imparting p-type is added to form p-type impurity regions 148 to 1
50 is formed. In this embodiment, the p-type impurity regions 148 to 150 are formed by an ion doping method using diborane (B ₂ H ₆ ). Note that phosphorus is added to the impurity regions at different concentrations by the first doping treatment and the second doping treatment, but the boron concentration is 2 × 10 ²⁰ to 2 × 10 ^{21 in} any of the regions. By performing the doping process so as to be / cm ³ , no problem arises because it functions as the source region and drain region of the p-channel TFT.

In addition, when the film is not reduced by the second etching process, for example, when SF ₆ is used as the etching gas, the insulating film 2 is formed before the third doping process in order to facilitate boron doping.
Etching to reduce the thickness of 07 (reactive ion etching using CHF ₃ gas (RIE)
Act)) may be performed.

Next, as shown in FIG. 2D, a step of activating the impurity element added to each semiconductor layer is performed. This activation process is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, it may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. The activation treatment was performed by heat treatment. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

Although not shown, the impurity element is diffused by this activation treatment, and an n-type impurity region (
The boundary between the low concentration) and the impurity region (high concentration) is almost eliminated.

In this embodiment, at the same time as the activation treatment, nickel used as a catalyst during crystallization is gettered to an impurity region containing high-concentration phosphorus, and nickel in a semiconductor layer mainly serving as a channel formation region The concentration is reduced. A TFT having a channel formation region manufactured in this way has a low off-current value and good crystallinity, so high field effect mobility can be obtained.
Good properties can be achieved.

Next, heat treatment is performed in a hydrogen atmosphere to hydrogenate the semiconductor layer. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be used.

In the case where a laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the hydrogenation.

Next, the surface of the source wiring 126 in the pixel portion and the electrode surface in the terminal portion are plated.
FIG. 7A shows a top view immediately after the plating process, and FIG. 7B shows a cross-sectional view thereof. In FIG. 7, reference numeral 400 denotes a terminal portion, and 401 denotes an electrode connected to an external terminal. Further, FIG. 7 shows one TFT of the driver circuit portion for simplification, and only the source wiring 126 is shown in the pixel portion. In this example, the plating process was performed using a copper plating solution (manufactured by EEJA: Microfab Cu2200). Also, during this plating, as shown in FIG.
Wirings or electrodes to be plated are connected by a dummy pattern so as to have the same potential. In a later step, the electrodes are separated from each other when the substrate is divided. Moreover, you may form a short ring with a dummy pattern.

Next, a first interlayer insulating film 155 is formed to cover the source wiring of the pixel. As the first interlayer insulating film 155, an inorganic insulating film containing silicon as a main component may be used.

Next, a second interlayer insulating film 156 made of an organic insulating material is formed on the first interlayer insulating film 155.
Form. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed.

Next, the pixel electrode 147 made of a transparent conductive film was patterned on the second interlayer insulating film using a photomask. The transparent conductive film used as the pixel electrode 147 is, for example, ITO (indium tin oxide alloy), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (Z
nO) or the like may be used.

Next, the second insulating film is selectively etched using a photomask so that each impurity region (
137, 138, 149, 150, 151, 153, 144), a contact hole reaching the source wiring 126 of the pixel portion, a contact hole reaching the gate electrode 124, and a contact hole reaching the electrode 125b. .

Then, the electrodes 157 to 160 and the source wiring of the driver circuit that are electrically connected to the impurity regions (137, 138, 149, 150), the impurity regions 144, and the impurity regions 15 respectively.
3, electrodes 150 and 163 that are electrically connected to the electrode 3, an electrode (connection electrode) 161 that electrically connects the impurity region 151 serving as the source region and the source wiring 126 of the pixel portion, and the gate electrode 12
4 is electrically connected to the gate wiring 162, and the capacitor wiring 1 is electrically connected to the electrode 125b.
69 is formed.

In addition, the pixel electrode 147 is connected to the pixel electrode 147 by an electrode 163 that overlaps with the pixel electrode 147.
Electrode 1 which is electrically connected to the impurity region 153 of T206 and overlaps with and overlaps with the pixel electrode 147
50 is electrically connected to the impurity region 144 of the storage capacitor 207.

In this embodiment, the electrodes 150 and 163 are formed after the pixel electrode is formed. However, after forming the contact hole and forming the electrode, the pixel electrode made of a transparent conductive film so as to overlap the electrode is formed. May be formed.

In addition, impurity regions 135, 136, and 144 that function as one electrode of the storage capacitor 207.
145 is doped with an impurity element imparting p-type.
The storage capacitor 207 has the electrode 12 connected to the capacitor wiring 169 using the insulating film 106 as a dielectric.
5a, 125b and the semiconductor layer.

As described above, the C including the n-channel TFT 203 and the p-channel TFT 204 is formed.
A driving circuit 201 including a MOS circuit 202, and a pixel TFT 206 composed of an n-channel TFT
In addition, the pixel portion 205 including the storage capacitor 207 can be formed over the same substrate. (
FIG. 3B) In this specification, such a substrate is referred to as an active matrix substrate for convenience.

A top view of a pixel portion of an active matrix substrate manufactured in this embodiment is shown in FIG. In addition,
The same reference numerals are used for the portions corresponding to FIG. A chain line AA ′ in FIG. 3B corresponds to a cross-sectional view taken along the chain line AA ′ in FIG. In addition, a chain line BB in FIG.
'Corresponds to the cross-sectional view taken along the chain line BB' in FIG. FIG. 4 shows a top view immediately after forming the source wiring 126 of the pixel.

In the pixel structure of this embodiment, the end portion of the pixel electrode 147 overlaps with the source wiring 126 so that the gap between the pixel electrodes is shielded without using a black matrix.

Further, according to the steps shown in this example, the number of photomasks necessary for manufacturing the active matrix substrate could be six.

A process for manufacturing an active matrix liquid crystal display device from the active matrix substrate thus obtained will be described below. FIG. 6 is used for the description.

After obtaining the active matrix substrate in the state of FIG. 3B, an alignment film 301 is formed over the active matrix substrate of FIG. 3B and a rubbing process is performed. In this embodiment, the alignment film 3
Prior to forming 01, columnar spacers for maintaining the distance between the substrates were formed at desired positions by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.

Next, the counter substrate 300 is prepared. The counter substrate is provided with a color filter in which a colored layer 302 and a light shielding layer are arranged corresponding to each pixel. A planarizing film 304 is provided to cover the color filter and the light shielding layer. Next, a counter electrode 305 made of a transparent conductive film was formed on the planarizing film 304 in the pixel portion, an alignment film 306 was formed on the entire surface of the counter substrate, and a rubbing process was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are attached to each other with a sealant 307. A filler is mixed in the sealing material 307, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. after that,
A liquid crystal material 308 is injected between both the substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 308. Then, the active matrix substrate or the counter substrate is divided into a desired shape. Here, the dummy pattern provided for the plating process is divided.

FIG. 8A shows a top view after division, and FIG. 8B shows a cross-sectional view cut along a dotted line DD ′. In FIG. 8, reference numeral 400 denotes a terminal portion, and 401 denotes an electrode connected to an external terminal. Further, FIG. 8 shows one TFT in the driver circuit portion for simplification, and the source wiring 12 in the pixel portion.
Only 6 were shown. The electrode 401 is electrically connected to the wirings 157 to 160.
In the terminal portion 400, a part of the plated electrode 401 is exposed, and a transparent conductive film 404 made of ITO is formed.

Further, a polarizing plate 309 and the like were appropriately provided using a known technique. And FPC was affixed on the exposed part among terminal parts using a well-known technique. FIG. 8C shows a cross-sectional view of the FPC 405 after bonding.

The structure of the liquid crystal module thus obtained will be described with reference to the top view of FIG. Note that FIG.
The same reference numerals are used for portions corresponding to.

The top view shown in FIG. 9 is a pixel portion, a drive circuit, an FPC (flexible printed wiring board: Flex
The active matrix substrate on which the external input terminal 309 to which the ible printed circuit) 311 is attached, the wiring 310 for connecting the external input terminal to the input portion of each circuit, and the counter substrate 300 on which a color filter is provided are provided. Affixed via a sealant 307.

A light shielding layer 303a is provided on the counter substrate side so as to overlap with the gate wiring side driving circuit 201a, and a light shielding layer 403b is formed on the counter substrate side so as to overlap with the source wiring side driving circuit 201b. In addition, the color filter 302 provided on the counter substrate side over the pixel portion 205 includes a light-shielding layer and a colored layer of each color of red (R), green (G), and blue (B) corresponding to each pixel. It has been. When actually displaying, red (R)
A color display is formed with three colors of a colored layer, a green (G) colored layer, and a blue (B) colored layer.
The arrangement of the colored layers of these colors is arbitrary.

Here, the color filter 302 is provided on the counter substrate for colorization; however, there is no particular limitation, and when an active matrix substrate is manufactured, a color filter may be formed on the active matrix substrate.

In addition, a light shielding layer 303 is provided between adjacent pixels in the color filter,
The area other than the display area is shielded from light. Further, a light shielding layer may be provided also in a region covering the driver circuit. The area that covers the drive circuit is not particularly provided with a light-blocking layer because it is covered with a cover when the liquid crystal display device is incorporated later as a display portion of an electronic device. Further, when the active matrix substrate is manufactured, a light shielding layer may be formed on the active matrix substrate.

Further, an FPC 411 composed of a base film and wiring is bonded to the external input terminal with an anisotropic conductive resin. Furthermore, the mechanical strength is increased by the reinforcing plate.

Although an example in which all the drive circuits are formed on the substrate is shown here, several ICs may be used as part of the drive circuit.

The liquid crystal module manufactured as described above can be used as a display portion of various electronic devices. When this liquid crystal module is incorporated, a backlight 310 and a light guide plate 311 are provided and covered with a cover 312, the active matrix liquid crystal display device shown in FIG. 6 is completed.
Note that the cover 312 and the liquid crystal module are bonded together using an adhesive or an organic resin. Also,
When the substrate and the counter substrate are bonded to each other, the organic resin may be filled between the frame and the substrate by being surrounded by a frame and bonded.

The present invention is characterized in that the source wiring of the pixel portion is formed in a process different from the source wiring of the driver circuit. In this embodiment, differences from the prior art will be described in detail with reference to FIG. In FIG. 10, for simplification, only three source wirings 91 and three gate wirings 92 are shown in the pixel portion. In addition, the source wiring 91 of the pixel portion is a strip shape parallel to each other, and the interval is equal to the pixel pitch.

FIG. 10 shows a block configuration for performing digital driving. In this embodiment, a source side driver circuit 93, a pixel portion 94, and a gate side driver circuit 95 are provided.
Note that in this specification, a driving circuit is a generic term including a source side driving circuit and a gate side driving circuit.

The source side driving circuit 93 includes a shift register 93a, a latch (A) 93b, and a latch (B).
93c, a D / A converter 93d, and a buffer 93e are provided. The gate side driving circuit 95 includes a shift register 95a, a level shifter 95b, and a buffer 95c.
If necessary, a level shifter circuit may be provided between the latch (B) 93c and the D / A converter 93d.

In this embodiment, as shown in FIG. 10, a contact portion exists between the source side driving circuit 93 and the pixel portion 94. This is because the source wiring of the source side driver circuit and the source wiring 91 of the pixel portion are formed by different processes. In the present invention, the source wiring of the pixel portion is formed by a process different from the source wiring of the source side driver circuit in order to perform plating on the wiring using the same material as the gate electrode and cover it with a low resistance material. Yes.

Further, in order to perform the plating process, all the source wirings of the pixel portion are connected by a wiring pattern so as to have the same potential, and an electrode for the plating process is provided. Similarly, the terminal portions are connected by a wiring pattern, and electrodes for plating are provided. In FIG. 10, electrodes for plating are separately provided. However, they may be further connected by a wiring pattern and plated at one time. Moreover, the dotted line in FIG. 10 is a parting line of the substrate, and indicates a part to be cut after the plating process.

The pixel portion 94 includes a plurality of pixels, and each of the plurality of pixels is provided with a TFT element. The pixel portion 94 is provided with a large number of gate wirings 92 connected to the gate side driving circuit in parallel with each other. In addition, it is desirable that the terminal portion is covered with a low resistance material by plating the electrode using the same material as the gate electrode.

Note that a gate side driver circuit may be provided on the opposite side of the gate side driver circuit 95 with the pixel portion 94 interposed therebetween.

In the case of analog driving, a sampling circuit may be provided instead of the latch circuit.

  Note that this embodiment can be combined with Embodiment 1.

In the first embodiment, an example in which the tapered portion is selectively etched is shown, but this embodiment shows an example in which etching is not performed. Since only the pixel portion is different, only the pixel portion is shown in FIG.

This embodiment is an example in which the third etching process of FIG. FIG.
In FIG. 1A, the pixel electrode 700 made of a transparent conductive film is formed as the gate electrode of the pixel TFT 709 as in FIG.

FIG. 11A is different from Embodiment 1 in the structure of the gate electrode, and includes a first conductive layer 707,
Reference numeral 708 has a tapered portion. Therefore, the first conductive layer 707 overlaps the impurity region with the insulating film interposed therebetween.

The first conductive layers 707 and 708 having a tapered portion are the first conductive layer 1 of Example 1.
This corresponds to 24a.

FIG. 11B illustrates an example of a triple gate structure. In FIG. 11B,
The first conductive layer 804 overlaps with the impurity regions 803 and 805 with the insulating film interposed therebetween, the first conductive layer 807 overlaps with the impurity regions 806 and 808 with the insulating film interposed therebetween, and the first conductive layer 810 overlaps with the insulating film. The impurity regions 809 and 811 overlap with each other.

In this example, off current can be reduced by adopting a triple gate structure. Further, the off-current may be further reduced by reducing the width of the gate electrode, for example, 1.5 μm.

  Note that this embodiment can be freely combined with Embodiment 1 or Embodiment 2.

In Example 1, an example of manufacturing an active matrix substrate used for a transmissive liquid crystal display device is shown, but this example shows a reflective type. Since only the pixel portion is different, only the pixel portion is shown in FIG.

As the substrate, a glass substrate, a quartz substrate, or a plastic substrate can be used. Furthermore, since this embodiment is a reflection type, it is not particularly limited, and a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed can also be used.

In FIG. 12, according to the first embodiment, a plating process is performed to obtain a source wiring 1401, a second interlayer insulating film is formed, and then patterned using a photomask to form a contact hole, and each electrode and gate wiring This is an example in which a pixel electrode 1406 is formed. The pixel electrode 1406 is
It is electrically connected to the impurity region 1405. The materials of these electrodes and pixel electrode 1406 are:
A material having excellent reflectivity such as a film containing Al or Ag as a main component or a laminated film thereof is used. Note that in FIG. 12, the pixel TFT 1402 has a double gate structure and has two channel formation regions which overlap with the gate electrodes 1403 and 1404 with an insulating film interposed therebetween.

In the manufacturing method for obtaining the structure of FIG. 12, since the pixel electrode and the gate wiring can be manufactured at the same time, the number of photomasks necessary for manufacturing the active matrix substrate can be five.

  In this embodiment, an example in which source wiring is formed in a process different from that in Embodiment 1 is shown in FIG.

FIG. 13A illustrates an example in which the source wiring 903 in the pixel portion is plated, an interlayer insulating film is formed, a contact hole is formed in the interlayer insulating film, and then the terminal portion 900 is plated.

First, the electrode 901 of the terminal portion is formed in the same process as the gate electrode 902 of the driver circuit portion. A source wiring 903 is formed in the same process as this electrode. First, only the source wiring 903 in the pixel portion is selectively plated. Thereafter, an interlayer insulating film is formed, and a contact hole is formed. When forming this contact hole, a part of the electrode 901 of the terminal portion 900 is exposed. Subsequently, only the exposed region of the electrode 901 in the terminal portion is subjected to a plating process to perform a plating film 9.
04 is formed. Thereafter, lead wiring, source wiring, and drain wiring are formed. In the subsequent steps, the structure shown in FIG.

However, the activation of the impurity element contained in the semiconductor layer is preferably performed before the plating film 904 is formed.

Similarly to the first embodiment, when plating, wirings or electrodes to be plated are connected by a dummy pattern so as to have the same potential. In a later step, the electrodes are separated from each other when the substrate is divided. Moreover, you may form a short ring with these dummy patterns.

FIG. 13B illustrates an example in which plating is performed in a step different from that in FIG. In this embodiment, the gate electrode 1002 is formed and the source wiring 1003 is not formed at the same time.

After forming an insulating film for protecting the gate electrode 1002, the impurity element added to each semiconductor layer is activated, and a low-resistance metal material (typically aluminum, silver, copper) is formed on the insulating film by a photolithography process. A source wiring 1003 of a pixel portion made of a material mainly composed of
The electrode 1001 of the terminal portion is formed at the same time. As described above, in the present invention, since the source wiring of the pixel portion is formed of a low-resistance metal material, it can be driven sufficiently even if the area of the pixel portion is increased. Further, in order to reduce the number of masks, the source wiring may be formed by a printing method.

Next, a plating process (electrolytic plating method) is performed to form a metal film on the surface of the source wiring 1003 in the pixel portion and the surface of the electrode 1001 in the terminal portion. The subsequent steps are shown in FIG.
The structure shown in B) may be formed.

  FIG. 13C illustrates an example in which a source wiring is formed in a step different from that in FIG.

In this embodiment, the source wiring is formed by a printing method. In order to improve the positional accuracy of the source wiring of the pixel, a conductive layer was provided.

In this example, the conductive layers 905a and 905b were formed in the same process as the gate electrode. Next, the impurity element was activated without covering the gate electrode with the insulating film. As activation, for example, thermal annealing is performed under reduced pressure in an inert atmosphere, thereby suppressing increase in resistance due to oxidation of the conductive layer. Next, a source wiring was formed using a printing method so as to fill the gap between the conductive layers. Printing method (screen printing) by providing a conductive layer along the source wiring
It is possible to prevent disconnection that is likely to occur. In the subsequent steps, the structure shown in FIG.

In screen printing, for example, a paste (diluent) mixed with metal particles (Ag, Al, etc.) or ink is used as a mask with a plate having an opening of a desired pattern as a mask. Then, a desired pattern of wiring is formed by performing thermal firing. Such a printing method is relatively inexpensive and suitable for the present invention because it can cope with a large area.

In addition, a relief printing method using a rotating drum, an intaglio printing method, and various offset printing methods can be applied to the present invention instead of the screen printing method.

As described above, the source wiring of the pixel portion can be formed by various methods.

  Note that this embodiment can be freely combined with any one of Embodiments 1 to 4.

Although the top gate TFT is shown in Embodiment 1, the present invention is not limited to the TFT structure and can be applied. In this embodiment, an example of a pixel TFT 1502 having a bottom gate structure is shown in FIG.

First, a gate electrode 1503 and a source wiring are formed over a substrate, and then a gate insulating film is formed. Next, a semiconductor film is formed so as to overlap with the gate electrode with the gate insulating film interposed therebetween. Next, an insulating layer is selectively formed in a portion to be a channel formation region in the semiconductor film, and doping is performed. Next, after performing activation treatment, the semiconductor film and the gate insulating film are selectively removed. At this time, the insulating film covering the source wiring is removed to expose the surface. Next, the source wiring 1501 is formed by reducing the resistance by performing plating on the surface of the source wiring.

Next, an interlayer insulating film is formed, a pixel electrode 1504 made of ITO is formed, and a contact hole is formed. Next, an electrode connecting the source region of the pixel TFT 1502 and the source wiring 1501, a gate wiring connecting to the gate electrode, and an electrode connecting the drain region of the pixel TFT 1502 and the pixel electrode 1504 are formed.
Thus, the pixel TFT 1502 is completed.

  Note that this embodiment can be freely combined with any one of Embodiments 1 to 5.

  In this embodiment, an example in which source wiring is formed in a process different from that in Embodiment 1 is shown in FIG.

FIG. 15 shows a pixel electrode 1600 made of ITO on an interlayer insulating film after an interlayer insulating film is formed.
In this example, the source wiring 1601 is formed.

In this embodiment, the source wiring is formed by screen printing, and the source wiring and the pixel T
A connection electrode that connects the source region of the FT 1602 is provided.

In the screen printing, for example, a paste (diluent) in which metal particles (Ag, Al, Cu, etc.) are mixed or a plate having an opening of a desired pattern as a mask is used as a mask, and the paste is a substrate to be printed from the opening. A wiring having a desired pattern is formed by forming the upper layer and then performing thermal baking. Such a printing method is relatively inexpensive and suitable for the present invention because it can cope with a large area.

In addition, a relief printing method using a rotating drum, an intaglio printing method, and various offset printing methods can be applied to the present invention instead of the screen printing method.

In this embodiment, the source wiring is formed of copper, and the connection electrode and the gate wiring are formed of a three-layer stack of Ti / Al / Ti.

  Note that this embodiment can be freely combined with any one of Embodiments 1 to 4.

In this embodiment, an example of a top view of a pixel in a triple gate structure is shown in FIG.
Shown in

In FIG. 17, 1201 is a semiconductor layer, 1202 is a gate electrode, 1203 is a capacitor electrode, 120
4 is a source wiring; 1205 is a gate wiring; 1206 is a capacitive wiring connected to a capacitive electrode;
Reference numeral 207 denotes an electrode connecting the semiconductor layer and the source wiring, 1209 denotes a pixel electrode, and 1208 denotes an electrode connecting the semiconductor layer and the pixel electrode.

In this embodiment, the gate electrode 1202 is formed over the insulating film covering the semiconductor layer 1201 in the same process.
And the capacitor electrode 1203 is formed. The source wiring 1204 is formed in the same process as these electrodes or in a different process. In this example, after the addition of the impurity element of the semiconductor layer and its activation treatment,
In another process, it was formed on the gate insulating film, and the surface was plated to reduce the resistance of the wiring. In this embodiment, the gate electrode 1202, the capacitor electrode 1203, and the source wiring 120
4, a gate wiring 1205, a capacitor wiring 1206, and electrodes 1207, 120
8 is formed in the same process.
In addition, an electrode 1208 is provided to partially overlap and overlap with a pixel electrode 1209 made of a transparent conductive film formed on the interlayer insulating film. In addition, as shown in FIG.
A capacitor wiring 1206 is disposed between the electrode 1207 and the electrode 1207.

The gate electrode 1202 overlaps with the semiconductor layer 1201 at three positions with a gate insulating film interposed therebetween, and has a triple gate structure. The cross-sectional view in the vicinity of the gate electrode is almost the same as that in FIG.

FIG. 11B shows an example in which the capacitor of the pixel portion is formed of a semiconductor layer different from the pixel TFT, but in FIG. 17, the capacitor is formed of a part of the semiconductor layer of the pixel TFT. In order to increase the capacity, the thickness of the insulating film may be reduced to about 80 nm.

In this example, off current can be reduced by adopting a triple gate structure. Further, the off current may be further reduced by reducing the width of the gate electrode 1202, for example, 1.5 μm.

  Note that this embodiment can be freely combined with any one of Embodiments 1 to 7.

In this example, as the heat treatment in Example 1, PPTA (Plural Pulse Thermal Ann
An example using ealing) is shown.

PPTA means heating by a light source (halogen lamp, metal halide lamp, high-pressure mercury lamp, high-pressure sodium lamp, xenon lamp, etc.) and cooling by circulation of a refrigerant (nitrogen, helium, argon, krypton, xenon, etc.) into the processing chamber. This is a heat treatment in which the cycle is repeated a plurality of times. The light emission time per light source is 0.1 to 60 seconds, preferably 0.1
It is 20 seconds, and light is irradiated several times. Note that the light source is lit in a pulsed manner by the power source and the control circuit so that the holding period of the semiconductor film is 0.5 to 5 seconds.

By irradiating light that is selectively absorbed by the semiconductor film by PPTA from a light source provided on one side or both sides of the semiconductor film, the substrate itself is not heated so much. Is selectively heated (temperature increase rate: 100 to 200 ° C./second). Also,
In order to suppress the temperature rise of the substrate, cooling is performed from the surroundings with a refrigerant (temperature decrease rate: 50 to 150 ° C./second).

  The example used for activation among the heat processing in Example 1 is shown below.

In the activation shown in FIG. 2D, activation is performed with PPTA. Pulse light is irradiated from one side or both sides of the substrate using a tungsten halogen lamp as a light source. At this time, the flow rate of He is increased or decreased in synchronization with the blinking of the tungsten halogen lamp, and the semiconductor film is selectively heated.

The PPTA activates the impurity element, and the metal element used for crystallization included in the semiconductor layer can be gettered from the channel formation region to the impurity region. Note that it is more effective that an impurity element imparting p-type is added to the impurity region in addition to phosphorus. Therefore, it is preferable to add a step of adding boron that imparts p-type after the first doping. Further, the PPTA treatment chamber may be in a reduced pressure state of 13.3 Pa or less to prevent oxidation and contamination.

  Note that this embodiment can be freely combined with any one of Embodiments 1 to 8.

The driver circuit and the pixel portion formed by implementing the present invention can be used for various modules (active matrix liquid crystal module, active matrix EC module).
That is, the present invention can be implemented in all electronic devices in which they are incorporated in the display portion.

Such electronic devices include video cameras, digital cameras, head mounted displays (goggles type displays), car navigation systems, projectors, car stereos,
A personal computer, a portable information terminal (such as a mobile computer, a mobile phone, or an electronic book) can be used. Examples of these are shown in FIGS.

FIG. 18A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The present invention can be applied to the display portion 2003.

FIG. 18B shows a mobile computer (mobile computer).
A camera unit 2202, an image receiving unit 2203, an operation switch 2204, a display unit 2205, and the like are included.
The present invention can be applied to the display portion 2205.

FIG. 18C shows a player that uses a recording medium (hereinafter referred to as a recording medium) in which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404,
Operation switch 2405 and the like are included. This player uses DVD (Dig as a recording medium).
(tial Versatile Disc), CD, etc. can be used for music appreciation, movie appreciation, games and the Internet. The present invention can be applied to the display portion 2402.

FIG. 19A illustrates a portable book (electronic book), which includes a main body 3001 and display portions 3002 and 300.
3, a storage medium 3004, an operation switch 3005, an antenna 3006, and the like. The present invention can be applied to the display portions 3002 and 3003.

FIG. 19B illustrates a display, which includes a main body 3101, a support base 3102, and a display portion 3103.
Etc. The present invention can be applied to the display portion 3103 whose diagonal is 10 to 50 inches.

As described above, the applicable range of the present invention is so wide that the present invention can be applied to methods for manufacturing electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-9.

Claims (3)

A semiconductor device having first to fifth conductive layers, a semiconductor layer, and an insulating layer,
The first conductive layer has a region functioning as a gate electrode of a transistor;
The semiconductor layer has a channel formation region of the transistor,
The insulating layer has a region between the first conductive layer and the semiconductor layer;
The second conductive layer is electrically connected to the semiconductor layer;
The third conductive layer is electrically connected to the semiconductor layer;
The third conductive layer is electrically connected to the fourth conductive layer;
The fourth conductive layer has a region functioning as a wiring,
The fifth conductive layer is electrically separated from the second conductive layer;
The fifth conductive layer is electrically separated from the third conductive layer;
The semiconductor device, wherein the fifth conductive layer has a region overlapping with at least part of a channel formation region of the transistor included in the semiconductor layer. A semiconductor device according to claim 1;
FPC,
Having a module. A semiconductor device according to claim 1 or a module according to claim 2;
An operation switch, an image receiver, an antenna, or a speaker;
Electronics.

Images