JP2014082494A - Substrate processing method - Google Patents
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- JP2014082494A JP2014082494A JP2013211925A JP2013211925A JP2014082494A JP 2014082494 A JP2014082494 A JP 2014082494A JP 2013211925 A JP2013211925 A JP 2013211925A JP 2013211925 A JP2013211925 A JP 2013211925A JP 2014082494 A JP2014082494 A JP 2014082494A
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- insulating layer
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- 239000000758 substrate Substances 0.000 title claims abstract description 72
- 238000003672 processing method Methods 0.000 title claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 62
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000006227 byproduct Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 44
- 239000007789 gas Substances 0.000 claims description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000012495 reaction gas Substances 0.000 claims description 7
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000010301 surface-oxidation reaction Methods 0.000 description 5
- 238000004148 unit process Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- AJROUILWTHWZFO-UHFFFAOYSA-N [F-].[NH4+].[Si] Chemical compound [F-].[NH4+].[Si] AJROUILWTHWZFO-UHFFFAOYSA-N 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- -1 that is Inorganic materials 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
本発明は半導体製造方法に関し、具体的に、半導体層と絶縁層とを除去する基板処理方法に関する。 The present invention relates to a semiconductor manufacturing method, and more particularly to a substrate processing method for removing a semiconductor layer and an insulating layer.
メモリ素子又は表示素子は基板と前記基板上の半導体層とを包含することができる。半導体層は基板上で絶縁層と共に積層構造に配置され得る。絶縁層と半導体層とはフォトリソグラフィー工程及び蝕刻工程によってパターニングされ得る。蝕刻工程は乾式蝕刻方法又は湿式蝕刻方法を包含することができる。蝕刻工程は半導体層と絶縁層とに対する蝕刻選択比にしたがって遂行されている。蝕刻選択比は蝕刻ガス又は蝕刻液の固有の特性によって決定され得る。したがって、一般的な蝕刻工程は微細パターンのトリミング不良を引き起こす短所がある。 The memory element or the display element can include a substrate and a semiconductor layer on the substrate. The semiconductor layer can be arranged in a stacked structure along with the insulating layer on the substrate. The insulating layer and the semiconductor layer may be patterned by a photolithography process and an etching process. The etching process may include a dry etching method or a wet etching method. The etching process is performed according to an etching selection ratio with respect to the semiconductor layer and the insulating layer. The etch selectivity can be determined by the intrinsic properties of the etch gas or etchant. Therefore, the general etching process has a disadvantage that causes a fine pattern trimming defect.
本発明が解決しようとする技術的課題は、絶縁層と半導体層との蝕刻段差を容易に調節できる基板処理方法を提供することにある。 A technical problem to be solved by the present invention is to provide a substrate processing method capable of easily adjusting an etching step between an insulating layer and a semiconductor layer.
本発明の実施形態による基板処理方法は、基板上に半導体層と絶縁層とを提供する段階と、前記基板上に活性ガスを提供して前記半導体層の第１上部面にキャッピング絶縁層を形成する段階と、前記基板上に蝕刻ガスを提供して前記絶縁層の第２上部面と前記キャッピング絶縁層とを蝕刻副産物で形成する段階と、前記蝕刻副産物を除去して前記絶縁層と前記半導体層との蝕刻段差を調節する段階と、を含む。 A substrate processing method according to an embodiment of the present invention includes providing a semiconductor layer and an insulating layer on a substrate, and providing an active gas on the substrate to form a capping insulating layer on a first upper surface of the semiconductor layer. Providing an etching gas on the substrate to form a second upper surface of the insulating layer and the capping insulating layer with an etching by-product; removing the etching by-product to remove the insulating layer and the semiconductor; Adjusting an etching step with the layer.
本発明の一実施形態によれば、前記半導体層はポリシリコンを包含することができる。
本発明の他の実施形態によれば、前記絶縁層はシリコン酸化膜を包含することができる。
本発明の一実施形態によれば、前記キャッピング絶縁層はシリコン酸化膜を包含することができる。
According to an embodiment of the present invention, the semiconductor layer may include polysilicon.
According to another embodiment of the present invention, the insulating layer may include a silicon oxide film.
According to an embodiment of the present invention, the capping insulating layer may include a silicon oxide film.
本発明の他の実施形態によれば、前記絶縁層はシリコン窒化膜を包含することができる。 According to another embodiment of the present invention, the insulating layer may include a silicon nitride film.
本発明の一実施形態によれば、前記キャッピング絶縁層の形成段階は、酸素のリモートプラズマ処理工程を包含することができる。 According to an embodiment of the present invention, the step of forming the capping insulating layer may include an oxygen remote plasma treatment process.
本発明の他の実施形態によれば、前記蝕刻ガスはリモートプラズマ処理工程での三フッ化窒素を包含することができる。 According to another embodiment of the present invention, the etching gas may include nitrogen trifluoride in a remote plasma processing process.
本発明の一実施形態によれば、前記蝕刻副産物はアンモニア、フッ酸、又はシリコンを包含することができる。 According to an embodiment of the present invention, the etching byproduct may include ammonia, hydrofluoric acid, or silicon.
本発明の他の実施形態によれば、前記蝕刻副産物の除去段階は熱処理工程を包含することができる。 According to another embodiment of the present invention, the etching by-product removing step may include a heat treatment process.
本発明の一実施形態によれば、前記熱処理工程は１００℃以上で遂行できる。 According to an embodiment of the present invention, the heat treatment process can be performed at 100 ° C. or more.
本発明の他の実施形態によれば、前記活性ガスは酸素を包含することができる。 According to another embodiment of the present invention, the active gas may include oxygen.
本発明の一実施形態によれば、前記蝕刻副産物の形成段階は反応ガスを提供することをさらに含むことができる。 According to an embodiment of the present invention, the step of forming the etching by-product may further include providing a reactive gas.
本発明の他の実施形態によれば、前記反応ガスは水素又は窒素を包含することができる。 According to another embodiment of the present invention, the reaction gas may include hydrogen or nitrogen.
本発明の実施形態による基板処理方法は絶縁層と半導体層との表面酸化工程、蝕刻工程、及び熱処理工程を包含することができる。表面酸化工程は半導体層の第１上部表面にキャッピング絶縁層を形成する工程であり得る。蝕刻工程は前記キャッピング絶縁層と前記絶縁層とを蝕刻副産物で形成する工程であり得る。熱処理工程は蝕刻副産物を除去する工程であり得る。 The substrate processing method according to the embodiment of the present invention may include a surface oxidation process, an etching process, and a heat treatment process of the insulating layer and the semiconductor layer. The surface oxidation process may be a process of forming a capping insulating layer on the first upper surface of the semiconductor layer. The etching process may be a process of forming the capping insulating layer and the insulating layer with an etching byproduct. The heat treatment process may be a process of removing etching by-products.
したがって、本発明の実施形態による基板処理方法は絶縁層と半導体層との蝕刻段差を容易に調節することができる。 Therefore, the substrate processing method according to the embodiment of the present invention can easily adjust the etching step between the insulating layer and the semiconductor layer.
本発明の実施形態は下記の技術分野で通常の知識を有する者に本発明をさらに完全に説明するために提供されるものであり、下記の実施形態は様々な他の形態に変形され得り、本発明の範囲が下記の実施形態に限定されるものではない。むしろ、これらの実施形態は本開示をさらに充実させ、完全にさせて、当業者に本発明の思想を完全に伝達するために提供されるものである。また、図面で各層の大きさは説明の便宜及び明確性のために誇張されることもあり得る。 The embodiments of the present invention are provided to more fully explain the present invention to those having ordinary skill in the following technical fields, and the following embodiments may be modified in various other forms. The scope of the present invention is not limited to the following embodiment. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the size of each layer may be exaggerated for convenience of explanation and clarity.
明細書の全体に掛けて領域、半径、距離等のような１つの構成要素が他の構成要素に“連続されて”、“連結されて”、又は“カップリングされて”位置すると言及する時は、前記１つの構成要素が直接的に他の構成要素に“連続されて”、“連結されて”、又は“カップリングされて”接触するか、或いはその間に介在されるその他の構成要素が存在できると解釈できる。一方、１つの構成要素が他の構成要素に“直接的に連続されて”、“直接連結されて”、又は“直接カップリングされて”位置すると言及する時は、その間に介在される他の構成要素が存在しないことと解釈される。同一の符号は同一の要素を称する。本明細書で使用されたように、用語“及び／又は”は該当列挙された項目の中でいずれか１つ及び１つ以上のすべての組合を含む。 When referring to one component, such as area, radius, distance, etc., throughout the specification as being “continuous”, “coupled”, or “coupled” to other components Other components that are either “continuously”, “coupled”, or “coupled” in contact with one other component, or that are interposed between them. It can be interpreted that it can exist. On the other hand, when one component is referred to as being “directly connected”, “directly connected”, or “directly coupled” to another component, It is interpreted that the component does not exist. The same symbols refer to the same elements. As used herein, the term “and / or” includes any and all combinations of one or more of the listed items.
本明細書で第１、第２等の用語が多様な部材、部品、領域、面積を説明するために使用されるが、これらの部材、部品、領域、面積はこれらの用語によって限定されてはならないことは明確である。これらの用語は１つの部材、部品、領域、層又は部分を他の領域、層又は面積と区別するためのみに使用される。したがって、以下で説明する第１部材、部品、領域、面積は本発明の開示から逸脱しなくとも第２部材、部品、領域、面積を示すことができる。 In this specification, terms such as first and second are used to describe various members, parts, regions, and areas, but these members, components, regions, and areas are not limited by these terms. It is clear that it must not be. These terms are only used to distinguish one member, part, region, layer or part from another region, layer or area. Accordingly, the first member, component, region, and area described below can indicate the second member, component, region, and area without departing from the disclosure of the present invention.
また、“隣”又は“隣接”のような相対的な用語は図面で図解されるように他の構成要素に対するいずれの要素の関係を記述するためにここで使用され得る。相対的用語は図面で描いている方向に追加して素子の他の方向を含むことを意図することと理解できる。たとえば、他の方向は、図面で描いている方向対して９０°の範囲内に入る方向であってもよい。本明細書に使用される相対的な説明はこれによって解釈できる。 Also, relative terms such as “adjacent” or “adjacent” may be used herein to describe the relationship of any element to other components as illustrated in the drawings. It is understood that relative terms are intended to include other directions of the element in addition to the direction depicted in the drawings. For example, the other direction may be a direction that falls within a range of 90 ° with respect to the direction depicted in the drawing. The relative description used herein can be construed thereby.
本明細書で使用された用語は特定実施形態を説明するために使用され、本発明を制限するためのものではない。本明細書で使用されたように、単数形態は文脈の上に他の場合を明らかに示すものでなければ、複数の形態を包含することができる。また、本明細書で使用される場合、“含む（ｃｏｍｐｒｉｓｅ）”及び／又は“包含する（ｃｏｍｐｒｉｓｉｎｇ）”は言及された形状、数字、段階と、動作、部材、要素及び／又はこれらグループの存在を特定するものであり、１つ以上の他の形状、数字、動作、部材、要素及び／又はグループがの存在又は付加を排除するものではない。 The terminology used herein is used to describe particular embodiments and is not intended to limit the invention. As used herein, the singular form may include a plurality of forms unless the context clearly indicates otherwise. Also, as used herein, “comprise” and / or “comprising” is the presence of a referenced shape, number, step and action, member, element and / or group thereof. And does not exclude the presence or addition of one or more other shapes, numbers, actions, members, elements and / or groups.
以下、本発明の実施形態は本発明の理想的な実施形態を概略的に図示する図面を参照して説明する。図面において、例えば、製造技術及び／又は公差（ｔｏｌｅｒａｎｃｅ）にしたがって、図示された形状の変形が予想され得る。したがって、本発明の実施形態は本明細書に図示された領域の特定形状に制限されることとして解釈されてはならず、例えば製造上で招来される形状の変化を包含しなければならない。 In the following, embodiments of the present invention will be described with reference to the drawings schematically illustrating an ideal embodiment of the present invention. In the drawings, deformations of the illustrated shape can be expected, for example, according to manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to encompass variations in shapes that result, for example, from manufacturing.
図１は本発明の基板処理方法を説明するための基板処理装置を示す図面である。 FIG. 1 is a view showing a substrate processing apparatus for explaining a substrate processing method of the present invention.
図１を参照すれば、基板処理装置は、チャンバー１００、ガス供給部２００、及び制御部３００を包含することができる。 Referring to FIG. 1, the substrate processing apparatus may include a chamber 100, a gas supply unit 200, and a control unit 300.
チャンバー１００は外部から密閉された空間を提供する。真空ポンプ１４０はチャンバー１００の内部の空気をポンピングする。チャンバー１００はヒーター１１０、リフトピン１２０、及び隔壁（ｂａｆｆｌｅ、１３０）を包含することができる。ヒーター１１０は基板１１２を加熱することができる。基板１１２はリフトピン１２０によってヒーター１１０上に安着（ｌｏａｄｉｎｇ）され得る。リフトピン１２０はアンローディングの時に基板１１２をヒーター１１０から昇降させることができる。 The chamber 100 provides a space sealed from the outside. The vacuum pump 140 pumps the air inside the chamber 100. The chamber 100 may include a heater 110, a lift pin 120, and a baffle (130). The heater 110 can heat the substrate 112. The substrate 112 may be loaded on the heater 110 by lift pins 120. The lift pins 120 can raise and lower the substrate 112 from the heater 110 during unloading.
バッフル１３０はチャンバー１００を活性領域１３２と反応領域１３４とに分離できる。活性領域１３２は活性ガス、第１反応ガス、及び第２反応ガスが提供される領域である。活性領域１３２は上部領域１３１と下部領域１３３とに区分され得る。上部領域１３１はプラズマ発生領域である。活性ガス、第１反応ガス、及び第２反応ガスは高周波パワーによって上部領域１３１でプラズマ状態に励起されることができる。下部領域１３３は活性ガス、第１反応ガス、又は第２反応ガスの混合領域である。反応領域１３４は基板１１２の処理領域である。基板１１２は活性ガスと第１及び第２反応ガスによって、エッチング又は副産物が蒸着され得る。 The baffle 130 can separate the chamber 100 into an active region 132 and a reaction region 134. The active region 132 is a region where the active gas, the first reactive gas, and the second reactive gas are provided. The active region 132 may be divided into an upper region 131 and a lower region 133. The upper region 131 is a plasma generation region. The active gas, the first reactive gas, and the second reactive gas can be excited into a plasma state in the upper region 131 by high frequency power. The lower region 133 is a mixed region of the active gas, the first reaction gas, or the second reaction gas. The reaction area 134 is a processing area of the substrate 112. Etching or by-products may be deposited on the substrate 112 using the active gas and the first and second reaction gases.
ガス供給部２００は活性ガス供給部２１０、反応ガス供給部２２０、蝕刻ガス供給部２３０を包含することができる。活性ガスは酸素Ｏ２を包含することができる。反応ガスは水素Ｈ２又はアンモニアＮＨ３を包含することができる。蝕刻ガスはフッ酸ＨＦ、三フッ化窒素ＮＦ３を包含することができる。ガス供給部２００で活性領域１３２に連結される配管にバルブ２４０が配置され得る。バルブ２４０は制御部３００の制御信号にしたがって、ガス供給部２００のガス供給を調節することができる。制御部３００は温度センサー（図示せず）の感知信号に応答してヒーター１１０の温度を制御することができる。 The gas supply unit 200 may include an active gas supply unit 210, a reaction gas supply unit 220, and an etching gas supply unit 230. Active gas may include oxygen O 2. The reaction gas can include hydrogen H 2 or ammonia NH 3 . The etching gas can include hydrofluoric acid HF and nitrogen trifluoride NF 3 . A valve 240 may be disposed in a pipe connected to the active region 132 by the gas supply unit 200. The valve 240 can adjust the gas supply of the gas supply unit 200 according to the control signal of the control unit 300. The controller 300 may control the temperature of the heater 110 in response to a sensing signal from a temperature sensor (not shown).
このように構成された基板処理装置を利用する本発明の基板処理方法に対して説明する。 The substrate processing method of the present invention using the substrate processing apparatus configured as described above will be described.
図２は本発明の実施形態による基板処理方法を示したフローチャートである。 FIG. 2 is a flowchart illustrating a substrate processing method according to an embodiment of the present invention.
図３乃至図６は図２の基板処理方法にしたがう工程断面図である。 3 to 6 are process cross-sectional views according to the substrate processing method of FIG.
図１乃至図３を参照すれば、基板１１２上に絶縁層１０と半導体層２０とを提供する（Ｓ１０）。絶縁層１０はシリコン酸化膜又はシリコン窒化膜を包含することができる。半導体層２０はポリシリコンを包含することができる。ポリシリコンは導電性不純物でドーピングされ得る。絶縁層１０及び半導体層２０はチャンバー１０内のヒーター１１０上へローディングされ得る。 1 to 3, the insulating layer 10 and the semiconductor layer 20 are provided on the substrate 112 (S10). The insulating layer 10 can include a silicon oxide film or a silicon nitride film. The semiconductor layer 20 can include polysilicon. Polysilicon can be doped with conductive impurities. The insulating layer 10 and the semiconductor layer 20 may be loaded on the heater 110 in the chamber 10.
図１、図２、及び図４を参照すれば、基板１１２上に活性ガスを提供して半導体層２０の第１上部面にキャッピング絶縁層２２を形成する（Ｓ２０）。活性ガスは活性領域１３２の上部領域１３１へ供給され得る。例えば、酸素は上部領域１３１でプラズマ反応処理されて基板１１２上へ流動（ｆｌｏｗ）されることができる。プラズマ反応処理された酸素は絶縁層１０のシリコン酸化膜と反応されない。半導体層１３２のポリシリコンは酸素に選択的に反応され得る。キャッピング絶縁層２２は半導体層１３２の最外殻の第１上部面に形成され得る。キャッピング絶縁層２２の厚さは酸素に露出された時間と基板１１２の温度とに比例して増加され得る。 Referring to FIGS. 1, 2, and 4, an active gas is provided on the substrate 112 to form a capping insulating layer 22 on the first upper surface of the semiconductor layer 20 (S20). The active gas may be supplied to the upper region 131 of the active region 132. For example, oxygen can be plasma-reacted in the upper region 131 and flow onto the substrate 112. The oxygen subjected to the plasma reaction treatment does not react with the silicon oxide film of the insulating layer 10. The polysilicon of the semiconductor layer 132 can be selectively reacted with oxygen. The capping insulating layer 22 may be formed on the first upper surface of the outermost shell of the semiconductor layer 132. The thickness of the capping insulating layer 22 can be increased in proportion to the time exposed to oxygen and the temperature of the substrate 112.
図１、図２、及び図５を参照すれば、基板１１２上に蝕刻ガス及び反応ガスを提供して絶縁層１０の第２上部面と、キャッピング絶縁層２２を蝕刻副産物３０で形成する（Ｓ３０）。蝕刻ガスは三フッ化窒素であり得る。三フッ化窒素は上部領域１３１又は下部領域１３３へ提供され得る。反応ガスは上部領域１３１へ供給され得る。蝕刻ガスは絶縁層１０とキャッピング絶縁層２２と反応され得る。例えば、弗素はシリコン酸化膜内での活発に拡散されて反応され得る。反面、半導体層２０は蝕刻ガスから保護され得る。弗素はシリコン酸化膜よりポリシリコンで遅く反応され得る。したがって、絶縁層１０は蝕刻ガスから半導体層２０に比べて高い選択蝕刻比を有することができる。 Referring to FIGS. 1, 2, and 5, an etching gas and a reactive gas are provided on the substrate 112 to form a second upper surface of the insulating layer 10 and a capping insulating layer 22 using an etching byproduct 30 (S 30). ). The etching gas can be nitrogen trifluoride. Nitrogen trifluoride can be provided to the upper region 131 or the lower region 133. The reaction gas can be supplied to the upper region 131. The etching gas can react with the insulating layer 10 and the capping insulating layer 22. For example, fluorine can be actively diffused and reacted in the silicon oxide film. On the other hand, the semiconductor layer 20 can be protected from the etching gas. Fluorine can react more slowly with polysilicon than with silicon oxide. Therefore, the insulating layer 10 can have a higher selective etching ratio than the semiconductor layer 20 from the etching gas.
絶縁層１０とキャッピング絶縁層２２とは各々シリコン酸化膜であり得る。絶縁層１０は蝕刻ガスに露出された時間又は基板１１２の加熱温度にしたがって比例して増加される厚さの蝕刻副産物３０に変化され得る。蝕刻副産物３０はアンモニア、フッ酸、フッ化アンモニア、シリコン酸化物（ｓｉｌｉｃｏｎ ｏｘｉｄｅ）を包含することができる。したがって、本発明の実施形態による基板処理方法は絶縁層１０と半導体層２０との蝕刻段差を容易に調節することができる。 The insulating layer 10 and the capping insulating layer 22 can each be a silicon oxide film. The insulating layer 10 may be converted into an etching by-product 30 having a thickness that is proportionally increased according to the time exposed to the etching gas or the heating temperature of the substrate 112. The etching by-product 30 may include ammonia, hydrofluoric acid, ammonia fluoride, and silicon oxide. Therefore, the substrate processing method according to the embodiment of the present invention can easily adjust the etching step between the insulating layer 10 and the semiconductor layer 20.
図１、図２、及び図６を参照すれば、基板１１２を加熱して蝕刻副産物３０を除去する（Ｓ４０）。ヒーター１１０は基板１１２を約１００℃程度に加熱することができる。蝕刻副産物３０はヒーター１１０の熱エネルギーによって気化され得る。気化された蝕刻副産物３０はフッ化シリコンアンモニウム（ＮＨ４）２ＳｉＦ６であり得る。 Referring to FIGS. 1, 2, and 6, the substrate 112 is heated to remove the etching byproduct 30 (S40). The heater 110 can heat the substrate 112 to about 100 ° C. The etching by-product 30 can be vaporized by the thermal energy of the heater 110. The vaporized etch byproduct 30 may be silicon ammonium fluoride (NH 4 ) 2 SiF 6 .
したがって、本発明の実施形態による基板処理方法は絶縁層１０と半導体層２０との蝕刻段差を容易に調節することができる。 Therefore, the substrate processing method according to the embodiment of the present invention can easily adjust the etching step between the insulating layer 10 and the semiconductor layer 20.
図７乃至図１０は本発明の基板処理方法が適用されたＮＡＮＤフラッシュメモリ製造方法を示す工程断面図である。 7 to 10 are process sectional views showing a NAND flash memory manufacturing method to which the substrate processing method of the present invention is applied.
図７を参照すれば、活性層２４と、前記活性層２４上の複数のゲートスタック４０と、前記複数のゲートスタック４０の間のギャップフィル（ｇａｐ ｆｉｌｌ）酸化膜５０を提供する。活性層２４は基板１１２に連結されたバルクシリコンを包含することができる。ギャップフィル酸化膜５０はシリコン酸化膜を包含することができる。ゲートスタック４０は活性層２４上のトンネル酸化膜１２と、フローティングゲート２６とを包含することができる。活性層２４はバルクシリコン、即ち単結晶シリコンを包含することができる。トンネル酸化膜１２はシリコン酸化膜を包含することができる。フローティングゲート２６はポリシリコンを包含することができる。 Referring to FIG. 7, an active layer 24, a plurality of gate stacks 40 on the active layer 24, and a gap fill oxide film 50 between the plurality of gate stacks 40 are provided. The active layer 24 can include bulk silicon coupled to the substrate 112. The gap fill oxide film 50 may include a silicon oxide film. The gate stack 40 can include the tunnel oxide film 12 on the active layer 24 and the floating gate 26. The active layer 24 may include bulk silicon, that is, single crystal silicon. The tunnel oxide film 12 can include a silicon oxide film. The floating gate 26 can include polysilicon.
図８を参照すれば、ギャップフィル酸化膜５０を一定の深さまで除去する。ギャップフィル酸化膜５０は蝕刻ガスによって、フローティングゲート２６に比べて高い蝕刻選択比に除去され得る。この時、基板１１２は酸素に露出されないこともあり得る。蝕刻ガスはフローティングゲート２６及びギャップフィル酸化膜５０の各々の上部面に蝕刻副産物３０を形成できる。 Referring to FIG. 8, the gap fill oxide film 50 is removed to a certain depth. The gap fill oxide film 50 can be removed to a higher etching selectivity than the floating gate 26 by the etching gas. At this time, the substrate 112 may not be exposed to oxygen. The etching gas can form an etching by-product 30 on the upper surface of each of the floating gate 26 and the gap fill oxide film 50.
図９及び図１０を参照すれば、ギャップフィル酸化膜５０とフローティングゲート２６とを等方的に除去する。ギャップフィル酸化膜５０とフローティングゲート２６とは単位工程での蝕刻選択比が減少され得る。単位工程は表面酸化工程（Ｓ２０）、蝕刻工程（Ｓ３０）、及び熱処理工程（Ｓ４０）を包含することができる。単位工程は反復的に遂行できる。フローティングゲート２６は微細な線幅にトリミング（ｔｒｉｍｍｉｎｇ）され得る。 9 and 10, the gap fill oxide film 50 and the floating gate 26 are isotropically removed. The etch selectivity between the gap fill oxide film 50 and the floating gate 26 in the unit process can be reduced. The unit process may include a surface oxidation process (S20), an etching process (S30), and a heat treatment process (S40). The unit process can be performed iteratively. The floating gate 26 can be trimmed to a fine line width.
したがって、本発明の第１応用例にしたがう基板処理方法は蝕刻選択比の調節を利用してフローティングゲート２６を微細線幅にトリミングすることができる。 Accordingly, the substrate processing method according to the first application example of the present invention can trim the floating gate 26 to a fine line width by using the adjustment of the etching selection ratio.
図１１及び図１２は本発明の基板処理方法が適用された立体的な（ｔｈｒｅｅ−ｄｉｍｅｎｓｉｏｎａｌ）メモリの製造方法を示す工程断面図である。 11 and 12 are process cross-sectional views showing a method for manufacturing a three-dimensional memory to which the substrate processing method of the present invention is applied.
図１１を参照すれば、積層構造の絶縁層１０と半導体層２０を提供する。絶縁層１０はシリコン窒化膜を包含することができる。半導体層２０はポリシリコンを包含することができる。 Referring to FIG. 11, an insulating layer 10 and a semiconductor layer 20 having a stacked structure are provided. The insulating layer 10 can include a silicon nitride film. The semiconductor layer 20 can include polysilicon.
図１２を参照すれば、絶縁層１０に比べて半導体層２０を選択的に除去する。半導体層２０は単位工程によって除去され得る。上述したように、単位工程は表面酸化工程（Ｓ２０）、蝕刻工程（Ｓ３０）、熱処理工程（Ｓ４０）を包含することができる。半導体層２０は表面酸化工程（Ｓ２０）でシリコン酸化膜により形成され得る。シリコン酸化膜は蝕刻工程（Ｓ３０）で反応されて蝕刻副産物（図５の３０）で形成され得る。絶縁層１０は蝕刻ガスと反応されないことがあり得る。蝕刻副産物３０は熱処理工程（Ｓ４０）で除去され得る。半導体層２０は絶縁層に比べて選択的に微細に除去され得る。 Referring to FIG. 12, the semiconductor layer 20 is selectively removed as compared with the insulating layer 10. The semiconductor layer 20 can be removed by a unit process. As described above, the unit process can include a surface oxidation process (S20), an etching process (S30), and a heat treatment process (S40). The semiconductor layer 20 may be formed of a silicon oxide film in the surface oxidation step (S20). The silicon oxide film may be formed by etching by-products (30 in FIG. 5) by reacting in the etching process (S30). The insulating layer 10 may not react with the etching gas. The etching byproduct 30 can be removed in the heat treatment step (S40). The semiconductor layer 20 can be selectively and finely removed as compared with the insulating layer.
したがって、本発明の応用例にしたがう立体的なメモリの製造方法は絶縁層１０と半導体層２０との間に水平方向の蝕刻段差を調節することができる。 Therefore, the three-dimensional memory manufacturing method according to the application example of the present invention can adjust the horizontal etching step between the insulating layer 10 and the semiconductor layer 20.
以上で説明した本発明が前述した実施形態及び添付された図面に限定されなく、本発明の技術的思想を逸脱しない範囲内で様々な置換、変形及び変更が可能であることは、本発明が属する技術分野で通常の知識を有する者に明白である。 The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications and changes can be made without departing from the technical idea of the present invention. It will be obvious to those with ordinary knowledge in the technical field to which they belong.
１０ 絶縁層、
２０ 半導体層、
２２ キャッピング絶縁層、
２４ 活性層、
２６ フローティングゲート、
３０ 蝕刻副産物、
４０ ゲートスタック、
５０ ギャップフィル絶縁膜、
１００ チャンバー、
１１０ ヒーター、
１１２ 基板、
１３０ バッフル、
１３１ 上部領域、
１３２ 活性領域、
１３３ 下部領域、
１４０ ポンプ、
２００ ガス供給部、
３００ 制御部。
10 Insulating layer,
20 semiconductor layer,
22 Capping insulation layer,
24 active layer,
26 Floating gate,
30 Etching by-products,
40 gate stack,
50 gap fill insulating film,
100 chambers,
110 heaters,
112 substrates,
130 baffles,
131 upper region,
132 active region,
133 lower region,
140 pumps,
200 gas supply,
300 Control unit.
Claims (13)
前記基板上に活性ガスを提供して前記半導体層の第１上部面にキャッピング絶縁層を形成する段階と、
前記基板上に蝕刻ガスを提供して前記絶縁層の第２上部面と前記キャッピング絶縁層とを蝕刻副産物で形成する段階と、
前記蝕刻副産物を除去して前記絶縁層と前記半導体層との蝕刻段差を調節する段階と、を含む基板処理方法。 Providing a semiconductor layer and an insulating layer on a substrate;
Providing an active gas on the substrate to form a capping insulating layer on the first upper surface of the semiconductor layer;
Providing an etching gas on the substrate to form a second upper surface of the insulating layer and the capping insulating layer as etching by-products;
Removing the etching by-product and adjusting an etching step between the insulating layer and the semiconductor layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| JP2008159892A (en) * | 2006-12-25 | 2008-07-10 | Univ Nagoya | Pattern formation method and manufacturing method of semiconductor device |
| JP2008182199A (en) * | 2006-12-07 | 2008-08-07 | Applied Materials Inc | Multi-step dep-etch-dep (deposition-etching-deposition) high-density plasma chemical vapor deposition process for filling dielectric gap |
| WO2011112812A2 (en) * | 2010-03-10 | 2011-09-15 | Applied Materials, Inc. | Apparatus and methods for cyclical oxidation and etching |
| JP2012089817A (en) * | 2010-09-21 | 2012-05-10 | Toshiba Corp | Semiconductor memory device and method for manufacturing the same |
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| JP2008182199A (en) * | 2006-12-07 | 2008-08-07 | Applied Materials Inc | Multi-step dep-etch-dep (deposition-etching-deposition) high-density plasma chemical vapor deposition process for filling dielectric gap |
| JP2008159892A (en) * | 2006-12-25 | 2008-07-10 | Univ Nagoya | Pattern formation method and manufacturing method of semiconductor device |
| WO2011112812A2 (en) * | 2010-03-10 | 2011-09-15 | Applied Materials, Inc. | Apparatus and methods for cyclical oxidation and etching |
| JP2013522883A (en) * | 2010-03-10 | 2013-06-13 | アプライド マテリアルズ インコーポレイテッド | Apparatus and method for periodic oxidation and etching |
| JP2012089817A (en) * | 2010-09-21 | 2012-05-10 | Toshiba Corp | Semiconductor memory device and method for manufacturing the same |
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| TWI512822B (en) | 2015-12-11 |
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| JP5767295B2 (en) | 2015-08-19 |
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