JP2014072766A - Communication system, transmitter and receiver used therefor and communication method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication system capable of precisely establishing synchronization with a small size circuit at a low cost even under multipath fading circumstances.SOLUTION: The transmitter transmits a low speed unique word U1 having transmission speed lower than that of data D1; a unique word U2 having transmission speed identical to that of the data D1; and a data D1. The receiver detects the low speed unique word U1 from the received signals and estimates an existing range of the unique word U2 based on the detection result. The receiver establishes the symbol synchronization and the frame synchronization based on a correlation value between the signals within a prediction range A1 and the known unique word U2. Since the existing range of the unique word U2 is estimated based on the low speed unique word U1 which is subjected to little influence of the multipath fading, the detection accuracy of the unique word U2 is increased. Therefore, the synchronization establishment accuracy is increased by establishing the synchronization based on the signals within the prediction range A1. Also, a simple processing is required for increasing the synchronization establishment accuracy.

Description

  The present invention relates to a communication system in which a signal transmitted by radio from a transmitter is received by a receiver, a transmitter and a receiver used therefor, and a communication method.

  General wireless communication is asynchronous communication because the transmitter and the receiver operate with different clocks. Therefore, the receiver performs oversampling to sample the received baseband signal at a plurality of timings per symbol so as to be able to cope with reception of the baseband signal from the transmitter at any timing. Extract the timing that can be detected. This extraction process is referred to as a symbol synchronization process. In order to recognize a frame which is a basic unit of communication, it is necessary to identify the beginning of a header or data in the frame. This identification process is referred to as a frame synchronization process.

  As a conventional technique for establishing symbol synchronization, a zero cross detection method is widely known. In this zero cross detection method, a preamble (a signal following 101010...) That repeats 1 and 0 alternately is arranged at the head of the baseband signal. At the receiver, the baseband signal is oversampled, and the sign inversion timing of the preamble, that is, the timing of zero crossing is read. Then, based on the read zero-cross timing, a sampling timing capable of accurately detecting the symbol is obtained, and the sampling timing is set as the symbol synchronization timing. For example, the sampling timing closest to the middle between the zero cross and the next zero cross is set as the symbol synchronization timing.

  Next, FIG. 38 shows a method for establishing conventional frame synchronization for a baseband signal with symbol synchronization. It is assumed that a value obtained by oversampling a baseband signal, that is, a sample value of the baseband signal is originally quantized in the symbol synchronization establishment process. In the conventional method of establishing frame synchronization, the value quantized as described above is discriminated based on the binarization threshold value and replaced with the binary value for the sample value sequence at the sampling timing set at the symbol synchronization timing. (S101). Then, a correlation value between the sample value string and a known unique word that is also binary is calculated (S102). If the calculated correlation value is greater than or equal to a preset correlation threshold value (Yes in S103), it is determined that the sample value sequence matches the unique word, and the timing at which they match is the frame synchronization timing. Is set. In this way, frame synchronization is established (S104).

  By the way, in a radio communication system, intersymbol interference of received signals caused by multipath fading is cited as one of the problems. As shown in FIG. 39, this interference is caused by the fact that the transmitted signal arrives at the receiving antenna through a plurality of different paths (multipaths) with different delay times, and is added to the receiving antenna. The In a multipath environment, direct waves coming directly from the transmitting antenna and indirect waves reflected by obstacles are input to the receiving antenna, or only indirect waves that do not have direct waves and pass through multiple paths are transmitted to the receiving antenna. Or

  When such a phenomenon occurs, the received signal waveform may be distorted. The received signal waveform tends to be more easily distorted as the signal transmission speed is higher. The reason will be described with reference to FIG. As shown in the figure, when the signal transmission rate is high, the symbol length of the signal is shortened, so that the relative ratio of the delay time to the symbol length is high. Therefore, for example, when there are two signals that have passed through different paths, and the other signal is delayed due to multipath fading with respect to one signal and the symbol length of the signal is close to the delay time, the first signal of one signal The overlapping portion of the symbol and the 0th symbol of the other signal becomes longer. As a result, the distortion of the received signal waveform with respect to the symbol length becomes relatively large. In the figure, only two signals are taken up. However, in practice, a large number of multi-pulse signals having different delay amounts are added, so that the distortion can be further increased. When the distortion becomes large in this way, the above-described symbol synchronization establishment process cannot detect the original zero-cross timing, and therefore, there is a problem that stable symbol synchronization cannot be obtained. As a result, the above-described frame synchronization establishment process The synchronization accuracy may also be affected.

  Thus, as a typical measure for eliminating the influence of multipath fading, there is a multicarrier transmission technique such as OFDM (Orthogonal Frequency Division Multiplexing) (see, for example, Patent Document 1). It is possible to reduce the influence of multipath fading while maintaining the communication speed by dividing the information to be transmitted and transmitting in parallel on multiple carriers (subcarriers) and reducing the transmission speed of each carrier. Technology. In this technique, the symbol length is increased by reducing the transmission rate of each carrier, and the delay per symbol due to multipath fading is relatively sufficiently shorter than the symbol length as shown in FIG. . Therefore, even if it is affected by multipath fading, the distortion of the received signal waveform with respect to the symbol length is relatively small, so that symbol synchronization is easily established, and as a result, frame synchronization is also established stably. Can do.

JP 2010-103900 A

  However, multicarrier transmission requires a complicated configuration in which the frequency axis and the time axis are converted and processed by inverse Fourier transform and Fourier transform. For this reason, the communication system using the multicarrier transmission technique has a drawback that the cost becomes high, and the circuit scale increases and it is difficult to downsize the circuit.

  Therefore, as a method for reducing the influence of waveform distortion due to multipath fading by a single carrier without using multicarrier technology, there is a technique for lowering the transmission rate of the preamble than the transmission rate of the data to be communicated. Conceivable. However, with this technique, it is difficult to obtain a sampling timing capable of accurately detecting a data symbol from the preamble. Therefore, accurate symbol synchronization is difficult, and frame synchronization accuracy is reduced.

  The present invention has been made to solve this problem. An object of the present invention is to provide a communication system that can establish synchronization with high accuracy by a low-cost and small-scale circuit even in a multipath fading environment, a transmitter and a receiver used therefor, and a communication method. To do.

  In order to achieve the above object, a communication system according to the present invention includes a first synchronization bit string having a transmission speed lower than that of data to be transmitted, a second synchronization bit string having the same transmission speed as the data, and the data as a frame. The converted baseband signal is up-converted and converted into an RF signal, and the transmitter transmits the RF signal wirelessly, receives the transmitted RF signal, and downconverts the RF signal to extract the baseband signal. And detecting the first synchronization bit string in the baseband signal, and predicting a range in which the second synchronization bit string exists in the baseband signal based on the detection result, That establishes symbol synchronization and frame synchronization based on a correlation value between the baseband signal of the second and the known second synchronization bit string stored in advance Characterized in that it comprises a.

  The transmitter includes a low-speed bit string generation unit that generates the first synchronization bit string, a bit string generation unit that generates the second synchronization bit string, the first synchronization bit string, and the second synchronization bit string. A bit string and a radio transmitter that generates a baseband signal by framing and modulating the data, upconverts the baseband signal to convert it to an RF signal, and wirelessly transmits the RF signal The receiver receives an RF signal wirelessly transmitted by the wireless transmitter and down-converts the baseband signal to detect the baseband signal extracted by the wireless receiver; Detecting the first synchronization bit string in the baseband signal detected by the detector, and based on the detection result, A low-speed bit string detection unit that predicts a range in which the second synchronization bit string exists in a low-band signal, and the baseband signal in the range predicted by the low-speed bit string detection unit and the known first information stored in advance It is preferable to include a synchronization establishment unit that calculates a correlation value with the two synchronization bit strings and establishes symbol synchronization and frame synchronization based on the calculated correlation value.

  The transmitter further includes a usage environment input unit for inputting information on multipath fading in a usage environment of the transmitter and the receiver, and the wireless transmission unit is input by the usage environment input unit. It is preferable that the transmission speed of the first synchronization bit string can be switched based on the received information.

  It is preferable that the second synchronization bit string is configured by a pseudo random signal, and the wireless transmission unit continuously and repeatedly transmits the pseudo random signal.

  The receiver further includes a narrowband filter that extracts the first synchronization bit string from the baseband signal detected by the detection unit, and the low-speed bit string detection unit passes the narrowband filter. It is preferable that the first synchronization bit string is detected from a baseband signal.

  The receiver may further include a normalization unit that normalizes a level of a baseband signal input to the low-speed bit string detection unit and the synchronization establishment unit.

  The synchronization establishing unit includes an average value calculating unit that calculates a moving average value of a baseband signal input to the synchronization establishing unit, and the correlation value is set to a moving average value calculated by the average value calculating unit. If it is equal to or greater than the threshold value set based on this, the sampling timing of the correlation value may be set as the symbol synchronization timing, and the timing when the correlation value becomes equal to or greater than the set threshold value may be set as the frame synchronization timing.

  The wireless transmission unit periodically transmits a frame including the first synchronization bit string and the second synchronization bit string, and the low-speed bit string detection unit is configured to detect the second synchronization bit string from the time of detection. A counter that counts elapsed time, and the count time by the counter is within a known period from the time of detection of the second synchronization bit string until the start of input of the next first synchronization bit string Alternatively, the re-detection operation of the first synchronization bit string may be stopped.

  The wireless transmission unit transmits a data end signal indicating the end of the data, and the receiver detects the data end signal from the baseband signal detected by the detection unit, thereby ending the data. A data end detection unit for detecting timing; and the low-speed bit string detection unit from the time of detection of the second synchronization bit string to the end timing of the data detected by the data end detection unit. The re-detection operation of one synchronization bit string may be stopped.

  A plurality of the receivers are provided in the communication system, and the wireless transmission unit transmits a polling signal indicating a next signal transmission timing different for each receiver to the plurality of receivers, Each of the plurality of receivers includes a reception timing detection unit that detects a next signal reception timing based on a polling signal transmitted by the wireless transmission unit and received by the wireless reception unit, and the low-speed bit string detection unit is The re-detection operation of the first synchronization bit string may be stopped from when the wireless reception unit has received the polling signal until the next signal reception timing detected by the reception timing detection unit. .

  The receiver further includes a sampling unit that samples the baseband signal received by the wireless reception unit, and the detection unit detects a sample value sequence of the baseband signal sampled by the sampling unit, and In the correlation value calculation process, the synchronization establishment unit obtains the sample value and the bit value in the same order in time series for the sample value sequence detected by the detection unit and the second synchronization bit sequence. It is preferable to multiply and multiply the multiplication results using one register.

  The transmitter of the present invention is a transmitter used in the communication system.

  The receiver of this invention is a receiver used for the said communication system.

  In the communication method of the present invention, a first synchronization bit string having a transmission speed lower than that of data to be transmitted, a second synchronization bit string having the same transmission speed as the data, and a baseband signal obtained by framing the data are uploaded. A conversion step of converting into an RF signal, transmitting the RF signal by radio, receiving the RF signal transmitted by radio, down-converting the RF signal to extract a baseband signal, and extracting the baseband signal The first synchronization bit string is detected, and based on the detection result, a range in which the second synchronization bit string exists in the baseband signal is predicted, and the baseband within the predicted range is detected. A reception step for establishing symbol synchronization and frame synchronization based on a correlation value between the signal and the second bit string for synchronization stored in advance. And wherein the Mukoto.

  The transmission step includes a low-speed bit string generation step for generating the first synchronization bit string, a bit string generation step for generating the second synchronization bit string, the first synchronization bit string, and the second synchronization bit string. A wireless transmission step of generating a baseband signal by framing and modulating the bit string and the data, upconverting the baseband signal to convert it to an RF signal, and wirelessly transmitting the RF signal; The reception step receives the RF signal wirelessly transmitted by the wireless transmission step and down-converts it to extract a baseband signal, and detects the baseband signal extracted by the wireless reception step. A detection step and a previous step in the baseband signal detected by the detection step. A low-speed bit string detection step for detecting a first synchronization bit string and predicting a range in which the second synchronization bit string exists in the baseband signal based on the detection result; and a prediction by the low-speed bit string detection step A synchronization value for calculating a correlation value between the baseband signal within the determined range and the known second synchronization bit string stored in advance, and establishing symbol synchronization and frame synchronization based on the calculated correlation value And an establishing step.

  According to the present invention, since the range in which the second synchronization bit string exists is predicted based on the first synchronization bit string that is not easily affected by inter-symbol interference due to multipath fading, the second synchronization bit string Increase detection accuracy. Therefore, the synchronization establishment accuracy can be improved by attempting to establish synchronization based on the signal within the prediction range. Further, the processing necessary for improving the synchronization establishment accuracy is simpler than multi-carrier technology such as OFDM, and as a result, the circuit scale can be reduced and the cost of the circuit can be reduced. it can.

1 is a block diagram of a communication system according to an embodiment of the present invention. The frame block diagram of the baseband signal of the said communication system. The figure which shows the sampling timing to the unique word and data by the receiver of the said communication system. The figure which shows the sampling timing to the low-speed unique word and unique word by the said receiver. The block diagram of the low-speed unique word detection circuit of the said receiver. The block diagram of the synchronization establishment circuit of the said receiver. The figure which shows the correlation value calculation method of the said low speed unique word detection circuit. The figure which shows the correlation value calculation method of the said synchronization establishment circuit. The flowchart of the transmission process of the baseband signal in the transmitter of the said communication system. The flowchart of the reception process of the baseband signal in the said receiver. The flowchart of the synchronization establishment process to the baseband signal in the said synchronization establishment circuit. The figure which shows the fluctuation | variation of the correlation value with respect to the received signal in the said receiver. (A) thru | or (d) is a figure for demonstrating the correlation value calculation method of the said synchronization establishment circuit. (A) thru | or (d) is a figure for demonstrating the correlation value calculation method of the said synchronization establishment circuit. The block diagram of the communication system which concerns on the 1st modification of the said embodiment. The block diagram of the low-speed unique word detection circuit of the receiver in the said communication system. The frame structure figure of a baseband signal when the influence of the multipath fading in the said communication system is small and large. The figure which shows the fluctuation | variation of the correlation value with respect to the received signal in the receiver of the communication system which concerns on the 2nd modification of the said embodiment. The figure which shows the fluctuation | variation of the correlation value with respect to the received signal in the receiver of the communication system which concerns on the comparative example of this modification. The block diagram of the receiver of the communication system which concerns on the 3rd modification of the said embodiment. The block diagram of the receiver of the communication system which concerns on the 4th modification of the said embodiment. The flowchart of the reception process of the baseband signal in the said receiver. The block diagram of the synchronization establishment circuit of the communication system which concerns on the 5th modification of the said embodiment. The flowchart of the synchronization establishment process to the baseband signal in the said synchronization establishment circuit. The figure which shows the transmission signal by the transmitter of the communication system which concerns on the 6th modification of the said embodiment. The block diagram of the synchronizing circuit of the receiver of the said communication system. 6 is a timing chart of low-speed unique word redetection stop processing in the synchronization circuit. The flowchart of the low detection unique word redetection stop process in the said synchronous circuit. The block diagram of the communication system which concerns on the 7th modification of the said embodiment. The block diagram of the synchronizing circuit of the receiver of the said communication system. 6 is a timing chart of low-speed unique word redetection stop processing in the synchronization circuit. The flowchart of the low detection unique word redetection stop process in the said synchronous circuit. The block diagram of the communication system which concerns on the 8th modification of the said embodiment. The figure which shows the communication timing from the transmitter in the said communication system to each receiver. The block diagram of the synchronizing circuit of each said receiver. The flowchart of the low detection unique word redetection stop process in the said synchronous circuit. The figure which shows the correlation value calculation method of the communication system which concerns on the 9th modification of the said embodiment. 10 is a flowchart of conventional frame synchronization processing. The figure for demonstrating the influence which multipath fading has on communication. The figure which shows the received signal by the receiver when a signal with a high transmission rate is delayed due to multipath. The figure which shows the received signal by the receiver when the signal with a slow transmission rate delays due to multipath.

  FIG. 1 shows a configuration of a communication system according to an embodiment of the present invention. The communication system 1 includes a transmitter 2 and a receiver 3 that communicate in a wireless manner. The transmitter 2 modulates data to be transmitted to generate a symbol sequence, up-converts a baseband signal composed of the symbol sequence to convert it to an RF signal, and wirelessly transmits the RF signal. The baseband signal is transmitted in units of frames having a predetermined data length. The data length of the frame may be a plurality of patterns. The receiver 3 receives the RF signal transmitted from the transmitter 2, acquires a baseband signal by down-converting the received RF signal, detects the acquired baseband signal, and reads data. .

  By the way, since the communication between the transmitter 2 and the receiver 3 is wireless, the receiver 3 does not know the timing at which a signal is transmitted from the transmitter 2 at first, and is in an asynchronous state. It is in. Therefore, in order for the receiver 3 to read data from the baseband signal, it is necessary not only to detect the baseband signal but also to establish symbol synchronization and frame synchronization between the transmitter 2 and the receiver 3.

  Therefore, in this embodiment, as shown in FIG. 2, a low-speed unique word U1 (first synchronization bit string) and a unique word U2 (second synchronization bit string) for establishing synchronization are added to the head of the frame F1. Has been. The low speed unique word U1 is set so that the transmission speed is lower than that of the data D1, and the unique word U2 is set so that the transmission speed is substantially the same as that of the data D1. The low speed unique word U1 has a lower transmission rate and a longer symbol length than the unique word U2. The transmitter 2 converts the low-speed unique word U1, the unique word U2 and the transmission target data D1 into a frame and modulates it into a baseband signal. The low-speed unique word U1 and the unique word U2 are not limited to signals that alternately repeat 0 and 1 as illustrated. The receiver 3 detects the baseband signal, detects the low-speed unique word U1 in the detected baseband signal, and predicts the range where the unique word U2 in the baseband signal exists based on the detection result. . Then, the receiver 3 establishes symbol synchronization and frame synchronization based on a correlation value between a baseband signal existing within the predicted range and a known unique word U2 stored in advance. Hereinafter, when simply referred to as synchronization, symbol synchronization and frame synchronization are collectively indicated. Hereinafter, the description will return to FIG. 1, but FIG. 2 will be referred to again as appropriate.

  The transmitter 2 includes a low-speed unique word generation circuit 21 (low-speed bit string generation unit) that generates a low-speed unique word U1, a unique word generation circuit 22 (bit string generation unit) that generates a unique word U2, and a transmission circuit 23 (wireless transmission). Part). The low-speed unique word generation circuit 21 sets the transmission speed of the low-speed unique word U1 to 1 / n (n is larger than n: 1) of the transmission speed of the data D1. With this setting, the symbol frequency of the low-speed unique word U1 is set to 1 / n times the symbol frequency of the data D1, and the symbol length of the low-speed unique word U1 is set to n times the symbol length of the data D1. The symbol frequency is the number of symbols transmitted per second. That is, the symbol frequency is lowered by setting the transmission rate low, and the symbol frequency is raised by setting the transmission rate high. Since the unique word generation circuit 22 sets the transmission rate of the unique word U2 to be substantially the same as the transmission rate of the data D1, the symbol frequency and the symbol length are the same between the unique word U2 and the data D1. The transmission circuit 23 frames the low-speed unique word U1, the unique word U2, and the data D1 and modulates them to generate a baseband signal. The transmission circuit 23 up-converts the baseband signal to convert it to an RF signal, and wirelessly transmits the RF signal from the antenna 24 to the receiver 3.

  The receiver 3 includes a reception circuit 31 (radio reception unit) that receives an RF signal wirelessly transmitted by the transmission circuit 23 via the reception antenna 30, down-converts, and acquires a baseband signal. In addition, the receiver 3 includes an AD converter 32 (sampling unit) that performs AD conversion on the baseband signal acquired by the receiving circuit 31. The receiver 3 further includes a synchronization circuit 33 that establishes synchronization with the baseband signal that has passed through the AD converter 32, and a signal processing circuit 34 that processes the baseband signal whose synchronization is established by the synchronization circuit 33.

  When AD converting the baseband signal, the AD converter 32 oversamples the baseband signal at a sampling frequency higher than the symbol frequency of the unique word U2 and the data D1. Then, the AD converter 32 quantizes the sample value of the baseband signal obtained by the oversampling with M (M: integer greater than or equal to 2) bits.

  Here, the sampling process of the AD converter 32 will be described with reference to FIG. This figure shows a case where the sampling target is the unique word U2 and a case where the sampling target is the data D1. The sampling process in these two cases is common. The AD converter 32 samples the entire baseband signal B1 at a sampling frequency at which the unique word U2 and one symbol Sb of the data D1 can be sampled at a plurality of sampling timings. Specifically, the AD converter 32 samples the signal value of the baseband signal B1 at, for example, four sampling timings (0) to (3) per symbol Sb (four times sampling). The sampling timings (0) to (3) are shifted at equal intervals in time. In the case of quadruple sampling, the interval is 1/4 of the period of the symbol Sb, that is, the baseband signal B1 is a symbol. Sampling is performed at a frequency four times the frequency of Sb. The number of sampling timings for one symbol Sb is not limited to the above four, and may be plural. In the present embodiment, a sampling timing that can accurately capture the value of the symbol Sb is detected from the sampling timings (0) to (3), and the sampling timing is set as the symbol synchronization timing. Established.

  As shown in FIG. 4, the symbol length T1 of the low-speed unique word U1 is n times the symbol length T2 of the data D1 and the unique word U2. Therefore, the low-speed unique word U1 is sampled at 4 × n sampling timings per symbol by the 4 × sampling process described above. Note that the low-speed unique word U1 and the unique word U2 are not limited to the illustrated number of bits. Returning to the description of FIG.

  The synchronization circuit 33 detects a baseband signal received by the receiving circuit 31 and a low-speed unique word detection that detects a low-speed unique word U1 in the baseband signal detected by the detection circuit 35. Circuit 36 (low-speed bit string detector). The detection circuit 35 detects (decodes) the sample value sequence of the baseband signal quantized by the AD converter 32 by delay detection or the like. The low speed unique word detection circuit 36 predicts a range where the unique word U2 exists in the baseband signal based on the detection result of the low speed unique word U1. The synchronization circuit 33 calculates a correlation value between a baseband signal existing within the range predicted by the low-speed unique word detection circuit 36 and a known unique word U2 stored in advance (synchronization establishment circuit 37 (synchronization establishment). Part). The synchronization establishment circuit 37 establishes symbol synchronization and frame synchronization based on the calculated correlation value.

  FIG. 5 shows a configuration of the low-speed unique word detection circuit 36. The low-speed unique word detection circuit 36 includes a bit string extraction circuit (hereinafter referred to as an extraction circuit) 36a, a storage circuit 36b, a correlation value calculation circuit (hereinafter referred to as a calculation circuit) 36c, a threshold setting circuit 36d, a comparison circuit 36e, and a prediction circuit 36f. Have.

  The extraction circuit 36a extracts each sample value sequence of 4 × n sampling timings from the sample value sequence detected by the detection circuit 35 at each sampling timing. The number of sample values in the sample value sequence to be extracted is set to the same number as the number of bits of the low-speed unique word U1. The storage circuit 36b stores a known low-speed unique word U1 in advance.

  The calculation circuit 36c calculates a correlation value between the sample value sequence extracted by the extraction circuit 36a and the low-speed unique word U1 stored in advance in the storage circuit 36b at each sampling timing. The calculation circuit 36c multiplies the sample value string extracted by the extraction circuit 36a and the low-speed unique word U1 stored in the storage circuit 36b by the sample value and the bit value in the same order in time series, The sum of the multiplication results is calculated as a correlation value. At this time, in the actual calculation, signal processing corresponding to multiplication of the sample value sequence and the low-speed unique word U1 is executed. The correlation value calculated by the calculation circuit 36c increases as the sample value string extracted by the extraction circuit 36a approaches the bit string of the low-speed unique word U1. The value of each bit of the low-speed unique word U1 stored in advance in the storage circuit 36b is an ideal value composed of binary values of 0 or 1. The binary values 0 and 1 are converted so as to be treated in the same way as binary values having the same absolute value but different signs, for example, -1 and +1, in predetermined signal processing in the calculation circuit 36c. The The value subjected to the conversion process is used as a bit value for the correlation value calculation process by the calculation circuit 36c.

  The threshold setting circuit 36d presets a correlation value threshold based on an input from an operation unit (not shown) or an interface unit. The set threshold value (hereinafter referred to as the first set threshold value) is a signal processing so that the absolute value of the maximum possible correlation value (ideal correlation value) is multiplied by a coefficient of 1 or less, for example, 0.7. It is controlled by. The reason why the first set threshold is set to such a value is that even if the received signal waveform is distorted and the correlation value becomes small, the first set threshold is distinguished between the correlation value of the low-speed unique word U1 and the correlation value of noise. This is because it is not necessary to completely match the ideal correlation value as long as it is possible. The comparison circuit 36e compares the correlation value calculated by the calculation circuit 36c with the first set threshold value at each sampling timing, and determines whether or not the calculated correlation value is greater than or equal to the first set threshold value. When the comparison circuit 36e determines that the correlation value is greater than or equal to the first set threshold, the prediction circuit 36f recognizes that the low-speed unique word U1 has been detected, and determines the range in which the unique word U2 in the baseband signal exists. Predict.

  FIG. 6 shows the configuration of the synchronization establishment circuit 37. The synchronization establishment circuit 37 includes a bit string extraction circuit (hereinafter referred to as an extraction circuit) 37a, a storage circuit 37b, a correlation value calculation circuit (hereinafter referred to as a calculation circuit) 37c, a threshold setting circuit 37d, a comparison circuit 37e, a synchronization detection circuit 37f, and a synchronization A setting circuit 37g is included.

  The extraction circuit 37a extracts a sample value sequence at each sampling timing (0) to (3) (see FIG. 3) from the sample value sequence detected by the detection circuit 35 at each sampling timing. The number of sample values of the extracted sample value sequence is the same as the number of bits of the unique word U2. The storage circuit 37b stores a known unique word U2 in advance.

  By the way, the sample value sequence of each sampling timing (0) to (3) extracted by the extraction circuit 37a is a sample value sequence obtained by sampling the baseband signal once per symbol for each sampling timing. The calculation circuit 37c calculates a correlation value between the sample value sequence within the prediction range of the low-speed unique word U1 and the bit sequence of the unique word U2 stored in advance in the storage circuit 37b at each sampling timing. In this calculation process, the calculation circuit 37c multiplies the sample value sequence and the unique word U2 by the sample value and the bit value in the same order in time series order, calculates the sum of the multiplication results, and calculates the correlation. Value. At this time, in actual calculation, signal processing corresponding to multiplication of the sample value string and the unique word U2 is executed. The correlation value calculated by the calculation circuit 37c becomes higher as the sample value string is closer to the unique word U2. The value of each bit of the unique word U2 stored in advance in the storage circuit 37b is an ideal value composed of binary values of 0 or 1. The binary values 0 and 1 are converted so as to be treated in the same manner as binary values having the same absolute value but different signs, for example, -1 and +1, in predetermined signal processing in the calculation circuit 37c. The The value subjected to the conversion process is used as a bit value for the correlation value calculation process by the calculation circuit 37c.

  The threshold setting circuit 37d presets a correlation value threshold that is a criterion for establishing synchronization based on an input from an operation unit or an interface unit (not shown). The set threshold value (hereinafter referred to as the second set threshold value) is obtained by signal processing so that the absolute value of the maximum possible correlation value (ideal correlation value) is multiplied by a coefficient of 1 or less, for example, 0.7. Be controlled. The reason why the second set threshold is set to such a value is that even if the received signal waveform is distorted and the correlation value becomes small, the second set threshold can be distinguished from the correlation value of the unique word U2 and the correlation value of noise. This is because it is not necessary to completely match the ideal correlation value if possible. The comparison circuit 37e compares the correlation value between the correlation value at the sampling timing calculated by the calculation circuit 37c and the second setting threshold at each sampling timing, and whether or not the calculated correlation value is equal to or greater than the second setting threshold. Determine whether.

  Assume that one of the correlation values of the sampling timing calculated by the calculation circuit 37c is determined by the comparison circuit 37e to be greater than or equal to the second set threshold value. The synchronization detection circuit 37f detects the sampling timing of the correlation value as the symbol synchronization timing. Further, the synchronization detection circuit 37f detects the timing at which the correlation value is determined to be equal to or higher than the second setting threshold as the frame synchronization timing. The synchronization setting circuit 37g sets the sampling timing detected as the symbol synchronization timing by the synchronization detection circuit 37f to the symbol synchronization timing of the baseband signal detected by the detection circuit 35. The synchronization setting circuit 37g sets the timing detected by the synchronization detection circuit 37f as the frame synchronization timing to the frame synchronization timing of the baseband signal detected by the detection circuit 35. In this way, the synchronization setting circuit 37g sets the symbol synchronization timing and the frame synchronization timing based on the correlation value calculated by the calculation circuit 37c, and establishes synchronization.

  After synchronization is established, the synchronization setting circuit 37g extracts and outputs each sample value after detection of the symbol synchronization timing as each symbol value of the detected baseband signal. For example, when the sampling timing (1) among the sampling timings (0) to (3) is set to the symbol synchronization timing, the synchronization setting circuit 37g converts each sample value sampled at the sampling timing (1) to the symbol Output as a value. Therefore, the signal output from the synchronization setting circuit 37g is a sample value sequence obtained by sampling the baseband signal after detection at a frequency that is one time the symbol frequency (sample value sequence obtained by sampling the baseband signal once). The synchronization setting circuit 37g does not output the sample value sequence of other sampling timings, that is, the sample value sequence of the sampling timings (0), (2), and (3) in the above example.

  FIG. 7 shows a correlation value calculation method by the calculation circuit 36c. The calculation circuit 36c replaces the sample value quantized with M bits with the binary value of -1 or 1 for the sample value sequence extracted by the extraction circuit 36a, and correlates the sample value sequence with the low-speed unique word U1. Is calculated. In this calculation process, the result of hard decision by binarization of the sample value after detection is used. In the present embodiment, the hard decision is performed in the above calculation process to reduce the circuit scale, but it may be a soft decision that uses the sample value after detection as it is without being binarized. . The low speed unique word U1 is not limited to the number of bits shown.

  FIG. 8 shows a correlation value calculation method by the calculation circuit 37c. The calculation circuit 37 c uses the sample value sequence extracted by the extraction circuit 37 a as it is without replacing the sample value quantized with M bits with the binary value of −1 or 1, and uses the sample value sequence as it is. And the correlation value between the unique word U2 and the bit string. In this calculation process, since the sample value after detection quantized by soft-decision of the sample value after detection is used as it is, the certainty as to whether the sample value is binary is used as it is. It is done. The unique word U2 is not limited to the number of bits shown.

  Next, communication processing in the communication system 1 will be described with reference to FIGS. 9 and 10 in addition to FIGS. 1 and 2. FIG. 9 shows a signal transmission step by cooperation of each circuit of the transmitter 2, and FIG. 10 shows a reception step by cooperation of each circuit of the receiver 3.

  As shown in FIG. 9, the low speed unique word generation circuit 21 generates a low speed unique word U1 (S11; low speed bit string generation step), and the unique word generation circuit 22 generates a unique word U2 (S12; bit string generation). Part). Thereafter, the transmission circuit 23 frames the low-speed unique word U1, the unique word U2 and the data D1 and modulates them to generate a baseband signal (S13; wireless transmission step). Then, the transmission circuit 23 up-converts the baseband signal to convert it into an RF signal, and wirelessly transmits the RF signal (S14; wireless transmission step). During the wireless transmission, the low-speed unique word U1, the unique word U2, and the data D1 are transmitted in this order.

  As shown in FIG. 10, the reception circuit 31 receives an RF signal, down-converts the received RF signal to obtain a baseband signal (S21; wireless reception step), and the AD converter 32 The acquired baseband signal is AD converted (S22). The detection circuit 35 detects the baseband signal after AD conversion (S23; detection step). The low-speed unique word detection circuit 36 detects the low-speed unique word U1 in the baseband signal detected in S23 (Yes in S24). At that time, the low-speed unique word detection circuit 36 predicts a range where the unique word U2 exists in the baseband signal based on the detection result (S25; low-speed bit string detection step). The synchronization establishment circuit 37 calculates a correlation value between the baseband signal existing within the prediction range in S25 and the bit string of the unique word U2, and establishes symbol synchronization and frame synchronization based on the calculated correlation value (S26). ; Synchronization establishment step).

  Next, synchronization establishment processing by cooperation of each circuit of the synchronization establishment circuit 37 will be described with reference to FIG. 11 in addition to FIG. 2, FIG. 3, FIG. 5 and FIG. FIG. 11 shows the procedure of the synchronization establishment process. Here, N is the number of bits of the unique word U2.

  The extraction circuit 37a sequentially extracts an N-bit sample value sequence for each sampling timing (0) to (3) from the sample value sequence of the baseband signal after detection by the detection circuit 35 (S31). The calculation circuit 37c calculates a correlation value between the sample value string extracted in S31 and the bit string of the unique word U2 stored in advance in the storage circuit 37b (S32). The correlation value is calculated at every sampling timing.

  The comparison circuit 37e compares the correlation value calculated in S32 with the second set threshold value (S33), and determines at each sampling timing whether the calculated correlation value is equal to or greater than the second set threshold value.

  When it is determined that the correlation value calculated in S33 is equal to or greater than the second set threshold (Yes in S34), the synchronization detection circuit 37f detects the sampling timing of the correlation value as the symbol synchronization timing. At the same time, the synchronization detection circuit 37f detects the timing at which the correlation value is determined to be greater than or equal to the second set threshold as frame synchronization timing (S35). The synchronization setting circuit 37g sets the synchronization timing detected in S35 for the sample value sequence after detection by the detection circuit 35 (S36; synchronization establishment step). When it is determined that the correlation value calculated in S32 is less than the second set threshold (No in S34), the process returns to S31.

In the present embodiment, the low-speed unique word U1 has a lower transmission speed and a longer symbol length than the unique word U2 and the data D1. Therefore, even if the reception signal waveform of the low speed unique word U1 is distorted due to multipath fading, the distortion of the reception signal waveform with respect to the symbol length can be made relatively smaller than that of the unique word U2. Therefore, the influence on the low-speed unique word U1 due to multipath fading can be reduced. As a result, the low-speed unique word U1 can be accurately detected, and based on the detection, the range in which the unique word U2 exists is predicted, thereby increasing the accuracy of detecting the unique word U2. Therefore, by calculating the correlation value between the baseband signal in the prediction range A1 and the known unique word U2 and establishing synchronization, the correlation value becomes the second set threshold C as shown in FIG. It is possible to prevent erroneous synchronization at a timing outside the prediction range A1 that exceeds _TH . Therefore, the probability of erroneous synchronization can be reduced, and synchronization establishment accuracy can be improved. Further, the processing necessary for improving the synchronization establishment accuracy is simpler than multi-carrier technology such as OFDM, and as a result, the circuit scale can be reduced and the cost of the circuit can be reduced. it can. The prediction range A1 is a range in which the entire unique word U2 can exist, but the maximum correlation value is actually the timing when all the unique words U2 have been received. Therefore, in FIG. 12, the prediction range A1 is shown near the last symbol of the unique word U2.

  Further, in the prediction range A1 (see FIG. 12) in which the existence of the unique word U2 is predicted, there is a place where the correlation value between the bit string in the prediction word A2 and the bit string of the unique word U2 becomes high. It is assumed that the threshold will be exceeded. Therefore, by establishing synchronization based only on the correlation value within the prediction range A1, the possibility of erroneous synchronization can be reduced, and efficient synchronization can be established.

  If the correlation value of any sampling timing among the sampling timings (0) to (3) is equal to or higher than the second setting threshold, the sampling timing is set as the symbol synchronization timing. The timing at which the correlation value becomes equal to or greater than the second setting threshold is set as the frame synchronization timing. Therefore, both symbol synchronization and frame synchronization can be established at the same time, the time required for establishing these synchronizations can be shortened, and the processing speed can be increased. Further, in order to establish symbol synchronization, it is not necessary to detect a zero cross by arranging a signal that repeats 1 and 0 alternately at the head of the baseband signal. Therefore, a signal that repeats 1 and 0 alternately becomes unnecessary and a zero-cross detection circuit is not required.

  Further, in the sample value sequence of the baseband signal after detection, the sample value is quantized with M bits and is used as it is without being binarized by the calculation circuit 37c to calculate the correlation value. . Therefore, even if the received baseband signal waveform is distorted due to multipath fading, it is based on rounding at the time of binarization compared to the case of calculating the correlation value after converting the quantized sample value to binary. Correlation value error is eliminated. Therefore, it is possible to improve the accuracy of establishing synchronization based on the correlation value. Further, the processing necessary for improving the accuracy of establishing synchronization is simpler than multi-carrier techniques such as OFDM, and therefore the circuit scale can be reduced and the cost of the circuit can be reduced. .

  The effect of the calculation method of the calculation circuit 37c will be further described. As comparison targets of the calculation method, sample values are replaced with binary values of 1 or −1 with a threshold value of 0, and two examples of correlation values calculated after a so-called hard decision are shown in FIGS. ). In these examples, the bit string of the unique word U2 has a 3-bit configuration of 1, -1, 1, and so on. The value and the number of bits of each bit of the unique word U2 are not limited to this. Hereinafter, a method of calculating a correlation value by replacing a sample value with a binary value is referred to as a binarization calculation method.

  FIG. 13A shows a case where the extracted sample value sequence is a sample value sequence of the unique word U2 in the received signal and is, for example, 0.8, −0.3, and −0.1. In this example, the sample value −0.1 has an ideal value of 1 and the sign is inverted compared to the ideal value, but the difference from the threshold is only 0.1. However, the sample value -0.1 is rounded to -1 by binarization to -1 or 1 with 0 as the threshold, and the difference from the threshold is considered to be 1. As a result, the correlation value of the extracted sample value sequence is 1.0.

  On the other hand, FIG. 13B shows sample value sequences of other signals that are not the unique word U2 in the received signal, for example, 0.8, −0.3, −0. 7 is shown. The correlation value in this case is also 1.0.

  As shown in these results, in the binarization calculation method, the difference between the correlation value when the unique word U2 is received and the correlation value when another signal is received may be small. As the example shows, sometimes it is zero. Therefore, it may be difficult to distinguish the unique word U2 from other signals in the received signal, and there is a risk of erroneous synchronization.

  On the other hand, in the calculation method of the calculation circuit 37c, even if the conditions are the same as those in FIGS. 13A and 13B, the correlation value is 1 as shown in FIGS. 13C and 13D. 0.0 and 0.4, and the difference between the correlation values in each case is 0.6. As shown in this result, in the calculation method of the present embodiment, the difference between the correlation value when the unique word U2 is received and the correlation value when other signals are received increases. Therefore, it is easy to distinguish the unique word U2 from other signals in the received signal, and the synchronization accuracy is increased.

  By the way, in the binarization calculation method, as shown in FIGS. 14A and 14B, even if the sample value is, for example, 0.8, −0.3, 0.1, or 0.9, Even if −0.9 and 0.9, the correlation value is 3.0, which is the same. When the correlation value setting threshold is set to 2.0, for example, the correlation value is equal to or greater than the setting threshold at the sampling timings in FIGS. 14A and 14B, and therefore it cannot be determined which sampling timing is good. Since the sample value sequence at the latter sampling timing is closer to the unique word U2, it is more appropriate to set the timing at which the sample value sequence is extracted as the synchronization timing. However, it is difficult because the correlation values of both sample value sequences are equal.

  On the other hand, in the calculation method of this embodiment, as shown in FIGS. 14C and 14D, the correlation values in the above two examples are 1.2 and 2.7, respectively, and any sampling timing is obtained. Can be determined. As described above, in the calculation method of the present embodiment, the correlation value is calculated in detail according to the sample value string, and therefore, a more appropriate timing can be set as the synchronization timing based on the correlation value. Is even higher.

  14 (a) and 14 (c), the sample value of −0.1 in FIGS. 13 (a) and 13 (c) is 0.1 instead, which is closer to the ideal value 1. Shows the case. As shown in FIG. 14A, in the case of the binarization calculation method, the correlation value is 2.0 (= 3.0) even though the sample value is only 0.2 close to the ideal value. -1.0) also increases. On the other hand, as shown in FIG. 14C, in the case of the calculation method of the present embodiment, the correlation value is 1.2, and the increase in the correlation value is 0.2 (= 1.2-1. Stay 0).

  As can be seen by comparing these two examples, with the binarization calculation method, the correlation value may increase significantly even if the sample value changes slightly in the vicinity of the threshold value. Therefore, a timing that is not appropriate is set as the synchronization timing. The synchronization accuracy may be reduced. On the other hand, in the calculation method of the present embodiment, since the correlation value is appropriately calculated according to the sample value, a more appropriate timing can be set as the synchronization timing, and the synchronization accuracy is further improved.

Next, modifications of the above embodiment will be described with reference to the drawings. The same reference numerals are given to the same components as those of the above-described embodiment, and when the configuration is described, FIGS. Only the configuration and processing different from the above embodiment will be described below.
(First modification)
By the way, if there are many obstacles or reflecting objects that reflect communication signals in the usage environment of the transmitter 2 and the receiver 3, the distortion of the received signal waveform of the receiver 3 increases due to the influence of multipath fading. There is a high possibility that the synchronization accuracy may be reduced. Therefore, in order to reduce such influence, it is conceivable to increase the symbol length of the baseband signal and relatively reduce the distortion of the received signal waveform with respect to the symbol length regardless of the use environment. However, simply increasing the symbol length slows the transmission rate. The first modification has a configuration that solves this problem.

  FIG. 15 shows a configuration of the communication system 1 according to the first modification. In this modification, the transmitter 2 further includes a use environment input unit 25 for inputting information on multipath fading in the use environment of the transmitter 2 and the receiver 3 (hereinafter referred to as fading information). The transmission circuit 23 is configured to be able to switch the transmission rate of the low-speed unique word U1 based on the fading information input by the use environment input unit 25. The transmission circuit 23 switches the transmission rate of the low-speed unique word U1 so that the transmission rate is 1 / n times the transmission rate of the data D1 regardless of the transmission rate of the low-speed unique word U1. That is, the transmission speed of the low-speed unique word U1 is set to, for example, 1/2 times or 1/3 times the transmission speed of the data D1. The transmission rate of the low-speed unique word U1 is not limited to the above, and may be slower than the transmission rate of the data D1. The receiver 3 also has a usage environment input unit 38 for inputting fading information. The usage environment input units 25 and 38 can input the degree of influence on communication due to multipath fading in two stages, for example. The number of stages representing the degree of influence is not limited to two, and may be three or more. The use environment input units 25 and 38 are configured by an information input operation device, for example, an operation key or a touch panel.

  FIG. 16 shows the configuration of the synchronization establishment circuit 37. In the transmission circuit 23, the extraction circuit 36a stores in advance in the memory, for each fading information, the multiple 1 / n of the transmission speed of the low-speed unique word U1 that is switched according to the input fading information. The memory circuit 37b may also be used as this memory.

  When the fading information is input by the use environment input unit 38, the extraction circuit 36a refers to the memory and recognizes the multiple 1 / n to be switched based on the fading information by the transmission circuit 23. Then, the extraction circuit 36a extracts each sample value sequence of 4 × n sampling timings for each sampling timing from the sample value sequences detected by the detection circuit 35 (see FIG. 1).

  FIG. 17 shows the transmission rate of the low-speed unique word U1 when the influence of multipath fading is large and small. When information indicating that the influence of multipath fading is small is input by the usage environment input unit 25, the transmission speed of the low-speed unique word U1 is high (however, the transmission speed of the unique word U2 and the data D1 is low). Are switched as follows. As a result, the symbol length T1 is shortened, and the length T3 obtained by multiplying the symbol length T1 by the number of symbols of the low-speed unique word U1 is also shortened. On the other hand, when information indicating that the influence of multipath fading is large is input by the usage environment input unit 25, the transmission speed of the low-speed unique word U1 is switched to be low, and the symbol length T1 becomes long and low-speed. The length T3 of the unique word U1 is also increased.

  In this modification, the transmission rate of the low-speed unique word U1 can be switched according to the use environment. Therefore, for example, when used in an environment where the influence of multipath fading is small, even if the symbol length is shortened by increasing the transmission speed of the low-speed unique word U1, the received signal waveform distortion relative to the symbol length is relatively Can be small. Therefore, the detection accuracy of the low speed unique word U1 can be kept high. As a result, it is possible to increase the transmission speed while preventing a decrease in synchronization accuracy. On the other hand, when used in an environment where the influence of multipath fading is large, the symbol length becomes longer due to the lower transmission rate of the low-speed unique word U1. Therefore, the distortion of the received signal waveform with respect to the symbol length can be made relatively small, and a decrease in synchronization accuracy can be prevented. As a result, the balance between transmission speed and synchronization accuracy can be made suitable for the use environment, and accurate and efficient communication is possible.

(Second modification)
FIG. 18 shows a received signal by the receiver 3 of the communication system according to the second modification, and a correlation value between the received signal and the bit string of the unique word U2. In this modification, the unique word U2 is configured by a pseudo-random signal, for example, a 15-bit M sequence. The number of bits of the M sequence is not limited to this. The transmission circuit 23 of the transmitter 2 continuously and repeatedly transmits the M sequence that is the unique word U2, for example, continuously three times. The M sequences that are continuously transmitted are the same signal. The receiving circuit 31 of the receiver 3 receives the M sequence three times in succession. The storage circuit 37b of the receiver 3 stores in advance the entire M sequence identical to the M sequence transmitted from the transmission circuit 23 or a part thereof as a unique word U2, and the calculation circuit 37c receives the M sequence, The correlation value with the sample value sequence of the received signal by the circuit 31 is calculated.

  The M sequence is composed of binary values of 1 and 0, and the number of 0s is one more than the number of 1s. The binary values 0 and 1 are converted so as to be treated in the same way as binary values having the same absolute value but different signs, for example, -1 and +1, in predetermined signal processing in the calculation circuit 36c. The When the sum of each bit of the M sequence after the conversion is obtained, the sum is -1. For the M sequence and the M sequence obtained by cyclically shifting the M sequence, when bits in the same order are multiplied, the bit string obtained by the multiplication is obtained by further cyclically shifting the original M sequence. There is a characteristic that it becomes the same. Therefore, the sum total of each bit of the bit string is also -1.

  The prediction circuit 36f predicts a range in which the second M sequence in the baseband signal exists when the low-speed unique word U1 is detected. Here, the prediction range is A2. During reception of the baseband signal within the prediction range A2, if the M sequence in the baseband signal remains an ideal value, the baseband signal and the unique word U2 are received during reception of the second M sequence. The correlation value is 15 due to the above characteristics of the M series. On the other hand, before and after the reception, the correlation value is the sum of each bit of the bit string obtained by multiplying the M sequence and the cyclically shifted version of the M sequence for each bit. -1. Note that the prediction range A2 is a range in which the entire second M-sequence can exist, but the fact that the correlation value is actually maximized is the timing when all the M-sequences have been received. 18, the prediction range A2 is indicated near the last symbol of the second M series.

  Here, the comparative example of this modification is shown in FIG. As shown in FIG. 19, when the transmitter transmits the M sequence only once and transmits other signals before and after that, the correlation value at the M sequence reception timing A3 by the receiver is 15. However, the correlation value is disturbed before and after the reception, and there is a possibility that the correlation value becomes large even when the M sequence is not received.

  Compared to such an example, in the present modification, the difference between the correlation value when the receiver 3 receives the unique word U2 (M sequence) and the correlation value (degree of coincidence) when other signals are received. Will definitely grow. In particular, when the receiver 3 continuously receives three unique words U2, the difference between the correlation value when the second unique word U2 is received and the correlation value when other signals are received is Definitely grows. Therefore, by limiting the range in which the presence of the unique word U2 is predicted, for example, to a range in which the second unique word U2 can exist, the influence of multipath fading or noise on the synchronization can be reduced. The synchronization accuracy can be improved.

(Third Modification)
FIG. 20 shows a configuration of the receiver 3 of the communication system according to the third modification. The receiver 3 further includes a narrowband filter 39 that extracts the low-speed unique word U1 from the baseband signal detected by the detection circuit 35. Since the low-speed unique word U1 has a lower transmission speed and a longer symbol length than the unique word U2 and the data D1, the narrow-band filter 39 can extract only the low-speed unique word U1. It is configured. Specifically, the pass band of the narrow band filter 39 has a width equal to or greater than the frequency bandwidth of the low speed unique word U1, and is narrower than the pass band of the filter through which the unique word U2 and the data D1 can pass. The low speed unique word detection circuit 36 detects the low speed unique word U1 from the baseband signal that has passed through the narrowband filter 39.

  In this modification, the detection accuracy of the low-speed unique word U1 by the low-speed unique word detection circuit 36 can be improved.

(Fourth modification)
FIG. 21 shows the configuration of the receiver 3 of the communication system according to the fourth modification and the baseband signal waveform in the receiver 3. The receiver 3 further includes a normalization circuit 40 (normalization unit) inserted between the AD converter 32 and the synchronization circuit 33. The normalization circuit 40 is a so-called normalizer, which adjusts and normalizes the reception level of the baseband signal, and is input to the low-speed unique word detection circuit 36 and the synchronization establishment circuit 37 via the detection circuit 35. Normalize the baseband signal. The normalization circuit 40 sends the normalized baseband signal to the synchronization establishment circuit 37, thereby making the level of the baseband signal (hereinafter simply referred to as input signal) input to the synchronization establishment circuit 37 constant and stable. Make it.

  FIG. 22 shows a procedure of baseband signal reception processing in the receiver 3 of the present modification. The reception process is the same as the reception process of the above embodiment (see FIG. 10) except that the process of S41 is added between S22 and S23. In the reception process of this modification, the normalization circuit 40 normalizes the baseband signal sampled in the process of S22 (S41).

  In this modified example, even when the level of the input signal to the synchronization establishment circuit 37 fluctuates greatly due to a change in the communication environment or the like, the signal is normalized before detection of the low speed unique word U1 and establishment of synchronization. As a result, signal level fluctuations are suppressed, so that detection accuracy and synchronization accuracy are increased.

(Fifth modification)
FIG. 23 shows a configuration of the synchronization establishment circuit 37 of the communication system according to the fifth modification. The synchronization establishment circuit 37 is an average value calculation circuit that calculates the moving average value of the input signal to the synchronization establishment circuit 37, specifically, the sample value of the baseband signal detected by the detection circuit 35 and input to the synchronization establishment circuit 37. 37h (average value calculation unit) is further included. The average value calculation circuit 37h obtains a moving average value in a range of a plurality of symbols of the input signal.

  The threshold setting circuit 37d sets a second setting threshold (correlation value threshold) based on the moving average value calculated by the average value calculation circuit 37h. For example, the threshold setting circuit 37d decreases the second setting threshold continuously or stepwise when the calculated moving average value decreases, and increases the second setting threshold continuously or stepwise when the moving average value increases. When the moving average value becomes lower than the predetermined value, the threshold setting circuit 37d may keep the setting threshold value at a specific value in order to make erroneous synchronization less likely to occur.

  FIG. 24 shows the procedure of synchronization processing in the synchronization establishment circuit 37. The synchronization process is obtained by adding the processes of S51 and S52 between the processes of S32 and S33 in the synchronization process of the above embodiment (see FIG. 11). In the synchronization process of this modification, the average value calculation circuit 37h calculates the moving average value of the sample values of the baseband signal (S51). Then, the threshold setting circuit 37d sets the second setting threshold based on the moving average value calculated in S51 (S52).

  In this modification, even if the level of the input signal fluctuates significantly due to changes in the communication environment or the like, the set threshold value calculated based on the moving average value of the input signal is linked to the fluctuation. Therefore, the symbol synchronization establishment based on the comparison result between the correlation value and the set threshold corresponds to the communication environment change or the like. Therefore, it is possible to establish stable symbol synchronization, and thus stable frame synchronization. In addition, the circuit necessary for handling the level fluctuation of the input signal is not a circuit having a complicated configuration like the normalization circuit 40 of the fourth modified example, but calculates a moving average value of the detected baseband signal. Since only the average calculation circuit is required, the scale can be reduced as compared with the fourth modification.

  As a method of enabling stable synchronization establishment using the moving average value of the input signal, in the above modification, the second set threshold is set based on the moving average value of the input signal without changing the input signal. The On the other hand, as a method described above, the second setting threshold value may be fixed, and the value of the input signal may be divided by the moving average value.

(Sixth Modification)
FIG. 25 shows a signal transmitted from the transmitter 2 of the communication system according to the sixth modification. The transmitter 2 periodically transmits the frame F1. Each frame F1 includes a low-speed unique word U1 and a unique word U2. The frame length of the frame F1 is set in advance.

  FIG. 26 shows the configuration of the low-speed unique word detection circuit 36 and the synchronization establishment circuit 37 of this modification, and FIG. 27 shows the low-speed unique word U1 re-detection stop period. The low speed unique word detection circuit 36 controls the on / off of the counter 36g that counts the elapsed time from the detection of the unique word U2 and the other circuits in the synchronization establishment circuit 37 based on the time counted by the counter 36g. Circuit 36h. While the time counted by the counter 36g is within a known period from when the unique word U2 is detected to when the next low-speed unique word U1 starts to be input, the control circuit 36h compares the extraction circuit 36a, the calculation circuit 36c, and the comparison circuit 36h. The circuit 36e, the prediction circuit 36f, and the like are turned off. By this off control, the control circuit 36h stops the low-speed unique word U1 redetection operation by these circuits. This stop of the re-detection operation is a process for preventing erroneous synchronization. Hereinafter, the known period is referred to as a redetection stop period. This re-detection stop period is from when the unique word U2 is detected until the next low-speed unique word U1 starts to be input, and during the period from when the low-speed unique word U1 is detected to when the unique word U2 is detected. Redetection of word U1 is not stopped. The reason is that since the bit string of the unique word U2 can be set in advance, there is no problem if the bit string is set to a bit string that is difficult to be erroneously detected as the low-speed unique word U1.

  The control circuit 36h grasps the detection of the unique word U2 based on the synchronization establishment signal transmitted from the synchronization detection circuit 37f at the time of detection. When detecting the symbol synchronization timing and the frame synchronization timing, the synchronization detection circuit 37f recognizes that the unique word U2 has been detected, and transmits a synchronization establishment signal to the control circuit 36h. When the control circuit 36h receives the synchronization establishment signal from the synchronization detection circuit 37f, the control circuit 36h controls the counter 36g so that the counter 36g starts counting time using a clock signal having a constant frequency emitted from the oscillator. Further, when the control circuit 36h receives the synchronization establishment signal, the control circuit 36h transmits a re-detection stop signal instructing OFF to the extraction circuit 36a, the calculation circuit 36c, the comparison circuit 36e, the prediction circuit 36f, and the like. The low-speed unique word U1 redetection operation by the circuit is stopped.

  The re-detection stop period is substantially equal to the period from when the unique word U2 has been input until the beginning of the next low-speed unique word U1 is input. The re-detection stop period does not necessarily need to coincide with the period, and the above period is set so that the detection process of the low-speed unique word U1 can be started with a margin until the beginning of the next low-speed unique word U1 is input. It may be set shorter. Here, A is a count value when the re-detection stop period is time-counted by the counter 36g. The control circuit 36h continues to transmit the re-detection stop signal while the count value by the counter 36g is within A. When the count value by the counter 36g becomes A (when the redetection stop period elapses), the control circuit 36h stops transmitting the redetection stop signal, and the extraction circuit 36a, the calculation circuit 36c, the comparison circuit 36e, the prediction circuit 36f, and the like. Is turned on and the count value is reset.

  FIG. 28 shows the low detection unique word U1 redetection stop process in the control circuit 36h. When receiving the synchronization establishment signal from the synchronization detection circuit 37f (Yes in S61), the control circuit 36h starts a time cant using the counter 36g (S62), and stops the low-speed unique word redetection operation (S63). When the count value by the counter 36g becomes A or more (No in S64), the control circuit 36h restarts the low-speed unique word redetection operation (S65), and resets the count value by the counter 36g (S66).

  The configuration for stopping the re-detection operation of the low-speed unique word U1 is not limited to the above. For example, when the control circuit 36h receives a synchronization establishment signal from the synchronization detection circuit 37f, the redetection stop signal may be sent only once to the extraction circuit 36a, the calculation circuit 36c, the comparison circuit 36e, the prediction circuit 36f, and the like. In this case, when the count value by the counter 36g becomes A, the control circuit 36h transmits an operation start request signal for turning on the operation to the extraction circuit 36a, the calculation circuit 36c, the comparison circuit 36e, the prediction circuit 36f, and the like.

  In this modification, a signal having a waveform that coincides with or approximates to the low speed unique word U1 is generated accidentally from the reception of the unique word U2 of a certain frame F1 to the reception of the low speed unique word U1 of the next frame F1. To do. Even in such a case, the low-speed unique word U1 is not erroneously detected based on the signal. Therefore, mis-synchronization can be prevented and the occurrence of a synchronization error can be suppressed.

(Seventh Modification)
FIG. 29 shows a configuration of the communication system 1 according to the seventh modification. In this modification, the transmitter 2 periodically transmits the frame F1. Each frame F1 includes a low-speed unique word U1 and a unique word U2. The transmission circuit 23 includes a data end signal indicating the end of the data D1 in the data D1 for transmission. The data end signal is disposed at the end of the data D1, for example.

  The signal processing circuit 34 of the receiver 3 further includes a data end detection circuit 34 a (data end detection unit) that detects a data end signal from the baseband signal detected by the detection circuit 35. The data end detection circuit 34a detects the end timing of the data D1 by detecting the data end signal. When the data end detection circuit 34a detects the end timing of the data D1, the data end detection circuit 34a transmits a data end detection signal indicating the end timing to the low-speed unique word detection circuit 36.

  The low-speed unique word detection circuit 36 has a control circuit 36h that stops the re-detection operation of the low-speed unique word U1 from the detection of the unique word U2 to the end timing of the data D1 detected by the data end detection circuit 34a. The control circuit 36h grasps the end timing based on the data end detection signal from the data end detection circuit 34a.

  FIG. 30 shows the configuration of the low-speed unique word detection circuit 36 and the synchronization establishment circuit 37 of this modification, and FIG. 31 shows the low-speed unique word U1 redetection stop period. The control circuit 36h grasps the detection of the unique word U2 based on the synchronization establishment signal transmitted from the synchronization detection circuit 37f at the time of detection. When detecting the symbol synchronization timing and the frame synchronization timing, the synchronization detection circuit 37f recognizes that the unique word U2 has been detected, and transmits a synchronization establishment signal to the control circuit 36h. When the control circuit 36h receives the synchronization establishment signal from the synchronization detection circuit 37f, the control circuit 36h transmits a redetection stop signal that instructs the extraction circuit 36a, the calculation circuit 36c, the comparison circuit 36e, the prediction circuit 36f, and the like to turn off the operation. The transmission causes the control circuit 36h to turn off those circuits and stop the low-speed unique word U1 redetection operation by these circuits.

  The control circuit 36h continues to transmit the redetection stop signal until the end timing of the data D1 indicated by the data end detection signal, and stops transmitting the redetection stop signal at the end timing. With this transmission stop, the control circuit 36h turns on the extraction circuit 36a, the calculation circuit 36c, the comparison circuit 36e, and the prediction circuit 36f.

  FIG. 32 shows the low-speed unique word U1 redetection stop process in the control circuit 36h of the present modification. The redetection stop process is obtained by eliminating the processes of S62 and S66 in the redetection stop process of the sixth modified example (see FIG. 28) and changing S64 to the process of S71. In the process of S71, the control circuit 36h returns to the process of S63 until the end timing of the data D1 until it reaches the end timing of the data D1 after stopping the low-speed unique word redetection operation (No in S71). (Yes in S71), the process proceeds to S65.

  In the present modification, the false detection prevention effect of the low speed unique word U1 can be obtained as in the sixth modification. Even if the data length of the data D1 is changed, erroneous detection of the low-speed unique word U1 can be reliably prevented until the end timing of the data D1.

(Eighth modification)
FIG. 33 shows the configuration of the communication system 1 according to the eighth modification, and FIG. 34 shows the low detection unique word U1 redetection stop period in each of the receivers 3A and 3B of the communication system 1. The communication system 1 of the present modification is provided with two receivers 3A and 3B in which a reception timing detection circuit 34b (reception timing detection unit) is added to the configuration of the receiver 3 of the above embodiment. In the present modification, the number of receivers configured as described above is not limited to two, and a plurality of receivers may be provided.

  The transmission circuit 23 of the transmitter 2 transmits a polling signal indicating the next signal transmission timing that differs for each receiver to the receivers 3A and 3B. The polling signal is also composed of a low-speed unique word U1, a unique word U2, and data D1 as in the case of general signals, and information indicating the next signal transmission timing is included in the data D1. Signal transmission timings to the receivers 3A and 3B are set so as not to overlap each other. Although not shown, the transmission circuit 23 periodically transmits a polling signal.

  Each of the receivers 3A and 3B includes a reception timing detection circuit 34b (reception timing detection unit) that detects a next signal reception timing based on a polling signal transmitted by the transmission circuit 23 and received by the reception circuit 31. Have. When the reception timing detection circuit 34b detects the next signal reception timing, the reception timing detection circuit 34b transmits a reception timing notification signal for notifying the signal reception timing to the low-speed unique word detection circuit 36.

  The low-speed unique word detection circuit 36 controls to stop the re-detection operation of the low-speed unique word U1 from the time when the reception circuit 31 has received the polling signal until the next signal reception timing detected by the reception timing detection circuit 34b. A circuit 36h is included. The control circuit 36h grasps the signal reception timing based on the reception timing notification signal from the reception timing detection circuit 34b. In addition to the above-described period, the control circuit 36h also includes a period from when the synchronization establishment circuit 37 establishes synchronization based on the unique word U2 in the polling signal to when the reception circuit 31 finishes receiving the polling signal. The re-detection operation is stopped.

  FIG. 35 shows the configuration of the low-speed unique word detection circuit 36 and the synchronization establishment circuit 37 of this modification. The control circuit 36h grasps the synchronization establishment based on the unique word U2 based on the synchronization establishment signal transmitted from the synchronization detection circuit 37f when the unique word U2 is detected. When detecting the symbol synchronization timing and the frame synchronization timing, the synchronization detection circuit 37f recognizes that the unique word U2 has been detected, and transmits a synchronization establishment signal to the control circuit 36h. When the control circuit 36h receives the synchronization establishment signal from the synchronization detection circuit 37f, the control circuit 36h transmits a re-detection stop signal that instructs the extraction circuit 36a, the calculation circuit 36c, the comparison circuit 36e, and the prediction circuit 36f to turn off the operation. The transmission causes the control circuit 36h to turn off those circuits and stop the low-speed unique word U1 redetection operation by these circuits.

  The control circuit 36h continues to transmit the redetection stop signal until the signal reception timing indicated by the reception timing notification signal, and stops transmitting the redetection stop signal when the signal reception timing is reached. With this transmission stop, the control circuit 36h turns on the extraction circuit 36a, the calculation circuit 36c, the comparison circuit 36e, and the prediction circuit 36f.

  FIG. 36 shows the low-speed unique word U1 redetection stop process in the control circuit 36h of the present modification. The redetection stop process is obtained by changing S71 to the process of S81 in the redetection stop process (see FIG. 32) of the seventh modified example. In the process of S81, after stopping the low-speed unique word redetection operation, the control circuit 36h returns to the process of S63 until the next signal reception timing is reached (No in S78). (Yes in S81), the process proceeds to S65.

  In each of the receivers 3A and 3B according to the present modification, the low-speed unique word U1 re-detection operation is stopped during the period from when the polling signal is received until the next signal reception timing detected based on the polling signal. . Therefore, when the transmitter 2 transmits a signal to another receiver during that period, even if a signal having the same waveform as that of the low speed unique word U1 is included in the signal accidentally, It is possible to prevent the low-speed unique word U1 from being erroneously detected based on the signal. Therefore, erroneous synchronization with the signal can be prevented.

  In each receiver 3A, 3B, the low-speed unique word is received after the synchronization is established by the unique word U2 in the polling signal until the polling signal is completely received, that is, during the period in which the data D1 in the polling signal is received. The U1 redetection operation stops. Accordingly, even if the data D1 includes a signal having a signal waveform that is the same as or close to that of the low-speed unique word U1, the low-speed unique word U1 is erroneously detected based on such a signal. Can be avoided.

(Ninth Modification)
FIG. 37 shows a correlation value calculation method of the calculation circuit 37c in the communication system according to the ninth modification. Similarly to the above embodiment, the calculation circuit 37c multiplies the sample value sequence detected by the detection circuit 35 and the unique word U2 by the sample value and the bit value in the same order in time series order, The sum of the multiplication results is calculated and used as a correlation value. However, the calculation circuit 37c cumulatively adds the multiplication results of the sample value and the bit value in the correlation value calculation process using one register. Specifically, the calculation circuit 37c stores the multiplication result of the first values in one register, and the multiplication result of the second values is used as the first multiplication stored in the register. The result is added and the addition result is stored in the register. In this way, the calculation circuit 37c sequentially adds the multiplication results and stores the addition results in the register. The unique word U2 is not limited to the number of bits shown.

  Normally, a register used for calculating a correlation value between the sample value sequence and the bit sequence of the unique word U2 is required to be equal to or greater than the number of bits of the unique word U2. There is only one register. Therefore, the circuit scale of the calculation circuit 37c can be reduced, and the cost can be reduced.

  In addition, this invention is not limited to the structure of the said embodiment and each modification, A various deformation | transformation is possible according to the intended purpose. For example, any characteristic configuration of the above-described modifications may be combined with any other configuration.

  In addition, a filter may be provided between the AD converter 32 and the synchronization circuit 33 to pass only the baseband signal component and remove the noise component. The calculation circuit 36c multiplies the sample value and the bit value in the same order in time series in the calculation process of the correlation value between the sample value sequence detected by the detection circuit 35 and the low-speed unique word U1, These multiplication results may be cumulatively added using one register.

  Also, the synchronization setting circuit 37g sets the sampling timing at which the correlation value is maximized within the range where the presence of the unique word U2 is predicted as the symbol synchronization timing, and sets the timing at which the correlation value is maximized as the frame synchronization timing. May be. In addition, the synchronization setting circuit 37g sets the sampling timing at which the correlation value is equal to or greater than the second setting threshold within the above-described range to the symbol synchronization timing, and the correlation value is equal to or greater than the second setting threshold. The timing may be set to frame synchronization timing.

DESCRIPTION OF SYMBOLS 1 Communication system 2 Transmitter 21 Low speed bit stream generation circuit (low speed bit stream generation part)
22 Bit string generation circuit (bit string generation unit)
23 Transmitter circuit (wireless transmitter)
3 Receiver 31 Receiver circuit (wireless receiver)
32 AD converter (sampling unit)
34a Data end detection circuit (data end detection unit)
34b Reception timing detection circuit (reception timing detection unit)
35 Detection circuit (detection part)
36 Low-speed bit string detection circuit (low-speed bit string detection unit)
36g counter 37 synchronization establishment circuit (synchronization establishment unit)
37h Average value calculation circuit (average value calculation unit)
39 Narrowband filter 40 Normalization circuit (normalization unit)
A1, A2 Prediction range B1 Baseband signal F1 Frame D1 Data U1 Low-speed unique word (first synchronization bit string)
U2 unique word (second synchronization bit string)

Claims (15)

  The first synchronization bit string having a transmission speed lower than that of the data to be transmitted, the second synchronization bit string having the same transmission speed as the data, and the baseband signal obtained by framing the data are up-converted and converted to an RF signal. A transmitter for wirelessly transmitting the RF signal; receiving the wirelessly transmitted RF signal; downconverting the RF signal to extract a baseband signal; and extracting the baseband signal in the baseband signal. A bit string is detected, and based on the detection result, a range in which the second synchronization bit string exists in the baseband signal is predicted, and the baseband signal in the range is stored in advance. A communication system comprising: a receiver that establishes symbol synchronization and frame synchronization based on a correlation value with the second synchronization bit string. The transmitter is
A low-speed bit string generation unit for generating the first synchronization bit string;
A bit string generation unit for generating the second synchronization bit string;
Generating a baseband signal by framing and modulating the first synchronization bit string, the second synchronization bit string, and the data, up-converting the baseband signal to convert it to an RF signal, A wireless transmission unit that wirelessly transmits an RF signal,
The receiver is
A radio reception unit that extracts a baseband signal by receiving and down-converting the RF signal wirelessly transmitted by the radio transmission unit;
A detector for detecting a baseband signal extracted by the wireless receiver;
The first synchronization bit string in the baseband signal detected by the detection unit is detected, and a range where the second synchronization bit string exists in the baseband signal is predicted based on the detection result. A low-speed bit string detector,
A correlation value between the baseband signal within the range predicted by the low-speed bit string detection unit and the known second synchronization bit string stored in advance is calculated, and symbol synchronization is performed based on the calculated correlation value. And a synchronization establishment unit that establishes frame synchronization. The transmitter further includes a usage environment input unit for inputting information on multipath fading in the usage environment of the transmitter and the receiver.
3. The communication according to claim 2, wherein the wireless transmission unit is configured to be able to switch a transmission rate of the first synchronization bit string based on information input by the use environment input unit. system. The second synchronization bit string is composed of a pseudo-random signal,
The communication system according to claim 2, wherein the wireless transmission unit transmits the pseudo-random signal continuously and repeatedly. The receiver further includes a narrowband filter for extracting the first synchronization bit string from the baseband signal detected by the detection unit,
5. The communication according to claim 2, wherein the low-speed bit string detection unit detects the first synchronization bit string from the baseband signal that has passed through the narrowband filter. system.   6. The receiver according to claim 2, further comprising a normalization unit that normalizes a level of a baseband signal input to the low-speed bit string detection unit and the synchronization establishment unit. The communication system according to item.   The synchronization establishing unit includes an average value calculating unit that calculates a moving average value of a baseband signal input to the synchronization establishing unit, and the correlation value is set to a moving average value calculated by the average value calculating unit. The sampling timing of the correlation value is set as a symbol synchronization timing if it is equal to or greater than a threshold value set based on the threshold value, and the timing at which the correlation value is equal to or greater than the set threshold value is set as a frame synchronization timing. The communication system according to any one of claims 2 to 5. The wireless transmission unit periodically transmits a frame including the first synchronization bit string and the second synchronization bit string,
The low-speed bit string detection unit includes a counter that counts an elapsed time from the time of detection of the second synchronization bit string, and the count time by the counter is the next time from the time of detection of the second synchronization bit string. 8. The re-detection operation of the first synchronization bit string is stopped during a known period until the first synchronization bit string starts to be input. 8. A communication system according to claim 1. The wireless transmission unit transmits a data end signal indicating the end of the data,
The receiver further includes a data end detection unit that detects an end timing of the data by detecting the data end signal from the baseband signal detected by the detection unit,
The low-speed bit string detection unit stops the re-detection operation of the first synchronization bit string from the time of detection of the second synchronization bit string to the end timing of the data detected by the data end detection unit. The communication system according to any one of claims 2 to 7, wherein: A plurality of the receivers are provided in the communication system,
The wireless transmission unit transmits a polling signal indicating a next signal transmission timing different for each receiver to the plurality of receivers,
Each of the plurality of receivers includes a reception timing detection unit that detects a next signal reception timing based on a polling signal transmitted by the wireless transmission unit and received by the wireless reception unit,
The low-speed bit string detection unit performs the re-detection operation of the first synchronization bit string from when the wireless reception unit has received the polling signal until the next signal reception timing detected by the reception timing detection unit. The communication system according to any one of claims 2 to 7, wherein the communication system is stopped. The receiver further includes a sampling unit that samples a baseband signal received by the wireless reception unit,
The detection unit detects a sample value sequence of the baseband signal sampled by the sampling unit,
The synchronization establishment unit, in the correlation value calculation process, for the sample value sequence detected by the detection unit and the second synchronization bit sequence, sample values and bit values in the same order in time series The communication system according to any one of claims 2 to 10, wherein the multiplication results are cumulatively added using a single register.   The transmitter used for the communication system as described in any one of Claims 1 thru | or 11.   The receiver used for the communication system as described in any one of Claims 1 thru | or 11.   The first synchronization bit string having a transmission speed lower than that of the data to be transmitted, the second synchronization bit string having the same transmission speed as the data, and the baseband signal obtained by framing the data are up-converted and converted to an RF signal. Transmitting the RF signal wirelessly; receiving the transmitted RF signal; down-converting the RF signal to extract a baseband signal; and for the first synchronization in the baseband signal A bit string is detected, and based on the detection result, a range in which the second synchronization bit string exists in the baseband signal is predicted, and the baseband signal in the predicted range is stored in advance. And a reception step of establishing symbol synchronization and frame synchronization based on a correlation value with the second synchronization bit string. Law. The transmitting step includes
A low-speed bit string generation step for generating the first synchronization bit string;
A bit string generation step of generating the second synchronization bit string;
Generating a baseband signal by framing and modulating the first synchronization bit string, the second synchronization bit string, and the data, up-converting the baseband signal to convert it to an RF signal, Wirelessly transmitting an RF signal wirelessly, and
The receiving step includes
A radio reception step of extracting a baseband signal by receiving and down-converting the RF signal wirelessly transmitted in the radio transmission step;
A detection step of detecting the baseband signal extracted by the wireless reception step;
The first synchronization bit string in the baseband signal detected by the detection step is detected, and a range in which the second synchronization bit string exists in the baseband signal is predicted based on the detection result. A low-speed bit string detection step;
A correlation value between the baseband signal within the range predicted by the low-speed bit string detection step and the known second synchronization bit string stored in advance is calculated, and symbol synchronization is performed based on the calculated correlation value. And a synchronization establishing step of establishing frame synchronization.

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