JP2013537363A - Method for forming a through-wafer interconnect in a semiconductor structure using a sacrificial material, and a semiconductor structure formed by such a method - Google Patents

Abstract

A method of manufacturing a semiconductor structure includes providing a sacrificial (132) material in a via recess (112), forming a first portion (174) of a through-wafer interconnect in the semiconductor structure; Forming a second portion (212) of the through-wafer interconnect by replacing the sacrificial material with a conductive material. The semiconductor structure is formed by such a method. For example, the semiconductor structure may comprise a sacrificial material in the via recess and a first portion of the through-wafer interconnect aligned with the via recess. The semiconductor structure includes a through-wafer interconnect that includes two or more portions having a boundary therebetween.
[Selection] FIG.

Description

  [0001] The present invention relates generally to a method of forming a semiconductor structure with through-wafer interconnects and a semiconductor structure formed by such a method.

  [0002] Semiconductor structures include semiconductor materials such as electronic signal processors, memory devices, photoelectric devices (eg, light emitting diodes (LEDs), laser diodes, solar cells, etc.), microelectromechanical devices, and nanoelectromechanical devices. It includes the device used (ie, a semiconductor device) and is formed when the device is manufactured. In such semiconductor structures, it is often necessary or desirable to electrically and / or structurally couple one semiconductor structure to another device or structure (eg, another semiconductor structure). . Such a process for bonding a semiconductor structure to another device or structure is often referred to as a three-dimensional (3D) integration process.

  [0003] 3D integration of two or more semiconductor structures can provide a number of advantages for microelectronic applications. For example, 3D integration of microelectronic components can provide improvements in electrical performance and power consumption while at the same time reducing the footprint area of the device. For example, P.I. See Garrou et al. “The Handbook of 3D Integration”, Wiley-VCH (2008).

  [0004] 3D integration of a semiconductor structure is the mounting of a semiconductor chip to one or more additional semiconductor chips (ie, chip-to-die (D2D)), one or more additional semiconductor chips. Mounting of semiconductor chips to a semiconductor wafer (ie, chip-to-wafer (D2W)) and mounting of semiconductor wafers to one or more additional semiconductor wafers (ie, wafer-to-wafer (W2W)) to-wafer)), or a combination thereof.

  [0005] Often, individual semiconductor chips or semiconductor wafers are relatively thin and can be difficult to handle in an apparatus to process those chips or wafers. Thus, a so-called “carrier” chip or “carrier” wafer may be attached to an actual chip or actual wafer with active and passive components of an active semiconductor device therein. Typically, the carrier chip or carrier wafer does not include active or passive components of the semiconductor device to be formed. Such carrier chips and carrier wafers are referred to herein as “carrier substrates”. The carrier substrate increases the overall thickness of the chip or wafer and allows the active and passive components of the semiconductor device to be fabricated on top of the chip or wafer mounted to the carrier substrate. Handling of this chip or wafer by the processing equipment used to process the active and / or passive components therein is facilitated.

  [0006] In order to establish an electrical connection between an active component in a semiconductor structure and a conductive feature of another device or structure on which the semiconductor structure is mounted, a "through-wafer interconnect" "Or" TWI "is known to use what is referred to herein. The through-wafer interconnect is a conductive via that extends through at least a portion of the semiconductor structure.

  [0007] In some embodiments, the present invention includes a method of manufacturing a semiconductor structure. Sacrificial material may be applied in at least one via recess that extends partially through the semiconductor structure. A first portion of at least one through-wafer interconnect may be formed in the semiconductor structure. The first portion of the at least one through-wafer interconnect may be aligned with the at least one via recess. The sacrificial material in the at least one via recess is replaced with a conductive material so that the second of the at least one through-wafer interconnect in electrical contact with the first portion of the at least one through-wafer interconnect. Form the part.

  [0008] The invention also includes a further embodiment of a method of manufacturing a semiconductor structure. According to such a method, the sacrificial material is applied in at least one via recess that extends into the surface of the semiconductor structure. A layer of semiconductor material may be provided over the surface of the semiconductor structure, and at least one device structure may be fabricated using the layer of semiconductor material. A first portion of at least one through-wafer interconnect that extends through the layer of semiconductor material is formed. The semiconductor structure may be thinned from the opposite side of the layer of semiconductor material. The sacrificial material may be removed from within the at least one via recess in the semiconductor structure, the first portion of the at least one through-wafer interconnect may be exposed in the via recess, and the conductive material However, the second portion of the at least one through-wafer interconnect may be formed by being applied in the via recess.

  [0009] In yet other embodiments, the invention includes a semiconductor structure formed by the methods disclosed herein. For example, in some embodiments, a semiconductor structure includes a sacrificial material in at least one via recess extending partially through the semiconductor structure from the surface of the semiconductor structure, and a surface of the semiconductor structure. And at least one device structure including at least a portion of the semiconductor material disposed over the surface of the semiconductor structure. A first portion of at least one through-wafer interconnect extends through the semiconductor material disposed over the surface of the semiconductor structure, and the first portion of at least one through-wafer interconnect is , Aligned with at least one via recess.

  [0010] In a further embodiment, the present invention provides an active surface, a back surface, at least one transistor located in a semiconductor structure between the active surface and the back surface, and at least one of the active surface and the back surface. And at least one through-wafer interconnect extending at least partially through the semiconductor structure. The at least one through-wafer interconnect includes a first portion, a second portion, and an identifiable boundary between the first portion microstructure and the second portion microstructure.

[0011] While this specification concludes with claims that particularly point out and distinctly claim what is considered as embodiments of the invention, the advantages of the embodiments of the present invention may be combined with the accompanying drawings. It will be easier to grasp by reading the description of some examples of embodiments of the present invention.
[0012] FIG. 4 is a schematic cross-sectional side view of a portion of a semiconductor structure. [0013] FIG. 2 is a schematic cross-sectional side view of a portion of another semiconductor structure that may be formed by providing a via recess that partially penetrates the semiconductor structure of FIG. [0014] A portion of another semiconductor structure that may be formed in the via recess in the semiconductor structure of FIG. 2 by applying a dielectric material over or over the exposed surface of the semiconductor structure. FIG. [0015] FIG. 4 is a schematic cross-sectional side view of a portion of another semiconductor structure that may be formed by applying a material such as polysilicon into the via recess of the semiconductor structure of FIG. [0016] FIG. 5 is a schematic cross-sectional side view of a portion of a bonded semiconductor structure that may be formed by bonding another semiconductor structure to the semiconductor structure of FIG. [0017] FIG. 6 is a schematic cross-sectional side view of a portion of another semiconductor structure that may be formed by thinning another semiconductor structure in the bonded semiconductor structure of FIG. [0018] FIG. 7 is an enlarged view of a portion of another semiconductor structure that may be formed by fabricating a transistor and a shallow trench isolation structure in and / or on a portion of the bonded semiconductor structure of FIG. . [0019] Enlarging a portion of another semiconductor structure that can be formed by providing a dielectric material layer overlying the semiconductor structure of FIG. 7 and by providing a portion of a through-wafer interconnect that extends through the semiconductor structure. FIG. [0020] FIG. 9 is an enlarged view of a portion of another semiconductor structure that may be formed by fabricating one or more layers comprising a conductive structure covering a surface of the semiconductor structure of FIG. [0021] FIG. 10 is an enlarged view of a portion of another semiconductor structure that may be formed by bonding the semiconductor structure of FIG. 9 to a carrier substrate. [0022] FIG. 11 is an enlarged view of a portion of another semiconductor structure that may be formed by removing polysilicon material from a via recess in the semiconductor structure of FIG. [0023] Another semiconductor structure that may be formed by applying an electrically conductive material in the via recess of the semiconductor structure of FIG. 11 to form an additional portion of the through-wafer interconnect in the via recess. It is an enlarged view of a part. [0024] FIG. 13 is an enlarged view of a portion of another semiconductor structure that can be formed by removing the carrier substrate from the semiconductor structure of FIG. 12 and providing a conductive bump over the exposed end of the through-wafer interconnect. is there. [0025] FIG. 12 illustrates another method that may be utilized to process the semiconductor as illustrated in FIG. 10 into a semiconductor structure as illustrated in FIG. FIG. 12 illustrates another method that may be utilized to process a semiconductor as shown in FIG. 10 into a semiconductor structure as shown in FIG. FIG. 12 illustrates another method that may be utilized to process a semiconductor as shown in FIG. 10 into a semiconductor structure as shown in FIG. [0026] FIG. 13 illustrates yet another method that may be utilized to process the semiconductor as illustrated in FIG. 10 into a semiconductor structure as illustrated in FIG. FIG. 12 illustrates yet another method that can be utilized to process a semiconductor as shown in FIG. 10 into a semiconductor structure as shown in FIG. FIG. 12 illustrates yet another method that can be utilized to process a semiconductor as shown in FIG. 10 into a semiconductor structure as shown in FIG. FIG. 12 illustrates yet another method that may be utilized to process the semiconductor as shown in FIG. 10 into a semiconductor structure as shown in FIG.

  [0027] The following description presents specific details, such as material types and processing conditions, in order to fully describe the embodiments of the present disclosure and their implementation. However, as will be appreciated by one skilled in the art, embodiments of the present disclosure may be practiced without the use of these specific details and in combination with conventional manufacturing techniques. Further, the description presented herein does not form a complete process flow for manufacturing semiconductor devices or semiconductor systems. This specification merely describes in detail the process actions and structures necessary to understand the embodiments of the present invention. The materials described herein include spin coating, blanket coating, Bridgeman and Czochralski process, chemical vapor deposition (“CVD”), plasma enhanced chemical vapor deposition (“PECVD”), atomic layer deposition (“ALD”). , Plasma atomic layer deposition (PEALD), or physical vapor deposition (“PVD”), may be formed (eg, deposited or grown) by any suitable technique. Although the materials described and exemplified herein can be formed as layers, these materials are not limited to layers and may be formed in other three-dimensional configurations.

  [0028] As used herein, the terms "horizontal" and "vertical" refer to the principal plane or principal of a semiconductor structure (eg, wafer, chip, substrate, etc.), regardless of the orientation of the semiconductor structure. Defines the relative position of an element or structure with respect to the surface and is interpreted in a vertical dimension relative to the orientation of the structure being described. As used herein, the term “vertical” means and includes a dimension that is substantially perpendicular to the major surface of the semiconductor structure, and the term “horizontal” refers to the major of the semiconductor structure. Means a dimension substantially parallel to the surface.

  [0029] The term "semiconductor structure" as used herein means and includes any structure used in the formation of semiconductor devices. Semiconductor structures include, for example, chips and wafers (eg, carrier and device substrates) and assemblies or composite structures that include two or more chips and / or wafers that are three-dimensionally integrated with each other. The semiconductor structure also includes a completed semiconductor device and an intermediate structure formed during manufacture of the semiconductor device. The semiconductor structure may include a conductive material, a semiconductor material, and / or a non-conductive material.

  [0030] The term "processed semiconductor structure" as used herein means and includes any semiconductor structure that comprises one or more at least partially formed device structures. The processed semiconductor structure is a small part of the semiconductor structure, and all the processed semiconductor structures are semiconductor structures.

  [0031] As used herein, the term "joined semiconductor structure" means and includes any structure comprising two or more semiconductor structures attached together. The bonded semiconductor structure is a small part of the semiconductor structure, and all the bonded semiconductor structures are semiconductor structures. In addition, a bonded semiconductor structure comprising one or more processed semiconductor structures is also a processed semiconductor structure.

  [0032] The term "device structure" as used herein is or comprises at least a portion of an active component or passive component of a semiconductor device to be formed on or in a semiconductor structure. Means or includes any portion of the processed semiconductor structure that defines or defines it. For example, the device structure includes active and passive components of an integrated circuit such as transistors, converters, capacitors, resistors, conductive lines, conductive vias, and conductive contact pads.

  [0033] As used herein, the term "through-wafer interconnect" or "TWI" refers to a first semiconductor structure and a second semiconductor structure between a first semiconductor structure and a second semiconductor structure. Any extending through at least a portion of the first semiconductor structure used to provide structural and / or electrical interconnections across the interface between the two semiconductor structures Means and includes conductive vias. Through-wafer interconnects are also indicated in the art by other terms such as “through silicon via” or “through substrate via” (TSV) and “through wafer via” or “TWV”. Typically, the TWI extends through the semiconductor structure in a direction generally perpendicular to the generally planar major surface of the semiconductor structure (ie, in a direction parallel to the “Z” axis).

  [0034] The term "active surface" as used herein, when used in connection with a processed semiconductor structure, in the exposed major surface of the processed semiconductor structure and / or Or means and includes an exposed major surface of a processed semiconductor structure that has been or will be processed to form one or more device structures thereon.

  [0035] The term "backside surface" as used herein, when used in connection with a processed semiconductor structure, refers to the side opposite the active surface of the processed semiconductor structure. , Means and includes the exposed major surface of the treated semiconductor structure.

  [0036] As used herein, the term "III-V type semiconductor material" refers to one or more elements of group IIIA of the periodic table (B, Al, Ga, In, and Ti) and periodic table Means and includes any material composed primarily of one or more elements of Group VA (N, P, As, Sb, and Bi).

  [0037] The term "coefficient of thermal expansion" as used herein refers to the average linear coefficient of thermal expansion of a material or structure at room temperature when used with respect to the material or structure.

  [0038] As discussed in further detail below, in some embodiments, the present invention includes a method of forming a semiconductor structure having one or more through-wafer interconnects therein. The through-wafer interconnect may comprise two or more parts formed in separate processes.

FIG. 1 is a schematic cross-sectional side view of a portion of a first semiconductor structure 100. The first semiconductor structure 100 may comprise a layer or substrate of material 102. For example, the material 102 may be a ceramic such as an oxide (eg, silicon dioxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )) or a nitride (eg, silicon nitride (Si ₃ N ₄ ) or boron nitride (BN)). May be included. As another example, the first semiconductor material 100 may include a semiconductor material such as silicon (Si), germanium (Ge), a group III-V semiconductor material, and the like. Further, material 102 may include a single crystal semiconductor material or an epitaxial layer of semiconductor material. As one non-limiting example, the material 102 of the first semiconductor structure 100 may comprise a single crystal bulk silicon material.

  [0040] FIG. 2 shows another semiconductor structure 110 that may be formed by providing a via recess 112 in the semiconductor structure 100 of FIG. Via recess 112 may be used to form a portion of the through-wafer interconnect, as will be described in more detail below. As shown in FIG. 2, the via recess 112 may extend from the first major surface 104 of the semiconductor structure 110 into and at least partially through the material 102 of the semiconductor structure 110. In some embodiments, via recess 112 may comprise a blind via recess that extends only partially through material 102 of semiconductor structure 110.

  [0041] The via recess 112 may have a generally cylindrical cross-sectional shape or any other cross-sectional shape. Via recesses 112 may have an average cross-sectional dimension (eg, average diameter) of about 1 micrometer (1 μm) or less, or about 10 micrometers (10 μm) or less, or even 50 micrometers (50 μm) or less. Further, via recess 112 may have an average aspect ratio (ie, a ratio of average height to average cross-sectional dimension) ranging from about 0.5 to about 10.0.

FIG. 3 illustrates another semiconductor structure 120 that may be formed by applying a dielectric material 122 to the surface of the material 102 within the via recess 112. By way of example and not limitation, the dielectric material 122 may be an oxide (eg, silicon dioxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )), nitride (eg, silicon nitride (Si ₃ N ₄ ) or nitride). Boron (BN)), or ceramics such as oxynitride (eg, silicon oxynitride) may be included. Dielectric material 122 may be formed in situ on or in the exposed surface of material 102 in via recess 112. In further embodiments, dielectric material 122 may be deposited over the exposed surface of material 102 in via recess 112. As one specific, non-limiting example, material 102 may include a bulk silicon material, dielectric material 122 may include silicon oxide, and dielectric material 122 may include material 102 in via recess 112. It may be formed by oxidizing the exposed surface. In some embodiments, dielectric material 122 may also be deposited over first major surface 104 of semiconductor structure 110 (FIG. 2), as shown in FIG.

[0043] Referring to FIG. 4, the via recess 112 (FIG. 3) may be filled with a sacrificial material 132. FIG. The sacrificial material 132 includes a material that will eventually be removed and replaced with another material, as discussed below. The sacrificial material 132 may include, for example, a polycrystalline silicon material. In other words, the sacrificial material 132 may include silicon having a microstructure that includes a plurality of interconnected silicon particles that are randomly oriented within the microstructure. Such silicon materials are commonly referred to in the art as “polysilicon” materials. In further embodiments, the sacrificial material 132 is an optional material that can be etched more selectively than the material 102 (and optional dielectric material 122), such as ceramic, semiconductor material (eg, polycrystalline SiGe), polymer material, metal, etc. Other materials may also be included. In some embodiments, the sacrificial material 132 may include one or more additional dielectric materials, such as oxides, nitrides, or oxynitrides (eg, silicon dioxide). The sacrificial material 132 treats the semiconductor structure at a temperature greater than about 400 ° C., which is the temperature at which the semiconductor structure may be exposed during the manufacture of transistors or other device structures, as described in more detail below. The components selected so that the atoms of the sacrificial material 132 do not diffuse in a significant manner into the surrounding region of the semiconductor structure, or a significant amount of atoms in the surroundings during such a process at elevated temperatures. Even when it diffuses into the structure, it may have a component that does not adversely affect the semiconductor structure. In some embodiments, the sacrificial material 132 is within a range of about 40 percent (40%) of the coefficient of thermal expansion exhibited by the material 102 and within a range of about 20 percent (20%) of the coefficient of thermal expansion exhibited by the material 102. Or even may exhibit a coefficient of thermal expansion that is in the range of about 5 percent (5%) of the coefficient of thermal expansion exhibited by material 102. Further, in some embodiments, the sacrificial material 132 is about 5.0 × 10 ⁻⁶ ° C.− ¹ or less, about 3.0 × 10 ⁻⁶ ° C.− ¹ or less, or even about 1.0 × 10 10 A material having a coefficient of thermal expansion of ⁻⁶ ° C. ⁻¹ or less may be included.

  [0044] After applying the sacrificial material 132 in the via recess 112 (FIG. 3), the surface 134 of the semiconductor structure 130 is exposed to the exposed surface of the material 102 at the surface 134 of the semiconductor structure 130. And may be planarized to have at least substantially the same plane and the same extension. More specifically, the sacrificial material 132 may be conformally formed over the first major surface 104 (and optional dielectric material 122), for example, using a CVD method or the like. The sacrificial material 132 may be formed to a thickness such that the via recess 112 is at least substantially completely filled with the sacrificial material 132. The excess sacrificial material 132 (and optional dielectric material 132) may then be removed to planarize the surface 134 of the semiconductor structure 130. For example, the surface 134 of the semiconductor structure 130 may utilize a chemical process (eg, a wet chemical etch process or a dry chemical etch process) or a mechanical process (eg, a polishing process or a lapping process), or by a chemical mechanical polishing (CMP) process. , May be planarized.

  [0045] After applying the sacrificial material 132 in the via recess 112 (FIG. 3) as described above, a thin layer of semiconductor material may be provided over the surface 134 of the semiconductor structure 130. As a non-limiting example, a thin layer of semiconductor material may be provided over the surface 134 of the semiconductor structure 130, as will be described below with reference to FIGS.

  [0046] FIG. 5 illustrates a bonded semiconductor structure that may be formed by bonding another semiconductor structure comprising a substrate 142 to the surface 134 of the semiconductor structure 130 of FIG. The substrate 142 may include a semiconductor material such as silicon (Si), germanium (Ge), or a III-V semiconductor material. Further, the material of the substrate 142 may include a single crystal semiconductor material or an epitaxial layer of semiconductor material. As a non-limiting example, the material of the substrate 142 may include a single crystal bulk silicon material.

  [0047] The substrate 142 may have a direct atomic bond between the bonding surface of the semiconductor structure 130 and the bonding surface of the substrate 142 along a bonding interface between the bonding surface of the semiconductor structure 130 and the bonding surface of the substrate 142. The substrate 142 may be bonded to the surface 134 using a direct bonding process where the substrate 142 is bonded directly to the semiconductor structure 130 (FIG. 4) by creating a direct molecular bond. In other words, the substrate 142 may be bonded directly to the semiconductor structure 130 without using an adhesive or any other intermediate bonding material between the substrate 142 and the semiconductor structure 130. . The nature of atomic or molecular bonds between the substrate 142 and the semiconductor structure 130 is determined by the respective material components of the substrate 142 and the semiconductor structure 130. Thus, according to some embodiments, the direct atomic bond or direct molecular bond is between, for example, at least one of silicon oxide and germanium oxide and at least one of silicon, germanium, silicon oxide, and germanium oxide. It may occur.

[0048] By way of example and not limitation, the bonding surface of the substrate 142 may include an oxide material (eg, silicon dioxide (SiO ₂ )), and the bonding surface of the semiconductor structure 130 may be the same oxide material ( For example, it may be at least substantially composed of silicon dioxide (SiO ₂ ). In such embodiments, a silicon oxide-silicon oxide surface direct bonding process may be utilized to bond the bonding surface of the substrate 142 to the bonding surface of the semiconductor structure 130. In such an embodiment, as shown in FIG. 5, the bonding material 148 (eg, a layer of oxide such as silicon dioxide) is applied to the substrate 142 at the bonding interface between the substrate 142 and the semiconductor structure 130 (FIG. 4). And the semiconductor structure 130. The bonding material 148 may have an average thickness of, for example, about 1,000 mm.

  [0049] In a further embodiment, the bonding surface of the substrate 142 may include a semiconductor material (eg, silicon), and the bonding surface of the semiconductor structure 130 is at least substantially composed of the same semiconductor material (eg, silicon). May be. In such embodiments, a silicon-silicon surface direct bonding process may be utilized to bond the bonding surface of the substrate 142 to the bonding surface of the semiconductor structure 130.

  [0050] In some embodiments, the direct bonding between each bonding surface of the substrate 142 and each bonding surface of the semiconductor structure 130 has a relatively smooth surface so that the bonding surface of the substrate 142 has a relatively smooth surface. And may be established by forming bonding surfaces of the semiconductor structure 130 and then abutting the bonding surfaces together and maintaining contact between the bonding surfaces during the annealing process.

[0051] For example, the bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 are each about 2 nanometers (2.0 nm) or less, about 1 nanometer (1.0 nm) or less, or even about 1/4. It may be formed to have a root mean square surface roughness (R _RMS ) of nanometers (0.25 nm) or less. In some embodiments, the bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 are each about 1/4 nanometer (0.25 nm) to about 2 nanometer (2.0 nm), or even about It may be formed to have a root mean square surface roughness (R _RMS ) of ½ nanometer (0.5 nm) to about 1 nanometer (1.0 nm).

  [0052] The annealing process may be performed in a furnace at a temperature of about 100 degrees Celsius (100 degrees Celsius) to about 400 degrees Celsius (400 degrees Celsius) for about 2 minutes to about 15 hours in a furnace. Heating may be included.

  [0053] The bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 may each be formed to be relatively smooth as described above using at least one of a mechanical polishing process and a chemical etching process. . For example, a chemical mechanical polishing (CMP) process may be utilized to planarize and / or reduce the respective surface roughness of the bonding surface of the substrate 142 and the semiconductor structure 130.

  [0054] The first portion 144 of the substrate 142 is removed from the semiconductor structure 140 of FIG. 5 to leave behind a second portion 146 of the substrate 142 that covers the surface 134 and is bonded to FIG. A semiconductor structure 150 may be formed. In other words, the first portion 144 of the substrate 142 may be separated from the second portion 146 of the substrate 142. The semiconductor structure 150 of FIG. 6 includes a thin layer 152 of semiconductor material that covers a surface 134. This thin layer 152 of semiconductor material is formed by the second portion 144 of the substrate 142 (FIG. 5).

  [0055] Referring again to FIG. 5, by way of example and not limitation, a smart cut (SMART-CUT) (in order to separate the first portion 144 of the substrate 142 from the second portion 146 of the substrate 142). A process known in the art as a registered trademark process may be used. Such processes include, for example, Bruel, US Reissue Patent No. 39,484 (issued February 6, 2007), Aspar et al., US Pat. No. 6,303,468 (issued October 16, 2001), Aspar. U.S. Patent No. 6,335,258 (issued January 1, 2002), Moriceau et al. US Patent No. 6,756,286 (issued June 29, 2004), Aspar et al. US Patent No. 6 , 809,044 (issued October 26, 2004), and U.S. Pat. No. 6,946,365 to Aspar et al. (Issued September 20, 2005).

  [0056] A plurality of ions (eg, hydrogen, helium, or inert gas ions) may be implanted into the substrate 142. The ions may be implanted into the substrate 142 before or after mounting the substrate 142 to the semiconductor 130 of FIG. 4 as described above. For example, ions may be implanted into the substrate 142 from an ion source (not shown) positioned on the side of the substrate 142. Ions may be implanted into the substrate 142 along a direction substantially perpendicular to the major surface of the substrate 142. As is well known in the art, the depth at which ions are implanted into the substrate is at least partially correlated to the energy at which ions are implanted into the substrate. In general, ions implanted at a lower energy will be implanted at a relatively shallower depth, and ions implanted at a higher energy will be implanted at a relatively deeper depth.

  [0057] The ions may be implanted into the substrate 142 at a predetermined energy selected to implant ions into the substrate 142 to a desired depth. As one particular non-limiting example, the ions are such that the average thickness T of the second portion 146 of the substrate 142 is less than or equal to about 300 nanometers (300 nm), or even less than or equal to about 100 nanometers (100 nm). May be disposed in the substrate 142 at a selected depth. As is well known in the art, inevitably at least some ions may be implanted to a depth other than the desired implantation depth, and the ions may have a depth relative to the depth into the substrate 142 from the surface of the substrate 142. The concentration graph may exhibit a substantially bell-shaped (symmetric or asymmetric) curve with a maximum at the desired implantation depth.

  [0058] Upon implantation into the substrate 142, the ions may define a fracture surface 143 (shown as a dashed line in FIG. 5) in the substrate 142. The fracture surface 143 may include a layer or region in the substrate 142 that is linear with (eg, centered on) the maximum ion concentration plane of the substrate 142. The fracture surface 143 may define a weakened area in the substrate 142 where the substrate 142 may be cleaved or broken along that area in a later process. The substrate 142 is cleaved along the fracture surface 143 by heating the substrate 142, applying mechanical force to the substrate 142, or applying energy to the substrate 142 in another manner. Or it may be broken.

  [0059] In a further embodiment, the second portion 146 of the substrate 142 bonds a relatively thick layer of material, such as the substrate 142 (eg, a layer having an average thickness greater than about 300 microns), and then the surface 134. 4 may be provided over the surface 134 of the semiconductor structure 130 of FIG. 4 by thinning the relatively thick substrate 142 from the side 149 of the opposite substrate 142. For example, the substrate 142 may be thinned using a chemical process (eg, a wet chemical etch process or a dry chemical etch process), a mechanical process (eg, a polishing process or a lapping process), or a chemical mechanical polishing (CMP) process. .

  [0060] In yet other embodiments, a relatively thin layer of semiconductor material (which may be at least substantially similar in composition and configuration to the second portion 146 of the substrate 142) is provided in the semiconductor structure of FIG. It may be formed in situ over (eg, on) the surface 134 of the body 130. For example, a relatively thin layer of silicon material may be formed by depositing a material such as silicon over the surface 134 of the semiconductor structure 130 of FIG. 4 to a desired thickness.

  [0061] After providing a thin layer 152 of semiconductor material over the surface 134 of the semiconductor structure 130 of FIG. 3, one or more device structures are on and / or in the thin layer 152 of semiconductor material. It may be formed. In other words, one or more device structures may be formed using a thin layer 152 of semiconductor material. By way of example and not limitation, a plurality of transistors may be fabricated using a thin layer 152 of semiconductor material.

  [0062] FIG. 7 illustrates the bonded semiconductor device 150 of FIG. 6 surrounded by a dashed line 158 after processing the semiconductor structure 150 to form the bonded and processed semiconductor structure 160 of FIG. A part of is shown. The semiconductor structure 160 includes one or more transistors 162. For clarity, only one transistor 162 is shown in FIG. As shown in FIG. 7, each transistor 162 may include a source including a source region 163A and a source contact 163B, a drain including a drain region 164A and a drain contact 164B, and a gate structure 165. Source region 163A and drain region 164A may each include a region of thin layer 152 of semiconductor material doped with one or more dopants to render it conductive. The source region 163A and the drain region 164A may be separated from each other by a channel region 166 that may include an undoped region of the thin layer 152 of semiconductor material. The gate structure 165 may be disposed laterally over the channel region 166 between the source and drain of the transistor 162. Source contact 163B, drain contact 164B, and gate structure 165 may each include a conductive material, such as one or more metals, or a doped polysilicon material. The conductive material of the gate structure 165 may be electrically isolated from the thin layer 152 of semiconductor material by one or more dielectric materials (eg, oxide, nitride, oxynitride, etc.).

  [0063] As shown in FIG. 7, one or more shallow trench isolation structures 168 may be formed in and through the thin layer 152 of semiconductor material proximal to the transistor 162. . Shallow trench isolation structure 168 may include a dielectric material and may be used to electrically isolate each transistor 162 from other transistors or other device structures of semiconductor structure 160. By way of example and not limitation, the shallow trench isolation structure 168 may include a dielectric material such as oxide, nitride, oxynitride, and the like. The shallow trench isolation structure 168 may be aligned vertically with the via recess 112 and the sacrificial material 132 contained within the via recess 112 (ie, perpendicular to the major surface of the semiconductor structure 160, such as the surface 134). May be aligned along any direction). In other words, the via recess 112 and the sacrificial material 132 have a straight line passing through the sacrificial material 132 in one of the shallow trench isolation structure 168 and the via recess 112, and the main structure of the semiconductor structure 160 such as the surface 134. They may be positioned relative to each other so that they can be pulled at least substantially perpendicular to the surface.

  [0064] Referring to FIG. 8, the bonded and processed semiconductor structure 170 has the semiconductor structure of FIG. 7 with one or more transistors 162 and shallow trench isolation structures 168 formed therein and / or thereon. A layer 172 of dielectric material (eg, interlayer dielectric material) is provided over the exposed surface 169 of the body 160 to form a first portion 174 of the through-wafer interconnect in the shallow trench isolation structure 168. May be formed.

  [0065] A layer 172 of dielectric material may be formed over or disposed over the surface 169 to cover the gate structure 165 of the transistor 162 as shown in FIG. It may have a sufficient average thickness. The dielectric material layer 172 may comprise a dielectric material such as oxide, nitride, oxynitride, or the like.

  [0066] With continued reference to FIG. 8, the first portion 174 of the through-wafer interconnect may be formed in the semiconductor structure 170. The first portion 174 of the through-wafer interconnect may include a conductive material such as one or more metals, doped polysilicon, and the like. A first portion 174 of the through-wafer interconnect extends through the dielectric material layer 172, through the shallow trench isolation structure 168, through the optional bonding material 148, and via recesses in the material 102. 112 may be formed by forming a via recess 176 in the sacrificial material 132 in 112. In some embodiments, the shallow trench isolation structure 168 may not extend completely through the thin layer 152 of semiconductor material, and the via recess 176 may be formed on the thin layer 152 of semiconductor material. It may extend through at least a portion. The via recess 176 may be formed using, for example, a masking process and an etching process. A mask layer may be provided over the exposed major surface 178 of the layer 172 of dielectric material. This mask layer may be patterned to form holes or holes that extend through the mask layer at locations where it is desired to form via recesses 176. The holes in the mask layer may have a cross-sectional size and cross-sectional shape corresponding to the desired cross-sectional size and cross-sectional shape of the via recess 176 to be formed. The semiconductor structure 170 then uses one or more etchants to etch various materials that will extend through the via recess 176 without etching the mask layer (at a significant rate). You may be exposed to. For example, a wet chemical etch process or a dry chemical etch process may form a via recess 176 through the dielectric material layer 172, the shallow trench isolation structure 168, and the optional bonding material 148 to the sacrificial material 132. In addition, it may be used.

  [0067] In some embodiments, via recess 176 may have an average aspect ratio (ie, ratio of average height to average cross-sectional dimension) within a range ranging from about 0.5 to about 10.0. Good.

  [0068] After formation of the via recess 176, a conductive material may be applied in the via recess 176. For example, one or more metallic materials may be disposed in the via recess 176 using an electroless plating process and / or an electrolytic plating process.

  [0069] The first portion 174 of the through-wafer interconnect is similar to the shallow trench isolation structure 168 through which it extends, and the sacrificial material 132 contained within the via recess 112. (I.e., aligned along a direction perpendicular to the major surface of the semiconductor structure 170, such as the surface 134). In other words, the first portion 174 of the through-wafer interconnect and the sacrificial material 132 pass through the first portion 174 of the through-wafer interconnect and the volume portion of the sacrificial material 132 within one of the via recesses 112. The straight lines may be positioned relative to each other so that they can be drawn at least substantially perpendicular to the major surface of the semiconductor structure 170, such as the surface 134.

  [0070] After formation of the first portion 174 of the through-wafer interconnect, additional processing covers the exposed major surface 178 of the layer of dielectric material 172, conductive vias, conductive lines, conductive traces. And may be implemented to form additional device structures such as conductive pads. Such processes may include what is referred to in the art as a “back end of line” (BEOL) process.

  [0071] For example, FIG. 9 illustrates a bonded and processed semiconductor structure 180 that may be formed by manufacturing a plurality of device structures 182 in one or more surrounding dielectric materials 184. Device structure 182 comprises one or more of conductive vias, conductive lines, conductive traces, and conductive pads including conductive material such as one or more metals or doped polysilicon. May be. The one or more surrounding dielectric materials 184 may include oxides, nitrides, oxynitrides, and the like. Various device structures 182 and surrounding dielectric material 184 may be formed lithographically (ie, layer by layer) over major surface 178 of layer 172 of dielectric material using processes known in the art. Good.

  [0072] After formation of the device structure 182 overlying the layer of dielectric material 172 as discussed above in connection with FIG. 9, a portion of the material 102 is removed from the semiconductor structure 180 to provide the junction of FIG. The sacrificial material 132 that penetrates the material 102 may be exposed, as shown in the processed semiconductor structure 190. This portion of the material 102 may be removed from the exposed major surface 103 (FIG. 9) of the material 102 on the side of the semiconductor structure 180 opposite the active surface 186. By way of example and not limitation, this portion of material 102 may be removed utilizing, for example, one or more of a chemical etching process, a mechanical polishing process, or a chemical mechanical polishing (CMP) process. . Also, if the dielectric material 122 is disposed between the sacrificial material 132 and the material 102 as shown in FIG. 9, a portion of the dielectric material 122 is removed, as shown in FIG. In addition, the sacrificial material 132 may be exposed outside the semiconductor structure 190.

  [0073] Optionally, the active surface 186 of the semiconductor structure 180 of FIG. 9 removes the material 102 and exposes the sacrificial material 132 to assist in handling the semiconductor structure during removal of the material 102. Before, it may be bonded to the carrier substrate 192 as illustrated in FIG.

[0074] After exposing the sacrificial material 132 to the outside of the semiconductor structure 190 as illustrated in FIG. 10, the sacrificial material 132 is formed to form the bonded and processed semiconductor structure 200 illustrated in FIG. The via recess 112 may be removed. By way of example and not limitation, a wet chemical etching process may be utilized to remove the sacrificial material 132 from within the via recess 112. An etchant that etches (eg, removes) the sacrificial material 132 from the semiconductor structure 200 at a rate that is faster than the rate at which the dielectric material 122 and any bonding material 148 are removed may be used to remove the sacrificial material 132. Good. In other words, an etchant that is selective to the sacrificial material 132 (and optionally to the optional dielectric material 122) and the bonding material 148 may be used to remove the sacrificial material 132. . In embodiments where the sacrificial material includes a polysilicon material, the etchant may include a mixture of nitric acid, hydrofluoric acid, and water. In embodiments where the sacrificial material 132 includes other dielectric materials such as silicon dioxide, the sacrificial material 132 uses an etch solution or plasma etch process that includes hydrofluoric acid (eg, sulfur hexafluoride SF ₆ etch chemistry). ) May be selectively etched.

  [0075] As illustrated in FIG. 12, the conductive material forms voids in via recess 112 (removal of sacrificial material 132) to form second portion 212 of through-wafer interconnect 214. Inside). The through-wafer interconnect 214 includes a first portion 174 and a second portion 212. Direct physical and electrical contact may be established between the first portion 174 and the second portion 212 of the through-wafer interconnect 214.

  [0076] The conductive material of the second portion 212 of the through-wafer interconnect 214 may include a conductive material such as one or more metals, doped polysilicon, and the like. In some embodiments, the conductive material of the second portion 212 of the through-wafer interconnect 214 is at least substantially the same as the conductive material of the first portion 174 of the through-wafer interconnect 214. May be. This conductive material may be applied in the via recesses 112, 176. For example, one or a metallic material may be disposed in the via recess 176 utilizing an electroless plating process and / or an electrolytic plating process.

  The through-wafer interconnect 214 includes a first portion 174 and a second portion 212. By forming the first portion 174 and the second portion 212 in separate processes at different successive times during the manufacture of the semiconductor structure 210, in some embodiments of the present invention, wafer through There may be a distinct identifiable boundary 216 of the microstructure between the first portion 174 and the second portion 212 of the interconnect 214. This identifiable boundary 216 may be located proximal to the major surface of the thin layer 152 of semiconductor material. For example, the identifiable boundary 216 may be coplanar with the bonding material 148 disposed on the major surface of the thin layer 152 of semiconductor material. Further, the semiconductor structure 210 may be oriented parallel to the active surface 186 as illustrated in FIG.

  [0078] In some embodiments, the through-wafer interconnect 214 has an average aspect ratio (ie, ratio of average height to average cross-sectional dimension) in a range ranging from about 0.5 to about 10.0. May be.

  [0079] After forming the through-wafer interconnect 214 as described above, the carrier substrate 192 is bonded and processed in FIG. 12 to form the bonded and processed semiconductor structure 220 in FIG. It may be removed from the structure 210. As illustrated in FIG. 13, conductive bumps 222 are structured with the exposed end of the second portion 212 of the through-wafer interconnect 214 at the backside surface 224 of the semiconductor structure 220 opposite the active surface 186. And may be electrically and electrically coupled. The conductive bump 222 may include a conductive material such as a conductive solder alloy.

  [0080] Optionally, the semiconductor structure 220 shown in FIG. 13 may be further processed and packaged as needed or desired. Subsequently, the semiconductor structure 220 is structurally and mechanically coupled to another structure, such as a printed circuit board, another semiconductor structure (eg, another chip or wafer), etc. using conductive bumps 222. May be. In further embodiments, the semiconductor structure 220 may be transferred to another structure using other devices and techniques known in the art, such as the use of conductive leads, anisotropic conductive films, etc. It may be structurally and electrically coupled.

  [0081] Referring again to FIG. 10, in some embodiments of the present invention, the sacrificial material 132 in the via recess 112 may be selectively etched without etching other materials of the semiconductor structure 190. It can be relatively difficult. In such embodiments, it may be desirable to protect other materials of the semiconductor structure 190 prior to etching the sacrificial material 132, as described herein above.

[0082] For example, FIG. 14 illustrates an embodiment of the semiconductor structure 190 of FIG. 10 in a manner that covers at least substantially all of the exposed surface of the semiconductor structure 230 except in certain cases on certain surfaces of the carrier substrate 192. Illustrated is a semiconductor structure 230 that may be formed by depositing a mask layer 232 over the surface. The mask layer 232 may be an oxide (eg, silicon dioxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )), nitride (eg, silicon nitride (Si ₃ N ₄ ) or boron nitride (BN)), or oxynitride. A ceramic material such as

  [0083] As illustrated in FIG. 15, the mask layer 232 extends through the mask layer 232 to form an opening 242 that ultimately results in the bonded and processed semiconductor structure 240 of FIG. May be patterned. Photolithographic masking and etching processes such as are known in the art may be utilized to form the opening 242 through the mask layer 232. The opening 242 may be sized, shaped, and positioned so that the sacrificial material 132 in the via recess 112 is exposed through the opening 242. The semiconductor structure 240 may then be subjected to a wet etch process or a dry etch process using an etchant that is selective to the sacrificial material 132 over the material of the mask layer 232. Such an etching process removes the sacrificial material 132 from within the via recess 112, resulting in the semiconductor structure 250 of FIG. The mask layer 232 may then be removed from the semiconductor structure 250 of FIG. 16 to form a semiconductor structure that is at least substantially identical to the semiconductor structure 200 of FIG.

[0084] In a further method, sacrificial material 132 is formed such that upon thinning of material 102 as discussed above in connection with FIGS. 9 and 10, material 102 forms semiconductor structure 260 of FIG. And / or may be recessed from the optional dielectric material 122. By way of example and not limitation, material 102 may be recessed from sacrificial material 132 and / or optional dielectric material 122 by about 2,000 inches. After forming the semiconductor structure 260 of FIG. 17, a mask layer 272 may be deposited over the semiconductor structure 260 to form the semiconductor structure 270 of FIG. The mask layer 272 may be an oxide (eg, silicon dioxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )), nitride (eg, silicon nitride (Si ₃ N ₄ ) or boron nitride (BN)), or oxynitride. A ceramic material such as As shown in FIG. 18, the semiconductor structure 270 may include a major surface 274 on the opposite side of the carrier substrate 192.

  [0085] The major surface 274 of the semiconductor structure 270 of FIG. 18 is shown with portions of the mask layer 272 (and portions of the optional dielectric material 122) covering the volume of the sacrificial material 132 in the via recess 112 removed. A planarization process, such as a chemical mechanical polishing (CMP) process, may be performed to form 19 bonded and processed semiconductor structures 280. As illustrated in FIG. 19, the sacrificial material 132 may be exposed through the mask layer 272 after planarization of the major surface 274 (FIG. 18). Then, after the sacrificial material 132 is exposed, the semiconductor structure 280 may be subjected to a wet etching process or a dry etching process using an etchant that is selective to the sacrificial material 132 over the material of the mask layer 272. Such an etching process results in the removal of the sacrificial material 132 from within the via recess 112, resulting in the bonded and processed semiconductor structure 290 of FIG. The mask layer 272 may then be removed from the semiconductor structure 290 of FIG. 20 to form a semiconductor structure that is at least substantially identical to the semiconductor structure 200 of FIG. The semiconductor structure may be further processed as described above.

  [0086] Formation of the through-wafer interconnect in a multi-step process (eg, a two-step process) as described above in connection with the through-wafer interconnect 214 is such that the aspect ratio of the individual portions of the through-wafer interconnect is: Less than the overall aspect ratio of the through-wafer interconnect, which makes it easier to etch via recesses in which the individual portions of the through-wafer interconnect are formed, insulating the exposed surface in the via recess Yield of semiconductor structures that work properly during manufacturing due to improved coverage of dielectric material and improved plating of conductive material in via recesses to form individual sections of through-wafer interconnects Can be improved. Further, the fabrication of transistors, such as transistor 162 as described herein, may expose the semiconductor structure to temperatures greater than about 400 degrees Celsius. If the conductive metal is placed in the via recess during processing of the semiconductor structure at such a high temperature, the metal atoms diffuse into other regions of the semiconductor structure, which contributes to the operation of the semiconductor structure. Can have adverse effects. Furthermore, mismatches between the thermal expansion coefficients of such metallic materials and the thermal expansion coefficients of the surrounding dielectric and semiconductor materials can cause structural damage to the semiconductor structure. Therefore, by applying a sacrificial material in a via recess in the semiconductor structure before the manufacture of the transistor and replacing the sacrificial material with another conductive material after the manufacture of the transistor, such structural damage is avoided or such a structure The possibility of causing mechanical damage can be reduced.

  [0087] Further non-limiting embodiments of the invention are described below.

  [0088] Embodiment 1: A method of manufacturing a semiconductor structure, comprising providing a sacrificial material in at least one via recess extending partially through the semiconductor structure; and in the semiconductor structure Forming a first portion of at least one through-wafer interconnect, aligning at least one via recess with the first portion of at least one through-wafer interconnect, and at least one via recess. Replacing the sacrificial material in the conductive material and forming a second portion of the at least one through-wafer interconnect in electrical contact with the first portion of the at least one through-wafer interconnect. ,Method.

  [0089] Embodiment 2: The method of embodiment 1, wherein forming a first portion of at least one through-wafer interconnect in a semiconductor structure passes through at least one dielectric material. Extending the first portion of the through-wafer interconnect.

  [0090] Embodiment 3: The method of embodiment 1, wherein providing a sacrificial material in at least one via recess extending partially through the semiconductor structure from the surface of the semiconductor structure to the semiconductor Forming at least one blind via recess extending partially through the structure, and at least one of a polysilicon material, a III-V semiconductor material, and a dielectric material in the at least one blind via recess. Providing one.

  [0091] Embodiment 4: The method of Embodiment 3, wherein providing at least one of polysilicon material, III-V semiconductor material, and dielectric material in at least one blind via recess, at least Providing a polysilicon material in one blind via recess.

  [0092] Embodiment 5: The method of Embodiment 3, further comprising forming at least one via recess through the bulk silicon material.

  [0093] Embodiment 6: The method of embodiment 4, further comprising providing a dielectric material between the bulk silicon material and the polysilicon material in the at least one blind via recess.

  [0094] Embodiment 7: The method of Embodiment 3, further comprising providing a thin layer of semiconductor material covering the surface of the semiconductor structure after providing polysilicon material in the at least one blind via recess. ,Method.

  [0095] Embodiment 8: The method of Embodiment 7, wherein the provision of a thin layer of semiconductor material covering the surface of the semiconductor structure breaks down the substrate by implanting ions into the substrate comprising the semiconductor material. Forming a cross-section, bonding the substrate to the surface of the semiconductor structure, rupturing the substrate along the fracture surface, and bonding to the surface of the semiconductor structure from the remaining portion of the substrate Separating the thin layer of semiconductor material that remains in the processed state.

  [0096] Embodiment 9: The method of Embodiment 8, wherein bonding the substrate to the surface of the semiconductor structure includes directly bonding the substrate to the surface of the semiconductor structure. Method.

  [0097] Embodiment 10: The method of embodiment 7, further comprising forming at least a portion of the device structure using a thin layer of semiconductor material.

  [0098] Embodiment 11: The method of embodiment 10, wherein the thin layer of semiconductor material is used to form at least a portion of the device structure, and the thin layer of semiconductor material is used to form at least a portion of the transistor. Forming a method.

  [0099] Embodiment 12: The method of Embodiment 7, wherein providing a thin layer of semiconductor material covering a surface of the semiconductor structure has a thin layer having an average thickness of about 300 nanometers (300 nm) or less. Forming a method.

  [0100] Embodiment 13: The method of Embodiment 12, wherein providing a thin layer of semiconductor material covering a surface of the semiconductor structure comprises a thin layer having an average thickness of about 100 nanometers (100 nm) or less. Forming a method.

  [0101] Embodiment 14: The method of any one of Embodiments 1 to 3, after forming the first portion of the at least one through-wafer interconnect, and replacing the sacrificial material with a conductive material; The method further comprises thinning the semiconductor structure prior to forming the second portion of the at least one through-wafer interconnect.

  [0102] Embodiment 15: The method of Embodiment 14, wherein thinning the semiconductor structure includes exposing a sacrificial material to the outside of the semiconductor structure.

  [0103] Embodiment 16: The method of Embodiment 14, wherein the semiconductor structure is attached to a carrier substrate before the semiconductor structure is thinned, and the semiconductor structure is thinned after the semiconductor structure is thinned. Removing the carrier substrate from the method.

  [0104] Embodiment 17: A method of manufacturing a semiconductor structure, comprising providing a sacrificial material in at least one via recess extending into a surface of the semiconductor structure, and covering the surface of the semiconductor structure Providing a layer of semiconductor material; using the layer of semiconductor material to manufacture at least one device structure; and forming a first through-wafer interconnect that extends through the layer of semiconductor material. Forming a portion of the semiconductor structure, thinning the semiconductor structure from a side opposite the layer of semiconductor material, removing sacrificial material from within at least one via recess in the semiconductor structure, Exposing a first portion of at least one through-wafer interconnect within and providing a conductive material within the via recess to form a second portion of at least one through-wafer interconnect And a Rukoto, method.

  [0105] Embodiment 18: The method of Embodiment 17, wherein providing a sacrificial material in at least one via recess includes providing a polysilicon material in at least one via recess.

  [0106] Embodiment 19: The method of Embodiment 17 or Embodiment 18, further comprising providing a dielectric material between the sacrificial material and the semiconductor structure in the at least one via recess.

  [0107] Embodiment 20: The method of any one of Embodiments 17-19, wherein the layer of semiconductor material is provided over the surface of the semiconductor structure to provide a layer of semiconductor material from the substrate to the semiconductor structure. A method comprising transcribing.

  [0108] Embodiment 21: The method of embodiment 20, wherein transferring a layer of semiconductor material from the substrate to the semiconductor structure includes implanting ions into the substrate and bonding the substrate to the semiconductor structure. Joining, and breaking the substrate along a surface defined by ions implanted into the substrate, separating the layer of semiconductor material from the remainder of the substrate.

  [0109] Embodiment 22: The method of any one of Embodiments 17-21, wherein providing a layer of semiconductor material over the surface of the semiconductor structure provides an average thickness of about 100 nanometers (100 nm) or less. Selecting a layer of semiconductor material to have a thickness.

  [0110] Embodiment 23: The method of any one of Embodiments 17-22, wherein the semiconductor structure is attached to the carrier substrate before thinning the semiconductor structure, and the semiconductor structure is thinned. Removing the carrier substrate from the semiconductor structure after forming.

  [0111] Embodiment 24: The method of any one of Embodiments 17-23, further comprising forming conductive bumps on at least one through-wafer interconnect.

  [0112] Embodiment 25: A sacrificial material in at least one via recess extending partially through the semiconductor structure from the surface of the semiconductor structure, and a semiconductor material disposed over the surface of the semiconductor structure At least one device structure including at least a portion of a semiconductor material disposed over the surface of the semiconductor structure; and at least one extending through the semiconductor material disposed over the surface of the semiconductor structure. A first portion of one through-wafer interconnect, wherein the first portion of at least one through-wafer interconnect is aligned with at least one via recess. Semiconductor structure.

  [0113] Embodiment 26: The semiconductor structure of embodiment 25, wherein the volume portion of the dielectric material is at least partially surrounded by a semiconductor material disposed over the surface of the semiconductor structure, and at least 1 A semiconductor structure, wherein the first portion of one through-wafer interconnect further comprises a volume of dielectric material extending through and in direct contact with the volume of dielectric material.

  [0114] Embodiment 27: The semiconductor structure of Embodiment 26, wherein the volume portion of the dielectric material includes a shallow trench isolation structure.

  [0115] Embodiment 28: The semiconductor structure of any one of Embodiments 25 to 27, wherein the sacrificial material comprises a polysilicon material.

  [0116] Embodiment 29: The semiconductor structure of any one of Embodiments 25 to 28, wherein at least one device structure comprises at least one transistor.

  [0117] Embodiment 30: The semiconductor structure of any one of Embodiments 25 to 29, wherein the sacrificial material is on the opposite side of the semiconductor material disposed over the surface of the semiconductor structure. A semiconductor structure exposed outside the body.

  [0118] Embodiment 31: The semiconductor structure of any one of Embodiments 25-30, further comprising a carrier substrate attached to the semiconductor structure.

  [0119] Embodiment 32: The semiconductor structure of any one of Embodiments 25-31, wherein the semiconductor material disposed over the surface of the semiconductor structure has an average thickness of about 300 nanometers (300 nm) or less. A semiconductor structure comprising a layer of semiconductor material having a thickness.

  [0120] Embodiment 33: The semiconductor structure of embodiment 32, wherein the layer of semiconductor material has an average thickness of about 100 nanometers (100 nm) or less.

  [0121] Embodiment 34: At least one transistor located within a semiconductor structure between an active surface, a backside surface, an active surface and a backside surface, and at least a semiconductor structure from at least one of the active surface and the backside surface At least one through-wafer interconnect extending partially through the first portion, the second portion, the first portion microstructure and the second portion microstructure; A semiconductor structure comprising at least one through-wafer interconnect with an identifiable boundary between the two.

  [0122] Embodiment 35: The semiconductor structure of embodiment 34, wherein the at least one transistor includes at least a portion of a thin layer of semiconductor material.

  [0123] Embodiment 36: The semiconductor structure of embodiment 35, wherein the thin layer of semiconductor material has an average thickness of about 100 nanometers (100 nm) or less.

  [0124] Embodiment 37: The semiconductor structure of embodiment 35 or 36, wherein the identifiable boundary is located proximal to the major surface of the thin layer of semiconductor material.

  [0125] Embodiment 38: The semiconductor structure of any one of Embodiments 34 through 37, wherein the identifiable boundary is oriented parallel to at least one of the active surface and the back surface. .

Claims (25)

A method of manufacturing a semiconductor structure, comprising:
Providing a sacrificial material in at least one via recess extending partially through the semiconductor structure;
Forming a first portion of at least one through-wafer interconnect in the semiconductor structure and aligning the first portion of the at least one through-wafer interconnect with the at least one via recess. When,
The sacrificial material in the at least one via recess is replaced with a conductive material and the at least one through-wafer interconnect portion in electrical contact with the first portion of the at least one through-wafer interconnect portion. Forming a portion of 2;
Including a method.   The step of forming a first portion of at least one through-wafer interconnect in the semiconductor structure extends through the dielectric material to extend the first portion of the at least one through-wafer interconnect. The method of claim 1 further comprising the step of: Providing the sacrificial material in the at least one via recess extending partially through the semiconductor structure;
Forming at least one blind via recess extending partially through the semiconductor structure from a surface of the semiconductor structure;
Providing at least one of polysilicon material, silicon germanium (SiGe), group III-V semiconductor material, and dielectric material in the at least one blind via recess;
The method of claim 1 comprising:   Providing at least one of polysilicon material, silicon germanium (SiGe), group III-V semiconductor material, and dielectric material in the at least one blind via recess; 4. The method of claim 3, comprising applying a polysilicon material to the substrate.   The method of claim 3, further comprising forming the at least one via recess through a bulk silicon material.   6. The method of claim 5, further comprising providing a dielectric material between the bulk silicon material and the polysilicon material in the at least one blind via recess.   The method of claim 3, further comprising providing a thin layer of semiconductor material covering a surface of the semiconductor structure after the step of providing the polysilicon material in the at least one blind via recess. Providing the thin layer of semiconductor material covering the surface of the semiconductor structure;
Forming a fracture surface in the substrate by implanting ions into the substrate comprising a semiconductor material;
Bonding the substrate to the surface of the semiconductor structure;
Breaking the substrate along the fracture surface and separating the thin layer of semiconductor material that remains bonded to the surface of the semiconductor structure from the remainder of the substrate;
The method of claim 7 comprising:   The method of claim 8, wherein bonding the substrate to the surface of the semiconductor structure comprises bonding the substrate directly to the surface of the semiconductor structure.   The method of claim 7, further comprising forming at least a portion of a device structure using the thin layer of semiconductor material.   11. The method of claim 10, wherein forming the at least a portion of the device using the thin layer of semiconductor material comprises forming at least a portion of a transistor using the thin layer of semiconductor material. .   8. The step of providing the thin layer of semiconductor material covering the surface of the semiconductor structure comprises forming the thin layer having an average thickness of about 300 nanometers (300 nm) or less. the method of.   The step of providing the thin layer of semiconductor material covering the surface of the semiconductor structure comprises forming the thin layer having an average thickness of about 100 nanometers (100 nm) or less. the method of.   After the step of forming the first portion of the at least one through-wafer interconnect, and replacing the sacrificial material with the conductive material, the second portion of the at least one through-wafer interconnect is The method of claim 1, further comprising thinning the semiconductor structure prior to the forming step.   The method of claim 14, wherein thinning the semiconductor structure comprises exposing the sacrificial material to the outside of the semiconductor structure. Attaching the semiconductor structure to a carrier substrate before thinning the semiconductor structure;
Removing the carrier substrate from the semiconductor structure after the step of thinning the semiconductor structure;
15. The method of claim 14, further comprising: A sacrificial material in at least one via recess extending partially through the semiconductor structure from the surface of the semiconductor structure;
A semiconductor material disposed over the surface of the semiconductor structure;
At least one device structure including at least a portion of the semiconductor material disposed over the surface of the semiconductor structure;
A first portion of at least one through-wafer interconnect extending through the semiconductor material disposed over the surface of the semiconductor structure and aligned with the at least one via recess; A first portion of at least one through-wafer interconnect; and
A semiconductor structure comprising:   And further comprising a volume of dielectric material at least partially surrounded by the semiconductor material disposed over the surface of the semiconductor structure, wherein the first portion of the at least one through-wafer interconnect is The semiconductor structure of claim 17, extending through the volume of dielectric material and in direct contact with the volume of dielectric material.   The semiconductor structure of claim 18, wherein the volume portion of dielectric material comprises a shallow trench isolation structure.   The semiconductor structure of claim 17, wherein the sacrificial material comprises a polysilicon material.   The semiconductor structure of claim 17, wherein the at least one device structure comprises at least one transistor.   The semiconductor structure of claim 17, wherein the sacrificial material is exposed to the outside of the semiconductor structure at a side opposite to the semiconductor material disposed over the surface of the semiconductor structure.   The semiconductor structure of claim 22, further comprising a carrier substrate attached to the semiconductor structure.   The semiconductor structure of claim 17, wherein the semiconductor material disposed over the surface of the semiconductor structure comprises a layer of the semiconductor material having an average thickness of about 300 nanometers (300 nm) or less.   The semiconductor structure of claim 19, wherein the layer of the semiconductor material has an average thickness of about 100 nanometers (100 nm) or less.

Images