JP2013222314A - Electronic circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce design difficulty and improve signal quality in electronic circuit boards including a memory provided with a plurality of synchronous dynamic random access memories (SDRAM).SOLUTION: An electronic circuit board 10 comprises: a memory 12 that includes N (N is an integer of more than three) pieces of SDRAM (for example, M0 to M7) provided on a single side; and a memory controller 11 that controls the memory 12. The N pieces of SDRAM are wired by a Fly-by structure so as to input differential clock signals (for example, two differential clock signals CLK1 and CLK2) of L (L is an integer of more than two smaller than N) systems to the N pieces of SDRAM. The memory controller 11 uses the differential clock signal of the L system to control the N pieces of SDRAM on the basis of respective delay amounts of the N pieces of SDRAM determined by a write leveling approach.

Description

  The present invention relates to an electronic circuit board including a memory having a plurality of SDRAMs.

  DDR3 SDRAM (Double-Data-Rate3 Synchronous Dynamic Random Access Memory) is a kind of DRAM standard composed of semiconductor integrated circuits, and is used in various electronic devices such as personal computers (PCs) and image forming apparatuses such as multifunction peripherals. Used as a main storage device.

  Patent Document 1 describes a memory control circuit of a standard SDRAM in which a phase difference between read data and a read clock is kept constant. In this memory control circuit, the data bus driver and the receiver are arranged separately, the data bus is connected from the data bus driver to the receiver, the SDRAM memory module is connected to the data bus, and the clock signal line is the data signal It is connected to each SDRAM so that the signal propagation delay time is equal to that of the bus, and is configured to operate as a synchronization signal for reading data read by the receiver of the memory control circuit.

  Patent Document 2 describes a memory control integrated circuit that can adjust an external change to an optimum position with a minimum frequency even at different frequencies. This memory control integrated circuit is a memory control integrated circuit that receives a signal from an upper device and an input clock and controls the SDRAM, and has a memory control unit, a PLL (Phase-locked loop), and a clock distribution unit, The control unit outputs a signal for controlling the SDRAM, the PLL inputs an input clock and a feedback clock, supplies a clock synchronized with the input clock and the feedback clock to the clock distribution unit, and an SDRAM clock supplied to the SDRAM by the clock distribution unit And a circuit configured to output a feedback clock to be input to the PLL and a read clock for latching data from the SDRAM.

  Patent Document 3 describes a stable memory control circuit that has no possibility of generating jamming waves to other devices and does not attenuate the waveform of a memory control signal or a clock signal. The memory control circuit includes a memory controller that controls the memory, a drive current variable driver that drives a memory address bus and a memory control signal, a DIMM in which the memory is modularized, a DIMM detection circuit that detects a mounted capacity of the DIMM, It is composed of a drive current setting circuit that sets the drive capability of the driver and a CPU, and automatically adjusts the drive capability of the driver according to the capacity of the mounted memory, so that signal waveforms such as clock, address bus, memory control etc. To realize a stable circuit operation.

  Patent Document 4 describes a semiconductor device that can accurately calculate a phase difference between a clock signal and a control signal in a memory that operates in synchronization with the clock signal. This semiconductor device is a semiconductor device that operates in synchronization with a clock signal and controls a memory having a sampling circuit that samples the clock signal at the rising edge of the control signal, and outputs the control signal with a delay within a predetermined range. And an indefinite range of sampling results caused by not satisfying the setup time or hold time of the sampling circuit based on the sampling result from the sampling circuit obtained while changing the delay amount of the control signal by the delay unit. And an adjusting means for obtaining the phase difference between the clock signal and the control signal based on the indefinite range extracted by the extracting means and adjusting the delay amount of the control signal.

  In addition, as a module standard of DDR3 SDRAM, Non-Patent Document 1 describes design specifications of Unbuffered Double Data Rate Synchronous DRAM Dual In-Line Small Outline Memory Modules (DDR3 SDRAM SO-DIMMs) determined by the JEDEC Semiconductor Technology Association. Has been.

JP 2000-194594 A JP 2001-160000 A JP-A-2004-46502 JP 2011-253501 A

“PC3-6400 / PC3-8500 / PC3-10600 / PC3-12800 / PC3-14900 / PC3-17000 DDR3 Unbuffered SO-DIMM Reference Design Specification”, Revision 2.0, JEDEC Standard No. 21C, Page 4.20.18-1, December 2010

  Incidentally, a main memory is mounted on an electronic circuit board such as a PC motherboard. Among them, for those with a limited mounting area, such as a notebook PC, and those with a fixed memory capacity for embedded devices, the SDRAM is mounted directly on the through-substrate, that is, it has a plurality of SDRAMs on board. May implement main memory.

  However, depending on the platform used, there is a case where only the DIMM is supported and the on-board design specification is not disclosed. At that time, it is common to perform on-board design in accordance with the specifications of the JEDEC Semiconductor Technology Association, but this specification defines the design specifications (wiring length, pattern drawing, etc.) of the DIMM itself. In many cases, it is difficult to directly adopt the JEDEC specification due to the limitation of the through-hole substrate to be mounted, which makes designing difficult.

  In addition, not only when the main memory is mounted on-board, even when a DIMM board on which a plurality of SDRAMs are mounted on one side is an electronic circuit board mounted via a socket, a stub for the SDRAM is used. It is difficult to design a short length and high SDRAM installation density, and therefore signal quality is never good.

  Further, such a problem with respect to a single-sided substrate on which a plurality of SDRAMs are mounted is not limited to the technique described in Non-Patent Document 1, and may occur similarly in the techniques described in Patent Documents 1 to 4. In fact, in these techniques, in a module configured as a single-sided board, one clock signal is input to a single DIMM. Therefore, since the clock signal is used for all SDRAMs in the DIMM, the load is increased and the signal quality is deteriorated. Further, when connecting to all SDRAMs, the wiring of the clock signal line is adjusted as close as possible to the shortest distance. Although it is necessary, such adjustment is difficult, and even if the distance is shortest, the distance of the stub is often increased. In addition, if the stub distance becomes long, the signal quality also deteriorates.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce design difficulty and improve signal quality in an electronic circuit board including a memory having a plurality of SDRAMs. There is.

  In order to solve the above problems, a first technical means of the present invention is an electronic circuit including a memory having N (N is an integer of 3 or more) SDRAM on one side and a memory controller for controlling the memory. The N SDRAMs are wired in a Fly-by structure so that a differential clock signal of L (L is an integer of 2 or more smaller than N) system is input to the N SDRAMs. The memory controller controls the N SDRAMs using the L-system differential clock signals based on the delay amounts of the N SDRAMs determined by a write leveling method. Is.

  According to a second technical means of the present invention, in the first technical means, K is defined as a set of one or more integers smaller than L, and the (LK) th to the (LK) th differential clock input terminal. The (LK) th SDRAM group wired to input the differential clock signal of the system, and the (LK + 1) th differential clock from the (LK + 1) th differential clock input terminal. The (L−K + 1) th SDRAM group wired to input signals is the longest from the (L−K) th differential clock input terminal in the (L−K) th SDRAM group. From the (L−K + 1) th SDRAM group through the SDRAM having the wiring length to the SDRAM having the shortest wiring length from the (L−K + 1) th differential clock input terminal to the SDRAM having the shortest wiring length. Temporary when wired to The wiring length, in which is characterized in that a, the wiring length to the first (L-K + 1) -th SDRAM with the shortest wiring length from the differential clock input terminals the same length.

  According to a third technical means of the present invention, in the first or second technical means, L is a divisor of N, and each of the L differential clock signals is provided for each of N / L SDRAM groups. It is characterized by being wired to input.

  According to a fourth technical means of the present invention, in any one of the first to third technical means, the N SDRAMs are directly mounted on one side of the electronic circuit board. is there.

  According to a fifth technical means of the present invention, in any one of the first to third technical means, the N SDRAMs are mounted on one side of a substrate mounted on the electronic circuit board via a socket. It is characterized by being.

  According to a sixth technical means of the present invention, in any one of the first to fifth technical means, the SDRAM is a DDR3 SDRAM.

  According to the present invention, it is possible to reduce design difficulty and improve signal quality by using a plurality of clocks in an electronic circuit board having a memory having a plurality of SDRAMs.

It is the schematic which shows the electronic circuit board which changed the DIMM of Type B of a nonpatent literature 1 so that all eight SDRAM might be mounted on one side. It is the schematic which shows the electronic circuit board which changed the DIMM of Type D of a nonpatent literature 1 so that all eight SDRAM might be mounted on one side. It is a figure which shows the example of the electronic circuit board which mounted all eight SDRAM on board | substrate on one side. It is a figure which shows the detailed wiring example of the memory in FIG. It is an example of the electronic circuit board which concerns on this invention, Comprising: It is a figure which shows an example of the electronic circuit board which mounted all eight SDRAM on board | substrate on one side. It is a figure which shows the detailed wiring example of the memory in FIG. It is a figure which shows the example of arrangement | positioning of CPU, memory, and a memory controller in the electronic circuit board of FIG.

  The electronic circuit board according to the present invention is a board that can be mounted on various electronic devices such as a PC and an image forming apparatus. A configuration in which eight SDRAMs are mounted on one side of the electronic circuit board according to the present invention will be described.

  First, since an electronic circuit board on which one of these eight SDRAMs is mounted is not described in Non-Patent Document 1, Type 8 in which eight SDRAM chips described in Non-Patent Document 1 are mounted on both surfaces. A case where the electronic circuit board is configured by changing the design so that B and Type D are mounted on one side will be described with reference to FIGS.

  FIG. 1 is a schematic diagram showing an electronic circuit board in which the Type B DIMM described in Non-Patent Document 1 is modified so that all eight SDRAMs are mounted on one side. FIG. 2 is a schematic view showing an electronic circuit board in which the Type D DIMM described in 1 is changed so that all eight SDRAMs are mounted on one side on board. FIG.

  As shown in FIG. 1, when a Type B DIMM of both ranks and mounted on both sides is mounted on the electronic circuit board 100, a memory 102 composed of eight SDRAMs (M0 to M7) is mounted on one side, A memory controller 101 for controlling the memory 102 is mounted on the same surface. In this electronic circuit board 100, in order to adopt the Fly-by structure, the wiring between the original SDRAMs is mounted on one side so as to expand, but the differential clock signal CLK0 is the same as Type B. These signal lines are made into one system, and the signal lines are passed through the centers of the eight SDRAMs (M0 to M7).

  However, for example, as indicated by reference numeral 103, the distance of the branch portion (stub) from the branch point of the main signal line to the pin of each SDRAM becomes too long, and the wiring length specification defined on the memory controller 101 side is In addition, the signal quality deteriorates. Since Type B itself is a double-sided mounting, the distance of the stub from the branch point can be about the same as the thickness of the substrate, so that the length of the stub does not become a problem.

  In addition, as shown in FIG. 2, when a Type D DIMM of two ranks and mounted on both sides is mounted on the electronic circuit board 110 on-board, the memory 112 composed of eight SDRAMs (M0 to M7) is provided as in FIG. Is mounted on one side, and a memory controller 111 for controlling the memory 112 is mounted on the same side. In this electronic circuit board 110, in order to adopt the Fly-by structure, the wiring between the original SDRAMs is mounted on one side so as to expand, but as with Type D, the differential clock signal The signal lines are simply made into two systems (CLK0 and CLK1), and the signal lines are provided at positions close to the four SDRAMs (M0 to M3) and the four SDRAMs (M4 to M7) (however, In FIG. 2, the signal line passes through the center of the SDRAM).

  However, command / control signals (CMD / CTL signals) that need to be wired with the same length as CLK0 and CLK1 are between four SDRAMs (M0 to M3) and four SDRAMs (M4 to M7). It is necessary to pass through the middle. Therefore, for example, as indicated by reference numeral 113, the distance of the stub from the branch point of the main signal line of the command / control signal CMD / CTL to the pin of each SDRAM becomes too long, and is defined on the memory controller 111 side. In addition to satisfying the wiring length specification, signal quality deteriorates. Since Type D itself is a double-sided mounting, the distance of the stub from the branch point can be about the same as the thickness of the substrate, so that the length of the stub does not become a problem.

  Next, another wiring example will be described with reference to FIGS. FIG. 3 is a diagram showing an example of an electronic circuit board on which all eight SDRAMs are mounted on one side, and FIG. 4 is a diagram showing a detailed wiring example of the memory in FIG.

  The electronic circuit board 120 shown in FIG. 3 has a structure in which eight SDRAMs (chips) are connected in order by one rank and one side mounting with reference to Type F wiring of two ranks, double side mounting and a total of 16 chips. Yes. The memory 122 is mounted on the electronic circuit board 120 on board and can be said to be a virtual SO-DIMM.

  The memory controller 121 is a controller that controls the memory 122 and is mounted on the same surface as the memory 122. Further, from the memory controller 121, the signal line of the clock signal CLK0 and the signal line of the command / control system signal CMD / CTL are eight chips M3, M0, M1, M2, M4, M6, M7, M5. Wiring is performed in a Fly-by structure so as to be connected in this order. In addition, although not shown, the data line is also connected from the memory controller 11 to each of the eight chips M0 to M7 in the memory 122. Such a wiring (Fly-by wiring) is a wiring used as a waveform quality improvement technique, and is also a feature of the wiring of DDR3. Due to the specifications described in Non-Patent Document 1, CS (chip select) is used. For one system, the clock signal is also wired / controlled by one system.

  Details of the signal lines of the clock signal in the memory 122 will be described with reference to FIG. The memory 122 has input terminals 123a and 123b for inputting differential clock signals CK3 and CK3 # as clock signals. In the signal lines connected to the input terminals 123a and 123b, eight chips are wired in a Fly-by structure in the order of M3, M0, M1, M2, M4, M6, M7, and M5.

  Further, a capacitor 126 is provided between the signal lines near the input terminals 123a and 123b, and resistors 127a and 127b and a capacitor 128 are provided at the end of the signal line to maintain the potential difference between the clock signal CK3 and the clock signal CK3 #. ing. The resistors 127 a and 127 b are resistors that are generated when the signal lines are arranged in the middle layer of the substrate layer of the electronic circuit board 120 and are output from the middle layer to the surface layer in order to connect the signal lines to the capacitor 128. In FIG. 4, a portion corresponding to a stub from two signal lines to each SDRAM chip is emphasized, and in such a wiring method, wiring is performed so that the stub becomes extremely short. Is possible.

  Next, a wiring example of the electronic circuit board according to the present invention will be described with reference to FIGS. FIG. 5 is a diagram showing an example of an electronic circuit board according to the present invention, in which all eight SDRAMs are mounted on one side on board. FIG. 6 is a diagram showing a detailed wiring example of the memory in FIG.

  The electronic circuit board 10 according to the present invention includes a memory 12 having N SDRAMs and a memory controller 11. Here, N is an integer of 3 or more, and is generally 4 or more. 5 and FIG. 6, the memory 12 includes eight SDRAMs (SDRAM chips M0 to M7).

  Furthermore, the electronic circuit board 10 according to the present invention wires the N SDRAMs in a Fly-by structure so that L differential clock signals are input to the N SDRAMs. That is, N SDRAMs are connected in a daisy chain and wired. Here, L is an integer of 2 or more smaller than N, and in the example of FIG. 6, two types of differential clock signals of differential clock signals CK3 and CK3 # and differential clock signals CK4 and CK4 # are input. Wired.

  The memory controller 11 is a controller for controlling the memory 12, and based on the respective delay amounts of the N SDRAMs determined by the write leveling method, the N SDRAMs are converted using the L differential clock signals. Control. The differential clock signals CK and CK # are signals for determining a timing that serves as a reference for the operation of the DDR3 SDRAM. Each SDRAM uses a command or address based on the intersection of the rising edge of CK and the falling edge of CK #. (Read / Write) is received and data is input / output based on the intersection of CK and CK #. At this time, the command / control signal may be shifted based on the determined delay amount. The delay amount may be determined every time power is supplied.

  The description will be made on the assumption that the SDRAM is a DDR3 SDRAM. However, the present invention is not limited to this. N SDRAMs are wired in a Fly-by structure, and each of the N SDRAMs determined by the write leveling method is used. Any device that can control N SDRAMs using L differential clock signals based on the delay amount may be used. For example, a DDR4 SDRAM for which a standard is currently being formulated can be applied if it is standardized so that such control is possible.

  The configuration of the electronic circuit board 10 will be described with further reference to FIG. The electronic circuit board 10 shown in FIG. 5 has a configuration in which eight SDRAMs (SDRAM chips) are sequentially connected to the memory 12 in one rank and single-sided mounting, like the wiring of the electronic circuit board 120 shown in FIG. The memory 12 is mounted on the electronic circuit board 10 on board and can be said to be a virtual SO-DIMM. Thus, the SDRAM is preferably mounted directly on one side of the electronic circuit board 10. The storage capacity of the SDRAM includes 2 Gbit, 4 Gbit, and the like, but is not limited to this.

  The memory controller 11 is mounted on the same surface as the memory 12. Further, the signal line of the command / control system signal CMD / CTL is connected from the memory controller 11 so that the eight chips are connected in the order of the chips M3, M0, M1, M2, M4, M6, M7, and M5. It is wired with a -by structure. Although not shown, the memory controller 11 is also connected to data lines for each of the eight chips M0 to M7 in the memory 12. About the structure so far, the electronic circuit board 10 and the electronic circuit board 120 are the same.

  However, the electronic circuit board 10 is different from the electronic circuit board 120 in the wiring method of signal lines for clock signals. More specifically, from the memory controller 11, the signal line of the clock signal CLK0 is wired in a Fly-by structure so that four chips are connected in the order of chips M3, M0, M1, and M2. Further, the signal line of the clock signal CLK1 is wired from the memory controller 11 in a Fly-by structure so that the remaining four chips are connected in the order of chips M4, M6, M7, and M5.

  Also in the present invention, the Fly-by structure employed in the signal line of the clock signal and the signal line of the command / control system specifically realizes the shortest distance wiring by connecting the chips with a daisy chain, It is intended to improve quality.

  However, if the signal timing is shifted as it is, this problem is caused by adjusting the output timing by determining the delay amount of the command / control system signal etc. with respect to the clock signal by a method called “write leveling”. Has solved. As described above, the electronic circuit board 10 adopts the Fly-by wiring, which is a feature of the wiring of the DDR3, as in the electronic circuit board 120, but the CS has two clock signals wired to one system, The CS1 system is controlled.

  With regard to this control, SPD (Serial Presence Detect) data indicating various information such as the operation timing of each SDRAM is embedded in the BIOS (Basic Input / Output System) of the memory 12, and the memory controller 11 stores it from the BIOS at startup. If it is configured to be expanded, the operation of each SDRAM can be controlled. The SPD data may be stored in an EEPROM (Electrically Erasable Programmable Read-Only Memory) in the memory controller 11 and read from there. In that case, it becomes possible to select an operation timing etc. by the configuration setting by user operation.

  Details of the signal lines of the clock signal in the memory 12 will be described with reference to FIG. The memory 12 has input terminals 13a and 13b for inputting differential clock signals CK3 and CK3 # as clock signals. And as for the signal line connected to those input terminals 13a and 13b, four chips are wired by the Fly-by structure in order of chip M3, M0, M1, and M2. Further, a capacitor 15 is provided between the signal lines near the input terminals 13a and 13b, and resistors 17a and 17b and a capacitor 18 are provided at the ends of the signal lines to maintain the potential difference between the clock signal CK3 and the clock signal CK3 #. ing.

  Further, the memory 12 has input terminals 14a and 14b for inputting differential clock signals CK4 and CK4 # as clock signals. And the signal line connected to those input terminals 14a and 14b has four chips wired in a Fly-by structure in the order of chips M4, M6, M7 and M5. In addition, a capacitor 16 is provided between the signal lines near the input terminals 14a and 14b, and resistors 19a and 19b and a capacitor 20 are provided at the ends of the signal lines to maintain the potential difference between the clock signal CK4 and the clock signal CK4 #. ing.

  The resistors 17a and 17b are resistors that are generated when a signal line is arranged in the middle layer of the substrate layer of the electronic circuit board 10 and is output from the middle layer to the surface layer in order to connect the signal line to the capacitor 18. , 19b are resistances generated when the signal lines are connected to the capacitor 20 from the middle layer to the surface layer. However, in the present invention, the signal lines of the clock signal and other signals are not necessarily arranged in the middle layer (that is, in the substrate layer), and may be arranged in the surface layer.

  Also, in FIG. 6, as in FIG. 4, the portion corresponding to the stub from the four signal lines to each SDRAM chip is highlighted, but such a wiring method makes the stub extremely short. It is possible to wire and improve the signal quality.

  As described above, the electronic circuit board 10 shown in FIG. 5 separates the clock signal from the electronic circuit board 120 shown in FIG. As a result, the load of the clock signal is reduced from 8 chips to 4 chips, the signal quality is improved, and the adjustment of the wiring length of the signal line of the clock signal is facilitated (the difficulty level is reduced). As described above, according to the electronic circuit board 10, it is possible to reduce the difficulty of on-board design and improve the signal quality by using a plurality of clocks.

  Here, the memory controller 11 may be configured such that the same data can be read from and written to the chips M0 to M7 with the same command / control signal and data signal as the memory controller 121 in the electronic circuit board 120 of FIG. preferable.

  For this purpose, wiring of clock signal signal lines up to the first chip of the clock signal CLK1 (differential clock signals CK4, CK4 #) (fifth chip when viewed from the command / control signal system which is another signal system) is performed. The length needs to be equal to the wiring length when wiring up to the fifth chip with the clock signal CLK0 (differential clock signals CK3, CK3 #).

  Referring to FIG. 6, the first SDRAM group (chips M0 to M3) wired to input the first system differential clock signals CK3 and CK3 # from the first differential clock input terminals 13a and 13b. And the second SDRAM group (chips M4 to M7) wired to input the second differential clock signals CK4 and CK4 # from the second differential clock input terminals 14a and 14b. Set length restrictions.

  This restriction refers to the second through the SDRAM (chip M2) having the longest wiring length from the first differential clock input terminals 13a and 13b in the first SDRAM group (chips M0 to M3). Virtual wiring length when virtually wired from the second differential clock input terminals 14a and 14b of the SDRAM group (chips M4 to M7) to the SDRAM (chip M4) having the shortest wiring length (that is, TL0A + TL0B + TL1 + TL3 + TL4 + TL5 + TL6 + "wiring portion connecting the rear end of TL6 and the tip of TL9 with a straight line" + TL9 + TL2-9 length) and the wiring length from the second differential clock input terminals 14a and 14b to the chip M4 ( That is, the length of TL8A + TL8B + TL9 + TL2-9) is set to the same length. In FIG. 6, it does not seem to have the same length for simplification, but the wiring portion TL8B may be made the same length by zigzag, for example. The virtual wiring length is the wiring length when the differential clock signal is virtually wired, and will be described by actual wiring for the command / control signal and the data signal. The first SDRAM group from the input terminal This corresponds to the length of wiring from the chips M0 to M3 to the SDRAM (chip M4).

  As described above, as an electronic circuit board according to the present invention, eight SDRAMs (SDRAM chips) are mounted on-board, and different systems of differential clock signals (total of two systems of differentials) are provided for each of the four chips. An example in which eight chips are wired in a Fly-by structure so as to input a clock signal) is given.

  However, the present invention is not limited to this example, and can be configured as follows by applying the same idea as this example. That is, the electronic circuit board inputs the (LK) system differential clock signal from the (LK) th differential clock input terminal, where K is a set of one or more integers smaller than L. The (LK) th SDRAM group wired to the (L−K + 1) th differential clock signal is input from the (L−K + 1) th differential clock input terminal. For the (L−K + 1) th SDRAM group, a limitation on the wiring length is provided.

  This restriction refers to the SDRAM having the longest wiring length from the (LK) th differential clock input terminal in the (LK) th SDRAM group (the SDRAM having the longest wiring length, hereinafter referred to as the terminal). SDRAM having the shortest wiring length from the (L−K + 1) th differential clock input terminal of the (L−K + 1) th SDRAM group via the SDRAM) (SDRAM having the shortest wiring length; The virtual wiring length when virtually wired until the leading SDRAM is made the same as the wiring length from the (L−K + 1) th differential clock input terminal to the leading SDRAM. And so on.

  Here, N is not limited to 8, but may be 3 or more. Further, the example of FIG. 6 is an example when L = 2 and K = {1}. Although not shown, the same applies to the restrictions when L = 4 (that is, four clocks) and K = {1, 2, 3}. In this case, three adjacent SDRAM groups are also connected. The wiring may be performed so as to have the same wiring length as the virtual wiring length.

  In other words, the (L−K + 1) th differential clock input terminal is wired so as to input the (L−K + 1) th differential clock signal to the SDRAM at the leading end. So that the delay of the differential clock signal matches the data delay in the conventional DIMM (for example, the data delay in the electronic circuit board 120 in FIG. 3 is also the same). This facilitates control on the memory controller side.

  Further, as illustrated in FIG. 6, it is preferable that each of the L-system differential clock signals is wired so as to be input every N / L SDRAM groups. However, L is a divisor of N. As described above, the number of SDRAM groups is preferably the same, but the wiring length can be determined based on the same concept even if the number is not the same. For example, the memory may be configured such that N = 12, the first SDRAM group is composed of 4 chips, the second SDRAM group is composed of 6 chips, and the third SDRAM group is also composed of 6 chips.

  Next, referring to FIG. 7, an arrangement example of each component on the electronic circuit board will be given. 7 is a diagram illustrating an arrangement example of a CPU (Central Processing Unit), a memory, and a memory controller in the electronic circuit board of FIG.

  As shown in FIG. 7, in the electronic circuit board 10, the memory 12 and the memory controller 11 are mounted together with a processor such as a CPU 21. In this arrangement, the memory controller 11 is controlled by the CPU 21, and the memory controller 11 12 are controlled, it is preferable to arrange them in that order in order to shorten the wiring length. When the conventional electronic circuit board is configured in such an arrangement, it is only necessary to mount the memory 12 used in the present invention at the position where the memory is arranged.

  The above description is based on the assumption that N SDRAMs are directly mounted on one side of the electronic circuit board, that is, N SDRAMs are mounted on the board (of course, mounted on one side). The N SDRAMs may be mounted on one side of a substrate mounted on the electronic circuit board via a socket. This board corresponds to a single-sided mounting DIMM, and the DIMM and a memory controller for controlling the DIMM are provided on the electronic circuit board. Even when such a mounting method is adopted, it is possible to reduce the design difficulty and improve the signal quality by using a plurality of clocks.

DESCRIPTION OF SYMBOLS 10 ... Electronic circuit board, 11 ... Memory controller, 12 ... Memory, 13a, 13b, 14a, 14b ... Differential clock input terminal (input terminal), 15, 16, 18, 20 ... Capacitor, 17a, 17b, 19a, 19b ... resistance, 21 ... CPU.

Claims (6)

An electronic circuit board comprising a memory having N (N is an integer of 3 or more) SDRAM on one side, and a memory controller for controlling the memory,
The N SDRAMs are wired in a Fly-by structure so that L (L is an integer of 2 or more smaller than N) system differential clock signals are input to the N SDRAMs.
The memory controller controls the N SDRAMs using the L-system differential clock signals based on delay amounts of the N SDRAMs determined by a write leveling method. Circuit board. Assuming that K is a set of one or more integers smaller than L, the (L−K) -th differential clock signal is input from the (L−K) -th differential clock input terminal. The (L−K + 1) th SDRAM group wired to input the (L−K + 1) th differential clock signal from the (K) th SDRAM group and the (L−K + 1) th differential clock input terminal. About the group
The (L−K + 1) th SDRAM group via the SDRAM having the longest wiring length from the (L−K) th differential clock input terminal in the (L−K) th SDRAM group. Virtual wiring length when virtually wired from the (L−K + 1) th differential clock input terminal to the SDRAM having the shortest wiring length, and the (L−K + 1) th differential clock 2. The electronic circuit board according to claim 1, wherein a wiring length from the clock input terminal to the SDRAM having the shortest wiring length is the same. L is a divisor of N;
The electronic circuit board according to claim 1, wherein each of the L-system differential clock signals is wired so as to be input to each of N / L SDRAM groups.   The electronic circuit board according to claim 1, wherein the N SDRAMs are directly mounted on one surface of the electronic circuit board.   The electronic circuit board according to claim 1, wherein the N SDRAMs are mounted on one side of a board mounted on the electronic circuit board via a socket.   The electronic circuit board according to claim 1, wherein the SDRAM is a DDR3 SDRAM.

Images