JP2013118495A - A/d conversion circuit, a/d conversion method and a/d conversion program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog/digital (A/D) conversion circuit that prevents interference of noise having a high frequency component while suppressing an increase in circuit scale.SOLUTION: The A/D conversion circuit for converting an input analog signal to a digital signal comprises: sample-and-hold means for sampling a voltage value of the analog signal n times (n is an integer of two or greater) at predetermined time intervals and holding such voltage values; converted input signal generation means for generating a converted input signal on the basis of the n voltage values thus held; and A/D conversion means for generating the digital value on the basis of the converted input signal.

Description

  The present invention relates to a conversion circuit that is mounted on an electronic device and converts an analog signal into a digital signal, and in particular, analog digital (A / D) that prevents interference of noise having a high frequency component and suppresses an increase in circuit scale. ) A conversion circuit, an A / D conversion method, and an A / D conversion program.

  The electronic device mounted on the guided flying body needs to be designed in consideration of the condition of mounting space restrictions. In an electronic device intended to be mounted on a guided flying object, it is difficult to completely isolate an analog signal system in an electronic circuit in which analog signal processing and digital signal processing are mixed. Therefore, in the A / D conversion in such an electronic circuit, the electronic circuit is designed on the assumption that an analog signal on which the operation noise of the digital circuit having a high frequency component is superimposed is A / D converted. .

  A noise component having a frequency equal to or higher than the frequency of the A / D conversion rate, including the vicinity of the A / D conversion rate, interferes with the signal component as aliasing noise that cannot be removed in the converted digital signal. For an analog signal before A / D conversion, an anti-aliasing filter that removes this noise frequency component is required.

  However, in many cases, an arrangement of an anti-aliasing filter effective for removing aliasing noise requires a high-order LC circuit or an active filter circuit that requires a large mounting space. In addition, since there is a high possibility that noise directly enters the filter circuit, such a filter is often not introduced. When the filter circuit is not introduced, there is a problem that the digital signal obtained by converting from the analog signal has a non-removable variation, which limits the operation stability of the apparatus.

  In order to deal with such a problem, Patent Document 1 discloses that an A / D conversion circuit having a sufficiently large conversion rate with respect to a signal band is provided so that aliasing noise can be removed by a low order filter circuit such as a simple CR circuit. A method is disclosed in which the sampling frequency is sufficiently increased and filtering is performed on the converted digital signal to remove noise components.

  The configuration of the A / D conversion circuit described in Patent Document 1 is shown in FIGS.

  In FIG. 13, it is assumed that the anti-aliasing filter 1301 has a characteristic that sufficiently attenuates the sampling frequency fck with respect to the analog input signal V1. This prevents interference in which an unnecessary signal or noise having a frequency component that is an integral multiple of fck in the A / D conversion digital value ADQ of the A / D conversion unit 1303 returns to the signal band. This interference cannot be removed by the digital filter 1304.

  The sampling hold circuit 1302 samples the analog signal FQ at the sampling frequency fck, and holds the sampled FQ at a constant value while the A / D conversion unit 1303 performs A / D conversion on the analog signal, and outputs a sampling hold. Output as signal SQ.

  The A / D conversion unit 1303 converts the sampling hold output signal SQ and outputs it as an A / D conversion digital value ADQ.

  The digital filter 1304 removes frequency components other than the signal band included in the A / D conversion digital value ADQ, and outputs it as a digital signal output DGQ.

  The control circuit 1305 sets the sampling frequency of the sampling hold circuit 1302 and the processing parameter of the digital filter 1304.

  FIG. 14 shows the frequency characteristics of each part shown in FIG. 13 when the value of the sampling frequency of the digital filter 1304 is set to the same value as the sampling frequency fck of the sampling hold circuit 1302.

  In FIG. 14, the frequency characteristic of the anti-aliasing filter 1301 shown in FIG.

  A frequency characteristic of the fundamental wave component with respect to the input signal of the sampling hold circuit 1302 shown in FIG. 13 is indicated by 1403 in FIG. In addition, a generation characteristic of aliasing noise generated in the sampling hold circuit in a band equal to or lower than the frequency of 1/2 of fck is indicated by 1402 in FIG. In FIG. 14, the aliasing noise is replaced with the level on the sampling hold circuit input side. The frequency response of the digital filter 1304 shown in FIG. 13 is indicated by 1404 in FIG.

  As shown in FIG. 14, in the related art, the degree of interference of the aliasing noise component near the region where the frequency value is zero to the input signal band is determined by the fck of the anti-aliasing filter frequency characteristic 1401. It corresponds to the attenuation near the integer multiple point. In addition, this noise component is folded into the frequency band of the input signal and cannot be removed by the digital filter 1304.

  As described above, in the A / D conversion circuit in the related art, if a sufficiently large A / D conversion rate is set for the signal band and the sampling frequency can be sufficiently increased, the anti-aliasing filter is used. 1301 can increase the attenuation with respect to aliasing noise even with a low-order CR filter or the like.

  Therefore, if a sufficiently large A / D conversion rate can be set for the upper limit frequency of the signal band, a CR filter with a small circuit scale can be used, which causes a problem in mounting design. Absent.

  In Patent Document 2, the received signal is binarized, the binarized received signal is oversampled and processed by a digital filter, and the processed output is re-binarized, resulting in received serial data. A signal processing apparatus that performs equalization processing to reduce intersymbol interference is disclosed.

  Patent Document 3 generates a multi-phase clock with a clock having one frequency among clocks generated from a reference clock, and receives serial data converted from parallel data based on the clock generated with the reference clock. A data transmitting / receiving apparatus is disclosed in which sampling data is obtained by oversampling with this multiphase clock, and serial data is restored from bits extracted on average from the obtained sampling data in units of the multiphase clock.

  In Patent Document 4, a serial signal having a frequency different from a certain frequency is sampled by a multi-phase clock formed by shifting a clock having a certain frequency by a predetermined phase, and a reception signal superimposed on the serial signal is received. A data recovery method for restoring data is disclosed.

  Patent Document 5 discloses an amplifier circuit that performs input signal filtering as a continuous-time filter. The amplifier circuit includes a plurality of amplifiers, and a continuous-time filter is realized by passive elements and active elements included in the amplifiers, thereby preventing aliasing noise.

Japanese Patent No. 4470996 JP 2005-269261 A JP 2006-109082 A JP 2006-166229 A JP 2009-200809 A

  However, as the capacity of the electronic device mounted on the flying vehicle increases, the signal becomes wider, and the upper limit of the signal frequency band is governed by the upper limit value of the I / O data capture rate of the CPU due to an increase in the processing load of the CPU. The upper limit of the sampling rate of A / D conversion is often approached, and it has become difficult to ensure a sufficient ratio of the sampling rate to the signal band upper limit frequency.

  Further, in the electronic apparatus for mounting a guided flying object, in most cases, digital circuits of other circuit portions are mixed, and these operation noises are mixed in an analog signal transmission line for A / D conversion. These noises become aliasing noises that cannot be removed by the digital filter 1304 and cause variations in A / D conversion values. For this reason, the stability of the apparatus may not be ensured.

  In such a case, the A / D conversion circuit in Patent Document 1 requires that the anti-aliasing filter 1301 have a cutoff point at a position lower than the value of the sampling rate of A / D conversion. Further, it is necessary to provide the anti-aliasing filter with a low-pass filter characteristic having a steep cutoff characteristic by a high-order LC circuit or an active filter circuit so that the signal can pass therethrough. For this reason, the mounting scale of this portion is increased, and a large number of adjustment parts for obtaining the required filter characteristics are required. As a result, this is a great hindrance to the purpose of downsizing the device required for the electronic device mounted on the guide flying object. In addition, the manufacturing cost of the apparatus has been increased.

  The signal processing devices disclosed in Patent Literature 2, Patent Literature 3 and Patent Literature 4 are configured to suppress regular fluctuations in data transition time that occur when serial data is transmitted and transmitted on a transmission line. It does not support wide-area noise contamination.

  The amplifier circuit disclosed in Patent Document 5 is configured to perform offset adjustment according to the DC offset of the input signal and gain adjustment according to the amplitude, and to set a cutoff frequency in the filter. The amplifier circuit does not handle wide-range noise.

  An object of the present invention is to eliminate an anti-aliasing filter using an LC circuit or an active filter circuit whose mounting scale is large, and to suppress an increase in circuit mounting scale and adjustment parts, and an A / D conversion method And providing an A / D conversion program.

  In order to achieve the above object, an A / D conversion circuit according to the present invention is an analog-digital (A / D) conversion circuit that converts an input analog signal into a digital signal, and the voltage value of the analog signal is set to a predetermined value. Sampling hold means for sampling n times (n is an integer of 2 or more) every time and holding a voltage value; and conversion input signal generating means for generating a conversion input signal based on the held n voltage values; A / D conversion means for generating a digital signal based on the converted input signal.

  The A / D conversion method of the present invention is an analog-to-digital (A / D) conversion method for converting an input analog signal into a digital signal, and the voltage value of the analog signal is changed n times every predetermined time ( n is an integer greater than or equal to 2) collecting and holding a voltage value, generating a converted input signal based on the n held voltage values, and generating a digital signal based on the converted input signal And the step of performing.

  Furthermore, the A / D conversion program of the present invention is an analog-to-digital (A / D) conversion program for converting an input analog signal into a digital signal, and the voltage value of the analog signal is changed n times every predetermined time ( n is an integer greater than or equal to 2) Processing to collect and hold a voltage value, processing to generate a conversion input signal based on the n held voltage values, and to generate a digital signal based on the conversion input signal And processing to be executed by a computer.

  According to the present invention, the means necessary for the filter processing before A / D conversion includes the means for sampling and holding, and the means for adding by multiplying by the weighting factor. This eliminates the need for a capacitor or coil that is included in a normal analog filter circuit and increases the mounting scale. In particular, in an amplifier circuit including a high-order anti-aliasing filter that requires a large number of these elements, the integration can be significantly improved as compared with the related art.

1 shows an example of a configuration of an A / D conversion circuit according to a first embodiment of the present invention. 1 shows an exemplary configuration of a timing control circuit according to a first embodiment of the present invention. 3 is a timing chart showing an example of the operation of the A / D conversion circuit according to the first embodiment of the present invention. 3 is a timing chart showing an example of the operation of the A / D conversion circuit according to the first embodiment of the present invention. 1 shows an example of a configuration of a resistor network according to a first embodiment of the present invention. 1 shows a configuration of an equivalent circuit of a resistor network according to a first embodiment of the present invention. 2 shows an example of a signal processing flow in the A / D conversion circuit according to the first embodiment of the present invention. 3 shows characteristics of the amplitude frequency response of a signal processed by the A / D conversion circuit according to the first embodiment of the present invention. The characteristic of the amplitude frequency response of the signal processed by the A / D conversion circuit concerning the 2nd example of the present invention is shown. The characteristic of the amplitude frequency response of the signal processed by the A / D conversion circuit concerning the 2nd example of the present invention is shown. An example of the signal input to the A / D conversion circuit according to the second embodiment of the present invention is shown. An example of the signal processed and output by the A / D conversion circuit which concerns on 2nd Example of this invention is shown. 1 shows a configuration of an A / D conversion circuit according to related technology. An example of the frequency characteristic of the signal in each part which comprises the A / D conversion circuit which concerns on related technology is shown. 2 shows an example of the configuration of an A / D conversion circuit according to a second embodiment of the present invention.

  An embodiment of the present invention will be described with reference to the drawings. However, the present invention is not limited to the embodiments shown below.

(First embodiment)
(Constitution)
(Configuration of A / D conversion circuit)
FIG. 1 shows an example of the configuration of functional blocks of an A / D conversion circuit according to the first embodiment of the present invention.

  In FIG. 1, the A / D conversion circuit includes a pre-filter 1, a sampling hold filter unit 2, a scaling circuit 3, and an A / D conversion unit 4.

  The A / D converter circuit further includes an analog signal input terminal A1 for inputting an analog signal from the outside, a clock signal terminal C1 for inputting a reference time signal for circuit operation, and after converting the analog signal to a digital value, Including a digital signal output terminal D1.

  The prefilter 1 has an analog signal input terminal A1. A sampling hold filter unit 2 is connected to the pre-filter unit 1.

  The sampling and holding filter unit 2 has a clock signal terminal C 1, and a scaling circuit 3 is connected to the sampling and holding filter unit 2.

  An A / D conversion unit 4 is connected to the sampling hold filter unit 2 and the scaling circuit 3 and has a digital signal output terminal D1.

  The sampling hold filter unit 2 includes sampling hold circuits 21, 22, 23, a timing control circuit 24, and a resistor network 25.

  The sampling hold circuit 21 has input terminals for a plurality of channels, and the output terminal of the pre-filter 1 is connected to all of the plurality of input terminals of the sampling hold circuit 21. The output terminal of the sampling hold circuit 21 is connected to the sampling hold circuits 22 and 23. In addition, each of the sampling hold circuits 21 to 23 receives a control signal from the timing control circuit 24, and the operation timing is controlled. The timing control circuit 24 includes a clock signal terminal C1. The output end of the sampling hold circuit 22 is connected to the sampling hold circuit 23. A resistor network 25 is connected to the output terminal of the sampling hold circuit 23. The output end of the resistor network 25 is connected to the scaling circuit 3.

  The A / D converter 4 receives a control signal from the timing control circuit 24 of the sampling hold circuit 2 and controls the operation timing. Further, the A / D converter 4 includes a digital signal output terminal D1.

  Next, the signal flow and the operation of each component in the A / D conversion circuit according to this embodiment will be described below.

  The analog signal a1 is input to the prefilter 1 from the analog signal input terminal A1. The pre-filter 1 is a low-order filter, removes noise in a high frequency region included in the analog signal a1, and outputs it as an analog signal a2.

  The analog signal a2 is input to the input terminals of a plurality of channels of the sampling and holding circuit 21. The sampling hold circuit 21 is connected with n sampling pulse signal groups c2 from the timing control circuit 24 corresponding to the number of channels. The sampling and holding circuit 21 sequentially samples and holds the analog signal a2 by delaying the analog signal a2 by a sampling time interval according to the sampling pulse signal group c2. The held signals are branched from the n output terminals and output to the sampling hold circuits 22 and 23 as a sampling hold analog output group a3.

  To the sampling hold circuit 22, one sampling pulse signal c1 is connected from the timing control unit 24 in order to simultaneously sample the n sampling hold analog output groups a3 from the sampling hold circuit 21.

  The n sampling hold analog output groups a <b> 4 from the sampling hold circuit 22 are connected to the input terminal of the sampling hold circuit 23. The sampling hold circuit 23 receives one sampling pulse signal c3 from the timing control unit 24 for simultaneously sampling the n sampling hold analog output groups a3 and the n sampling hold analog output groups a4. The

  When the sampling hold of the sampling hold analog output group a3 is completed for all n channels, the sampling hold analog output group a3 is sampled and held in the sampling hold circuit 22. The held signal is output to the sampling hold circuit 23 as a sampling hold analog output group a4 of n output terminals.

  When the sampling period of the next n points elapses and the sampling hold of the sampling hold analog output group a3 is completed for all n channels, the sampling hold analog output group is combined with the preceding n point sampling output. a3 and the sampling hold analog output group a4 are input to the sampling hold circuit 23, and output from the 2n output terminals as the sampling hold analog output group a5.

  The sampling hold analog signal group a5 is updated simultaneously every time the analog signal a1 is sampled n points by the sampling hold circuit 21.

  A total of 2n sampling and holding analog output groups a5 from the sampling and holding circuit 23 are connected to 2n input terminals of the resistor network 25, and each is added with a predetermined weight.

  The resistor network 25 having 2n input terminals multiplies each signal of the sampling hold analog signal group a5 by a predetermined filter addition coefficient, and outputs an analog signal a6 as a filter output.

  The addition result analog signal a <b> 6 generated by the resistor network 25 is input to the scaling circuit 3.

  An A / D converter input analog signal a 7 is output from the scaling circuit 3 and input to the A / D converter 4. When the A / D conversion clock signal c4 is input to the A / D conversion unit 4 and the A / D conversion start pulse signal c5 is input to the A / D conversion unit 4, the conversion process is started.

  The scaling circuit 3 receives the analog signal a6, adjusts it to match the analog scale of the A / D conversion input, and outputs it as an A / D conversion input analog signal a7.

  The A / D conversion unit 4 converts the A / D conversion input analog signal a7 into a discrete numerical value and outputs it as a digital signal d1.

  The digital signal d1 from the A / D converter 4 is output to the outside through the digital signal output terminal D1.

  The clock signal c6 from the clock signal terminal C1 is input to the timing control circuit 24. A sampling pulse signal c1, a sampling pulse signal group c2, a sampling pulse signal c3, an A / D conversion start pulse signal c5, and an A / D conversion clock signal c4 are output from the timing control circuit 24. These signals are connected to the sampling hold circuit 22, the sampling hold circuit 21, the sampling hold circuit 23, and the A / D conversion unit 4, respectively.

1 is an RC filter or a low-order normal low-pass filter. Further, detailed configurations of the sampling hold circuits 21, 22, 23 and the A / D conversion unit 4 are well known to those skilled in the art, and are omitted here.
(Configuration of timing control circuit)
FIG. 2 shows an example of a detailed configuration of the timing control circuit 24 shown in FIG. In the figure, the clock signal input terminal C1 is connected to the input buffer circuit 24-1. The output of the input buffer circuit 24-1 is an A / D conversion clock signal generation frequency dividing circuit 24-2, a control sequence signal generation clock frequency dividing circuit 24-3, a sampling pulse generating circuit 14-6a, and a sampling pulse generating circuit 14-. 6b.

  The output of the A / D conversion clock signal generation frequency dividing circuit 24-2 is connected to the output buffer circuit 24-7b, and the output thereof is sent to the A / D conversion unit 4 shown in FIG. 1 as the A / D conversion clock signal c4. Is output.

  The output of the control sequence signal generation clock frequency dividing circuit 24-3 is connected to the sequence counter circuit 24-4 and the control sequence generation circuit 24-5. The sequence counter value f that is the output of the sequence counter circuit 24-4 is connected to the control sequence generation circuit 24-5.

  Sequence generation circuit outputs g1 to gn, which are outputs of the control sequence generation circuit 24-5, are connected to a sampling pulse generation circuit 24-6a. The sequence generation circuit outputs j and k are connected to the sampling pulse generation circuit 24-6b. Further, the A / D conversion start signal m output from the control sequence generation circuit 24-5 is connected to the output buffer circuit 24-7b, and further, as an A / D conversion start pulse signal c5, the A / D conversion start signal m shown in FIG. Connected to the D converter 4.

The output of the sampling pulse generation circuit 14-6a is connected to the output buffer circuit 24-7a, and is further output to the sampling hold circuit 21 shown in FIG. 1 as the sampling pulse signal group c2. The output of the sampling pulse generation circuit 14-6b is connected to the output buffer circuit 24-7a, and is further output as sampling pulse signals c1 and c3 to the sampling hold circuit 22 and the sampling hold circuit 23 shown in FIG. .
(Configuration of resistance network)
FIG. 5 shows an example of a circuit configuration inside the resistor network 25 shown in FIG.

Signals having voltage values V _{1 to} V _2n are input to the resistor network 25 via 2n input terminals, respectively. Each input signal, through resistor R ₁ to R _2n, is connected to the output terminal of the resistor network 25.

This circuit has the same operation as the equivalent circuit shown in FIG.
(Operation)
Next, an example of the operation of the A / D conversion circuit shown in FIGS. 1 and 2 will be described with reference to time charts shown in FIGS. In the time chart of FIG. 4, in this embodiment, the number n of outputs of the sampling hold analog output group a3 in FIG. N in the A / D conversion circuit of the present invention is not limited to 4.

  The operation of the timing control circuit 24 in FIG. 1 will be described with reference to FIG.

  In FIG. 2, the basic clock signal p from the clock signal input terminal C1 related to the control of the operation of the A / D conversion circuit according to the present embodiment is shown in the A / D conversion clock signal generation frequency dividing circuit 24-2. 1 is divided into clock frequencies required by the A / D converter 4 and output.

  The control sequence signal generation clock frequency dividing circuit 24-3 divides the frequency to a clock frequency required by the sequence counter circuit 24-4 and the control sequence generation circuit 24-5 and outputs it as a sequence counter clock signal e.

  Based on the sequence counter clock signal e, the sequence counter circuit 24-4 obtains a sequence counter value f indicating the generation position of the sequence generation circuit outputs g1 to gn, j, k and the A / D conversion start signal m. Generate.

  The control sequence generation circuit 24-5 generates sequence generation circuit outputs g1 to gn, j, k, and an A / D conversion start signal m.

  The sampling pulse generation circuit 24-6a generates sampling pulse signals h1 to hn having a pulse width necessary for sampling hold based on the basic clock signal p, and outputs them as a sampling pulse signal group c2 through the output buffer circuit 24-7a. To do.

  The sampling pulse generation circuit 24-6b generates sampling pulse signals c1 and c3 having a pulse width necessary for the sampling hold based on the sequence generation circuit outputs j and k and the basic clock signal p, and outputs the output buffer circuit 24. Output via -7a.

  The above operation is shown in FIG. 3 as a timing chart.

  Next, the operation of the sampling hold circuits 21 to 23 will be described with reference to FIG. The output number n of the sampling hold analog output group a3 is set to 4 for simplicity.

  In FIG. 1, an analog signal a <b> 1 from the analog signal input terminal A <b> 1 is input to the prefilter 1. The prefilter 1 removes a component in the high frequency region from the analog signal a1. That is, a signal having a continuous waveform shown as output WF1 in FIG. 4 is generated. This signal is input to the sampling and holding circuit 21 as the output of the prefilter 1.

In the sampling hold circuit 21, the voltage values V ₀ , V ₄ , V ₈ , and V ₁₂ in the waveform of the output WF 1 in FIG. 4 are sequentially sampled by the sampling pulse of h 1 shown in FIG. The waveform of the channel CH1 of the output WF2 is generated based on the sampled voltage value, and the sampling value is held.

Similarly, the voltage values V ₁ , V ₅ , V ₉ and V ₁₃ are sampled by the sampling pulse of h2, and the voltage values V ₂ , V ₆ , V ₁₀ and V ₁₄ are sampled by the sampling pulse of h3, and h4 The voltage values V ₃ , V ₇ , and V ₁₁ are sampled by the sampling pulse. The sampled voltage value is held as the waveforms of the channels CH2 to CH4 of the output WF2.

Waveform channels CH1 to CH4 of these outputs WF2 is the sampling pulses c1 shown in FIG. 3, first, the voltage value _{V 0} to _{V 3} is held by the sampling hold circuit 22 of FIG. 1, the sampling pulse of the next c1 Thus, the voltage values V _{4 to} V ₇ are held. These sampling values are held at the timing indicated by the output timing TM1 in FIG.

The sampling hold circuit 23 in FIG. 1 holds the voltage values V _{0 to} V ₃ immediately before the sampling hold circuit 22 in FIG. 1 samples the voltage values V _{4 to} V ₇ by the sampling pulse c3 shown in FIG. At this timing, the voltage values V _{0 to} V ₃ of the sampling hold circuit 22 and the outputs of the voltage values V _{4 to} V ₇ that are the outputs of the channels CH 1 to CH 4 of the sampling hold circuit 21 are sampled and held. By this operation, the voltage values V _{0 to} V ₇ are simultaneously sampled, held, and output.

Similarly, as shown in the output timing TM2 of FIG. 4, the sampling pulse of the next c3, the voltage value V ₄ to V ₁₁ are sampled and outputted from the sampling hold circuit 23 of FIG. 1.

  Next, signal processing in the A / D conversion circuit according to the present embodiment will be described in detail.

  The sampling hold analog output group a5 output from the sampling hold circuit 23 is input to the resistance network 25.

When the sampling hold the analog output group a5 becomes the voltage value V ₀ to V _7, the output from the resistor network 25, an equivalent circuit of the resistor network 25 of Figure 5 shown in FIG. 6,
V _a6 = RO * (V ₀ / R ₁ + V ₁ / R ₂ +... + V ₇ / R ₈ )
It becomes. RO is the reciprocal of the sum of the reciprocals of the resistance values R _{1 to} R ₈ of the individual resistors.

At this time, the voltage value of the A / D conversion input analog signal a7, which is the output of the scaling circuit 3, is obtained by the scaling circuit 3.
V _a7 = RO (1 + R _fa / R _ia ) (V ₀ / R ₁ + V ₁ / R ₂ +... + V ₇ / R ₈ )
It becomes. here,
C _i = (1 + R _fa / R _ia ) R0 / R _{i + 1}
Then, the above V _a7 is
V _a7 = F ₀ = C ₀ V ₀ + C ₁ V ₁ +... + C ₇ V ₇
Can be rewritten.

When the sampling hold the analog output group a5 is a voltage value V ₄ to V _11, the voltage value of the A / D converting the input analog signal a7 is
V _a7 = F ₁ = C ₀ V ₄ + C ₁ V ₅ +... + C ₇ V ₁₁
It becomes. Similarly, the voltage value of the kth a7 is
V _a7 = F _k = C ₀ V _4k + C ₁ V _{1 + 4k} + ... + C ₇ V _{7 + 4k}
It is expressed as

  These are shown as the waveform of the output WF5 in FIG.

The above is a case where the output number n of the sampling hold analog output group a3 is 4.
FIG. 7 shows a process when the above discussion is generalized without limiting the value of the number n of outputs to four. That is, a2 passed through the prefilter 703 is input to a circuit in which delay elements having a delay time of the sampling interval T shown in FIG. A voltage value is taken out from each of these delay elements, each of these voltage values is multiplied by C _{0 to} C _2n−1 and weighted, and the sum is taken as the output voltage value. The result obtained by sampling and holding at the interval of nT by the sampling and holding circuit 702 shown in FIG. 7 is the same as the above sum.

Here, the frequency transfer function of the portion shown in the weighted addition unit 701 in FIG.
_{G (jω) = (C 2n} -1 + C 2n-2 e -jωT + C 2n-3 e -2jωT + ··· + C 1 e - (2n-2) jωT + C 0 e - (2n-1) jωT)
It is. Therefore, the voltage value of the A / D conversion input analog signal a7 is equivalent to the result of sampling and holding the output waveform of the pre-filter 1 that has passed through the element having this frequency transfer function at intervals of nT. It can also be considered that an acyclic filter based on analog signals is formed.

When the output number n of the sampling hold analog output group a3 is set to 4, the above equation is rewritten as follows.
_{G (jω) = (C 7} + C 6 e -jωT + C 5 e -2jωT + C 4 e -3jωT + C 3 e -4jωT + C 2 e -5jωT + C 1 e -6jωT + C 0 e -7jωT)
^{_{= E -j7ωT / 2 (C 7}} e j7ωT / 2 + C 6 e j5ωT / 2 + C 5 e j3ωT / 2 + C 4 e jωT / 2 + C 3 e -jωT / 2 + C 2 e -j3ωT / 2 + C 1 e -j5ωT ^{_{/ 2 + C 0 e -j7ωT /}} 2)
In the present embodiment, C _{0 to} C ₇ are selected as follows.

C ₃ = C ₄ = K _{0/2
C 2 = C 5 = K 1} /2
_{C 1 = C 6 = K 2} /2
_{C 3 = C 7 = K 3} /2
At this time, the above equation is expressed using a cosine function as follows.
G _(jω) = e− ^{j7ωT / 2} (K ₀ cos (ωT / 2) + K ₁ cos (ω3T / 2) + K ₂ cos (ω5T / 2) + K ₃ cos (ω7T / 2))
In the above formula, the sampling interval T of the sampling hold unit 2 shown in FIG. 1 is the reciprocal of the sampling frequency.
T = 1 / _{f s}
As
ω = 2πf
The absolute value of the above equation is
| G _(jω) | = abs (K ₀ cos (πf / f _s ) + K ₁ cos (3πf / f _s ) + K ₂ cos (5πf / f _s ) + K ₃ cos (7πf / f _s ))
It becomes.

Next, a generalized relational expression is derived for the number n of outputs of the sampling hold analog output group a3. First,
_{C n-1 = C n =} K 0/2
_{C n-2 = C n +} 1 = K 1/2
_{C n-3 = C n +} 2 = K 2/2
...
_{C 0 = C 2n-1 =} K n-1/2
And At this time, the above equation becomes
G _(jω) = e− ^{j (2n−1) ωT / 2} Σ _{i = 0} ⁿ⁻¹ K _i cos (ω (2i + 1) T / 2)
It becomes. The absolute value of this expression is
| G _(jω) | = abs (Σ _{i = 0} ⁿ⁻¹ K _i cos ((2i + 1) πf / f _s ))
It is expressed as

  As shown by this equation, in the passband and in the roll-off region, it is possible to provide a low-pass filter characteristic without phase distortion in which the phase delay is linear with respect to the frequency.

Examples of the A / D conversion circuit according to the present invention will be described below.
Example 1
The number of outputs n is 4, and the above weight values are respectively
K ₀ = 0.415
K ₁ = 0.323
K ₂ = 0.188
K ₃ = 0.074
Set to.

If the sampling frequency of the sampling hold filter unit 2 shown in FIG. 1 and f _s, with respect to the normalized frequency f / f _s, the frequency response of the amplitude indicates a characteristic represented by 801 in FIG. 8. In this embodiment, the point of the normalized frequency f / f _s = 0.25 indicated by 802 in FIG. 8 corresponds to the A / D conversion unit sampling rate.
(Example 2)
Next, the result of the embodiment when the number of outputs n is 8 is shown.

Each of the above weight values is
K ₀ = 0.208
K ₁ = 0.197
K ₂ = 0.175
K ₃ = 0.145
K ₄ = 0.111
K ₅ = 0.079
K ₆ = 0.050
K ₇ = 0.034
And

In this case, with respect to the normalized frequency f / f _s, the frequency response of the amplitude indicates a characteristic represented by 901 in FIG. 9 and 10. In this embodiment, the point of the normalized frequency _f / _f s = 0.125 shown by 902 in FIG. 9 and 10 correspond to the A / D converter sampling rate.

  In this embodiment, if the frequency transfer function in the prefilter 703 shown in FIG. 7 has a second-order low-pass characteristic as shown by 1001 in FIG. 10, the analog signal input terminal A1 shown in FIG. The frequency response in the processing from the portion to the output 702 shown in FIG. 7 shows the characteristic represented by 1002 in FIG.

In addition, the point of the normalized frequency f / f _s = 0.0625 corresponding to a half value of the sampling rate of the A / D converter in this embodiment is indicated by 1004 in FIG. The aliasing noise frequency component in the region from 1/2 of the value of the A / D conversion unit sampling rate to the normalized frequency value f / f _s = 0.125 corresponding to the value of the A / D conversion unit sampling rate The characteristic of mixing in the signal band for A / D conversion is shown by a curve 1003 in FIG. This characteristic indicates that a practical suppression effect can be obtained even for noise near the sampling rate of the A / D converter. In this way, it is shown that interference due to aliasing noise is effectively suppressed with respect to noise components at frequency values higher than that including the frequency value of the A / D converter sampling rate.

  With respect to this configuration, reference numeral 1101 in FIG. 11 shows a waveform in which random noise in which the noise component is directly proportional to the frequency is superimposed on the sine wave. An example in which this waveform is directly sampled and A / D converted is shown at 1202 in FIG. At this time, the A / D conversion value largely fluctuates due to interference of aliasing noise. On the other hand, the waveform of the A / D conversion value generated according to the present embodiment when the number of outputs n is 8 at the same A / D conversion rate is shown at 1201 in FIG. This indicates that an A / D conversion operation in which interference of aliasing noise is suppressed can be obtained.

  As described above, the A / D conversion operation in the A / D conversion device according to the present embodiment includes the action of the anti-aliasing filter used in the related art as shown by the above-described example.

(effect)
As described in the embodiment described above, the present invention has the following effects.

  The first effect is that the circuit part having the function as an anti-aliasing filter is composed of only a sampling hold circuit, a resistor network, and a logic circuit, whereby a high-order LC circuit in the related art having similar characteristics. Alternatively, a higher degree of integration of the circuit can be obtained compared to a method in which an active filter circuit is arranged.

  The second effect is that the anti-aliasing filter characteristic theoretically depends only on the accuracy of the resistance value of the resistor network, and by controlling this accuracy, many anti-aliasing filter characteristics are used in the LC circuit or the active filter circuit. In other words, it is possible to eliminate the total adjustment work and adjustment parts by energization for correcting the influence of the variation in the characteristic of the reactance element.

  The third effect is that the filter characteristic of the present invention is obtained by a non-recursive filter using a sampling and holding circuit. Therefore, the LC circuit or the active filter has a condition that no phase distortion occurs in the pass band in the LC circuit or the active filter circuit. Compared to the case of using a circuit, the setting and adjustment can be easily performed.

(Second Embodiment)
FIG. 15 shows the configuration of an A / D converter according to the second embodiment of the present invention.

  The basic configuration of the A / D converter according to the present embodiment is the same as that of the A / D converter according to the first embodiment.

  That is, in FIG. 15, the configuration and operation up to the output point of the digital signal d1 that is the input signal of the digital filter 1501 are the same as the configuration and operation shown in FIG.

  In FIG. 15, a digital signal d1 that is an output of A / D conversion is connected to a digital filter 1501, and the output is output to the outside from the digital signal output terminal D1 of this circuit.

  The digital filter 1501 performs a process of cutting off frequency components higher than the input signal band. As a result, the residual component of the aliasing noise in the vicinity of the frequency point (1004 in FIG. 10) corresponding to ½ of the D / A conversion rate from the sampling hold filter unit 2 is further suppressed, and only the necessary signal component is present. Extracted.

  Thus, in the A / D conversion device according to the present embodiment, the aliasing noise up to the vicinity of the input signal band can be further suppressed by the digital filter 1501 that can be realized by an integrated circuit. As a result, it is possible to extract an A / D conversion output that is more faithful to the analog signal input to this circuit without significantly increasing the mounting scale.

  In the configuration of the A / D conversion device in the second embodiment, the digital filter 1501 may be a part of the processing by the CPU of the device in which this circuit is incorporated. Further, when there is no concentrated and large noise component in the vicinity of a frequency that is an integral multiple of the sampling frequency 1 / T of the sampling hold filter unit 2 in the input analog signal, interference of aliasing noise in the signal band can be ignored. Is known in advance, the prefilter 1 may be omitted.

  As described above, in the present invention, the sampling hold circuit 21 samples n times the conversion rate of the A / D conversion unit 4, and 2n sampled analog signals are output from the sampling hold circuit 23. . These are added and output by a resistor network 25 having 2n input terminals in which an addition coefficient can be set independently so as to obtain an appropriate frequency characteristic. For this reason, the above processing is equivalent to forming a non-recursive filter based on sample values retroactive to 2n. As a result, it is possible to realize a frequency characteristic that suppresses noise from around the A / D conversion rate to around n times the conversion rate. Note that a noise component in a high frequency region corresponding to an integer multiple of a sampling frequency component n times the A / D conversion rate that cannot be removed by this non-recursive filter is removed by a low-order prefilter 1 such as an RC filter. As a whole, interference due to aliasing noise can be suppressed.

  When the signal band approaches the A / D conversion rate and the noise near the A / D conversion rate needs to be suppressed in order to improve the capability of the electronic device mounted on the guided flying object, the related technology has a steep cutoff characteristic. Although a configuration for realizing anti-aliasing filter characteristics is disclosed, in the present invention, necessary characteristics can be realized by the sampling hold circuits 21, 22, 23 and the resistor network 25 that can be realized by an integrated circuit. Therefore, even in such a case, the anti-aliasing filter characteristic using the high-order LC filter circuit or the active filter circuit that leads to an increase in the mounting circuit scale becomes unnecessary. For this reason, the A / D conversion circuit according to the present invention satisfies the condition of suppressing the increase in the circuit mounting scale, which is required as an induction flying device mounting electronic device.

  The A / D conversion circuit according to the present invention needs to prevent interference of aliasing noise when A / D converting an analog signal including noise having a frequency component higher than a maximum A / D conversion rate that can be set. A high-order anti-aliasing filter of an acyclic filter based on an analog signal using a sampling hold circuit, which is a certain A / D conversion circuit, is arranged before A / D conversion. As a result, it is possible to eliminate high-order active filter circuits or LC filter circuits, which are difficult to achieve a high mounting density, and to suppress an increase in the circuit mounting scale that must be avoided as an electronic device for inductive flying vehicles. A circuit is provided.

  As mentioned above, although this invention was demonstrated with reference to two embodiment, this invention is not limited to said each embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention. Further, the present invention includes a combination of some or all of the configurations of the above-described embodiments as appropriate.

  In the above-described embodiments and examples, the output number n of the sampling hold analog output group is 2 or 4, but the scope of the present invention is not limited to this. Furthermore, in the present invention, two sampling and holding circuits are used in parallel to convert and acquire a digital signal based on 2n analog outputs. However, the present invention is not limited to this, and the number of sampling and holding circuits is three. It may be the above.

Further, in the above-described embodiment, the weight value in the process of generating the A / D conversion input analog signal is set to be large with respect to the data located near the center of the sampling data string, that is, the value of K ₀ is large. However, the present invention is not limited to this. The value of K ₀ through K _n may be arbitrarily determined depending on the frequency dependence of the resulting filter characteristic.

  The method described above can also be realized by a computer reading a program from a recording medium and executing it.

  The present invention is not limited to the above-described embodiment, and can be suitably applied to an electronic circuit that obtains a digital signal output from an analog signal input.

DESCRIPTION OF SYMBOLS 1 Prefilter 2 Sampling hold filter part 3 Scaling circuit 4 A / D conversion part 21 Sampling hold circuit 22 Sampling hold circuit 23 Sampling hold circuit 24 Timing control circuit 24-1 Input buffer circuit 24-2 A / D conversion clock signal generation Dividing circuit 24-3 Control sequence signal generating clock dividing circuit 24-4 Sequence counter circuit 24-5 Control sequence generating circuit 24-6a Sampling pulse generating circuit 24-6b Sampling pulse generating circuit 24-7a Output buffer circuit 24-7b Output buffer circuit 25 Resistor network 701 Weighted addition unit 702 Sampling hold circuit 703 Prefilter 1301 Anti-aliasing filter 1302 Sampling hold circuit 130 3 A / D converter 1304 Digital filter 1305 Control circuit 1401 Anti-aliasing frequency characteristic 1501 Digital filter

Claims (9)

An analog-digital (A / D) conversion circuit that converts an input analog signal into a digital signal,
Sampling hold means for sampling the voltage value of the analog signal n times (n is an integer of 2 or more) every predetermined time, and holding the voltage value;
Conversion input signal generation means for generating a conversion input signal based on the n voltage values held;
An A / D conversion circuit comprising: A / D conversion means for generating a digital signal based on the converted input signal. Further comprising holding means for acquiring and holding n voltage values sampled and held by the sampling hold means;
The conversion input signal generation means generates a conversion input signal based on the n voltage values held by the holding means and the n voltage values further sampled and held by the sampling hold means. The A / D conversion circuit according to claim 1, wherein: 3. The A / D conversion according to claim 1, wherein the conversion input signal generation unit generates the conversion input signal by multiplying the voltage value by a predetermined weight value and adding the value. circuit. 4. The apparatus according to claim 1, further comprising at least one of a pre-filter before the sampling hold unit and a digital filter after the A / D conversion unit. 5. A / D conversion circuit. An analog-digital (A / D) conversion method for converting an input analog signal into a digital signal,
Taking the voltage value of the analog signal n times (n is an integer of 2 or more) every predetermined time, and holding the voltage value;
Generating a converted input signal based on the held n voltage values;
A digital signal based on the converted input signal, and an A / D conversion method. Obtaining and holding the n voltage values that have been sampled and held; and
The conversion input signal is generated based on the n voltage values acquired and held and the n voltage values further sampled and held. / D conversion method. 7. The A / D conversion method according to claim 5, wherein the conversion input signal is generated by multiplying the voltage value by a predetermined weight value and adding the value. Filtering the input analog signal before taking a voltage value;
The A / D conversion method according to any one of claims 5 to 7, further comprising at least one of filtering the generated digital signal. An analog-digital (A / D) conversion program for converting an input analog signal into a digital signal,
A process of collecting the voltage value of the analog signal n times (n is an integer of 2 or more) every predetermined time and holding the voltage value;
A process of generating a conversion input signal based on the n voltage values held;
An A / D conversion program for causing a computer to execute processing for generating a digital signal based on the converted input signal.

Images