JP2013114072A - Thin film transistor array and method of manufacturing the same, and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor array which can easily repair a disconnection without excessively increasing the wiring density and also suppress a short circuit, a disconnection or the like in a case where it is given flexibility, a method of manufacturing the same, and a display device.SOLUTION: A thin film transistor array includes a first conductive layer, an insulator film facing at least part of the first conductive layer and having an opening with a planar shape according to the first conductive layer, and a second conductive layer including a patch part sealing the opening and in contact with the first conductive layer in the opening.

Description

  The present disclosure particularly relates to a thin film transistor (TFT) array suitable for an active matrix display device, a manufacturing method thereof, and a display device including the thin film transistor array.

  In a TFT array used in a display device, scanning lines and signal lines are arranged in a matrix on a glass substrate, and pixel electrodes are arranged in pixel regions partitioned by these scanning lines and signal lines. A TFT as a switching element is provided at the intersection between the scanning line and the signal line.

  Such a TFT array is formed by performing a series of photolithography processes, that is, a film forming process, a photoresist coating process, an exposure process, a developing process, an etching process, and a photoresist stripping process a plurality of times. Therefore, for example, disconnection may occur in the scanning line and the signal line due to film peeling or patterning failure due to foreign matter. Such a disconnection may cause a point defect or a line defect in some cases and may cause a decrease in manufacturing yield.

  Conventionally, for example, in Patent Document 1, when a contact hole is formed on a wiring and a disconnection occurs, a conductive film is formed using a conductive paste over two contact holes sandwiching the disconnected part, and the disconnection is repaired. A method has been proposed.

  Further, for example, in Patent Document 2, a bypass pattern capable of bypassing at least a part of the scanning lines or auxiliary capacitance lines provided in a grid pattern on the substrate is provided, and the bypass pattern and the disconnected wiring are made conductive by laser melt. A repair method has been proposed.

Japanese Patent Laid-Open No. 11-190858 JP 2011-22414 A

  However, in Patent Document 1, a space for providing a conductive paste film is necessary in a gap between originally necessary wirings. Therefore, there is a problem that the wiring density is increased, and defects such as a short circuit may increase. Furthermore, when giving flexibility, there is a possibility that the conductive paste portion has more defects such as short circuit and disconnection than the original structure portion. In Patent Document 2, there is a possibility that defects such as short circuit and disconnection increase in the laser melt portion as compared with the original structure portion when providing flexibility.

  An object of the present disclosure is to provide a thin film transistor array capable of repairing a disconnection without excessively increasing the wiring density and capable of suppressing a short circuit or a disconnection when providing flexibility, a manufacturing method thereof, and the An object of the present invention is to provide a display device including a thin film transistor array.

A thin film transistor array according to the present disclosure includes the following components (A) to (C).
(A) First conductive layer (B) Opposite to at least part of the first conductive layer, the insulating film (C) having a planar opening corresponding to the first conductive layer is closed and the first in the opening. Second conductive layer including a patch portion in contact with the conductive layer

  In the thin film transistor array of the present disclosure, an opening having a planar shape matching the first conductive layer is provided in the insulating film. The opening is closed by the patch portion of the second conductive layer, and the patch portion of the second conductive layer and the first conductive layer are in contact with each other in the opening. Therefore, the inside of the opening is a double layer of the first conductive layer and the patch portion of the second conductive layer, and even when the first conductive layer is disconnected, the disconnection is repaired by the patch portion of the second conductive layer. .

The manufacturing method of the 1st thin-film transistor by this indication includes the process of the following (A)-(C).
(A) Step of forming a first conductive layer (B) An insulating film is formed on the first conductive layer, and the insulating film is aligned with the first conductive layer so as to face at least part of the first conductive layer. (C) A step of forming a second conductive layer including a patch portion that closes the opening and contacts the first conductive layer in the opening on the insulating film.

The second thin film transistor manufacturing method according to the present disclosure includes the following steps (A) to (C).
(A) Step of forming a second conductive layer including a patch portion (B) An insulating film is formed on the second conductive layer, and the insulating film has a planar shape facing the patch portion and facing the patch portion. Step of providing opening (C) Step of forming a first conductive layer on the insulating film that closes the opening and contacts the patch portion in the opening

  A display device according to the present disclosure includes the thin film transistor array according to the present disclosure and a display layer.

  In the display device of the present disclosure, the display layer is driven by the thin film transistor array, and a display operation is performed.

  According to the thin film transistor array of the present disclosure or the display device of the present disclosure, the insulating film is provided with a planar opening corresponding to the first conductive layer, and the opening is closed by the patch portion of the second conductive layer. The patch portion and the first conductive layer are brought into contact with each other. Therefore, even when there is a break in the first conductive layer, the break can be repaired by the patch portion of the second conductive layer. Therefore, it is not necessary to provide a conductive paste film or a bypass pattern in the gap between the wirings, and it is possible to repair the disconnection without increasing the wiring density too much. In addition, defects such as short circuit and disconnection do not increase in the conductive paste part and the laser melt part, and it is possible to suppress short circuit and disconnection when providing flexibility with a flexible substrate.

  According to the first thin film transistor manufacturing method of the present disclosure, the insulating film is provided with the planar opening corresponding to the first conductive layer, the opening is closed by the patch portion of the second conductive layer, and the patch portion is formed in the opening. And the first conductive layer are brought into contact with each other. Further, according to the second thin film transistor manufacturing method of the present disclosure, the insulating film is provided with a planar opening corresponding to the patch portion of the second conductive layer, and the opening is closed with the first conductive layer. The patch portion and the first conductive layer are brought into contact with each other. Therefore, the thin film transistor array of the present disclosure can be easily manufactured.

2A and 2B are a cross-sectional view and a plan view illustrating an overall configuration of a display device according to a first embodiment of the present disclosure. It is sectional drawing showing the structure of the display area shown in FIG. FIG. 3 is a plan view illustrating a configuration of a first conductive layer, a gate insulating film, and a second conductive layer of the TFT array illustrated in FIG. 2. It is sectional drawing in the IV-IV line of FIG. It is sectional drawing in the VV line | wire of FIG. FIG. 3 is a cross-sectional view illustrating a method of manufacturing the display device illustrated in FIG. 2 in order of steps. FIG. 7 is a cross-sectional view illustrating a process following FIG. 6. FIG. 8 is a cross-sectional diagram illustrating a process following the process in FIG. 7. FIG. 9 is a cross-sectional diagram illustrating a process following the process in FIG. 8. 10 is a plan view illustrating a configuration of a first conductive layer, a gate insulating film, and a second conductive layer of a TFT array according to Modification 1. FIG. 10 is a plan view illustrating a configuration of a TFT array in a display device according to a second embodiment of the present disclosure. FIG. It is sectional drawing in the XII-XII line | wire of FIG. It is sectional drawing in the XIII-XIII line | wire of FIG. FIG. 12 is a cross-sectional view illustrating a method of manufacturing the display device illustrated in FIG. 11 in order of steps. FIG. 15 is a cross-sectional view illustrating a process following FIG. 14. FIG. 16 is a cross-sectional diagram illustrating a process following the process in FIG. 15. FIG. 17 is a cross-sectional diagram illustrating a process following the process in FIG. 16. FIG. 18 is a cross-sectional diagram illustrating a process following the process in FIG. 17. 10 is a plan view illustrating a configuration of a TFT array according to Modification 2. FIG. It is a top view showing the composition of the 1st conductive layer of the TFT array, the gate insulating film, and the 2nd conductive layer in the display concerning the 3rd embodiment of this indication. It is sectional drawing in the XXI-XXI line | wire of FIG. It is sectional drawing in the XXII-XXII line | wire of FIG. FIG. 20 is a cross-sectional view illustrating a method of manufacturing the display device illustrated in FIG. 19 in order of steps. FIG. 24 is a cross-sectional diagram illustrating a process following the process in FIG. 23. FIG. 25 is a cross-sectional diagram illustrating a process following the process in FIG. 24. FIG. 26 is a cross-sectional diagram illustrating a process following the process in FIG. 25. It is a top view showing schematic structure of the module containing the display apparatus of the said embodiment. It is a perspective view showing the external appearance of the application example 1 of the display apparatus of the said embodiment. 12 is a perspective view illustrating an appearance of application example 2. FIG. 12 is a perspective view illustrating an appearance of application example 3. FIG. (A) is a perspective view showing the external appearance seen from the front side of the application example 4, (B) is a perspective view showing the external appearance seen from the back side. 14 is a perspective view illustrating an appearance of application example 5. FIG. 16 is a perspective view illustrating an appearance of application example 6. FIG. (A) is a front view of the application example 6 in an open state, (B) is a side view thereof, (C) is a front view in a closed state, (D) is a left side view, and (E) is a right side view, (F) is a top view and (G) is a bottom view.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order.
1. First embodiment (an example in which a disconnection of a scanning line is repaired by a patch portion in the same layer as a signal line)
2. Modification 1 (example in which the patch part is applied to the entire TFT array)
3. Second Embodiment (Example in which a disconnection of a signal line is repaired by a patch portion in the same layer as the pixel electrode)
4). Modification 2 (example in which the patch part is applied to the entire TFT array)
5. Third Embodiment (Example in which a disconnection of a signal line is repaired by a patch portion in the same layer as a scanning line)
6). Application examples

(First embodiment)
FIG. 1 schematically illustrates a schematic configuration of the display device according to the first embodiment of the present disclosure. FIG. 1B illustrates a planar configuration (top configuration), and FIG. FIG. 1 shows a cross-sectional configuration taken along the line IA-IA in FIG. In this display device 1, a substrate 11, a TFT array 12, a display layer 13, and a transparent substrate 14 are laminated in this order. Specifically, the TFT array 12, the display layer 13, and the transparent substrate 14 are stacked on the display area 10A of the substrate 11, while the TFT array 12 is formed on the frame area (non-display area) 10B of the substrate 11. The display layer 13 and the transparent substrate 14 are not laminated.

  The substrate 11 is made of, for example, an inorganic material such as glass, a metal thin film, or a plastic material. Examples of the inorganic material include glass, quartz, silicon, and gallium arsenide. Examples of the plastic material include polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymethyl methacrylate (PMMA), polycarbonate (PC), polyethersulfone (PES), polyethyl ether ketone (PEEK), and aromatic. Examples include polyester (liquid crystal polymer). The substrate 11 may be a rigid substrate such as a wafer, or may be a flexible substrate (flexible substrate) such as thin glass or film.

  The TFT array 12 is a layer including a plurality of devices including a thin film (a conductive film such as a metal film or an insulating film). Examples of this device include a TFT as a switching element for selecting a pixel, a capacitor (such as a storage capacitor), a wiring (such as a scanning line or a signal line), an electrode (such as a pixel electrode), and the like. That is, the device included in the TFT array 12 is at least one of a TFT, a capacitor, a wiring, and an electrode. Here, the above-described TFT may be configured by either an inorganic TFT using an inorganic semiconductor layer as a channel layer or an organic TFT using an organic semiconductor layer.

  The display layer 13 has an electrophoretic display body between, for example, a pixel electrode and a counter electrode. That is, the display device 1 is an electrophoretic display (so-called electronic paper display) that displays an image (for example, character information) using an electrophoretic phenomenon. A pixel electrode is provided in the TFT array 12 for each pixel. The counter electrode is provided on one surface of the transparent substrate 14.

  The transparent substrate 14 is configured using, for example, the same material as the substrate 11. A moisture-proof film that prevents moisture from entering the display layer 13 and an optical function film that prevents external light from being reflected on the display surface may be provided on the transparent substrate 14.

  A barrier layer may be provided between the substrate 11 and the TFT array 12 in order to prevent deterioration of the TFT array 12 and the display layer 13 due to moisture or organic gas. Such a barrier layer is made of, for example, AlOxN1-X (where X = 0.01 to 0.2) or silicon nitride (Si3N4).

  FIG. 2 illustrates a cross-sectional configuration of the display region 10A illustrated in FIG. As described above, in the display area 10A, the TFT array 12, the display layer 13, the counter electrode 15, and the transparent substrate 14 are laminated in this order on the substrate 11. The TFT array 12 includes, for example, a lower conductive layer 20, a gate insulating film 30, a semiconductor layer 40 (not shown in FIG. 2, refer to FIG. 3), an upper conductive layer 50, and a passivation film (in order from the substrate 11 side). A protective film 61, a planarizing film 62, and an uppermost conductive layer 70. The counter electrode 15 is a common electrode provided over the entire display area 10 </ b> A on the surface of the transparent substrate 14 facing the display layer 13.

  FIG. 3 shows a planar configuration of the lower conductive layer 20, the gate insulating film 30, and the upper conductive layer 50 of the TFT array 12 shown in FIG. In FIG. 3 and subsequent figures, the direction perpendicular to the main surface of the substrate 11 is the z direction (stacking direction), the horizontal direction in the main surface of the substrate 11 is the x direction, and the vertical direction in the main surface of the substrate 11 is y. It is called direction.

  The lower conductive layer 20 includes, for example, a scanning line 21 and a lower electrode 22 of the capacitive element CS. In FIG. 3, the lower conductive layer 20 is represented by slanting leftward. The scanning line 21 extends on the substrate 11 in the y direction, and includes a gate electrode 21G (not shown in FIGS. 2 and 3; see FIG. 5) of the TFT. The scanning line 21 and the lower electrode 22 are made of the same material and are formed by the same process in the manufacturing method described later. The scanning line 21 and the lower electrode 22 are, for example, a single-layer film made of one of molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), aluminum (Al), and an aluminum alloy, Or it is comprised by the laminated film which consists of 2 or more types. Examples of the aluminum alloy include an aluminum-neodymium (Al—Nd) alloy.

The gate insulating film 30 is provided over the entire display region 10 </ b> A between the lower conductive layer 20, the semiconductor layer 40, and the upper conductive layer 50. The gate insulating film 30 is a single layer film made of, for example, one of SiO ₂ , Si ₃ N ₄ , SiNO, Al ₂ O _{3 and the} like.

  The semiconductor layer 40 is provided in an island shape at the intersection of the scanning line 21 and the signal line 51. The constituent material of the semiconductor layer 40 may be silicon, an oxide semiconductor, or an organic semiconductor.

  The upper conductive layer 50 includes a signal line 51 and an upper electrode 52 of the capacitive element CS. In FIG. 3, the upper conductive layer 50 is shaded. The signal line 51 extends in the x direction on the gate insulating film 30 and the semiconductor layer 40, and also serves as the source electrode 51S of the TFT. The upper electrode 52 is connected to the drain electrode 52D of the TFT. The signal line 51 and the upper electrode 52 are made of the same material and are formed in the same process in the manufacturing method described later. The signal line 51 and the upper electrode 52 are, for example, a single layer film made of one of molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), aluminum (Al), and an aluminum alloy, Or it is comprised by the laminated film which consists of 2 or more types. Examples of the aluminum alloy include an aluminum-neodymium alloy.

  The passivation film 61 functions as a protective film for the upper conductive layer 50, and the planarization film 62 planarizes the surface in order to form the pixel electrode 71 of the uppermost conductive layer 70. The passivation film 61 and the planarization film 62 are configured by, for example, either an organic film or an inorganic film, or a combination thereof.

  The uppermost conductive layer 70 is provided on the planarizing film 62 and includes a pixel electrode 71. The uppermost conductive layer 70 is made of, for example, molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), transparent electrodes such as ITO, IGO, and IGZO that are In alloys, aluminum (Al), and aluminum alloys. Are formed of a single-layer film made of one of the above or a laminated film made of two or more. Examples of the aluminum alloy include an aluminum-neodymium alloy.

  4 represents a cross-sectional configuration taken along line IV-IV in FIG. 3, and FIG. 5 represents a cross-sectional configuration taken along line VV in FIG. The gate insulating film 30 has an elongated rectangular planar opening 31 along the scanning line 21 on the scanning line 21. The opening 31 is closed by a patch portion 53 that forms a part of the upper conductive layer 50. The patch portion 53 is in contact with the scanning line 21 in the opening 31. Thereby, in this display device 1, it is possible to repair the disconnected portion 21 </ b> A of the scanning line 21 without excessively increasing the wiring density. When the flexible substrate 11 is provided with flexibility, a short circuit or disconnection is caused. Etc. can be suppressed.

  The opening 31 does not necessarily have the same shape and dimensions as the scanning line 21, and a plane shape (the shape is the same as that of the scanning line 21) in accordance with the scanning line 21 in consideration of a mask alignment margin in the manufacturing process. And dimensions such as width and length are smaller than those of the scanning line 21).

  The patch portion 53 has a function as a bypass wiring for repairing / repairing the disconnection portion 21 </ b> A of the scanning line 21 by forming a double wiring with the scanning line 21 in the opening 31. The patch portion 53 is, for example, an elongated rectangle along the scanning line 21, similar to the opening 31, and has a size that can block the entire opening 31.

  The patch portion 53 is included in the upper conductive layer 50 together with the signal line 51 and the upper electrode 52 of the capacitive element CS. That is, the patch portion 53, the signal line 51, and the upper electrode 52 are all made of the same material as a part of the upper conductive layer 50, and are formed by the same process in the manufacturing method described later. . However, the patch portion 53 is physically and electrically separated from the signal line 51 and the upper electrode 52.

  The opening 31 and the patch portion 53 are disposed in at least a part of a region where the scanning line 21 does not overlap the signal line 51 and avoids the intersection of the scanning line 21 and the signal line 51. Yes. Specifically, the opening 31 and the patch portion 53 are selectively provided in a portion where the disconnection portion 21A of the scanning line 21 is generated.

  Here, the lower conductive layer 20 corresponds to a specific example of “first conductive layer” in the present disclosure. The scanning line 21 corresponds to a specific example of “first wiring” in the present disclosure. The gate insulating film 30 corresponds to a specific example of “insulating film” in the present disclosure. The opening 31 corresponds to a specific example of “opening” in the present disclosure. The upper conductive layer 50 including the patch portion 53 corresponds to a specific example of “second conductive layer” in the present disclosure. The signal line 51 corresponds to a specific example of “second wiring” in the present disclosure.

  The display device 1 can be manufactured as follows, for example.

  6 to 9 show the manufacturing method of the display device 1 in the order of steps. 6 to 9, (A) represents a cross section taken along line IV-IV in FIG. 3, and (B) represents a cross section taken along line VV in FIG.

  First, as shown in FIG. 6, for example, a conductive material film (not shown) is formed on the substrate 11, and the conductive material film is subjected to photolithography and etching, whereby the scanning lines 21, the gates are formed. The lower conductive layer 20 including the electrode 21G and the lower electrode 22 of the capacitive element CS is formed.

  Here, the scanning line 21 may have a disconnection portion 21A (see FIG. 3) due to film peeling or patterning failure due to foreign matter. Moreover, when the board | substrate 11 is comprised with the plastic material, the disconnection part 21A may arise by the influence of local defects, such as a crack of a plastic surface, and a level | step difference. The larger the plastic substrate, the higher the possibility that such a local defect will hit the position where the scanning line 21 is formed. Further, since the scanning line 21 is provided at a position closest to the substrate 11, the influence of such a local defect of the substrate 11 is also increased. Therefore, the presence or absence of the disconnection portion 21A (see FIG. 3) of the scanning line 21 is checked by optical inspection or electrical inspection, and if the disconnection portion 21A has occurred, the position thereof is specified.

  Next, as illustrated in FIG. 7, the gate insulating film 30 is formed on the first conductive layer 20, and the scanning line 21 is formed on the gate insulating film 30 on the portion where the disconnection portion 21 </ b> A of the scanning line 21 is generated. An elongated rectangular planar opening 31 is provided. The opening 31 can be formed simultaneously by photolithography and etching at the time of forming a gate contact (not shown).

  After that, as shown in FIG. 8, the semiconductor layer 40 is formed on the portion that becomes the gate electrode 21 </ b> G of the scanning line 21.

  Subsequently, similarly as shown in FIG. 8, a conductive material film (not shown) is formed on the gate insulating film 30 and the semiconductor layer 40, and photolithography and etching are performed on the conductive material film. Thus, the upper conductive layer 50 including the signal line 51, the source electrode 51S, the upper electrode 52 of the capacitive element CS, the drain electrode 52D, and the patch portion 53 is formed. Thereby, the TFT and the capacitor element CS are formed. At the same time, the patch portion 53 comes into contact with the scanning line 21 in the opening 31, a double wiring of the patch portion 53 and the scanning line 21 is formed in the opening 31, and the disconnected portion 21A is repaired.

  On the other hand, conventionally, when a contact hole is formed on the wiring and disconnection occurs, a conductive film is formed using a conductive paste over two contact holes sandwiching the disconnected portion, and the disconnection is repaired. It was like that. For this reason, a process of forming a conductive film with a conductive paste is required during or after the process. Further, even when the conductive paste is not used, it is formed in a desired shape with a liquid conductive material, and thus an additional step of forming a conductive film is required.

  In the present embodiment, the patch portion 53 can be formed as a part of the upper conductive layer 50 by using the same material and the same process as the signal line 51 and the upper electrode 52 of the capacitor element CS. No additional process is required. Therefore, there is no need to add a step of forming a conductive film using a conductive paste separately during or after the process as in the prior art, and it is possible to suppress an increase in tact time and manufacturing cost.

  Further, the patch portion 53 can be formed so as to overlap the scanning line 21, and there is no need to provide a conductive paste film by interposing the gap between the scanning line 21 and the signal line 51 as in the conventional case. Therefore, the wiring density does not become too high, and the occurrence of defects such as a short circuit can be suppressed.

  Furthermore, the conventional disconnection and short-circuit correction using a laser is possible when the substrate 11 is made of glass, but when the substrate 11 is made of plastic, the plastic is Since it was damaged by heat, it could not be used. The effect was particularly great in the case of colored plastics.

  On the other hand, in the present embodiment, it is possible to repair the disconnected portion 21A without using a laser, which is suitable when the substrate 11 is made of plastic.

  In addition, when repairing with a conductive paste or laser melt as in the past, the conductive paste location or laser melt location is more likely to cause defects such as short-circuiting or disconnection than the original structure. There was a fear. On the other hand, in the present embodiment, a planar opening 31 corresponding to the scanning line 21 is formed, and the patch portion 53 is brought into contact with the scanning line 21 in the opening 31 to form a double wiring. Yes. The patch portion 53 is made of the same material as the signal line 51 and the upper electrode 52 which are the original structure portions, unlike the conventional conductive paste portion and laser melt portion. Therefore, in the case where flexibility is provided by a flexible substrate 11 such as plastic, it is possible to suppress an increase in short circuit and disconnection, unlike conventional conductive paste locations and laser melt locations.

  After that, as shown in FIG. 9, the uppermost conductive layer 70 including the passivation film 61, the planarizing film 62, and the pixel electrode 71 is sequentially formed on the upper conductive layer 50. As a result, the TFT array 12 shown in FIG. 2 is formed.

  Finally, as shown in FIG. 2, the display layer 13 is formed on the pixel electrode 71, and the transparent substrate 14 on which the counter electrode 15 is formed is disposed on the display layer 13. Thus, the display device 1 shown in FIGS. 1 to 5 is completed.

  In the display device 1, display is performed on the display layer 13 by an electrophoretic display body based on a video voltage applied between the pixel electrode 71 and the counter electrode 15.

  Here, the gate insulating film 30 is provided with an elongated rectangular planar opening 31 along the scanning line 21. The opening 31 is closed by the patch portion 53 of the upper conductive layer 50, and the patch portion 53 and the scanning line 21 are in contact with each other in the opening 31. Therefore, the opening 31 is a double wiring of the scanning line 21 and the patch portion 53, and the disconnected portion 21 </ b> A of the scanning line 21 is repaired by the patch portion 53. Therefore, even when the disconnection portion 21A occurs and the voltage is not normally applied to the scanning line 21, the patch portion 53 serves as a bypass wiring, and the voltage is also applied to the disconnection portion 21A and subsequent portions. Therefore, dot defects and line defects caused by the disconnected portion 21A are suppressed, and display quality is improved.

  As described above, in this embodiment, the gate insulating film 30 is provided with the opening 31 having a planar shape corresponding to the scanning line 21 so as to face the scanning line 21, and this opening 31 is formed in the patch portion 53 of the upper conductive layer 50. The patch portion 53 and the scanning line 21 are brought into contact with each other in the opening 31. Therefore, even when the disconnection portion 21 </ b> A occurs in the scanning line 21, the disconnection portion 21 </ b> A can be repaired by the patch portion 53. Accordingly, it is not necessary to provide a conductive paste film in the gap between the wirings as in the prior art, and it is possible to repair the disconnected portion 21A without excessively increasing the wiring density. In addition, defects such as short circuit and disconnection do not increase at the conductive paste location and the laser melt location as in the prior art, which is also suitable for providing flexibility by the flexible substrate 11.

  The patch portion 53 can be formed as a part of the upper conductive layer 50 by the same material and the same process as the signal line 51 and the upper electrode 52 of the capacitor element CS. No process is required. Therefore, there is no need to add a step of forming a conductive film using a conductive paste separately during or after the process as in the prior art, and it is possible to suppress an increase in tact time and manufacturing cost.

(Modification 1)
In the above-described embodiment, when the disconnection portion 21A occurs in the scanning line 21, the position of the disconnection portion 21A is specified, and the opening 31 and the patch portion 53 are selectively provided only at the location to repair the disconnection portion 21A. Explained when to do. However, as shown in FIG. 10, the opening 31 and the patch portion 53 can be arranged over the entire scanning line 21 of the TFT array 12 as a redundant design. That is, the opening 31 and the patch part 53 are arranged in the entire region where the scanning line 21 does not overlap the signal line 51 and avoids the intersection of the scanning line 21 and the signal line 51. Is also possible.

  In particular, when the substrate 11 made of plastic is used, a large number of disconnections 21A may occur due to the influence of local defects such as scratches and steps on the plastic surface. Therefore, it is possible to further improve the manufacturing efficiency and the yield by incorporating the formation of the opening 31 and the patch portion 53 in advance in the manufacturing process, rather than specifying the position of the disconnected portion 21A by defect inspection. In particular, the scanning line 21 is provided at a position closest to the substrate 11, and a disconnection portion 21 </ b> A due to a local defect on the surface of the substrate 11 is likely to occur, so that a higher effect can be obtained.

(Second Embodiment)
FIG. 11 illustrates a planar configuration of the TFT array 12 according to the second embodiment of the present disclosure. In the present embodiment, when a broken portion 51A occurs in the signal line 51, the broken portion 51A is repaired by the patch portion 72 in the same layer as the pixel electrode 71 in the uppermost conductive layer 70. . Except for this, the display device 1 according to the present embodiment has the same configuration, operation, and effects as those of the first embodiment. Accordingly, the corresponding components will be described with the same reference numerals.

  The lower conductive layer 20, the gate insulating film 30, the semiconductor layer 40, the upper conductive layer 50, the passivation film 61, the planarization film 62, and the pixel electrode 71 are configured in the same manner as in the first embodiment. In FIG. 11, for the sake of simplicity, the case where the disconnection portion 21 </ b> A does not occur in the scanning line 21 is illustrated, but the disconnection of the scanning line 21 is obtained by combining the present embodiment and the first embodiment. It is also possible to provide the opening 31 and the patch part 53 in the part 21A. In addition, by combining the present embodiment and the first modification, the opening 31 and the patch portion 53 can be arranged on the entire scanning line 21 of the TFT array 12 as a redundant design.

  12 shows a cross-sectional configuration taken along line XII-XII in FIG. 11, and FIG. 13 shows a cross-sectional configuration taken along line XIII-XIII in FIG. The passivation film 61 and the planarization film 62 have an elongated rectangular planar opening 63 along the signal line 51 on the signal line 51. The opening 63 is closed by a patch portion 72 that forms a part of the uppermost conductive layer 70. The patch part 72 is in contact with the signal line 51 in the opening 63. Thereby, in this display device 1, it is possible to repair the disconnected portion 51 </ b> A of the signal line 51 without excessively increasing the wiring density. When the flexible substrate 11 is provided with flexibility, a short circuit or disconnection is caused. Etc. can be suppressed.

  The opening 63 does not necessarily have the same shape and size as the signal line 51, and a plane shape (the shape is the same as that of the signal line 51) in accordance with the signal line 51 in consideration of a margin for mask alignment in the manufacturing process. And the dimensions such as width and length are smaller than the signal line 51).

  The patch part 72 has a function as a bypass wiring for repairing / repairing the disconnection part 51 </ b> A of the signal line 51 by forming a double wiring with the signal line 51 in the opening 63. The patch portion 72 is, for example, an elongated rectangle along the signal line 51, similar to the opening 63, and has a dimension capable of closing the entire opening 63.

  The patch portion 72 is included in the uppermost conductive layer 70 together with the pixel electrode 71. That is, the patch part 72 and the pixel electrode 71 are both made of the same material as part of the uppermost conductive layer 70 and are formed by the same process in the manufacturing method described later. However, the patch portion 72 is physically and electrically separated from the pixel electrode 71.

  The opening 63 and the patch portion 72 are arranged in at least a part of a region where the signal line 51 does not overlap the pixel electrode 71 and is provided alone. Specifically, the opening 63 and the patch portion 72 are selectively provided in a portion where the disconnection portion 51A of the signal line 51 is generated.

  Here, the upper conductive layer 50 corresponds to a specific example of “first conductive layer” in the present disclosure, and the signal line 51 corresponds to a specific example of “first wiring” in the present disclosure. The passivation film 61 and the planarization film 62 correspond to a specific example of “insulating film” in the present disclosure. The opening 63 corresponds to a specific example of “opening” in the present disclosure. The uppermost conductive layer 70 corresponds to a specific example of “second conductive layer” in the present disclosure, and the pixel electrode 71 corresponds to a specific example of “second wiring” in the present disclosure.

  The display device 1 can be manufactured as follows, for example.

  14 to 18 show the manufacturing method of the display device 1 in the order of steps. 14 to 18, (A) represents a cross section taken along line XII-XII in FIG. 11, and (B) represents a cross section taken along line XIII-XIII in FIG.

  First, as shown in FIG. 14, for example, a conductive material film (not shown) is formed on the substrate 11, and the conductive material film is subjected to photolithography and etching, whereby the scanning lines 21, gates are formed. The lower conductive layer 20 including the electrode 21G and the lower electrode 22 of the capacitive element CS is formed.

  Next, as shown in FIG. 15, a gate insulating film 30 is formed on the lower conductive layer 20. Subsequently, a semiconductor layer 40 (not shown in FIG. 15, refer to FIG. 11) is formed on the portion of the scanning line 21 to be the gate electrode 21G.

  After that, as shown in FIG. 16, a conductive material film (not shown) is formed on the gate insulating film 30 and the semiconductor layer 40, and photolithography and etching are performed on the conductive material film. Thus, the upper conductive layer 50 including the signal line 51, the source electrode 51S, the upper electrode 52 of the capacitive element CS, and the drain electrode 52D is formed. Thereby, the TFT and the capacitor element CS are formed.

  Here, the signal line 51 may have a disconnected portion 51A (see FIG. 11) due to film peeling or patterning failure due to foreign matter. In addition, when the substrate 11 is made of a plastic material, the disconnection portion 51A may be generated due to the influence of local defects such as scratches or steps on the plastic surface. The larger the plastic substrate, the higher the possibility that such a local defect will hit the position where the signal line 51 is formed. Therefore, the presence or absence of the disconnection portion 51A (see FIG. 11) of the signal line 51 is checked by optical inspection or electrical inspection, and if the disconnection portion 51A has occurred, the position thereof is specified.

  Subsequently, as shown in FIG. 17, a passivation film 61 and a planarizing film 62 are formed on the upper conductive layer 50, and a disconnection portion 51 </ b> A of the signal line 51 is generated in the passivation film 61 and the planarizing film 62. An elongated rectangular plane-shaped opening 63 along the signal line 51 is provided on the portion. The opening 63 can be formed simultaneously by photolithography and etching when forming the connection hole 64 with the pixel electrode 71.

  After that, as shown in FIG. 18, a conductive material film (not shown) is formed on the passivation film 61 and the planarizing film 62, and photolithography and etching are performed on the conductive material film. Thus, the pixel electrode 71 and the patch portion 72 are formed. Thereby, the pixel electrode 71 is connected to the upper electrode 52 of the capacitive element CS through the connection hole 64. At the same time, the patch portion 72 comes into contact with the signal line 51 in the opening 63, a double wiring of the patch portion 72 and the signal line 51 is formed in the opening 63, and the disconnected portion 51A is repaired. Thus, the TFT array 12 shown in FIG. 11 is formed.

  Here, the patch part 72 can be formed as a part of the uppermost conductive layer 70 by the same material and the same process as the pixel electrode 71, and an additional process for the patch part 72 is unnecessary. Therefore, there is no need to add a step of forming a conductive film using a conductive paste separately during or after the process as in the prior art, and it is possible to suppress an increase in tact time and manufacturing cost.

  Further, the patch portion 72 can be formed so as to overlap the signal line 51, and there is no need to provide a conductive paste film through the gap between the scanning line 21 and the signal line 51 as in the prior art. Therefore, the wiring density does not become too high, and the occurrence of defects such as a short circuit can be suppressed.

  Furthermore, the conventional disconnection and short-circuit correction using a laser is possible when the substrate 11 is made of glass, but when the substrate 11 is made of plastic, the plastic is heated. Cannot be used due to damage. The effect is particularly great in the case of colored plastics. On the other hand, in the present embodiment, it is possible to repair the disconnected portion 51A without using a laser, which is suitable when the substrate 11 is made of plastic.

  In addition, when repairing with a conductive paste or laser melt as in the past, the conductive paste location or laser melt location is more likely to cause defects such as short-circuiting or disconnection than the original structure. There was a fear. In contrast, in the present embodiment, a planar opening 63 that matches the signal line 51 is formed, and the patch portion 72 is brought into contact with the signal line 51 in the opening 63 to form a double wiring. Yes. The patch portion 72 is made of the same material as the pixel electrode 71 which is the original structure portion, unlike the conventional conductive paste portion and laser melt portion. Therefore, in the case where flexibility is provided by a flexible substrate 11 such as plastic, it is possible to suppress an increase in short circuit and disconnection, unlike conventional conductive paste locations and laser melt locations.

  Finally, as shown in FIG. 2, the display layer 13 is formed on the pixel electrode 71, and the transparent substrate 14 on which the counter electrode 15 is formed is disposed on the display layer 13. Thus, the display device 1 shown in FIGS. 1 and 2 is completed.

  In the display device 1, display is performed on the display layer 13 by an electrophoretic display body based on a video voltage applied between the pixel electrode 71 and the counter electrode 15.

  Here, the passivation film 61 and the planarization film 62 are provided with elongated rectangular planar openings 63 along the signal lines 51. The opening 63 is closed by the patch portion 72 of the uppermost conductive layer 70, and the patch portion 72 and the signal line 51 are in contact with each other in the opening 63. Therefore, the inside of the opening 63 is a double wiring of the signal line 51 and the patch portion 72, and the disconnected portion 51 </ b> A of the signal line 51 is repaired by the patch portion 72. Therefore, even when the disconnection portion 51A occurs and the voltage is not normally applied to the signal line 51, the patch portion 72 serves as a bypass wiring, and the voltage is also applied after the disconnection portion 51A. Therefore, dot defects and line defects caused by the disconnected portion 51A are suppressed, and display quality is improved.

  As described above, in this embodiment, the passivation film 61 and the planarization film 62 are provided with the opening 63 having a planar shape corresponding to the signal line 51 so as to face the signal line 51, and this opening 63 is formed on the uppermost conductive layer. The patch portion 72 is closed by 70 and the patch portion 72 and the signal line 51 are brought into contact with each other in the opening 63. Therefore, even when the disconnection portion 51 </ b> A occurs in the signal line 51, the disconnection portion 51 </ b> A can be repaired by the patch portion 72. Therefore, it is not necessary to provide a conductive paste film in the gap between the wirings as in the prior art, and it is possible to repair the disconnected portion 51A without excessively increasing the wiring density. In addition, defects such as short circuit and disconnection do not increase at the conductive paste location and the laser melt location as in the prior art, which is also suitable for providing flexibility by the flexible substrate 11.

  Further, the patch part 72 can be formed as a part of the uppermost conductive layer 70 by the same material and the same process as the pixel electrode 71, and an additional process for the patch part 72 is unnecessary. Therefore, there is no need to add a step of forming a conductive film using a conductive paste separately during or after the process as in the prior art, and it is possible to suppress an increase in tact time and manufacturing cost.

(Modification 2)
In the above-described embodiment, when the broken portion 51A occurs in the signal line 51, the position of the broken portion 51A is specified, and the opening 63 and the patch portion 72 are selectively provided only at the location to repair the broken portion 51A. Explained when to do. However, as shown in FIG. 19, the opening 63 and the patch portion 72 can be arranged over the entire signal line 51 of the TFT array 12 as a redundant design. In particular, when the substrate 11 made of plastic is used, a large number of disconnections 51A may occur due to the influence of local defects such as scratches and steps on the plastic surface. Therefore, it is possible to further improve the manufacturing efficiency and the yield by incorporating the formation of the opening 63 and the patch portion 72 in advance in the manufacturing process, rather than specifying the position of the disconnected portion 51A by defect inspection.

  FIG. 19 shows the case where the opening 63 and the patch part 72 are provided separately for each pixel while avoiding the intersection between the scanning line 21 and the signal line 51. The portion 72 can be provided in the entire region where the signal line 51 does not overlap with the pixel electrode 71 and is provided independently.

(Third embodiment)
FIG. 20 illustrates a planar configuration of the TFT array 12 according to the third embodiment of the present disclosure. In the present embodiment, when a broken portion 51A occurs in the signal line 51, the broken portion 51A is repaired in the lower conductive layer 20 by the patch portion 23 in the same layer as the scanning line 21 and the like. . Except for this, the display device 1 according to the present embodiment has the same configuration, operation, and effects as those of the first embodiment. Accordingly, the corresponding components will be described with the same reference numerals.

  The lower conductive layer 20, the gate insulating film 30, the semiconductor layer 40, the upper conductive layer 50, the passivation film 61, the planarizing film 62, and the uppermost conductive layer 70 are configured in the same manner as in the first embodiment. In FIG. 20, for the sake of simplicity, the case where the disconnection portion 21 </ b> A does not occur in the scan line 21 is shown, but the disconnection of the scan line 21 is obtained by combining this embodiment and the first embodiment. It is also possible to provide the opening 31 and the patch part 53 in the part 21A. In addition, the opening 31 and the patch part 53 can be formed as a redundant design on the entire scanning line 21 of the TFT array 12 by combining this embodiment and the first modification.

  FIG. 21 shows a cross-sectional configuration along the line XXI-XXI in FIG. 11, and FIG. 22 shows a cross-sectional configuration along the line XXII-XXII in FIG. The gate insulating film 30 has an elongated rectangular planar opening 32 along the signal line 51 below the signal line 51. The opening 32 is closed from below by a patch portion 23 that forms part of the lower conductive layer 20. The patch part 23 is in contact with the signal line 51 of the upper conductive layer 50 in the opening 32. Thereby, in this display device 1, it is possible to repair the disconnected portion 51 </ b> A of the signal line 51 without excessively increasing the wiring density. When the flexible substrate 11 is provided with flexibility, a short circuit or disconnection is caused. Etc. can be suppressed.

  The opening 32 does not necessarily have the same shape and dimensions as the signal line 51, and a plane shape (the shape is the same as that of the signal line 51) in accordance with the signal line 51 in consideration of a mask alignment margin in the manufacturing process. And the dimensions such as width and length are smaller than the signal line 51).

  The patch portion 23 has a function as a bypass wiring for repairing / repairing the disconnection portion 51 </ b> A of the signal line 51 by forming a double wiring with the signal line 51 in the opening 32. The patch portion 23 is, for example, an elongated rectangle along the signal line 51, similar to the opening 32, and has a size that can block the entire opening 32.

  The patch part 23 is included in the lower conductive layer 20 together with the scanning line 21 and the lower electrode 22 of the capacitive element CS. That is, the patch portion 23, the scanning line 21, and the lower electrode 22 of the capacitive element CS are all made of the same material as part of the lower conductive layer 20, and are formed by the same process in the manufacturing method described later. It is a thing. However, the patch portion 23 is physically and electrically separated from the scanning line 21 and the lower electrode 22.

  The opening 32 and the patch part 23 are desirably provided over the entire signal line 51 of the TFT array 12. That is, the opening 32 and the patch portion 23 are disposed in the entire region where the signal line 51 does not overlap the scanning line 21 and avoids the intersection of the scanning line 21 and the signal line 51. Preferably it is. This is because the patch portion 23 is formed before the signal line 51 in the manufacturing process described later, and thus it is difficult to specify the generation position of the disconnection portion 51A in advance.

  Here, the upper conductive layer 50 corresponds to a specific example of “first conductive layer” in the present disclosure, and the signal line 51 corresponds to a specific example of “first wiring” in the present disclosure. The insulating film 30 corresponds to a specific example of “insulating film” in the present disclosure. The opening 32 corresponds to a specific example of “opening” in the present disclosure. The lower conductive layer 20 corresponds to a specific example of “second conductive layer” in the present disclosure, and the scanning line 21 corresponds to a specific example of “second wiring” in the present disclosure.

  The display device 1 can be manufactured as follows, for example.

  23 to 26 show the method for manufacturing the display device 1 in the order of steps. 23 to 26, (A) represents a cross section taken along line XXI-XXI in FIG. 20, and (B) represents a cross section taken along line XXII-XXII in FIG.

  First, as shown in FIG. 23, for example, a conductive material film (not shown) is formed on the substrate 11, and photolithography and etching are performed on the conductive material film, whereby the scanning lines 21, gates are formed. The lower conductive layer 20 including the electrode 21G, the lower electrode 22 of the capacitive element CS, and the patch portion 23 is formed. The patch portion 23 is provided in a long and narrow rectangle along the signal line 51 in the entire region where the signal line 51 does not overlap the scanning line 21 in the region where the signal line 51 is to be formed.

  Next, as illustrated in FIG. 24, a gate insulating film 30 is formed on the lower conductive layer 20, and an elongated rectangular planar opening along the patch portion 23 is formed on the patch insulating portion 30 in the gate insulating film 30. 32 is provided. The opening 32 can be formed simultaneously by photolithography and etching at the time of forming a gate contact (not shown).

  Subsequently, a semiconductor layer 40 (not shown in FIG. 24, see FIG. 20) is formed on the portion of the scanning line 21 to be the gate electrode 21G.

  After that, as shown in FIG. 25, a conductive material film (not shown) is formed on the gate insulating film 30 and the semiconductor layer 40, and photolithography and etching are performed on the conductive material film. Thus, the upper conductive layer 50 including the signal line 51, the source electrode 51S, the upper electrode 52 of the capacitive element CS, and the drain electrode 52D is formed. Thereby, the TFT and the capacitor element CS are formed.

  Here, the signal line 51 may have a disconnection 51A (see FIG. 20) due to film peeling or patterning failure due to foreign matter. In addition, when the substrate 11 is made of a plastic material, the disconnection portion 51A may be generated due to the influence of local defects such as scratches or steps on the plastic surface. The larger the plastic substrate, the higher the possibility that such a local defect will hit the position where the signal line 51 is formed.

  However, the signal line 51 contacts the patch portion 23 in the opening 32, and a double wiring of the signal line 51 and the patch portion 23 is formed in the opening 32. Therefore, even when the signal line 51 has a disconnection 51 </ b> A, the disconnection 51 </ b> A is repaired by the patch unit 23.

  Here, the patch part 23 can be formed as a part of the lower conductive layer 20 by the same material and the same process as the scanning line 21 and the like, and an additional process for the patch part 23 is unnecessary. Therefore, there is no need to add a step of forming a conductive film using a conductive paste separately during or after the process as in the prior art, and it is possible to suppress an increase in tact time and manufacturing cost.

  In addition, the patch portion 23 can be formed so as to overlap the signal line 51, and it is not necessary to provide a conductive paste film through the gap between the scanning line 21 and the signal line 51 as in the prior art. Therefore, the wiring density does not become too high, and the occurrence of defects such as a short circuit can be suppressed.

  Furthermore, the conventional disconnection and short-circuit correction using a laser is possible when the substrate 11 is made of glass, but when the substrate 11 is made of plastic, the plastic is heated. Cannot be used due to damage. The effect is particularly great in the case of colored plastics. On the other hand, in the present embodiment, it is possible to repair the disconnected portion 51A without using a laser, which is suitable when the substrate 11 is made of plastic.

  In addition, when repairing with a conductive paste or laser melt as in the past, the conductive paste location or laser melt location is more likely to cause defects such as short-circuiting or disconnection than the original structure. There was a fear. In contrast, in the present embodiment, a planar opening 32 that matches the signal line 51 is formed, and the patch portion 23 is brought into contact with the signal line 51 in the opening 32 to form a double wiring. Yes. The patch part 23 is made of the same material as the scanning line 21 and the lower electrode 22 which are the original structure parts, unlike the conventional conductive paste part and laser melt part. Therefore, in the case where flexibility is provided by a flexible substrate 11 such as plastic, it is possible to suppress an increase in short circuit and disconnection, unlike conventional conductive paste locations and laser melt locations.

  Subsequently, as shown in FIG. 26, the uppermost conductive layer 70 including the passivation film 61, the planarizing film 62, and the pixel electrode 71 is formed in order on the upper conductive layer 50. As a result, the TFT array 12 shown in FIG. 2 is formed.

  Finally, as shown in FIG. 2, the display layer 13 is formed on the pixel electrode 71, and the transparent substrate 14 on which the counter electrode 15 is formed is disposed on the display layer 13. Thus, the display device 1 shown in FIGS. 1 to 5 is completed.

  In the display device 1, display is performed on the display layer 13 by an electrophoretic display body based on a video voltage applied between the pixel electrode 71 and the counter electrode 15.

  Here, the gate insulating film 30 is provided with an elongated rectangular opening 32 along the signal line 51. The opening 32 is closed by the patch portion 23 of the lower conductive layer 20, and the patch portion 23 and the signal line 51 are in contact with each other in the opening 32. Therefore, the inside of the opening 32 is a double wiring of the signal line 51 and the patch portion 23, and the disconnected portion 51 </ b> A of the signal line 51 is repaired by the patch portion 23. Therefore, even when the disconnection portion 51A occurs and the voltage is not normally applied to the signal line 51, the patch portion 23 serves as a bypass wiring, and the voltage is also applied after the disconnection portion 51A. Therefore, dot defects and line defects caused by the disconnected portion 51A are suppressed, and display quality is improved.

  As described above, in the present embodiment, the gate insulating film 30 is provided with the planar opening 32 that faces the signal line 51 and matches the signal line 51, and the opening 32 is formed in the patch portion 23 of the lower conductive layer 20. The patch part 23 and the signal line 51 are brought into contact with each other in the opening 32. Therefore, even when the signal line 51 has a disconnection 51 </ b> A, the disconnection 51 </ b> A can be repaired by the patch unit 23. Therefore, it is not necessary to provide a conductive paste film in the gap between the wirings as in the prior art, and it is possible to repair the disconnected portion 51A without excessively increasing the wiring density. In addition, defects such as short circuit and disconnection do not increase at the conductive paste location and the laser melt location as in the prior art, which is also suitable for providing flexibility by the flexible substrate 11.

  Further, the patch part 23 can be formed as a part of the lower conductive layer 20 by the same material and the same process as the scanning line 21 and the like, and an additional process for the patch part 23 is not necessary. Therefore, there is no need to add a step of forming a conductive film using a conductive paste separately during or after the process as in the prior art, and it is possible to suppress an increase in tact time and manufacturing cost.

(Application example)
Next, application examples of the display device according to the above embodiment will be described with reference to FIGS. The display device in the above embodiment can be applied to electronic devices in various fields such as a television device, a digital camera, a laptop personal computer, a mobile terminal device such as a mobile phone or a smartphone, or a video camera. In other words, this display device can be applied to electronic devices in various fields that display a video signal input from the outside or a video signal generated inside as an image or video.

(module)
The display device according to the above-described embodiment is incorporated into various electronic devices such as application examples 1 to 7 described later, for example, as a module illustrated in FIG. In this module, for example, an external connection terminal (not shown) is formed in the frame region 10B of the substrate 11 by extending the wiring. The external connection terminal may be provided with a flexible printed circuit (FPC) 81 for signal input / output.

(Application example 1)
FIG. 28A and FIG. 28B each illustrate the appearance of an electronic book to which the display device of the above embodiment is applied. The electronic book has, for example, a display unit 210 and a non-display unit 220, and the display unit 210 is configured by the display device of the above embodiment.

(Application example 2)
FIG. 29 illustrates an appearance of a smartphone to which the display device of the above embodiment is applied. This smartphone has, for example, a display unit 230 and a non-display unit 240, and the display unit 230 is configured by the display device of the above embodiment.

(Application example 3)
FIG. 30 illustrates an appearance of a television device to which the display device of the above embodiment is applied. This television apparatus has, for example, a video display screen unit 300 including a front panel 310 and a filter glass 320, and the video display screen unit 300 is configured by the display device of the above embodiment.

(Application example 4)
FIG. 31 shows the appearance of a digital camera to which the display device of the above embodiment is applied. The digital camera includes, for example, a flash light emitting unit 410, a display unit 420, a menu switch 430, and a shutter button 440, and the display unit 420 is configured by the display device of the above embodiment.

(Application example 5)
FIG. 32 illustrates the appearance of a notebook personal computer to which the display device of the above embodiment is applied. The notebook personal computer has, for example, a main body 510, a keyboard 520 for inputting characters and the like, and a display unit 530 for displaying an image. The display unit 530 is constituted by the display device of the above embodiment. Has been.

(Application example 6)
FIG. 33 shows the appearance of a video camera to which the display device of the above embodiment is applied. This video camera includes, for example, a main body 610, a subject photographing lens 620 provided on the front side surface of the main body 610, a start / stop switch 630 at the time of photographing, and a display 640. And this display part 640 is comprised by the display apparatus of the said embodiment.

(Application example 7)
FIG. 34 shows the appearance of a mobile phone to which the display device of the above embodiment is applied. For example, the mobile phone is obtained by connecting an upper housing 710 and a lower housing 720 with a connecting portion (hinge portion) 730, and includes a display 740, a sub-display 750, a picture light 760, and a camera 770. Yes. Of these, the display 740 or the sub-display 750 is configured by the display device of the above embodiment.

  Although the present disclosure has been described with reference to the embodiment, the present disclosure is not limited to the above-described embodiment, and various modifications can be made. For example, in the embodiment described above, the repair of the disconnection portion 21A of the scanning line 21 or the disconnection portion 51A of the signal line 51 of the TFT array 12 has been described as an example. It is also applicable to.

  Further, for example, the material and thickness of each layer described in the above embodiment, the film formation method and the film formation conditions are not limited, and other materials and thicknesses may be used, or other film formation methods and Film forming conditions may be used.

  Furthermore, in the above embodiment, the configurations of the display device 1 and the TFT array 12 are specifically described. However, it is not necessary to provide all the layers, and other layers may be further provided. For example, the source electrode 51S and the drain electrode 52D may be provided directly on the semiconductor layer 40 as shown in FIG. 5, but a connection hole (not shown) of an interlayer insulating film (not shown) may be provided if necessary. May be connected to the semiconductor layer 40.

  In addition, the present disclosure has described the case where the display layer 13 is configured by an electrophoretic display, but the display layer 13 may be an organic EL (Electroluminescence), liquid crystal, inorganic EL, or electrodeposition type. It is also possible to be constituted by other display bodies such as an electrochromic display body.

In addition, this technique can also take the following structures.
(1)
A first conductive layer;
An insulating film having a planar opening facing the first conductive layer facing at least a portion of the first conductive layer;
And a second conductive layer including a patch portion that closes the opening and is in contact with the first conductive layer in the opening.
(2)
The first conductive layer includes a first wiring,
The second conductive layer includes the patch part and a second wiring electrically separated from the patch part,
The thin film transistor array according to (1), wherein a double wiring of the first wiring and the patch portion is formed in the opening.
(3)
The first conductive layer is a lower conductive layer including a scanning line as the first wiring,
The thin film transistor array according to (2), wherein the second conductive layer is an upper conductive layer including the patch portion and a signal line as the second wiring.
(4)
The first conductive layer is an upper conductive layer including a signal line as the first wiring,
The thin film transistor array according to (2) or (3), wherein the second conductive layer is an uppermost conductive layer including the patch portion and a pixel electrode as the second wiring.
(5)
The first conductive layer is an upper conductive layer including a signal line as the first wiring,
The thin film transistor array according to (2) or (3), wherein the second conductive layer is a lower conductive layer including the patch portion and a scanning line as the second wiring.
(6)
The thin film transistor array according to any one of (2) to (5), wherein the opening and the patch portion are selectively provided in a portion where the disconnection portion of the first wiring is generated.
(7)
The thin film transistor array according to any one of (2) to (5), wherein the opening and the patch portion are arranged over the entire first wiring.
(8)
The thin film transistor array according to any one of (1) to (7), provided on a flexible substrate.
(9)
Forming a first conductive layer;
Forming an insulating film on the first conductive layer, and providing the insulating film with a planar opening corresponding to the first conductive layer opposite to at least a portion of the first conductive layer;
And forming a second conductive layer including a patch portion that closes the opening and contacts the first conductive layer in the opening on the insulating film.
(10)
The first conductive layer includes a first wiring,
The second conductive layer includes the patch part and a second wiring electrically separated from the patch part,
The method for manufacturing a thin film transistor array according to (9), wherein a double wiring of the first wiring and the patch portion is formed in the opening.
(11)
Forming a lower conductive layer including a scanning line as the first wiring as the first conductive layer;
An upper conductive layer including the patch portion and a signal line as the second wiring is formed as the second conductive layer. The method for manufacturing a thin film transistor array according to (10).
(12)
Forming an upper conductive layer including a signal line as the first wiring as the first conductive layer;
The uppermost conductive layer including the patch portion and the pixel electrode as the second wiring is formed as the second conductive layer. The method for manufacturing a thin film transistor array according to (10) or (11).
(13)
Forming a second conductive layer including a patch portion;
Forming an insulating film on the second conductive layer, and providing the insulating film with a planar opening corresponding to the patch portion, facing the patch portion;
Forming a first conductive layer on the insulating film that closes the opening and is in contact with the patch portion in the opening.
(14)
The first conductive layer includes a first wiring,
The second conductive layer includes the patch part and a second wiring electrically separated from the patch part,
The method of manufacturing a thin film transistor array according to (13), wherein a double wiring of the first wiring and the patch portion is formed in the opening.
(15)
Forming an upper conductive layer including a signal line as the first wiring as the first conductive layer;
A method of manufacturing a thin film transistor array according to (14), wherein a lower conductive layer including the patch portion and a scanning line as the second wiring is formed as the second conductive layer.
(16)
A thin film transistor array and a display layer;
The thin film transistor array
A first conductive layer;
An insulating film having a planar opening facing the first conductive layer facing at least a portion of the first conductive layer;
And a second conductive layer including a patch portion that closes the opening and contacts the first conductive layer in the opening.

  DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 11 ... Board | substrate, 12 ... TFT array, 13 ... Display layer, 14 ... Transparent substrate, 15 ... Counter electrode, 20 ... Lower conductive layer, 21 ... Scanning line, 21G ... Gate electrode, 22 ... Lower electrode, 23, 53, 72 ... patch part, 30 ... gate insulating film, 31, 32, 63 ... opening, 40 ... semiconductor layer, 50 ... upper conductive layer, 51 ... signal line, 51S ... source electrode, 52 ... upper electrode, 52D DESCRIPTION OF SYMBOLS ... Drain electrode 61 ... Passivation film | membrane 62 ... Flattening film | membrane 70 ... Uppermost conductive layer, 71 ... Pixel electrode, CS ... Capacitance element.

Claims (16)

A first conductive layer;
An insulating film having a planar opening facing the first conductive layer facing at least a portion of the first conductive layer;
And a second conductive layer including a patch portion that closes the opening and is in contact with the first conductive layer in the opening. The first conductive layer includes a first wiring,
The second conductive layer includes the patch part and a second wiring electrically separated from the patch part,
The thin film transistor array according to claim 1, wherein a double wiring of the first wiring and the patch portion is formed in the opening. The first conductive layer is a lower conductive layer including a scanning line as the first wiring,
The thin film transistor array according to claim 2, wherein the second conductive layer is an upper conductive layer including the patch portion and a signal line as the second wiring. The first conductive layer is an upper conductive layer including a signal line as the first wiring,
The thin film transistor array according to claim 2, wherein the second conductive layer is an uppermost conductive layer including the patch portion and a pixel electrode as the second wiring. The first conductive layer is an upper conductive layer including a signal line as the first wiring,
The thin film transistor array according to claim 2, wherein the second conductive layer is a lower conductive layer including the patch part and a scanning line as the second wiring. The thin film transistor array according to claim 2, wherein the opening and the patch portion are selectively provided in a portion where the disconnection portion of the first wiring is generated. The thin film transistor array according to claim 2, wherein the opening and the patch portion are disposed over the entire first wiring. The thin film transistor array according to claim 1, wherein the thin film transistor array is provided on a flexible substrate. Forming a first conductive layer;
Forming an insulating film on the first conductive layer, and providing the insulating film with a planar opening corresponding to the first conductive layer opposite to at least a portion of the first conductive layer;
And forming a second conductive layer including a patch portion that closes the opening and contacts the first conductive layer in the opening on the insulating film. The first conductive layer includes a first wiring,
The second conductive layer includes the patch part and a second wiring electrically separated from the patch part,
The thin film transistor array manufacturing method according to claim 9, wherein a double wiring of the first wiring and the patch portion is formed in the opening. Forming a lower conductive layer including a scanning line as the first wiring as the first conductive layer;
The method for manufacturing a thin film transistor array according to claim 10, wherein an upper conductive layer including the patch portion and a signal line as the second wiring is formed as the second conductive layer. Forming an upper conductive layer including a signal line as the first wiring as the first conductive layer;
The method of manufacturing a thin film transistor array according to claim 10, wherein an uppermost conductive layer including the patch portion and a pixel electrode as the second wiring is formed as the second conductive layer. Forming a second conductive layer including a patch portion;
Forming an insulating film on the second conductive layer, and providing the insulating film with a planar opening corresponding to the patch portion, facing the patch portion;
Forming a first conductive layer on the insulating film that closes the opening and is in contact with the patch portion in the opening. The first conductive layer includes a first wiring,
The second conductive layer includes the patch part and a second wiring electrically separated from the patch part,
The method of manufacturing a thin film transistor array according to claim 13, wherein a double wiring of the first wiring and the patch portion is formed in the opening. Forming an upper conductive layer including a signal line as the first wiring as the first conductive layer;
The method of manufacturing a thin film transistor array according to claim 14, wherein a lower conductive layer including the patch portion and a scanning line as the second wiring is formed as the second conductive layer. A thin film transistor array and a display layer;
The thin film transistor array
A first conductive layer;
An insulating film having a planar opening facing the first conductive layer facing at least a portion of the first conductive layer;
And a second conductive layer including a patch portion that closes the opening and contacts the first conductive layer in the opening.

Images