JP2013157563A - Method for manufacturing semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor element capable of more surely forming an insulating film pattern to detail.SOLUTION: A method for manufacturing a semiconductor element comprises the steps of: sticking a pattern resist 31 in which a pattern is formed to an insulating film 11 formed on one principal surface of a semiconductor substrate 2; and removing a part of the insulating film 11 exposed to the outside (insulating film molding step).

Description

  The present invention relates to a method for manufacturing a semiconductor element.

  With the miniaturization and high functionality of semiconductor elements, fine patterns are formed on semiconductor substrates using photolithography technology. This fine pattern is used for a pattern such as an insulating film or wiring.

  For example, the semiconductor element described in Patent Document 1 includes an integrated circuit, a connection pad connected to the integrated circuit, and an insulating film covering the integrated circuit and the connection pad on one main surface of the semiconductor wafer. Has been. In the insulating film, an opening for exposing the central portion of the connection pad is formed. The opening of the insulating film is formed by a photolithography technique.

  The photolithography technique is generally performed in the following procedure. That is, a resist solution is applied to an insulating film provided on the surface of a semiconductor substrate formed of silicon or the like. The resist solution is irradiated with light that passes through a photomask on which a predetermined pattern is formed. A patterned resist is formed on the insulating film by utilizing the fact that the solubility of the resist solution in the developer changes when the resist solution is irradiated with light. By etching after this, the insulating film exposed without being protected by the patterned resist is corroded, and the insulating film is formed in a predetermined pattern.

JP 2011-142247 A

  However, the photolithographic technique has complicated processing conditions and processes, and has a problem that the pattern is excessively lost when the resist solution is irradiated with light, or the pattern is insufficiently omitted. As a result, when etching is performed using a patterned resist, a defect may occur in the pattern of the insulating film.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a method of manufacturing a semiconductor element that can more reliably form an insulating film pattern in detail.

In order to solve the above problems, the present invention proposes the following means.
The method of manufacturing a semiconductor element of the present invention includes a resist attaching step of attaching a pattern resist having a pattern formed on an insulating film formed on one main surface of a semiconductor substrate, and a portion of the insulating film exposed to the outside. And an insulating film forming step for removing the film.
A pattern resist in which a pattern has been formed in advance can be accurately formed to a fine pattern as compared with a case where a resist is formed by a photolithography technique using a resist solution. Therefore, by using this pattern resist as a mask and removing the insulating film exposed to the outside by etching or the like, the pattern of the insulating film can be more reliably formed in detail.

In the method for manufacturing a semiconductor element, in the resist attaching step, the pattern resist formed on a base sheet is attached to the insulating film, and the base is formed from the pattern resist attached to the insulating film. It is more preferable to peel off the sheet.
According to the present invention, direct contact with the pattern resist can be suppressed, and the pattern resist can be handled integrally on the base sheet. As a result, the pattern resist can be easily attached to the insulating film.

In the method for manufacturing a semiconductor element, an adhesive layer is provided on a surface of the pattern resist opposite to the base sheet, and a bonding strength between the base sheet and the pattern resist is determined by the pattern resist and the pattern resist. More preferably, it is weaker than both the adhesive strength between the adhesive layer and the adhesive strength between the adhesive layer and the insulating film.
According to this invention, when the adhesive layer is attached to the insulating film and the base sheet is peeled off from the insulating film, the adhesive layer is attached to the insulating film and the pattern resist is attached to the adhesive layer due to the difference in adhesive strength. In the state, the base sheet and the pattern resist are separated. For this reason, a base sheet can be easily peeled off from the pattern resist affixed on the insulating film.

In the method for manufacturing a semiconductor element, the pattern resist is formed so as to be orthogonal to a surface of the insulating film to which the pattern resist is attached when the pattern resist is attached to the insulating film. More preferably, the insulating film is formed by using an etching solution in the insulating film forming step.
According to the present invention, when the insulating film is removed using the etching solution, the thickness of the etching solution adhering to the exposed insulating film becomes substantially uniform, so that the etching solution is almost uniformly formed on the exposed insulating film. Soak up. Therefore, the thickness of the insulating film remaining without being removed can be made substantially uniform.

In the method for manufacturing a semiconductor device, the pattern resist has an outer surface that is inclined so as to face a bonding surface to which the pattern resist is bonded in the insulating film when the pattern resist is bonded to the insulating film. In the insulating film forming step, it is more preferable to remove the insulating film using an etching solution.
According to the present invention, when the insulating film is removed using the etching solution, the thickness of the etching solution that adheres to the exposed insulating film becomes thinner as it approaches the pattern resist along the bonding surface. The closer to the resist, the smaller the amount of etchant that soaks into the exposed insulating film, and the more difficult the insulating film is removed. Thereby, the edge part of the insulating film remaining without being removed can be formed so as to become thinner toward the edge.

  According to the semiconductor element manufacturing method of the present invention, the pattern of the insulating film can be more reliably formed in detail.

It is a schematic sectional drawing which shows the semiconductor element manufactured by the manufacturing method which concerns on one Embodiment of this invention. It is a schematic sectional drawing which shows the state after a diffusion process in the manufacturing method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing which shows the state after the insulating film arrangement | positioning process in the manufacturing method of the same semiconductor element. It is sectional drawing of the pattern resist used at a resist sticking process in the manufacturing method of the same semiconductor element. It is sectional drawing explaining the state which has affixed the pattern resist at the resist affixing process in the manufacturing method of the same semiconductor element. It is a schematic sectional drawing which shows the state which apply | coated the etching liquid in the insulating film formation process in the manufacturing method of the same semiconductor element. It is a schematic sectional drawing which shows the state after an insulating film shaping | molding process in the manufacturing method of the same semiconductor element. In the manufacturing method of the same semiconductor device, it is a schematic sectional view showing the state after a mesa groove formation process. It is a schematic sectional drawing which shows the state after a surface treatment process in the manufacturing method of the same semiconductor element. FIG. 6 is a schematic cross sectional view showing a state after a solder layer forming step in the method for manufacturing a semiconductor element. It is a schematic sectional drawing which shows the state after a cutting process in the manufacturing method of the same semiconductor element. It is a schematic sectional drawing which shows the pattern resist used in the manufacturing method of the semiconductor element which concerns on the modification of one Embodiment of this invention. It is a schematic sectional drawing which shows the state after a resist sticking process in the manufacturing method of the same semiconductor element. It is a schematic sectional drawing which shows the state after an insulating film shaping | molding process in the manufacturing method of the same semiconductor element.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. Hereinafter, a case where the semiconductor element is a mesa diode will be described as an example.
As shown in FIG. 1, a mesa diode 1 according to this embodiment includes a semiconductor substrate 2, electrode layers 3 and 4 and solder layers 5 and 6 formed on both main surfaces 2a and 2b of the semiconductor substrate 2. And is generally configured.
The semiconductor substrate 2 has a first conductivity type (for example, n-type) semiconductor layer 21 (hereinafter referred to as an n-type semiconductor layer 21) opposite to the first conductivity type that forms one main surface 2 a of the semiconductor substrate 2. A second conductive type (for example, p-type) semiconductor layer 22 (hereinafter referred to as p-type semiconductor layer 22) and the other main surface 2b, and having a higher impurity concentration than the n-type semiconductor layer 21. It is configured so as to be sandwiched by a type semiconductor layer 23 (hereinafter referred to as a high concentration n-type semiconductor layer 23).

The impurity concentration of the n-type semiconductor layer 21 is, for example, 2 × 10 ¹⁴ atoms / cm ³ , and the impurity concentration of the p-type semiconductor layer 22 is, for example, 1 × 10 ¹⁹ atoms / cm ³ . Further, the high-concentration n-type semiconductor layer 23 is higher than the n-type semiconductor layer 21 and is, for example, 1 × 10 ¹⁹ atoms / cm ³ .
The semiconductor substrate 2 is formed, for example, in a rectangular shape in plan view, and a mesa groove 7 is formed on the outer peripheral edge of one main surface 2a thereof. The surface (inner surface) of the mesa groove 7 is curved and inclined in a concave shape from one main surface 2a of the semiconductor substrate 2 toward the side surface 2c. The junction interface (PN junction interface) between the n-type semiconductor layer 21 and the p-type semiconductor layer 22 is exposed on the surface of the mesa groove 7. In other words, the mesa groove 7 is formed deeper than the PN junction interface.

The surface of the mesa groove 7 is covered with a passivation film 8 made of glass or resin. The thickness of the passivation film 8 is substantially uniform. In the present embodiment, the passivation film 8 extends to the one main surface 2a of the semiconductor substrate 2 and covers the outer peripheral edge region of the one main surface 2a. In other words, the first electrode layer 3 and the solder layer 5 formed so as to overlap one main surface 2 a of the semiconductor substrate 2 are surrounded by the passivation film 8.
Further, a silicon oxide film 9 is formed in the outer peripheral edge region of the other main surface 2 b of the semiconductor substrate 2. Therefore, the second electrode layer 4 and the solder layer 6 formed to overlap the other main surface 2 b of the semiconductor substrate 2 are surrounded by the silicon oxide film 9.

Each electrode layer 3, 4 is configured by, for example, sequentially laminating a nickel silicide film (Ni—Si film) and a nickel plating layer on each main surface 2 a, 2 b of the semiconductor substrate 2.
The total thickness of the first electrode layer 3 and the solder layer 5 and the total thickness of the second electrode layer 4 and the solder layer 6 are the same as those of the passivation film 8 and the silicon oxide film 9, respectively. It is preferable to set it larger than the thickness.

Next, an example of a method for manufacturing the mesa diode 1 having the above configuration (hereinafter referred to as a manufacturing method) will be described.
When manufacturing the mesa diode 1, first, as shown in FIG. 2, a first surface 2 a of a first conductivity type (for example, n type) semiconductor substrate 2 is opposite to the first conductivity type. A second conductivity type semiconductor layer 22 (p-type semiconductor layer 22) is formed by diffusing two conductivity type (for example, p-type) impurities (diffusion process). Further, in the diffusion process of the present embodiment, the first conductivity type having a higher impurity concentration than the semiconductor substrate 2 is obtained by diffusing an impurity of the first conductivity type (n-type) into the other main surface 2 b of the semiconductor substrate 2. Semiconductor layer 23 (high-concentration n-type semiconductor layer 23) is formed.
The p-type semiconductor layer 22 is formed by disposing a sheet containing boron, aluminum, or the like on one main surface 2a of the semiconductor substrate 2 and baking it. On the other hand, the high-concentration n-type semiconductor layer 23 is formed by disposing and baking a sheet containing phosphorus or the like on the other main surface 2b of the semiconductor substrate 2.
The semiconductor substrate 2 after the diffusion step forms the same n-type semiconductor layer 21 as the semiconductor substrate 2 before the step, the p-type semiconductor layer 22 that forms one main surface 2a of the semiconductor substrate 2, and the other main surface 2b. The high-concentration n-type semiconductor layer 23 is sandwiched between them.

  After the diffusion step, as shown in FIG. 3, an insulating film 11 is formed on one main surface 2a of the semiconductor substrate 2 and an insulating film 12 is formed on the other main surface 2b (insulating film arranging step). The insulating films 11 and 12 are formed, for example, by heating and oxidizing the semiconductor substrate 2.

After the insulating film arranging step, a resist attaching step for attaching a pattern resist to the insulating films 11 and 12 is performed. The pattern resists 31 and 36 used in the resist attaching step will be described with reference to FIG.
The pattern resist 31 attached to the insulating film 11 is formed in a predetermined pattern on the base sheet 32, and an adhesive layer 33 is provided on the opposite side of the pattern resist 31 from the base sheet 32.
The pattern resist 31 can be formed using a known resin or the like. The pattern resist 31 does not need photosensitivity.
For the base sheet 32, it is preferable to use a sheet-like resin having a certain elastic modulus. This is for preventing the shape of the pattern resist 31 from being distorted.
An adhesive (not shown) is provided between the base sheet 32 and the pattern resist 31.

As shown in the enlarged view in FIG. 4, the pattern resist 31 is affixed to the affixing surface 11 a that is the outer surface of the insulating film 11. The outer surface 31a of the pattern resist 31 is formed to be orthogonal to the attachment surface 11a when the pattern resist 31 is attached to the attachment surface 11a via the adhesive layer 33. That is, the angle θ1 formed by the pasting surface 11a and the outer surface 31a is 90 °.
In this case, the adhesive layer 33 is provided on the pattern resist 31. Specifically, the angle θ1 is set to 90 ° by setting the angle formed by the adhesive surface 33a of the adhesive layer 33 and the outer surface 31a to 90 °. ° can be.
The bonding strength between the base sheet 32 and the pattern resist 31 by the adhesive per unit bonding area is any of the bonding strength between the pattern resist 31 and the bonding layer 33 and the bonding strength between the bonding layer 33 and the insulating film 11. Is set too weak.
The patterns formed on the pattern resists 31 and 36 are the same as the patterns to be formed on the insulating films 11 and 12, respectively.

The pattern resist 36 attached to the insulating film 12 is also formed in a predetermined pattern on the base sheet 37 and is used in a state where the adhesive layer 38 is provided on the opposite side of the pattern resist 36 from the base sheet 37. .
The pattern resist 36, the base sheet 37, and the adhesive layer 38 are formed in the same manner as the pattern resist 31, the base sheet 32, and the adhesive layer 33, respectively.

In the resist attaching process performed using the pattern resists 31 and 36 configured as described above, the adhesive layer 33 is attached to the attaching surface 11a of the insulating film 11 by handling the base sheet 32 as shown in FIG. Then, the base sheet 32 is peeled off from the pattern resist 31 attached to the insulating film 11 via the adhesive layer 33.
Similarly, for the pattern resist 36, the adhesive layer 38 is attached to the insulating film 12, and the base sheet 37 is peeled off from the pattern resist 36 attached to the insulating film 12 via the adhesive layer 38.
As a result, as shown in FIG. 6, the pattern resist 31 is attached to one main surface 2a of the semiconductor substrate 2 and the pattern resist 36 is attached to the other main surface 2b.

Subsequent to the resist attaching step, the exposed portions of the insulating films 11 and 12 are removed (insulating film forming step). Specifically, the insulating films 11 and 12 are removed by a known wet etching method using the etching solution L.
In this case, since the angle θ1 formed between the pasting surface 11a and the outer surface 31a is 90 °, the thickness T1 of the etching solution L is substantially uniform on the insulating film 11 side.
Etching solution L soaks into the exposed insulating films 11 and 12 almost uniformly, and the insulating films 11 and 12 become insulating film patterns 11A and 12A in which a predetermined pattern is formed as shown in FIG. The insulating film pattern 11A has a substantially uniform thickness.

The insulating film patterns 11A and 12A formed as described above will be described in detail. The insulating film pattern 11A formed on one main surface 2a of the semiconductor substrate 2 is a pattern (for mesa groove formation) for forming a mesa groove 7 (see FIG. 8) on one main surface 2a of the semiconductor substrate 2. Pattern).
On the other hand, the insulating film pattern 12A formed on the other main surface 2b of the semiconductor substrate 2 is used for cutting when the semiconductor substrate 2 is cut and divided into element units (see FIG. 1) in a cutting process described later. It is a pattern (pattern for cutting guides) for functioning as a guideline.
The insulating film pattern 12 </ b> A is formed at a position that overlaps the region where the mesa groove 7 is to be formed and the thickness direction of the semiconductor substrate 2, and divides the other main surface 2 b of the semiconductor substrate 2 into a plurality of regions. The insulating film pattern 12A becomes the silicon oxide film 9 in the mesa diode 1 shown in FIG.

After the insulating film forming step, as shown in FIG. 8, a plurality of mesa grooves 7 are formed on one main surface 2 a of the semiconductor substrate 2 at intervals, and one main surface 2 a is formed by the plurality of mesa grooves 7. Is divided into a plurality of regions (mesa groove forming step).
In this step, an arbitrary etching method such as dry etching or wet etching is performed using the insulating film pattern 11A and the pattern resist 31 laminated on one main surface 2a of the semiconductor substrate 2 as a mask, thereby A plurality of mesa grooves 7 are formed on one main surface 2a.

In this step, the mesa groove 7 is formed to be recessed from one main surface 2a of the semiconductor substrate 2, and is deeper than the junction interface (PN junction interface) between the n-type semiconductor layer 21 and the p-type semiconductor layer 22. Formed to be. That is, in the state after the above process, the PN junction interface is exposed on the inner surface of the mesa groove 7.
The mesa groove 7 formed as described above forms an outer peripheral edge of one main surface 2a of the semiconductor substrate 2 (see FIG. 1) divided into element units. That is, the mesa groove 7 is formed so as to overlap the insulating film pattern 12 </ b> A on the other main surface 2 b of the semiconductor substrate 2 in the thickness direction of the semiconductor substrate 2.
In the present embodiment, the pattern resists 31 and 36 are removed after the mesa groove forming step. However, for example, the pattern resists 31 and 36 may be removed before the mesa groove forming step or after a surface treatment step described later.

Thereafter, as shown in FIG. 9, a passivation film 8 made of glass, resin, or the like is deposited on the inner surface of the mesa groove 7 (surface treatment step). In this step, the passivation film 8 is formed on the inner surface of the mesa groove 7 so that the thickness thereof is substantially uniform. Therefore, the hollow shape of the mesa groove 7 is maintained even after the surface treatment process. In the illustrated example, the passivation film 8 is formed not only on the entire inner surface of the mesa groove 7 but also on the peripheral edge of the opening of the mesa groove 7 in one main surface 2a of the semiconductor substrate 2, but the passivation film 8 is at least What is necessary is just to form so that the PN junction interface exposed to the inner surface of the mesa groove | channel 7 may be covered.
Then, after this surface treatment step, the insulating film pattern 11A, the pattern resists 31, 36, and the adhesive layers 33, 38 are removed.

  Thereafter, as shown in FIG. 10, the first electrode layer 3 is formed in each of a plurality of regions of the one main surface 2a of the semiconductor substrate 2 defined by the mesa groove 7, and the other electrode partitioned by the insulating film pattern 12A is formed. Second electrode layer 4 is formed in each of a plurality of regions of main surface 2b (electrode layer forming step). These electrode layers 3 and 4 can be formed by performing various plating methods, annealing treatments, sintering treatments, and the like.

For example, when each of the electrode layers 3 and 4 is composed of a nickel silicide film and a nickel plating layer as described above, in the electrode layer forming step, first, both main surfaces 2a and 2a of the semiconductor substrate 2 are formed by electroless plating. A primary nickel plating layer is formed on 2b. Next, by performing an annealing process, the semiconductor substrate 2 and the primary nickel plating layer react to form a nickel silicide film in an interface region between the semiconductor substrate 2 and the primary nickel plating layer. In addition, after completion | finish of annealing, a nitric acid boil process etc. are implemented and an unnecessary primary nickel plating layer is removed.
Then, the formation of the electrode layers 3 and 4 is completed by forming a secondary nickel plating layer on each nickel silicide film by plating. The secondary nickel plating layer described above corresponds to the nickel plating layer in each of the electrode layers 3 and 4.

After this electrode layer forming step, solder layers 5 and 6 are respectively formed on the plurality of first electrode layers 3 and second electrode layers 4 (solder layer forming step).
The solder layers 5 and 6 can be formed by a method such as screen printing.

Subsequent to the solder layer forming step, as shown in FIG. 11, the semiconductor substrate 2 is cut so as to pass through the bottom of the mesa groove 7 and the insulating film pattern 12A, and the semiconductor substrate 2 is divided into element units. Thus, the mesa diode 1 is obtained.
In this cutting step, for example, using the insulating film pattern 12A formed on the other main surface 2b of the semiconductor substrate 2 as a guideline, the laser is directed from the other main surface 2b side of the semiconductor substrate 2 toward the bottom of the mesa groove 7. Cut (laser scribe), dicing, or the like may be performed.
In the cutting process, only laser cutting or dicing may be performed, but for example, after cutting a groove that does not reach the bottom of the mesa groove 7 on the other main surface 2b side by laser cutting or dicing, braking is performed. You may implement.
The mesa diode 1 is manufactured by the steps described so far.

  As described above, according to the manufacturing method of the present embodiment, the pattern resist 31 on which the pattern has been formed in advance is accurately formed to a fine pattern as compared with the conventional method of forming a resist by photolithography technology. be able to. Therefore, when the insulating film pattern 11A is formed by removing the insulating film 11 exposed to the outside by an etching method or the like using the pattern resist 31 as a mask in the insulating film forming step, the shape of the insulating film pattern 11A is detailed. It can form more reliably.

In the resist attaching process, since the pattern resist 31 is attached to the insulating film 11 using the base sheet 32, direct contact with the pattern resist 31 is suppressed, and the pattern resist 31 is handled integrally on the base sheet 32. Can do. Thereby, the pattern resist 31 can be easily attached to the insulating film 11.
The bonding strength between the base sheet 32 and the pattern resist 31 is weaker than both the bonding strength between the pattern resist 31 and the adhesive layer 33 and the adhesive strength between the adhesive layer 33 and the insulating film 11. When the adhesive layer 33 is attached to the insulating film 11 and the base sheet 32 is peeled off from the insulating film 11, the adhesive layer 33 is attached to the insulating film 11 and the pattern resist 31 is attached to the adhesive layer 33 due to the difference in adhesive strength. In the attached state, the base sheet 32 and the pattern resist 31 are separated. For this reason, the base sheet 32 can be easily peeled off from the pattern resist 31 attached to the insulating film 11.

  The pattern resist 31 has an outer surface 31a orthogonal to the attachment surface 11a when attached to the attachment surface 11a of the insulating film 11. Thus, when the insulating film 11 is removed using the etching liquid L, the thickness T1 of the etching liquid L deposited on the exposed insulating film 11 becomes almost uniform regardless of the location, and the exposed insulating film 11 The etchant L penetrates almost uniformly. Therefore, the thickness of the formed insulating film pattern 11A can be made substantially uniform.

As mentioned above, although one Embodiment of this invention was explained in full detail with reference to drawings, the concrete structure is not restricted to this Embodiment, The change of the structure of the range which does not deviate from the summary of this invention, etc. are included. .
For example, a pattern resist 46 as shown in FIG. 12 may be used in the resist attaching step of the above embodiment.
The pattern resist 46 has an outer surface 46 a that is inclined so as to face the attachment surface 11 a when attached to the attachment surface 11 a of the insulating film 11. That is, the angle θ2 formed by the pasting surface 11a and the outer surface 46a is an acute angle.
In this case where the adhesive layer 33 is provided on the pattern resist 46, specifically, the angle θ2 is made acute by making the angle formed by the adhesive surface 33a of the adhesive layer 33 and the outer surface 46a acute. can do.

The manufacturing method using the pattern resist 46 configured in this way is the same as the manufacturing method of the present embodiment described above, but the shape of the pattern resist 46 to be used is changed, so that the resist attaching step and the insulating film forming step are performed. Is as follows.
In the resist affixing step, the base sheet 32 is handled, so that the adhesive layer 33 is affixed to the affixing surface 11a of the insulating film 11 and is affixed to the insulating film 11 via the adhesive layer 33 as shown in FIG. The base sheet 32 is peeled off from the pattern resist 46.

In the insulating film forming process performed subsequent to the resist attaching process, a portion of the insulating film 11 exposed to the outside is removed by a known wet etching method using an etching solution L.
In this case, since the angle θ2 formed between the pasting surface 11a and the outer surface 46a is an acute angle, the thickness T2 of the etching solution L in the insulating film forming step becomes closer to the pattern resist 46 along the pasting surface 11a. getting thin. The closer to the pattern resist 46, the smaller the amount of the etching solution L that permeates into the exposed insulating film 11 and the more difficult the insulating film 11 is removed, so that the edge of the formed insulating film pattern 11B becomes as shown in FIG. , It is formed so as to become thinner toward the edge 11c.

In the embodiment, when the strength of the pattern resist 31 is relatively high, the pattern resist 31 may be directly attached to the insulating film 11 without using the base sheet 32 in the resist attaching step.
Although the semiconductor element is a mesa diode, the present invention is not limited to this, and the present invention can be applied to a thyristor or a planar semiconductor element.

  In the mesa diode manufacturing method similar to FIG. 1, when the insulating film 11 is not required, the insulating film 11 is interposed on one main surface 2a of the semiconductor substrate 2 after diffusion shown in FIG. It is also possible to attach the pattern resist 31 without performing the above-described mesa groove forming step.

1 Mesa diode (semiconductor element)
2 Semiconductor substrate 2a One main surface 11 Insulating film 11a Attached surface 31, 46 Pattern resist 31a, 46a Outer surface 32 Base sheet 33 Adhesive layer L Etching solution

Claims (5)

A resist attaching step of attaching a pattern resist in which a pattern is formed to an insulating film formed on one main surface of the semiconductor substrate;
An insulating film forming step of removing a portion of the insulating film exposed to the outside;
The manufacturing method of the semiconductor element characterized by the above-mentioned. In the resist pasting step,
The semiconductor device according to claim 1, wherein the pattern resist formed on a base sheet is attached to the insulating film, and the base sheet is peeled off from the pattern resist attached to the insulating film. Method. An adhesive layer is provided on the surface of the pattern resist opposite to the base sheet,
The bonding strength between the base sheet and the pattern resist is weaker than any of an adhesive strength between the pattern resist and the adhesive layer and an adhesive strength between the adhesive layer and the insulating film. 2. A method for producing a semiconductor device according to 2. The pattern resist has an outer surface formed so as to be orthogonal to an attachment surface to which the pattern resist is attached in the insulating film when the pattern resist is attached to the insulating film.
4. The method of manufacturing a semiconductor element according to claim 1, wherein in the insulating film forming step, the insulating film is removed using an etching solution. 5. The pattern resist has an outer surface that is inclined so as to face a pasting surface to which the pattern resist is pasted in the insulating film when pasted to the insulating film,
4. The method of manufacturing a semiconductor element according to claim 1, wherein in the insulating film forming step, the insulating film is removed using an etching solution. 5.

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