JP2013051022A - Recording medium, reproduction and recording method, reproduction and recording device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an expanded address without altering the bit number of an address which is embedded in a wobble.SOLUTION: Provided is a method of reproducing data from a recording medium or recording data on the recording medium. The recording medium has an address which is recorded by being wobbling-superimposed on a track on which data is recorded in synchronization with a cluster. The address has a virtual bit which serves as address information which is not recorded on the recording medium in part of the address. An address which has been subjected to an encoding process such that the virtual bit is restored is recorded on the recording medium. A data position is detected with the address from which the virtual bit has been restored by a decoding process, for the reproduction and the recording.

Description

  The present invention relates to a recording medium on which an address is recorded, for example, an optical disc, an optical disc reproducing and recording method, a reproducing apparatus for recording and reproducing data from the recording medium, and a recording apparatus.

  FIG. 6 of Patent Document 1 shows the correlation of the address information of the Blu-ray Disc, and the description “paragraph [0010]“ address unit number (AUN) is the physical sector number and the sector number as shown in FIG. It is useful as reference information for searching for a recording position because it is linked and linked with a physical address in pre-groove (ADIP) address. " According to the figure, regarding the relationship between the physical sector number (PSN) assigned to one sector data and the physical ADIP address (PAA) embedded in the wobble, 32 * Although PSN = 3 * PAA, 5 bits from PSN bit 31 to bit 27 are not assigned bits corresponding to PAA.

JP 2008-41243 A

  In the bit allocation as in Patent Document 1, if the PSN is larger than the conventional data amount expressed by 27 bits, the number of PAA bits to be embedded in the wobble becomes insufficient. In addition, when the number of bits of PAA is expanded, the wobble address structure must be significantly modified.

  An object of the present invention is to provide a recording medium, an address generation and detection method, a reproduction and recording apparatus capable of extending a wobble address without implementing a significant wobble structure modification.

  In order to solve the above problem, a virtual bit that is not recorded on the disc is generated, which is represented by the presence or absence of information embedded in part or all of the wobble address and the difference in rules.

  According to the present invention, it is possible to extend the address while maintaining the bit structure of the conventional wobble address structure.

FIG. 3 is a correlation diagram of addresses of the multilayer optical disc that is the first embodiment of the present invention. FIG. 3 is a timing diagram of address detection in the first exemplary embodiment of the present invention. FIG. 3 is a detection circuit diagram of address detection in the first exemplary embodiment of the present invention. FIG. 6 is a correlation diagram of addresses of a multilayer optical disc that is a second embodiment of the present invention. FIG. 6 is a timing diagram of address detection in the second embodiment of the present invention. FIG. 6 is a detection circuit diagram for address detection in a second exemplary embodiment of the present invention. FIG. 6 is a correlation diagram of addresses of a multilayer optical disc that is a third embodiment of the present invention. 6 is an example of a scramble circuit according to a third embodiment of the present invention. FIG. 10 is a timing diagram of address detection in a third embodiment of the present invention. FIG. 10 is a detection circuit diagram for address detection in a third exemplary embodiment of the present invention. FIG. 10 is a correlation diagram of addresses of an optical disc that is a fourth embodiment of the present invention. 1 is an optical disc recording / reproducing apparatus according to a first embodiment of the present invention. It is an address field structure figure of a multilayer optical disk. It is a data structure of a multilayer optical disk, an ECC structure, and a frame structure diagram. It is an ADIP data structure figure of a multilayer optical disk. It is an ADIP word structure figure of a multilayer optical disk. It is an ADIP Aux frame structure figure of a multilayer optical disk. FIG. 10 is an address correlation diagram of an optical disc that is a fifth embodiment of the present invention. FIG. 10 is a timing diagram of address detection in the fifth exemplary embodiment of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a correlation diagram of addresses of a multilayer optical disk according to the first embodiment of the present invention. 101 is the physical sector number (hereinafter referred to as PSN) which is the physical sector number of the sector, 102 is the address unit number (hereinafter referred to as AUN) which is the address embedded in the data of the cluster unit, and 103 is the physical ADIP address by wobble Is the actual address of the physical ADIP address (hereinafter referred to as PAA), 104 is the address actually embedded in the wobble of the physical ADIP address (hereinafter referred to as PAAW), 105 is the scramble circuit, and 106 is the exclusive OR (Ex-OR) Show. Here, scramble is one of arithmetic processes, and means a process for converting the value of each bit of an address or converting regularity. An example is shown in which the upper 3 bits of PAA 103 are assigned to the layer number, and 1-bit address expansion is performed from the conventional PAA 24 bits. Also, the bit information of PAA bit 24, which is a virtual bit for address extension, is assumed to be embedded in wobble in association with the lower 2 bits of PAA. In a conventional PAA 24-bit configuration, when assigned as a 3-bit layer number, 19-bit cluster number, and 2-bit intra-cluster count value, up to 8 layer numbers and 32 gigabytes per layer (64 kilobytes x 2 ¹⁹ ) An address can be assigned to data having a data capacity of. However, in the case of a high-density optical disk that exceeds 32 GB per layer, it is possible to assign addresses to data with a data capacity of 64 GB (64 KB x 2 ²⁰ ) per layer by extending the cluster number to 20 bits. However, since the layer number bit is reduced to 2 bits, it becomes impossible to generate addresses for 5 layers or more. Therefore, the layer number is expanded by 1 bit, and addresses up to 8 layers are generated with 3 bits equivalent to the conventional one.

  Here, the wobble address structure will be described. As shown in the ADIP data structure diagram of Fig. 15, the ADIP address 24 bits (AA23-AA0) 104 recorded on the disc and the 12-bit auxiliary data (AUX data, AX11-AX0) 1301 for storing disc information are 36 bits. A structure having information bits is defined, and an error correction code addition and code conversion are performed on the information bits to generate a code string per unit data. This code string is embedded in the wobble structure per unit period. A wobble structure with different wobble periodicity and phase is arranged based on certain rules, and a bit structure called ADIP unit is generated by expressing synchronization signals and data “0” and “1” due to the difference in arrangement etc. To do. Therefore, as shown in the ADIP word structure diagram of Fig. 16, the data after the ADIP data 36 bit error correction code addition conversion to the 60 bits of data (4 ADIP bit × 15 Block) in the structure of 1 ADIP word composed of 83 bits. A code string having a value of 60 bits is arranged. In addition, as shown in Fig. 17, auxiliary data is composed of 96 words of 12-bit data structure and rearranged to form 144 bytes (12 bits x 96 words), and data indicating disk information and error correction codes are arranged. Is done. It should be noted that the wobble length is such that one ADIP address (PAA) is obtained in 1/3 cycle of the data length of one cluster (32 * PSN) so that the relationship of 32 * PSN = 3 * PAA. Since the address structure is generated, it is possible to obtain an ADIP address that specifies a physical position on the disk by converting a code string obtained with a certain period of wobble. Therefore, the ADIP address recorded on the disc is 24 bits to the last, and when the bit number of the ADIP address is increased by 1 bit, the wobble address structure needs to be significantly modified. Either a 36-bit information bit structure, a parity addition method or conversion method for conversion into a code string, an arrangement period or wobble length, a correlation with a PSN, or a plurality of reviews is required. In this case, the structure becomes difficult to be compatible with the prior art, and the redundancy of the address generation / detection circuit and the complexity of the system control method become problems. Therefore, if the wobble address can be expanded without significantly modifying the wobble structure without changing the number of address bits embedded in the wobble, the control can be considerably facilitated.

  The address generation method shown in FIG. 1 will be described below. In the address range of PSN 28 bits (the remaining 4 bits are unused), PAA 25 bits are allocated as the address range on the wobble. However, if the ADIP structure as shown in Fig. 15 is maintained, the number of bits of the address embedded in the disk using wobble is only 24 bits, so the most significant PAA bit 24 is information to other bits as a virtual address bit. Embed. In this embodiment, the PAA bit 24 is input as a control bit for determining ON / OFF of the scramble process of the scramble circuit 105, and the lower 2 bits of the PAA bits 1-0 are subjected to the scramble process and embedded in the wobble. As an example of a scramble circuit that is an arithmetic processing for embedding information, when the method using the exclusive OR 106 is used, when the PAA bit 24 is “0”, the PAA bits 1-0 are 0,1 as in the prior art. , 2,0,1,2, ... and when PAA bit 24 is “1”, the value after exclusive OR operation is 3,2,1,3,2,1,… Will be counted. That is, according to the virtual bit PAA bit 24, the regularity of the count of the PAA bits 1-0 is changed. Therefore, the PAAW bits 1-0 that are the output from the scramble circuit 105 are actually embedded in the wobble so that the virtual bit PAA bit 24 is not embedded in the wobble. As an effect, it is possible to extend the address while maintaining the number of bits of the conventional wobble address.

  Next, a method for detecting the address PAAW embedded in the wobble will be described using an example of the timing diagram of FIG. 2 and the detection circuit diagram of FIG. As a wobble address detection method, in consideration of erroneous detection and non-detection, addresses are generated by protection by continuously detecting addresses. Therefore, the continuity of the lower addresses of PAAW bits 1-0 is checked, and PAA bit 24, which is a virtual bit, is restored. The lower continuity detection circuit 304 in FIG. 3 receives the address PAAW bits 1-0 detected from the wobble and the address bits 1-0 descrambled by the descrambling circuit 301. Since the descramble circuit 301 is scrambled by the exclusive OR 106 at the time of address generation, the result of the exclusive OR of “1” and the PAAW bits 1-0 is output after the descrambling operation. Since the virtual bit PAA bit 24 is assigned to the third bit of the layer number, the detection result varies depending on the layer number 0 to 3 (201) and the layer number 4 to 7 (202). Become. In the case of layer numbers 0 to 3 (201), the PAAW bit 1-0 is input to the lower continuity detection circuit 304 as 0, 1, 2, 0, 1, 2,. ", PAA bits 1-0 output the PAAW bits 1-0 as they are. On the other hand, in the case of layer numbers 4 to 7 (202), the PAAW bits 1-0 are input to the lower continuity detection circuit 304 as 3, 2, 1, 3, 2, 1,. Here, by detecting the detection value “3” of the address and decrementing the continuity, it is detected that there is a scramble process at the time of address generation, and the PAA bit 24 is output as “1”. For the lower PAA bits 1-0, 0, 1, 2, 0, 1, 2,..., Which are values after descrambling of the PAAW bits 1-0 are output. As a result, the count value in the cluster (PAA bits 1-0) is detected as the output of the lower continuity detection circuit 304, and further, the layer number detection circuit 302 from the generated PAA bits 24 and PAAW bits 23-22 detected from the wobble. 1 generates a layer number address (PAA bits 24-22) and detects a layer number. Further, in the higher address detection circuit 303, the cluster number address (PAA bits 21-2) is generated and the cluster number is detected from the PAAW bits 21-2 detected from the wobble. Therefore, the addresses obtained from the respective detection circuits 302, 303, and 304 can be input to the PAA address generation circuit 305 and converted into addresses of PAA bits 24-0.

  As described above, by generating an address by embedding virtual bits as information in other bits and restoring the address at the time of detection, the address structure of the wobble is not changed, and the physical address is not increased without increasing the number of bits of the address embedded in the wobble. The number of bits of the address indicating the target position can be expanded. In the physical ADIP address on Blu-ray Disc, if the layer number address is extended with virtual bits as the address assignment of the 2-bit layer number and the 20-bit cluster number, the layer number up to 8 layers and up to 64 GB Applicable to disk. Similarly, it can be applied to disks with up to 16 layer numbers and 32 gigabytes per layer if used to expand the layer number address with the conventional 3-bit layer number and 19-bit cluster number address assignment. . In addition, since virtual bits are controlled as scramble processing OFF in the case of layer numbers 0 to 3 as in the present embodiment, the result is the same value as PAA bit 23-0 and PAAW bit 23-0. Compatibility with conventional optical discs can be maintained.

  FIG. 12 shows an example of a recording / reproducing apparatus that reproduces data from and records data from the optical disk created by the address generation described in this embodiment. Reference numeral 1201 denotes an optical disc, 1202 denotes a pickup, 1203 denotes a spindle motor, 1204 denotes an address reproduction circuit, 1205 denotes a data recording / reproduction circuit, 1206 denotes an external host, and 1207 denotes a microcomputer that controls the entire system. A wobble signal read from the optical disk 1201 created using the address generation method shown in FIG. 1 via the pickup 1202 is input to the address reproduction circuit 1204 to detect address information. Thus, by using the address detection circuit described with reference to FIG. 3, it is possible to detect the position where data is recorded / reproduced, and to the host 1206 of the data obtained via the pickup 1202 and the data recording / reproduction circuit 1205. Data input / output and data recording / reproduction are possible.

  FIG. 4 is a correlation diagram of addresses of the multilayer optical disk according to the second embodiment of the present invention. As in the first embodiment, address expansion is performed using virtual bits that are not recorded on the disk while maintaining the ADIP data structure shown in FIG. The difference from FIG. 1 is that the virtual bit allocation is bit 21 instead of PAA bit 24. 401 is the actual address of Physical ADIP Address (hereinafter referred to as PAA), 402 is the wobble embedded address of Physical ADIP Address (hereinafter referred to as PAAW), which is the same as in FIG. 1, but only the bit assignment is different, and the other is the same. As an address generation method, as in the first embodiment, PAA bit 21 is input as a control bit for determining ON / OFF of scramble processing of scramble circuit 105, and scramble processing is performed on lower two bits of PAA bits 1-0. And embed in wobble. That is, according to the virtual bit PAA bit 21, the regularity of the count of PAA bits 1-0 is changed. As an effect, it is possible to extend the address while maintaining the number of bits of the conventional wobble address.

  A method for detecting the address PAAW embedded in the wobble will be described with reference to an example of a timing diagram in FIG. 5 and a detection circuit diagram in FIG. In the present embodiment, since the virtual bit PAA bit 21 is assigned not to the layer number address but to the cluster number address, switching of address generation occurs in each layer. In addition, as a scramble method that is an operation process for embedding information, since the lower two bits of PAA bits 1-0 are multiplied by exclusive OR 106, the lower continuity detection circuit 304 detects the presence or absence of scramble processing as before. To generate a virtual bit PAA bit 21 and detect PAA 1-0. As a result, the count value in the cluster (PAA bits 1-0) is detected as the output of the lower continuity detection circuit 304. Further, the PAA bit 21 detected from the lower continuity detection circuit 304 and the PAAW bit 20- 2 is used to generate the cluster number address (PAA bits 21-2), detect the cluster number, and use the PAAW bits 23-22 detected from the wobble to generate the layer number address (PAA bits 24- 22) Detection is performed. Therefore, the addresses obtained from the respective detection circuits 302, 303, and 304 can be input to the PAA address generation circuit 305 and converted into addresses of PAA bits 24-0.

  As described above, by generating an address by embedding virtual bits as information in other bits and restoring the address at the time of detection, the address structure of the wobble is not changed, and the physical address is not increased without increasing the number of bits of the address embedded in the wobble. The number of bits of the address indicating the target position can be expanded. Unlike the first embodiment, the virtual bit can be generated and detected in the same manner even if the virtual bit is assigned to the cluster number address of each layer instead of the layer number. Similarly to FIG. 12, the address detection circuit described in FIG. 6 is also used in the reproducing apparatus for reproducing data from the optical disk created by the address generation described in this embodiment and the recording apparatus for recording data on the optical disk. This makes it possible to detect the position where data is recorded and reproduced.

  FIG. 7 is a correlation diagram of addresses of the multilayer optical disk according to the third embodiment of the present invention. As in the first embodiment, address expansion is performed using virtual bits that are not recorded on the disk while maintaining the ADIP data structure shown in FIG. The difference from FIG. 1 is that the scrambling method is applied not only to the lower two bits of PAA bits 1-0 but also to the PAA 23-0 of the entire bits. 701 is the actual address of Physical ADIP Address (hereinafter referred to as PAA), 702 is the wobble embedded address (hereinafter referred to as PAAW) of Physical ADIP Address, and 703 is a scramble circuit similar to FIG. 1, but only the bit allocation is different, and the others are the same And As an address generation method, FIG. 8 shows an example of a scramble circuit 703 which is a calculation process for embedding information. In the case of FIG. 8, the exclusive OR 106 with the PAA bit 24 is used for each bit of the PAA bit 21-2 corresponding to the cluster number address, and the other bits are input / output as they are. Therefore, when PAA bit 24 is “0”, PAA bit 21-2 is incremented to 0,1,2,3,4,5, ..., FFFFFh, and PAA bit 24 is “1”. In this case, since it is a value after the scramble processing, it is decremented to FFFFFh, FFFFEh, FFFFDh,. That is, according to the virtual bit PAA bit 24, the regularity of the count of the PAA bits 21-2 is changed. As an effect, it is possible to extend the address while maintaining the number of bits of the conventional wobble address.

  A method for detecting the address PAAW embedded in the wobble will be described with reference to the timing diagram of FIG. 9 and an example of the detection circuit diagram of FIG. In this embodiment, the PAA bit 24, which is a virtual bit, is restored by checking the continuity of the higher address of the PAAW bits 21-2. Also, as the scrambling method, since the upper 20 bits of PAA bits 21-2 are multiplied by exclusive OR 106, the presence or absence of scrambling in the upper continuity detection circuit 303 (in this example, the difference in continuity between increment and decrement) ) To generate a virtual bit PAA bit 24 and detect PAA 21-2. In the case of layer numbers 0 to 3 (901), PAAW bit 21-2 is input as 0,1,2,3,4,5, ..., FFFFFh to upper continuity detection circuit 303, so PAA bit 24 is “0”, PAA bit 21-2 outputs PAAW bit 21-2 as it is. On the other hand, in the case of layer numbers 4 to 7 (902), the PAAW bit 21-2 is input to the upper continuity detection circuit 303 as FFFFFh, FFFFEh, FFFFDh, ..., 0, so the decrement is detected and the PAA bit 24 is output as “1” and after descrambling (in this example, “1” is the exclusive OR of PAAW bits 21-2) 0,1,2,3,4,5, ... , FFFFFh is output. As a result, the cluster number address (PAA bits 21-2) can be generated and the cluster number can be detected as the output of the upper continuity detection circuit 303. Further, the layer number detection circuit 302 generates the layer number address (PAA bits 24-22) and detects the layer number from the generated PAA bit 24 and the PAAW bits 23-22 detected from the wobble. In addition, the lower address detection circuit 304 detects the in-cluster count value (PAA bits 1-0) from the PAAW bits 1-0 detected from the wobble. Therefore, the addresses obtained from the respective detection circuits 302, 303, and 304 can be input to the PAA address generation circuit 305 and converted into addresses of PAA bits 24-0.

  As described above, by generating an address by embedding virtual bits as information in other bits and restoring the address at the time of detection, the address structure of the wobble is not changed, and the physical address is not increased without increasing the number of bits of the address embedded in the wobble. The number of bits of the address indicating the target position can be expanded. Unlike the first embodiment, the virtual bit information can be generated and detected in the same manner by embedding not only a part of the address but also the entire address. As in FIG. 12, the address detection circuit described in FIG. 10 is also used in the reproducing apparatus for reproducing data from the optical disk created by the address generation described in the present embodiment and the recording apparatus for recording data on the optical disk. This makes it possible to detect the position where data is recorded and reproduced.

FIG. 11 is an address correlation diagram of an optical disc according to the fourth embodiment of the present invention. As in the first embodiment, address expansion is performed using virtual bits that are not recorded on the disk while maintaining the ADIP data structure shown in FIG. The difference from Fig. 7 is that 5 bits PAA bits 28-24 are used as virtual bits corresponding to PSN bits 31-27, PAA bit 28-2 is the cluster number, and PAA bits 1-0 are set as the structure of PAA 103. It is a point assigned as a count value in the cluster. 1101 is the actual address of Physical ADIP Address (hereinafter referred to as PAA), 1102 is the wobble embedded address (hereinafter referred to as PAAW) of Physical ADIP Address, and 1103 is the same as FIG. 7 as the scramble circuit, but only the bit assignment is different, and the others are the same And By embedding information as a plurality of types as the scramble rule of the scramble circuit 1103, by detecting and switching each scramble rule (in the present embodiment, 2 ⁵ = 32 ways because ⁵ virtual bits are added), A plurality of virtual bits can be generated and detected in the same manner. That is, the regularity of the count of the PAA bits 23-0 is changed according to the virtual bits PAA bits 28-24. As an effect, it is possible to extend the address while maintaining the number of bits of the conventional wobble address.

  As described above, by generating an address by embedding virtual bits as information in other bits and restoring the address at the time of detection, the address structure of the wobble is not changed, and the physical address is not increased without increasing the number of bits of the address embedded in the wobble. The number of bits of the address indicating the target position can be expanded. Unlike the first to third embodiments, not only an extension of only one bit as a virtual bit but also generation and detection can be performed in the case of a plurality of bits. Also, in the first to third embodiments, the address configured by the layer number and the cluster number is described using an address configured only by the cluster number in the present embodiment. Is possible. Similarly to FIG. 12, in the reproducing apparatus for reproducing data from the optical disk created by the address generation described in the present embodiment and the recording apparatus for recording data on the optical disk, the position of the data recording / reproducing is similarly detected. Is possible.

  FIG. 18 is a correlation diagram of addresses of the optical disc according to the fifth embodiment of the present invention. As in the first embodiment, address expansion is performed using virtual bits that are not recorded on the disk while maintaining the ADIP data structure shown in FIG. The difference from Fig. 1 is that the virtual bit PAA bit 24 generates 2-bit information from the 3-bit information of PAA bits 2-0 instead of switching the conversion to lower 2 bits or switching the regularity ( 1 bit is a virtual bit). 1801 is the actual address of Physical ADIP Address (hereinafter referred to as PAA), and 1802 is the wobble embedded address (hereinafter referred to as PAAW) of Physical ADIP Address, which is the same as in FIG. 1, but only the bit allocation is different, and the others are the same. As an address generation method, the encoding circuit 1803 uses the regularity of the PAA bits 2-0 to convert to PAAW bits 1-0 and embed them in the wobble. That is, the number of bits can be reduced by generating 2 bits by encoding the 3-bit information. As an effect, it is possible to expand the address without changing the wobble address structure while maintaining the number of bits of the conventional wobble address.

  A method for detecting the address PAAW embedded in the wobble will be described with reference to the timing chart of FIG. In this embodiment, PAA bit 1 is defined as a virtual bit that is not embedded in the wobble, and an example in which PAAW bit 1 = PAA bit 2 and PAAW bit 0 = PAAW bit 0 is applied and embedded in the wobble will be described as an example. . In this case, it is necessary to perform decoding processing from the regularity of PAAW bits 1-0 to restore PAA bit 1. PAAW bits 1-0 are input to the decode circuit (not shown) as 00b, 01b, 00b, 10b, 11b, 10b, 00b, ..., so the PAAW bit 0 continuous regularity and PAAW bit 1 switching timing, etc. PAA bit 1 can be easily restored from this state transition. Therefore, PAA bits 2-0 are generated using the values of virtual bits PAA bit 1 and PAAW bits 1-0 obtained in the decoding process of PAAW bits 1-0, and converted to addresses of PAA bits 24-0. it can.

  As described above, by generating an address without embedding bits that can be restored from the regularity of other bits as virtual bits and restoring the address at the time of detection, the address structure of the wobble is not changed without changing the address structure of the wobble. The number of bits of the address indicating the physical position can be expanded without increasing the number of bits. In this embodiment, the PAA bit 1 is described as a virtual bit, but any bit can be used as long as it can be easily restored from the regularity of other bits. Even if it is associated with a specific bit, it can be generated and detected in the same manner. Similarly to FIG. 12, in the reproducing apparatus for reproducing data from the optical disk created by the address generation described in the present embodiment and the recording apparatus for recording data on the optical disk, the address in FIG. 18 is decoded to detect the address. By using this circuit, it is possible to detect the position where data is recorded / reproduced.

  13 and 14 are diagrams showing an AUN structure, a data structure, an ECC structure, and a frame structure used in the sixth embodiment of the present invention. A cluster which is a recording / playback unit includes an LDC (Long Distance Code) for main data (1 sector 2048 bytes × 32 sectors) and a BIS (Burst Indicator Subcode). The main data 64 kilobytes shown in FIG. 14 (a) is ECC-encoded as shown in FIG. 14 (b). A 4-byte EDC (Error Detection Code) is added to 2048 bytes, which is one sector of main data, and LDC encoding is performed on 32 sectors. Further, as a numerical relationship suitable for use as the main data Burst Indicator, BIS is ECC-encoded as shown in FIG. 14 (d) with respect to 720B data shown in FIG. 14 (c). Furthermore, the data of 248 x 304 bytes shown in Fig. 14 (b) is rearranged into LDC data of 152 x 496 bytes by a predetermined interleaving process, and the data of 62 x 24 bytes shown in Fig. 14 (d) is processed by a predetermined interleaving process. Sort by 3 × 496 bytes BIS data. Therefore, as shown in Fig. 14 (e), one frame is generated by adding a sync signal (Frame SYNC, FS) to 38 × 3 bytes (152 bytes) of LDC data and 1 × 3 bytes (3 bytes) of BIS data. And a cluster is formed with data of all 496 frames. Here, AUN as an address added to each cluster unit has an Address Field (hereinafter referred to as AF) structure shown in FIG. 13, and is included in the 720 bytes of the BIS data structure. 4-byte error correction parity (AF5-AF8) 1302 is added to 4-byte AUN (AF0-AF3) 102 and 1-byte flag bits (AF4) 1301 for storing various information. Configure the AF structure. Therefore, 16 AUNs are assigned to 32 sectors (32 PSNs) in the cluster structure.

  An address generation method for two types of addresses assigned in units of sectors will be described with reference to the address correlation diagram of the multilayer optical disk in FIG. For example, consider a case where addresses are assigned to layer numbers up to 8 layers and data having a data capacity of 64 gigabytes per layer. In order to assign a layer number of up to 8 layers and a 64-gigabyte data capacity with PSN 101 assigned to one sector, all 28 bits are required, but since 32 bits are originally prepared as PSN, it is expressed in 27 bits It is not necessary to expand the address bits when the amount of data is larger than the amount of data to be processed, and it can be easily handled by shifting the allocation of the address bits indicating the layer number. Similarly, in the case of AUN 102 in which 16 addresses are assigned to a cluster structure composed of PSN 101 of 32 sectors, 28 bits are also required. As can be seen from FIG. 13, since the AUN 102 originally uses 4 bytes (32 bits) of address bits to form the AF structure, there is no need to expand the address bits. Therefore, since the address of AUN 102 is not changed from the conventional address structure, there is no need to switch to the conventional address structure. In addition, BIS 1404 configured using AUN originally added 32 bytes of parity to 30 bytes, so it was given a stronger ECC than LDC 1402 added to user data. Therefore, high reliability can be maintained. On the other hand, PAA (PAAW 104) embedded in wobble has a conventional 24-bit structure, and it is difficult to assign addresses to data with a layer number of up to 8 layers and a data capacity of 64 gigabytes per layer, and address expansion is required It becomes. Therefore, as shown in FIG. 1, by generating the address by embedding the virtual bits that are not recorded on the disc as information in other bits as it is not embedded in the wobble, and restoring the address at the time of detection, the address structure of the wobble is The periodicity can be maintained without change, and the address indicating the physical position can be expanded without increasing the number of bits of the address embedded in the wobble.

  As described above, when address expansion is required due to high data density, etc., if the number of address bits is small and expansion is difficult, such as PAA, it is possible to use expansion bits that are not recorded on the disk. By embedding these bits as information, the address can be expanded without changing the address structure or periodicity significantly. In addition, the number of bits of the address is sufficient as in AUN, and furthermore, the bits that can be communicated in the cluster cycle such as the address flag can be expanded, so it is possible to add bit assignments without changing the periodicity. For this reason, compatibility with PSN, compatibility with conventional addresses, and reliability can be maintained to the maximum by not performing address expansion and conversion of regularity.

  In the above embodiments, scramble is used as an information embedding method, and examples (105 in FIG. 1, 105 in FIG. 4, 703 in FIG. 7 and FIG. 8) are used as scramble circuits. The present invention is not limited, and any circuit or method that can embed information and detect information using bit operations based on the presence or absence of scramble or a difference in scramble regularity can be similarly applied. . However, although it has been described as scrambled as address bit manipulation and value conversion processing, scramble means one of arithmetic processing, and any processing that converts each bit of an address or regularity It is not limited to scramble. Further, the encoding described in the fifth embodiment also means one of the arithmetic processes, and has been described using an example as an encoding circuit, but is not limited to this circuit, and each bit of the address is Any circuit or technique for embedding, associating, and converting information into other bits using regularity can be applied in the same manner and is not limited to encoding.

  Further, the number of virtual bits, the position where the virtual bit is arranged, the bit position where information such as scramble information is embedded, and the bit configuration of the address are not limited to the present embodiment. However, it is better for the position where the virtual bit itself is arranged to change as an address considering the detection stability, and the bit position where information such as scramble information is embedded is changed as an address considering the detection time. More is better.

  In this embodiment, the optical disk is used as a recording medium, and the address embedded in the wobble is used as the address. However, the present invention is not limited to this embodiment, and the address read from the generated address is not limited to this embodiment. If the idea of reducing bits so as to reduce the number of bits can be applied, the application can be similarly performed. Furthermore, although it has been described that the virtual bit is not embedded in the wobble, it may be stored in an area different from the read address area and used for address detection.

101 ... Physical Sector Number (PSN), 102 ... Address Unit Number (AUN), 103 ... Physical ADIP Address (PAA), 104 ... Physical ADIP Address (PAAW), 105 ... Scramble Circuit, 106 ... Exclusive OR, 301 ... Descramble circuit, 302 ... layer number detection circuit, 303 ... upper continuity detection circuit, 304 ... lower continuity detection circuit, 305 ... PAA address generation circuit, 401 ... Physical ADIP Address (PAA), 402 ... Physical ADIP Address (PAAW) ) ... 701 ... Physical ADIP Address (PAA), 702 ... Physical ADIP Address (PAAW), 703 ... Scramble circuit, 801 ... Exclusive OR, 1101 ... Physical ADIP Address (PAA), 1102 ... Physical ADIP Address (PAAW), 1103: Scramble circuit, 1201 ... Optical disc, 1202 ... Pickup, 1203 ... Spindle motor, 1204 ... Address playback circuit, 1205 ... Data recording / playback circuit, 1206 ... Host, 1207 ... Microcomputer, 1301 ... flag bits, 1302 ... parities, 1501 ... AUX data, 1801… Physical ADIP Ad dress (PAA), 1802 ... Physical ADIP Address (PAAW), 1803 ... Encoding circuit

Claims (6)

In a recording medium having a cluster for recording a plurality of data,
Having an address recorded by wobbling superposition on a track for recording data in synchronization with the cluster,
The address has a virtual bit serving as address information that is not recorded on a recording medium in a part of the address,
A recording medium on which an address after being encoded so that the virtual bit can be restored is recorded. A recording method in a recording medium having a cluster for recording a plurality of data,
Having an address recorded by wobbling superposition on a track for recording data in synchronization with the cluster,
The address has a virtual bit serving as address information that is not recorded on a recording medium in a part of the address,
A recording method for recording data on a recording medium on which an address after being encoded so that the virtual bit can be restored is recorded,
A recording method comprising: detecting and recording a data position from the address where the virtual bit is restored by a decoding process. A reproduction method in a recording medium having a cluster for recording a plurality of data,
Having an address recorded by wobbling superposition on a track for recording data in synchronization with the cluster,
The address has a virtual bit serving as address information that is not recorded on a recording medium in a part of the address,
A reproduction method for reproducing data from a recording medium on which an address after being encoded so that the virtual bit can be restored is recorded,
A reproduction method comprising: detecting and reproducing a data position from the address where the virtual bit is restored by a decoding process. A recording method for recording data on a recording medium having a cluster for recording a plurality of data,
The address indicating the physical position of the recording medium synchronized with the cluster is
A virtual bit serving as address information not recorded on a recording medium in a part of the address;
The address after being encoded so that the virtual bit can be restored,
Superimpose wobbling on the track to record data,
A recording method comprising recording on a recording medium. In a reproducing apparatus for reproducing data from a recording medium having a cluster for recording a plurality of data,
Having an address recorded by wobbling superposition on a track for recording data in synchronization with the cluster,
The address has a virtual bit serving as address information that is not recorded on a recording medium in a part of the address,
Means for reading data from a recording medium in which an address after being encoded so that the virtual bit can be restored is recorded;
Means for generating a virtual bit by decoding from an address detected from wobble;
Means for detecting the address from the virtual bit generation result;
A reproducing apparatus comprising means for detecting a data position from the detected address. In a recording medium having an area for recording a plurality of data and an address indicating a physical recording position corresponding to the data,
Using virtual bits for switching the presence or absence of regularity and regularity to the address as extension bits of the address,
A recording medium on which the scrambled address is recorded.

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