JP2012216577A - Insulated gate type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve a problem that, although a pn junction diode is formed between a drain and a source in a peripheral region outside an element region of a MOSFET, and a path for a current by counter-electromotive force is secured to prevent avalanche breakdown, in the case that an area of the peripheral region is reduced for the purpose of miniaturization of a chip size and enlargement of an element region area, an arrangement region for the pn junction diode is reduced, and the current path is reduced, which causes deterioration of resistance against avalanche breakdown.SOLUTION: In a peripheral gate region 25 sectioned by a gate drawing wire 8, a total area per unit area of a second contact part 10 connecting a p+ type impurity region 24 with a source electrode 17 is set to be larger than that of a first contact part 9 connecting a source region 15 of an element region 20 and the source electrode 17. Even when an area of the peripheral region is reduced, a path for a current by counter-electromotive force can be secured to prevent deterioration in avalanche resistance.

Description

  The present invention relates to an insulated gate semiconductor device, and more particularly to an insulated gate semiconductor device in which the area of an element region with respect to the entire chip is improved and degradation of avalanche resistance is suppressed.

  In an insulated gate semiconductor device used for a circuit including an inductance component in a load, a structure in which a pn junction diode is connected between the source and drain electrodes in a peripheral region outside the element region to release energy stored in the inductance of the load Is known (see, for example, Patent Document 1).

  With reference to FIG. 8, an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) will be described as an example of a conventional insulated gate semiconductor device.

  FIG. 8A is a plan view of the vicinity of the boundary between the element region 120 and the peripheral region 121 of the MOSFET, and the source electrode on the surface is omitted. The substrate SB constituting the MOSFET chip is formed by providing an n− type semiconductor layer 102 on an n + type semiconductor substrate, and an element region 120 of a MOSFET having a trench structure, for example, is disposed on the main surface thereof, and a peripheral region is formed outside thereof. 121 is arranged. The peripheral region 121 is a region from the outer peripheral end of the element region 120 to the end of the substrate SB.

  The element region 120 includes a trench 106 having a lattice pattern in plan view, a gate electrode 107 embedded in the trench 106, a source region 115 adjacent to the trench 106, and a body region 114 provided between the source regions 115. Thus, a transistor cell is formed in a region surrounded by the trench 106.

  The gate electrode 107 in the element region 120 is connected to the gate lead-out wiring 108 in the peripheral region of the substrate SB. The gate lead-out wiring 108 has a lead part 181 in which polysilicon is embedded in a trench 106 provided in the substrate SB, and a connecting part 182 connected to the lead part 181 and extending polysilicon on the main surface of the substrate SB. .

  The peripheral region 121 is provided with a plurality of regions partitioned by the gate electrode (outermost peripheral gate electrode 107p) disposed on the outermost periphery of the element region 120 and the gate lead-out wiring 108 (leading portion 181 and connecting portion 182). It is done. A source region is not disposed in a broken-line region (hereinafter referred to as a peripheral gate region 125) partitioned by the outermost peripheral gate electrode 107p and the gate lead-out wiring 108, and a p + type impurity region is formed on the surface of the n− type semiconductor layer 102. 124 is provided and a pn junction diode Di is arranged.

  FIG. 8B is a cross-sectional view taken along line bb of FIG.

  The substrate SB includes an n− type semiconductor layer 102 provided on an n + type semiconductor substrate 1, and a p type channel layer 104 is provided on the surface of the n− type semiconductor layer 102. The trench 106 is provided through the channel layer 104, and a gate insulating film (not shown) is provided on the inner wall. The gate electrode 107 is provided by burying polysilicon or the like in the trench 106. An n-type source region 115 is disposed around the trench 106 and adjacent thereto, and a p-type body region 114 is disposed on the surface of the channel layer 104 between the source regions 115.

  An interlayer insulating film 116 is provided on the gate electrode 107, and a source electrode 117 is provided so as to cover the element region 120. The source electrode 117 is connected to the source region 115 and the body region 114 through the first contact portion 109 provided in the interlayer insulating film 116.

  On the connecting portion 182, a gate metal wiring 118 connected thereto is provided, and the gate metal wiring 118 is connected to a gate pad electrode (not shown) provided on the main surface of the substrate SB.

  The channel layer 104 is wider than the element region 120, and its outer peripheral end extends to the peripheral gate region 125. A plurality of p + type impurity regions 124 are arranged on the surface of the channel layer 104 in the peripheral gate region 125. An interlayer insulating film 116 is provided on the surface of the channel layer 104 in the peripheral gate region 125, and the interlayer contact film 116 is provided with the second contact portion 110 on the p + -type impurity region 124. The p + -type impurity region 124 is in contact with the source electrode 117 through the second contact portion 110. Thereby, in the peripheral gate region 125, a pn junction diode Di is connected between the drain and the source.

  The first contact portion 109 and the second contact portion 110 are openings (contact holes) formed in the same process in the interlayer insulating film 116 provided on the surface of the channel layer 104, and are separated from the adjacent first contact portions 109. The distance L is equal to the separation distance L between the adjacent second contact portions 110. Further, the opening widths D ′ of the first contact part 109 and the second contact part 110 are also equal.

JP-A-10-321877 (page 22, FIG. 34, page 24, FIG. 40)

  The pn junction diode Di formed in the peripheral gate region 125 is disposed for the purpose of preventing the avalanche breakdown of the MOSFET.

  Specifically, for example, when a MOSFET is used in a drive control circuit for a motor or a relay, when a back electromotive force due to an inductive load is generated in the circuit, a current due to the back electromotive force flows through the MOSFET. This current makes it easy to turn on the parasitic bipolar transistor formed in the element region. If a large current flows locally, avalanche breakdown is caused. In such a case, a pn junction diode is connected in the opposite direction to the voltage between the source and drain in the peripheral gate region, and this is used as a current path by the counter electromotive force. As a result, the chance of the parasitic bipolar transistor in the element region 120 being easily turned on can be reduced, and avalanche breakdown of the element region 120 can be prevented.

  Incidentally, along with the expansion of the element region 120 for the purpose of reducing the on-resistance or the reduction of the chip size for low cost, the peripheral region 121 on the outer periphery (outside) of the element region 120 is being reduced.

  However, when the peripheral region 121 is reduced in the structure of FIG. 8, the peripheral gate region 125 is also reduced. That is, since the formation region of the pn junction diode Di is reduced, there is a problem that the current path due to the counter electromotive force is insufficient and the avalanche resistance is deteriorated.

  Further, as a result of reducing the area of the peripheral gate region 123, the distance between the insulating film step inevitably generated in the peripheral region 121 by the interlayer insulating film 116 and the second contact hole 110 also approaches, and the photo A defect that some of the plurality of second contact portions 110 cannot be normally opened due to an etching failure in the lithography process is likely to occur. As a result, the function of the pn junction diode Di cannot be exhibited sufficiently uniformly, and there is a problem of causing a characteristic defect such as oscillation of the VDSS waveform.

  The present invention has been made in view of such a problem, and includes one conductivity type semiconductor layer, an element region provided on a surface of the one conductivity type semiconductor layer, in which transistor cells of a polygonal insulated gate type semiconductor element are disposed, and the one A plurality of gate lead wirings disposed in a peripheral region of the conductive semiconductor layer and connected to the gate electrode of the transistor cell to connect the gate electrode to the gate pad electrode, and a plurality of insulating films covering the element region A contact portion; a source electrode provided on the element region and in contact with the source region of the transistor cell via the first contact portion; the gate lead-out wiring; and the gate electrode at the outermost periphery of the element region; A reverse-conductivity type impurity region provided on the surface of the one-conductivity-type semiconductor layer in the peripheral gate region surrounded by the gate electrode, and an insulation covering the peripheral gate region A plurality of second contact portions that connect the reverse conductivity type impurity region and the source electrode, and the total area of the second contact portions per unit area is defined as the first area per unit area. This can be solved by making it larger than the total area of the contact portions.

  According to the present invention, the separation distance between the first contact portions in the element region and the separation distance and area (opening width) of the second contact portion in the peripheral gate region are the same, and the area of the peripheral gate region is the same. In comparison, since the number of pn junction diodes (pn junction area) in the peripheral gate region can be increased, the current path due to the back electromotive force can be increased, and the avalanche resistance can be improved.

  That is, even when the peripheral region (peripheral gate region) is narrowed for the purpose of enlarging the element region or reducing the chip size, it is possible to prevent deterioration of the avalanche resistance.

  Further, by arranging a large number of the second contact portions densely on the element region side, even if some second contact portions have poor contact, the influence on the whole is more than conventional. In addition to increasing the manufacturing margin, it is possible to prevent the occurrence of device characteristic defects.

It is a top view explaining the insulated gate semiconductor device of embodiment of this invention. 1A is a plan view and FIG. 1B is a cross-sectional view illustrating an insulated gate semiconductor device according to an embodiment of the present invention. It is sectional drawing explaining the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is (A) top view and (B) sectional drawing explaining a prior art.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 7 by taking an n-channel MOSFET as an example.

  FIG. 1 is a plan view showing a MOSFET 100 of this embodiment.

  Referring to FIG. 1, substrate SB constituting the chip of MOSFET 100 is formed by stacking n − type semiconductor layer 2 on an n + type silicon semiconductor substrate (not shown here). The n − type semiconductor layer 2 is, for example, a silicon semiconductor layer formed by epitaxial growth or the like, and the transistor cell C of the MOSFET 100 having a polygonal shape (for example, a lattice shape) in a plan view is arranged on the surface of the n − type semiconductor layer 2. An element region 20 is provided.

  A source electrode 17 that contacts a source region (not shown) of the transistor cell C is provided on the entire surface of the element region 20.

  A gate lead-out wiring 8 is provided in the peripheral region 21 of the substrate SB (n− type semiconductor layer 2). The peripheral region 21 is a region outside the device region 20, and specifically, is a region from the outer peripheral end of the device region 20 to the end of the substrate SB (n− type semiconductor layer 2). Here, although the peripheral region 21 is shown as a region surrounding the outside of the element region 20 in a ring shape, it is a U-shaped, L-shaped, or linear region along the chip side. May be.

  The gate lead-out wiring 8 is connected to the gate metal layer 18 provided on at least a part of the gate lead-out wiring 8, and the gate electrode 7 constituting the transistor cell C is connected to the gate pad electrode 28. The lead portion 81 is provided in a stripe shape parallel to one side of the chip in plan view. The connecting portion 82 extends in a direction orthogonal to the drawing portion 81 in plan view, and connects a plurality of adjacent drawing portions 81.

  FIG. 2 is an enlarged view of the vicinity of the boundary between the element region 20 and the peripheral region 21, FIG. 2A is a plan view, a metal layer (source electrode 17 and gate metal layer 18) on the surface of the substrate SB, and an insulating film (Interlayer insulating film) is omitted. FIG. 2B is a cross-sectional view taken along the line aa in FIG.

  Referring to FIG. 2A, in element region 20, trench 6 is provided in a polygonal shape (for example, a lattice shape) in a plan view, an inner wall is covered with a gate insulating film (not shown), and gate electrode 7 is formed. Buried. A source region 15 that is an n + type impurity region is provided adjacent to the trench 6, and a body region 14 that is a p + type impurity region is provided in an island shape in a region surrounded by the source region 15. A region surrounded by the trench 6 constitutes a transistor cell C.

  An interlayer insulating film (not shown) is provided on the surface of the substrate SB (n− type semiconductor layer 2), and a first contact portion 9 opened so that the body region 14 is exposed for each transistor cell C is provided. Although the interlayer insulating film is not shown here, the first contact portion 9 provided on the interlayer insulating film is shown. The first contact portion 9 is provided in a size that substantially overlaps the body region 14.

  When the gate electrode 7 has a polygonal (lattice) shape in plan view as in the present embodiment, the gate electrode 7 disposed in a closed loop shape (see FIG. 1) on the outermost periphery (hereinafter referred to as the outermost peripheral gate electrode 7p). .) Exists. In the present embodiment, an inner region partitioned by the outermost peripheral gate electrode 7p is referred to as an element region 20, and an outer region to the end of the substrate SB is referred to as a peripheral region 21.

  In the peripheral region 21, the gate lead-out wiring 8 has a lead-out portion 81 having the same configuration as the gate electrode 7 in the element region 20 and a connecting portion 82 that connects them on the surface of the substrate SB. That is, here, the lead-out portion 81 is formed by burying polysilicon doped with impurities in the trench 6 provided in the substrate SB. The connecting portion 82 is formed by extending the polysilicon on the surface of the substrate SB and is connected to all the drawing portions 81.

  At least one peripheral gate region 25 is disposed in the peripheral region 21. The peripheral gate region 25 is a broken line region surrounded by the gate lead-out wiring 8 (lead-out portion 81, connecting portion 82) and the outermost peripheral gate electrode 7p.

  A p + type impurity region 24 is disposed on the surface of the substrate SB in each peripheral gate region 25. An interlayer insulating film (not shown) covering the surface of the element region 20 also covers the surface of the peripheral gate region 25. The interlayer insulating film on the peripheral gate region 25 is opened so that the p + -type impurity region 24 is exposed, and a plurality of second contact portions 10 are provided in one peripheral gate region 25. Although the interlayer insulating film is not shown here, the second contact portion 10 provided on the interlayer insulating film is shown.

  Referring to FIG. 2B, the substrate SB has a structure in which an n− type semiconductor layer (for example, an n− type silicon epitaxial layer) 2 is provided on an n + type silicon semiconductor substrate 1. A channel layer 4 which is a p-type impurity region is provided on the surface of the n − type semiconductor layer 2 which becomes a drain region.

  The trench 6 passes through the channel layer 4 and reaches the n − type semiconductor layer 2. A gate insulating film (not shown) is provided on the inner wall of the trench 6. Further, a gate electrode 7 is provided by burying a conductive material inside the trench 6. The conductive material is, for example, polysilicon, and n-type impurities, for example, are introduced into the polysilicon in order to reduce the resistance.

  The source region 15 is an n + type impurity region in which an n type impurity is implanted into the surface of the channel layer 4 adjacent to the trench 6. In addition, a body region 14 is provided on the surface of the channel layer 4 in a region surrounded by the source region 15 to stabilize the potential of the substrate.

  The gate electrode 7 is covered with an interlayer insulating film 16, and a source electrode 17 is provided thereon. The source electrode 17 is electrically connected to the source region 15 and the body region 14 via the first contact portion 9 provided between the interlayer insulating films 16.

  The gate electrode 7 is connected to a connecting portion 82 of the gate lead-out wiring 8 via a lead-out portion (not shown here) of the gate lead-out wiring 8 in the peripheral region 21. A gate metal layer 18 is provided on the connecting portion 82 to be in contact with the overlapping portion 82. Here, the gate metal layer 18 is connected to a gate pad electrode (not shown). A drain electrode 19 is provided on the back side of the substrate SB.

  The outer peripheral end portion of the channel layer 4 extends to the outside of the element region 20 and is provided beyond the end portion of the peripheral gate region 25 on the connecting portion 82 side to the outside. The p + type impurity region 24 of the peripheral gate region 25 is provided on the surface of the channel layer 4.

  The interlayer insulating film 16 also covers the peripheral gate region 25, and the interlayer insulating film 16 is provided with a plurality of second contact portions 10 that are partially opened to expose the p + -type impurity region 24.

  The p + -type impurity region 24 is a region formed by implanting and diffusing ions of p-type impurities into the surface of the channel layer 4 through the second contact portion 10. One p + -type impurity is added to one peripheral gate region 25. A region 24 is provided (see the dashed line in FIG. 2A). That is, one p + type impurity region 24 is provided so as to be continuous with the plurality of second contact portions 10. The p + -type impurity region 24 is formed by appropriately selecting the opening width D of the second contact portion 10, the separation distance L 2 thereof, and the diffusion depth (for example, 0.25 μm, which is equivalent to the body region 14). A plurality of diffusion regions provided immediately below the portion 10 are connected to each other to form one diffusion region. By providing a plurality of second contact portions 10 for one p + type impurity region 24, the surface of the substrate SB is compared with a case where one large contact portion where substantially the entire p + type impurity region 24 is exposed is provided. Can maintain flatness.

  Referring to FIGS. 2A and 2B, the second contact portion 10 is located on the element region 20 side so as to be separated from the outer peripheral end portion 25p of the peripheral gate region 25 (the wiring portion 82 of the gate connection wiring 8). Aggregated and distributed with a uniform separation distance L2. The step at the outer peripheral end 25p of the peripheral gate region 25 is increased due to the arrangement of the wiring portion 82, and the film residue of the interlayer insulating film 16 is generated in the opening in the photolithography process for forming the second contact portion 10. Because there is a fear. In other words, the controllability of the opening of the second contact portion 10 is ensured by forming the second contact portion 10 apart from the outer peripheral end portion 25p (wiring portion 82) of the peripheral gate region 25. Specifically, when the width WG of the peripheral gate region 25 is, for example, about 10 μm to 14 μm, the width WG1 for arranging the second contact portion 10 is, for example, about 5 μm to 7 μm from the end of the element region 20.

  In the peripheral gate region 25, no source region is arranged and no transistor operation is performed, but the n− type semiconductor layer 2, the p type channel layer 4 and the p + type impurity region 24 form a pn junction diode Di. The

  In the present embodiment, the separation distance L2 between the second contact portions 10 is made smaller than the separation distance L1 between the first contact portions 9, and the total area per unit area of the second contact portion 10 is larger than that of the first contact portion 9. By arranging the second contact portion 10 so as to increase, the number of pn junction diodes Di (pn junction area) in the peripheral gate region 25 can be increased as compared with the conventional structure shown in FIG.

  Specifically, the area of the peripheral region 21, the number of peripheral gate regions 25 provided in the peripheral region 21, the area of one peripheral gate region 25, and the areas of the first contact portion 9 and the second contact portion 10 are the conventional structures ( In the present embodiment, when the first contact portion and the second contact portion have the same separation distance L in the case of the conventional structure, the separation distance between the second contact portions 10 is the same. L2 is set to one third of the separation distance L1 (= L) between the first contact portions 9 and arranged in the peripheral gate region 25 more densely than in the past. Thereby, the number of pn junction diodes Di (pn junction area) can be increased three times.

  As a result, the current path due to the back electromotive force can be increased, and the avalanche resistance can be increased to 1.5 times that of the conventional structure in the actual measurement data.

  In other words, even when the area of the peripheral region (peripheral gate region 25) is reduced to one third, it can be said that an avalanche resistance comparable to that of the conventional case can be ensured.

  Further, it has been found that the increase in the second contact portion 10 can reduce the VDSS oscillation failure.

  In this cross section, the distance W from the end of the p + -type impurity region 24 on the element region 20 side to the outer peripheral end of the channel layer 4 of the peripheral gate region 25 is the thickness t of the n − -type semiconductor layer 2 (the bottom of the trench 6 To a lower end of the n − type semiconductor layer 2), thereby ensuring a predetermined breakdown voltage.

  When a higher breakdown voltage is required, a high-concentration p-type impurity region (not shown) may be provided at the outer peripheral end of the channel layer 4.

  FIG. 3 is a partially enlarged view of FIG. 2B for explaining the configuration of the transistor cell C. FIG.

  The film thickness of the gate insulating film 11 in the trench 6 is about several hundreds of squares depending on the driving voltage of the MOSFET 100. In this embodiment, the channel layer 4 in the region surrounded by the source region 15 is removed by etching to the vicinity of the bottom of the source region 15, and the body region 14 is provided on the exposed surface of the channel layer 4. That is, the surface of the body region 14 is provided at a position lower (deeper) than the surface of the source region 15. For example, the bottom surface of the source region 15 and the surface of the body region 14 are substantially the same height.

  The gate electrode 7 is covered with an interlayer insulating film 16. The interlayer insulating film 16 opens a part of an insulating film such as a TEOS (TetraEthOxySilane) film 16a and a BPSG (Boron Phosphor Silicate Glass) film 16b covering the surface of the substrate SB, and the first contact portion 9 exposing the body region 14 is exposed. And an insulating film is left on the gate electrode 7. In the present embodiment, since the body region 14 is provided below the source region 15, the first contact portion 9 includes a part of the TEOS film 16 a and the BPSG film 16 b and the substrate SB (channel layer 4) between the source regions 15. The body region 14 is exposed by removing a part thereof. The side surface of the source region 15 is exposed on the side wall of the first contact portion 9.

  A source electrode 17 that covers the entire surface of the element region 20 is provided on the substrate SB. Source electrode 17 is connected to source region 15 and body region 14 through first contact portion 9. More specifically, a barrier layer 17 a (for example, titanium (Ti) / titanium nitride (TiN)) is provided on the surface of the interlayer insulating film 16 and the side wall of the first contact portion 9. The barrier layer 17a covers and contacts the side surface of the source region 15. A metal layer (for example, tungsten (W)) is buried in the first contact portion 9 as the plug layer 17b. Further, a metal layer such as aluminum (Al) is provided so as to cover the entire surface of the interlayer insulating film 16, and a source electrode 17 is provided. Source electrode 17 is in electrical contact with the side surface of source region 15 and the surface of body region 14 via barrier layer 17a and plug layer 17b. As a result, a portion surrounded by the adjacent trench 6 becomes one transistor cell C.

The source electrode 17 extends from the element region 20 and covers the peripheral gate region 25, and is in contact with the p + -type impurity region 24 through the second contact portion 10. More specifically, a barrier layer 17 a is provided on the surface of the interlayer insulating film 16 and the side wall of the second contact portion 10. Then, the plug layer 17 b is embedded in the second contact portion 10. The source electrode 17 is in electrical contact with the p + -type impurity region 24 through the barrier layer 17a and the plug layer 17b. An example of a method for manufacturing the MOSFET 100 will be described with reference to FIGS.

  Referring to FIG. 4A, a substrate SB in which an n− type semiconductor layer 2 is stacked on an n + type silicon semiconductor substrate 1 is prepared. The n − type semiconductor layer is, for example, a silicon epitaxial layer.

  An NSG (Non-doped Silicate Glass) CVD oxide film (not shown) is formed on the entire surface by CVD, and using this as a mask, the n − type semiconductor layer 2 in the trench opening is dry-etched with CF-based and HBr-based gases. The trench 6 is formed.

  Etching damage of dry etching at the time of forming the trench 6 is removed by performing dummy oxidation and removal of the dummy oxide film. Thereafter, the entire surface is thermally oxidized to form a gate insulating film 11 on the inner wall of the trench 6. The gate insulating film 11 is formed to have several hundreds of squares (for example, a thickness of about 250 to 700 squares) according to the driving voltage.

  Non-doped polysilicon is deposited on the entire surface and filled in the trench 6 covered with the gate insulating film 11. The entire surface is doped with impurities to reduce resistance, and the entire surface is etched back. Thereby, the gate electrode 7 buried in the trench 6 is formed. Alternatively, the gate electrode 7 may be formed by depositing polysilicon doped with impurities and etching back the entire surface.

Referring to FIG. 4B, p-type boron (B), for example, is implanted into the entire surface of element region 20 and peripheral gate region 25. As an example, the dose is 1 × 10 ^{13 to} 3 × 10 ¹³ cm ⁻² , and the implantation energy is, for example, 350 KeV. Thereafter, heat treatment is performed to diffuse the impurities to form the channel layer 4.

Referring to FIG. 5A, a mask M from which a source region formation region is exposed is formed, n-type impurity (for example, arsenic (As)) is used as an example, implantation energy 140 KeV, and dose 4 × 10 ^{15 to} 6. Ion implantation is performed at × 10 ¹⁵ cm ⁻² to form an n + -type impurity implantation region 15a.

  Referring to FIG. 5B, the mask M is removed, a TEOS film 16a is deposited, for example, 800 to 1200 、, and a BPSG film 16b is deposited, for example, 10000 to 14000 to form an interlayer insulating film 16. By this reflow, n-type impurities are diffused and a source region 15 is formed on the surface of the channel layer 4 between adjacent trenches 6.

  Referring to FIG. 6A, the interlayer insulating film 16 in the body region and the p + -type impurity region formation region is removed by etching, the first contact portion 9 is formed in the element region 20, and the first gate region 25 in the peripheral gate region 25. The two contact portions 10 are formed, and the interlayer insulating film 16 is left on the gate electrode 7. The first contact portion 9 and the second contact portion 10 have the same opening width D, and the distance L2 between the second contact portions 10 is, for example, one third of the distance L1 between the first contact portions 9.

  In the first contact portion 9, the surface of the n − type semiconductor layer 2 is also removed by etching. 6A, the source region 15 between the trenches 9 is divided, and the source region 15 remains in a ring shape in a region surrounded by the trench 6 in plan view. The n − type semiconductor layer 2 is exposed at the bottom of the first contact portion 9 and the source region 15 is exposed at the side surface.

Thereafter, a p-type impurity (for example, boron) is ion-implanted to form a p + -type impurity implanted region 14 a in the element region 20 and a p + -type impurity implanted region 24 a in the peripheral gate region 25. The implantation energy is, for example, 50 KeV, and the dose amount is higher than the dose amount of the channel layer 4 and is about 1.5 × 10 ¹⁵ cm ^{−2 to} 2.0 × 10 ¹⁵ cm ⁻² . The ion implantation is performed by, for example, oblique ion implantation.

  A plurality of p + -type impurity implantation regions 14 a are provided in an island shape between the source regions 15, and the p + -type impurity implantation regions 24 a correspond to the second contact portion 10 on the surface of the channel layer 4 of the peripheral gate region 25, that is, A plurality are provided separately from each other.

  Referring to FIG. 6B, heat treatment is performed to diffuse the impurities in p + type impurity implantation region 14a and p + type impurity implantation region 24a. As a result, the body region 14 is formed in the element region 20 and the p + -type impurity region 24 is formed in the peripheral gate region 25.

  At this time, by appropriately selecting the opening width D of the second contact portion 10 and the distance L2 between them and the diffusion depth (for example, 0.25 μm equivalent to the body region 14), the plurality of p + -type impurity implantation regions 24a Impurities are diffused and connected to each other to form one p + type impurity region 24.

  Next, referring to FIG. 7A, a barrier layer 17 a is formed over the interlayer insulating film 16. The barrier layer 17 a is, for example, Ti / TiN, and covers the surface of the interlayer insulating film 16 and the side walls of the first contact portion 9 and the second contact portion 10.

  Thereafter, referring to FIG. 7B, plug layer 17 b is embedded in first contact portion 9 and second contact portion 10. The plug layer 17b is buried by, for example, etching back after depositing W (tungsten) on the entire surface. Then, a barrier layer 17a is formed on the surface of the interlayer insulating film 16 again.

  Thereafter, a metal layer of Al or the like is formed on the entire surface and patterned into a desired shape to form the source electrode 17, and the drain electrode 19 is formed on the back surface of the substrate SB (n + type silicon semiconductor substrate 1) by metal vapor deposition or the like. Thus, the final structure shown in FIG. 3 is obtained.

  In this embodiment, in order to maintain the flatness of the surface of the substrate SB, the opening width D of the second contact portion 10 is equal to the opening width D of the first contact portion 9, but the flatness of the surface of the substrate SB is reduced. The opening width D of the second contact portion 10 may be larger than that of the first contact portion 9 within a range that can be maintained. For example, the relationship between the separation distance L1 of the first contact portion 9 and the separation distance L2 of the second contact portion 10 (L2 <L1) and the total area of the second contact portion 10 per unit area are the first contact portions per unit area. The opening area D of the second contact portion 10 may be larger than that of the first contact portion 9 by, for example, about 1.5 times. If the difference in tolerance in the photolithography process is up to 1.5 times from experience, etching under the same conditions is possible. Even in this case, the path of the back electromotive force current can be increased by increasing the junction area of the pn junction diode Di.

  As described above, in the present embodiment, the case where the n-channel MOSFET 100 is arranged in the element region 20 has been described as an example. However, a p-channel MOSFET having a conductivity type opposite to this may be used, and a drain is provided on one chip. An insulated gate semiconductor device for a protection circuit of a secondary battery in which two MOSFETs are arranged in common may be used, and the same effect can be obtained.

  Furthermore, an n-channel IGBT (Insulated Gate Bipolar Transistor) or a p-channel IGBT having a conductivity type opposite to this is provided with a p-type semiconductor region under the n + type silicon semiconductor substrate 1 shown in FIG. Can be implemented in the same manner, and the same effect can be obtained.

1 n + type silicon semiconductor substrate
2 n-type semiconductor layer
7 Gate electrode
8 Gate lead wiring
81 drawer
82 connection
9 First contact part
10 Second contact part
25 Peripheral gate area

Claims (7)

One conductivity type semiconductor layer;
An element region provided on a surface of the one-conductivity-type semiconductor layer, in which transistor cells of a polygonal insulated gate semiconductor element are disposed;
A gate lead wiring disposed in a peripheral region of the one conductivity type semiconductor layer, connected to a gate electrode of the transistor cell and connecting the gate electrode to a gate pad electrode;
A plurality of first contact portions provided on an insulating film covering the element region;
A source electrode provided on the element region and in contact with a source region of the transistor cell via the first contact portion;
A reverse conductivity type impurity region provided on the surface of the one conductivity type semiconductor layer in a peripheral gate region surrounded by the gate lead-out wiring and the gate electrode at the outermost periphery of the element region;
A plurality of second contact portions provided on an insulating film covering the peripheral gate region and connecting the reverse conductivity type impurity region and the source electrode;
2. The insulated gate semiconductor device according to claim 1, wherein a total area of the second contact portions per unit area is larger than a total area of the first contact portions per unit area.   2. The insulated gate semiconductor device according to claim 1, wherein the number of the second contact portions per unit area is larger than the number of the first contact portions per unit area.   3. The insulated gate semiconductor device according to claim 2, wherein a distance between the adjacent second contact portions is smaller than a distance between the adjacent first contact portions.   4. The insulated gate semiconductor device according to claim 2, wherein areas of the first contact portion and the second contact portion are equal.   5. The insulated gate semiconductor device according to claim 1, wherein the reverse conductivity type impurity region is continuously provided below a plurality of the second contact portions. 6.   6. The insulated gate semiconductor device according to claim 1, wherein the second contact portion is arranged in a concentrated manner on the element region side of the peripheral gate region. 7.   A reverse conductivity type channel layer is provided on the surface of the one conductivity type semiconductor layer, and a distance from an end of the reverse conductivity type impurity region on the element region side to an outer peripheral end of the channel layer in the peripheral region is The insulated gate semiconductor device according to claim 1, wherein the insulated gate semiconductor device is larger than a distance from a bottom of the trench to a lower end of the one conductivity type semiconductor layer.

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