JP2012213145A - Transmission device, transmission method, image formation device, transmission device, and reception device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to perform long distance transmission of signals without decreasing a frequency of a parallel running clock, in signal transmission using the parallel running clock.SOLUTION: There is provided a transmission device which performs transmission of data signals between a communication device 1 on the transmission side and a communication device 4 on the reception side, in parallel with clock signals. The communication device 1 on the transmission side places data having a plurality of bits in one clock period, and transmits a plurality of data groups having at least continuous two bits among the plurality of bits as the same data to the communication device 4 on the reception side. The communication device on the reception side receives, as valid data, either one bit data after a second bit among the data group having the same data of at least continuous two bits of the received data.

Description

  The present invention relates to a transmission apparatus, a transmission method, an image forming apparatus, a transmission apparatus, and a reception apparatus, and in particular, a transmission apparatus that performs long-distance signal transmission using a parallel clock, a transmission method, and an image formation using the transmission apparatus. The present invention relates to an apparatus, a transmission apparatus and a reception apparatus constituting the transmission apparatus.

  In general, in a printer, a copier, or a multi-function machine equipped with both of these functions, a device called a wide machine that prints on paper with a wide width direction includes a main body and a movable part (on the head relay). In order to transmit a signal between them, it is necessary to perform a long distance transmission. For long-distance transmission of signals, a differential transmission method is often used in order to avoid the influence of EMI and deterioration of signal quality. Further, when FFC (Flat Flexible Cable) is used as a transmission cable and data transmission is performed by the differential transmission method, if the FFC is long, the high frequency component is lost and the signal is deteriorated, so this is avoided. Therefore, a conventional technique relating to a method for reliably transmitting a signal at a reduced transfer rate is described in, for example, Patent Document 1 and the like.

  This prior art uses a low-cost LVDS (Low Voltage Differential Signal) driver and LVDS receiver for the purpose of transmitting a signal reliably, and uses a frequency divider and a multiplier to increase the frequency. The present invention relates to a method of performing transmission by reducing the transfer rate of a signal to be converted into a low frequency and transmitted over a long distance. In other words, this conventional technique once divides a high-frequency signal to be transmitted over a long distance into a signal of a frequency (low frequency) that can be processed by a general-purpose driver IC or receiver IC by a frequency dividing circuit on the transmission side, and lowers the frequency rate. The converted signal is sent from the driver IC to the transmission line, is transmitted over a long distance through the transmission line, and the receiver IC on the receiving side that receives the signal converted to this low frequency rate receives the low signal received by the multiplier circuit. The frequency rate signal is restored to the original high frequency signal.

  In addition, in order to avoid the influence of EMI and the deterioration of signal quality caused by it, there is a case where SSCG (Spread Spectrum Clock Generator) is used. In this case, a jitter component is generated due to the influence of clock modulation. Therefore, transmission of signals becomes difficult. Therefore, another prior art relating to a method of reliably transmitting a signal by reducing the signal transfer rate is described in, for example, Patent Document 2 and the like.

  Other prior art uses an AFE that amplifies an analog electrical signal obtained by a CCD reading a document and converts it into a digital signal, and SSCG for the purpose of reducing adverse effects on images caused by SSCG. A timing signal that modulates a clock signal having a predetermined frequency and controls the CCD and AFE based on the obtained internal reference clock signal, and generates a control signal having a frequency variation; And an image data determination unit that determines whether or not the influence of SSCG appears as a streak in the image obtained by executing the image processing, and when the image data determination unit determines that “the influence of SSCG appears as a streak” The frequency of the control signal generated by the timing generator is changed.

  There are two types of signal transmission methods, a clock embedded type and a clock parallel type. Since the clock embedded type is expensive, the clock parallel type is often used. In the prior art described above, when a signal transmission rate is reduced by applying a clock parallel type signal transmission method, the frequency of the parallel clock must be reduced, and accordingly, the transmission side and the reception side are reduced. The system clock frequency of an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) that constitutes the communication device on the side must be lowered, resulting in a problem that the processing speed of the entire device is lowered. End up.

  An object of the present invention is to solve the above-mentioned problems of the prior art, and in a signal transmission using a parallel clock, a transmission device capable of performing long-distance transmission of a signal without reducing the frequency of the parallel clock, An object of the present invention is to provide a transmission method, an image forming apparatus using the transmission apparatus, a transmission apparatus and a reception apparatus constituting the transmission apparatus.

  In order to achieve the above object, the present invention provides a transmission apparatus for transmitting a data signal in parallel with a clock signal between a communication apparatus on a transmission side and a communication apparatus on a reception side. A plurality of bits of data are inserted in one clock cycle, and at that time, a plurality of data groups having at least two consecutive bits of the plurality of bits as the same data are transmitted to the communication device on the reception side, and the reception side The communication apparatus is characterized in that any one bit data after the second bit in the data group having the same data of at least two consecutive bits of the received data is received as valid data.

  According to the present invention, it is possible to perform long-distance transmission of a signal without reducing the transfer rate of the parallel clock, thereby reducing the processing speed in the system employing the signal transmission device according to the present invention. This can be prevented.

It is a block diagram which shows schematic structure of the whole transmission system containing the transmission apparatus by embodiment of this invention. In FIG. 1, it is a figure explaining the transmission waveform by the use condition of the SSCG circuit 2a, ie, the waveform of the eye pattern observed in the input terminal by the side of a receiver. It is a figure explaining the receiver skew margin in the communication apparatus on the receiving side. It is a figure explaining the example which does not satisfy | fill the prescription | regulation of the receiver skew margin demonstrated in FIG. It is a block diagram which shows the structural example of the transmission apparatus by one Embodiment of this invention. It is a figure explaining the specific example of the transmission method of the signal by a prior art. It is a figure explaining the specific example of the transmission method of the signal by embodiment of this invention. It is a block diagram which shows the structure of the communication apparatus by the side of transmission which changed the transmission method of data and was made to transmit signal data. It is a figure explaining the specific example of the transmission data structure in embodiment of this invention. It is a block diagram which shows the circuit structure of the communication apparatus of the transmission side. It is a block diagram which shows the circuit structure of the LVDS receiver which is a communication apparatus of the receiving side. It is a figure which shows the data sequence of the serial data transmitted to the receiving side in the case of the transmission method by a prior art. It is a figure which shows the data sequence which carried out the parallel conversion of the serial data shown in FIG. It is a figure which shows the data sequence of the serial data transmitted to the receiving side in the case of the transmission method by embodiment of this invention. It is a figure which shows the data sequence which carried out the parallel conversion of the serial data shown in FIG. It is a figure explaining the embedding method to the transmission data of a Mode switching signal. It is a figure explaining the structure which verifies that the transmission data transmitted by the transmission system shown and demonstrated in FIG. 1 are transmitted normally. It is a figure explaining the structure which switches the clock input into ASIC or FPGA3a which comprises the transmitter part of the transmission side of the transmission system shown and demonstrated in FIG. It is a figure explaining the structure which switches the mode of a SSCG circuit. 1 is a perspective view illustrating an appearance of an image forming apparatus including a transmission device according to an embodiment of the present invention. It is a longitudinal cross-sectional view explaining the structure of the image forming apparatus shown in FIG.

  Hereinafter, embodiments of a transmission apparatus, a transmission method, an image forming apparatus, a transmission apparatus, and a reception apparatus according to the present invention will be described in detail with reference to the drawings. The basic concept of signal transmission in the embodiment of the present invention to be described below is that the communication device on the transmission side transmits the same data as a plurality of data groups having a plurality of continuous bits, and the communication device on the reception side The second and subsequent bits of a data group including a plurality of consecutive identical data sent are regarded as valid data.

  FIG. 1 is a block diagram showing a schematic configuration of an entire transmission system including a transmission apparatus according to an embodiment of the present invention.

  The transmission system shown in FIG. 1 includes a transmission apparatus that is a transmission-side apparatus by a clock oscillator OSC1a, an SSCG circuit 2a, and an ASIC or FPGA 3a that constitutes a transmitter unit, and a reception apparatus that is a reception-side apparatus. Is configured by an ASIC or FPGA 4a constituting a receiver unit, and an ASIC or FPGA 3a constituting a transmitting device and an ASIC or FPGA 4a constituting a receiving device are connected by a transmission path.

  Then, the clock signal from the clock oscillator OSC1a is input to the ASIC or FPGA 3a constituting the transmitter unit as the system clock via the SSCG circuit 2a. The ASIC or FPGA 3a uses the input system clock to transmit transmission data. It is transmitted to the ASIC or FPGA 4a constituting the receiver unit.

  The transmission system having the above-described configuration can avoid the influence of EMI and the deterioration of signal quality caused by it, but the jitter component is generated due to the influence of clock modulation by SSCG. Transmission may be difficult. Therefore, it is necessary to reduce the signal transfer rate and reliably transmit the signal.

  Also, some devices such as ASIC and FPGA used in the transmission system shown in FIG. 1 may not support SSCG. For example, there is a case where a skew margin corresponding to SSCG is defined for input, but not for output. In this case, it is necessary to evaluate a signal output from a device that does not support SSCG. This signal was originally sufficient to evaluate RSKM (Receiver Skew Margine), which is a skew margin at the input end on the receiver side, but when SSCG is used, output is normally performed. There is no guarantee. Furthermore, it may be necessary to evaluate the output of the transmitter unit, which increases the man-hours.

  In the present invention to be described later, since transmission is started after confirming that transmission is normally performed, it is possible to prevent data loss and to reduce waveform evaluation processing. Become.

  FIG. 2 is a diagram for explaining a transmission waveform according to the use state of the SSCG circuit 2a in FIG. 1, that is, a waveform of an eye pattern observed at the input end on the receiver side, and FIG. 2 (a) is an eye pattern of the SSCG circuit OFF. 2B is an eye pattern waveform when the SSCG circuit is −1% (down spread), and FIG. 2C is an eye pattern when the SSCG circuit is −3% (down spread). The waveform is shown. The eye pattern can be obtained by repeatedly transmitting and overlapping the signals, and this eye pattern can determine the time width of the eye pattern that can correctly evaluate the transmitted signal, thereby The signal can be evaluated correctly.

  It can be seen from the waveforms of the three eye patterns shown in FIG. 2 that the jitter component increases as the modulation rate of the SSCG circuit increases. In addition, when an SSCG circuit is used, the influence of reflection from the driver side becomes significant.

  FIG. 3 is a diagram for explaining the receiver skew margin in the receiving-side communication apparatus, and for explaining the skew margin, which is the specified value of the receiver in the explanation of FIG. FIG. 3 shows a specified value (RSKM: receiver skew margin) of the receiver when receiving data at a certain transfer rate in the clock parallel receiver.

  The specified value of the receiver is a value of the receiver skew margin that is allowed to correctly receive data when the time width of 1 bit of the transferred data is 1 UI. In the example shown in FIG. The receiver skew margin value as a reference for evaluation is 0.25 UI or less. The value of the receiver skew margin can be calculated as the sum of the deviation of the trigger point due to the rounding of the clock edge, the skew of the transmission path, the skew at the driver output end on the transmission side, and the jitter amount.

  If the receiver skew margin cannot be satisfied, the transfer clock rate is reduced to increase the UI value (serial / parallel conversion ratio on the receiving side is fixed), or serial / parallel conversion ratio. It is conceivable to adopt a method of lowering (transfer clock is fixed). However, when there is a restriction that the serial / parallel conversion ratio on the receiver side is fixed, the former method is inevitably adopted.

  In addition, depending on the type of receiver on the receiving side, the receiver skew margin value does not depend on the transfer clock rate. In this case, the signal ( Data) cannot be transmitted normally. Furthermore, as an EMI countermeasure, when an SSCG circuit is used, the jitter component increases. As a result, the clock and data margins are cut, and it becomes impossible to transmit signals normally.

  Since the transmission apparatus according to the embodiment of the present invention can relax the jitter amount with respect to the rise of data, it has an advantage that it is easier to satisfy the receiver skew margin than the transmission apparatus according to the prior art. Yes. Thereby, according to the embodiment of the present invention, it is possible to realize long-distance transmission by a combination of a cheaper FFC and LVDS receiver. In the above description, the transmission system using the SSCG circuit 2a and its problems have been described. However, the transmission system including the transmission apparatus according to the embodiment of the present invention uses the SSCG circuit 2a in the system shown in FIG. Even if the transmission system is not, it becomes easy to satisfy the receiver skew margin.

  FIG. 4 is a diagram illustrating an example in which the receiver skew margin definition described in FIG. 3 is not satisfied.

  In general, when a signal is transmitted over a long distance, the signal is attenuated and the rising of the signal is lost, and the value of the receiver skew margin becomes larger than the specified value described with reference to FIG. As a result, the eye pattern in which the signal is repeatedly transmitted and superimposed to determine the time width in which the signal can be correctly received and the signal is evaluated is as shown by the long square in FIG. 4 shown as data DATA in FIG. As a result, the specified value of the receiver skew margin cannot be satisfied.

  In the embodiment of the present invention described below, the transmission-side communication device transmits the same 1-bit data as a plurality of consecutive bits, and the reception-side communication device transmits two or more consecutive identical data. One bit after the bit is used as valid data.

  FIG. 5 is a block diagram showing a configuration example of a transmission apparatus according to an embodiment of the present invention. The transmission apparatus according to the embodiment of the present invention described here uses, as a precondition, a signal transmission method of a clock parallel type as a signal transmission method.

  The embodiment of the present invention shown in FIG. 5 corresponds to the FPGA 3a constituting the transmitter unit of the transmitting device and the FPGA 4a constituting the receiver unit of the receiving device in FIG. The FPGA 1 and the LVDS receiver 4 as a receiving side communication device are connected by an FFC 3 for signals and clocks. An LVDS driver 2 is configured in the FPGA 1. The LVDS driver 2 includes an input latch 10 that latches an input transmission data signal Tx_in a 1 and a clock signal that is a system clock of the input FPGA 1. a control unit 11 that controls writing and reading to the input latch 10 upon receipt of a2, a PLL (Phase Locked Loop) circuit 12 that generates a clock signal for signal transmission from the input clock signal a2, and an input latch 10 Mux circuit 13 for parallel / serial conversion of the transmission data, and differential driver circuits 14 and 15 for converting the transmission data and clock signals from Mux circuit 13 and PLL circuit 12 to LVDS, respectively. Note that the length of the FFC in the wide-width machine using the transmission apparatus according to the embodiment of the present invention is generally 1 m to 3 m in many cases.

  Next, a signal flow in the transmission apparatus according to the embodiment of the present invention configured as described above will be described.

  A parallel data signal Tx_in a1 and a clock signal a2 are input to the LVDS driver 2 from the inside of the FPGA1. However, this clock signal is the system clock of FPGA1. Although not shown, the FPGA 1 includes other processing circuits and the like, and the data signal Tx_in a1 and the clock signal a2 are supplied from the outside of the FPGA 1.

  The data signal Tx_in a1 is input to the input latch circuit 10 in the LVDS driver 2 and is latched in the input latch circuit 10 by controlling the timing of latching by the control unit 11. The data signal Tx_in latched by the input latch circuit 10 is read by being controlled by the control unit 11 and passed to the Mux circuit 13. Then, the data level of the data signal subjected to parallel / serial conversion via the Mux circuit 13 is converted to LVDS in the differential driver circuit 14 and transmitted to the LVDS receiver 4 via the FFC 3.

  The clock signal a2 is supplied to the control unit 11 and also supplied to the Mux circuit 13 via the PLL circuit 12, and the level thereof is converted into LVDS in the differential driver circuit 15, and the LVDS receiver 4 passes through FFC3. Sent to.

  In the embodiment of the present invention, data conversion is performed by converting the same 1-bit data into a continuous multi-bit data string, but the processing for this is provided in the preceding stage of the LVDS driver 2 in the FPGA 1. This is performed by a logic circuit (not shown). This will be described later with reference to FIG.

  FIG. 6 is a diagram illustrating a specific example of a signal transmission method according to the prior art, FIG. 7 is a diagram illustrating a specific example of a signal transmission method according to an embodiment of the present invention, and FIGS. Reference will be made to the difference in signal transmission method between the prior art and the embodiment of the present invention. The example described here is an example when the serial / parallel ratio is 1: 7, that is, when 7-bit data can be inserted and transmitted within one clock cycle. This is an example in which a non-target clock signal in which the level High and Low of one clock is 3: 4 is used as a transfer clock that is a clock. It is possible to arbitrarily set how many bits of data are inserted in one clock cycle.

  In the case of the transmission method according to the prior art shown in FIG. 6, the communication device on the transmission side serially converts 7-bit parallel transfer data a to g as transfer data, and within one clock cycle in the order of a to g. Forward. The communication device on the receiving side receives each bit of the transferred data as valid. At this time, in order to transmit data normally, each eye pattern of each data can secure the specified value of the receiver which is the communication device on the receiving side as described with reference to FIGS. It is necessary to be.

  In contrast to the conventional data transmission as described above, in the case of the transmission method according to the embodiment of the present invention shown in FIG. 7, the LVDS driver 2 in the FPGA 1, which is the communication device on the transmission side, transfers the data as the transfer data. As described above, 2 bits or 3 bits of 7-bit data that can be transmitted within one cycle of the parallel clock are converted into the same continuous multi-bit serial data within one cycle of the parallel clock. Sending in. In the case of the illustrated example, the transfer data is illustrated as being transmitted as two groups of data having the same data in the order of a, a, a, b, b, b, b. This order can be three groups of data in which each group has the same data in the order of a, a, a, b, b, c, c. The communication device on the receiving side receives the transferred second bit data of the data group having a plurality of continuous identical data, or any one bit data after the second bit as valid. In the illustrated example, the data a of the second bit and the data b of the second bit are received as valid, but the data b is received as valid data of the third or fourth bit. May be. Further, when data is transmitted in the order of a, a, a, b, b, c, c as the transfer data, the second bit data a, b, c are received as valid data, respectively. .

  In the embodiment of the present invention, since the same data is transmitted over a plurality of bits as described above, the eye pattern defined for receiving data at the receiver on the receiving side can be widened, and thus transmitted. Even if the conditions for this are worse (in the example described with reference to FIG. 7, only 2-bit or 3-bit data can be transferred within one clock cycle), the specified value of the receiver as the communication device on the receiving side is secured. This makes it possible to transfer data reliably.

  FIG. 8 is a block diagram showing a configuration of a communication device on the transmission side that switches signal transmission methods and transmits signal data.

  The transmission-side communication device shown in FIG. 8 has an LVDS driver 2 in the FPGA 1 that constitutes the transmission-side communication device, as in the case of the transmission-side communication device described with reference to FIG. 2 receives an input latch 10 that latches Tx_in a1 and Mode switching signal a3 that are input transmission data signals, and a clock signal a2 that is a system clock of the input FPGA 1, and writes to and reads from the input latch 10 The controller 11 for controlling, the PLL (Phase Locked Loop) circuit 12 for generating a clock signal for signal transmission from the input clock signal a2, and the transmission data and the Mode switching signal from the input latch 10 are converted in parallel / serial. Mux circuit 13, transmission data from each of Mux circuit 13 and PLL circuit 12, Mo It is constituted by a differential driver circuits 14 for converting the e signal and the clock signal to LVDS.

  The transmission-side communication apparatus shown in FIG. 8 is different from the transmission-side communication apparatus shown in FIG. 5 in transmitting only Tx_in a1 as a data signal, but adding another mode switching signal a3. Transmission is performed together with the signal.

  The transmission apparatus using the transmission-side communication apparatus configured as shown in FIG. 8 uses the Mode switching signal, so that the signal transmission method can be transmitted to the receiver of the reception-side communication apparatus as described above. It is a transmission method according to an embodiment of the present invention, or all data within one clock cycle transmitted as transfer data by a transmission-side communication device as described in the prior art is assumed to be effective by the reception-side communication device. It is possible to determine whether the transmission method is received and to execute processing according to the transmission method.

  FIG. 9 is a diagram illustrating a specific example of a transmission data configuration in the embodiment of the present invention. In the example shown in FIG. 9 as well, the notation of the figure is reversed from that in FIGS. 6 and 7, but the data d1 before conversion of the transfer data is 1 as in the case described with reference to FIGS. It is assumed that 7 bits from data a to data g are transmitted in order from data a within a clock cycle, and these data a to g are transmitted as 2-bit data d2 and 2-bit data in one clock cycle. d3 and 3-bit data d4 are divided into three times and transmitted in three clock cycles.

  At the time of the first transmission, 2-bit data a and b before conversion are taken out and converted so that these data are transmitted within one clock cycle. In this case, the converted data strings are two data strings of a 3-bit data string of a, a, a and a 4-bit data string of b, b, b, b. It is sent to the LVDS driver and sent to the receiving side.

  At the time of the second transmission, 2-bit data c and d before conversion are taken out and converted so that these data are transmitted within the next one clock cycle. In this case, the converted data strings are two data strings, a 3-bit c, c, c data string and a 4-bit d, d, d, d data string. It is sent to the LVDS driver and sent to the receiving side.

  At the time of the third transmission, 3-bit data e, f, and g before conversion are taken out and converted so that these data are transmitted within the next one clock cycle. In this case, the data string after conversion includes three data strings including a 2-bit e, e data string, a 2-bit f, f data string, and a 3-bit g, g, g data string. The data string d4 is sent to the LVDS driver and sent to the receiving side.

  Although the waveform of the parallel clock is not shown in FIG. 9, if the data conversion as described above is performed, the falling portion of the waveform in one cycle of the parallel clock is sandwiched as in the third transmission. In some cases, the same data may be arranged, but the rounding of the edge of the falling edge of the waveform within one cycle of the parallel clock affects the specified value of the receiver described with reference to FIGS. There is no problem in carrying out the present invention.

  The data conversion as described above is not limited to the above example, as long as the converted data is a data string in which the converted data is the same data of 2 bits or more. Further, when the transmission environment is bad, it is possible to cope with the problem by changing the configuration of the converted data string as necessary.

  FIG. 10 is a block diagram showing a circuit configuration of a communication device on the transmission side. The circuit configuration of the communication device on the transmission side shown in FIG. 10 shows the internal circuit configuration of the FPGA 1 that is the communication device on the transmission side described with reference to FIG.

  As shown in FIG. 10, the FPGA 1 which is the communication device on the transmission side includes the same LVDS driver 22 as shown in FIG. 8 and the transmission data signal Tx_in a1 input from the outside. A FIFO MEMORY 20 that temporarily holds the Mode switching signal a3, a data string output from the FIFO MEMORY 20, and one of Tx_in a1 that is a transmission data signal input from the outside and the Mode switching signal a3 are selected and passed to the LVDS driver 22 And a selector 21.

  The transmission-side communication apparatus configured as described above transmits the transmission data signal Tx_in a1 input as a parallel data signal by the Mode select signal a3 by the transmission method according to the same method as in the prior art. It is possible to select whether to transmit by the transmission method according to the embodiment of the present invention. When the transmission method according to the embodiment of the present invention is used to continuously transmit a plurality of bits of data, the input data signal Tx_in a1 is temporarily held in the FIFO MEMORY20 and then selected by the selector 21 to be LVDS. It is input to the driver 22. That is, in the communication device on the transmission side described above, the data before conversion of the input data signal Tx_in a1 is temporarily stored in the FIFO MEMORY 20 and the transmitted data is sequentially sent to the selector 24. In the case of the transmission method according to the embodiment of the present invention, as described with reference to FIG. 9, the 7-bit data string before conversion is transmitted in three parts, so that the data output from the FIFO MEMORY 20 is written to the selector. Is written in three times. Data written to the selector is sequentially transferred to the LVDS driver 22.

  As can be seen from the above, when the transmission method according to the embodiment of the present invention is used, the rate at which the FIFO MEMORY 20 outputs to the selector is 1/0 compared to the rate at which the external data signal Tx_in a1 is input to the FIFO MEMORY 20. Therefore, the FIFO MEMORY 20 described above has a function of absorbing the input / output speed difference.

  When a transmission method similar to that in the case of the prior art is employed, the input transmission data signal Tx_in a1 and the Mode switching signal a3 are input to the selector 21 without going through the FIFO MEMORY 20, and are left as they are. The data is transmitted to the LVDS driver 22 through the selector 21.

  The FIFO MEMORY 20 and the selector 21 in the transmission-side communication apparatus described above constitute a logic circuit that converts the input transmission data signal so that the same data becomes a continuous data string of a plurality of bits. .

  FIG. 11 is a block diagram showing a circuit configuration of an LVDS receiver which is a communication device on the receiving side.

  The LVDS receiver 4 that is the communication device on the reception side shown in FIG. 11 includes differential receivers 41 and 42 that receive the data signal and the parallel clock signal transmitted from the LVDS driver 2 on the transmission side, and serial / parallel conversion of the data signal. A mux circuit 43 that receives the clock signal, an input latch circuit 45 that temporarily holds a data signal from the mux circuit 43, and a control circuit 46 that controls writing and reading of the input latch circuit 45. Composed.

  In the communication apparatus on the receiving side configured as described above, serial data and a parallel clock are input to the LVDS receiver 4 via the FFC. In the differential receivers 41 and 42, the levels of these data are converted into logic levels, and the differential signals are converted into single-ended signals. Then, the data is input to the Mux circuit 43 and serial / parallel converted by the Mux circuit 43. The input clock signal is supplied to the Mux circuit 43 and the control circuit 46 through the PLL circuit 44 and output as an external system clock. The parallel data signal output from the Mux circuit 43 is output to the outside through the latch circuit 45. The control circuit 46 performs control to write the parallel data signal output from the Mux circuit 43 into the latch circuit 45.

  In the above description, the data output to the outside of the LVDS receiver 4 discards the first bits of a plurality of identical bit data strings as will be described later when the data is transmitted in Mode indicating the transmission method according to the present invention. When processing is performed and data transmission is performed in Mode indicating a transmission method according to the prior art, it is assumed that all bits of data included in one clock cycle are valid data without discarding the data. Processing is done to handle.

  Next, a process of discarding the first bits of a plurality of received data strings of the same bit in the logic circuit connected to the output side of the LVDS receiver 4 of the receiving side communication apparatus in the embodiment of the present invention will be described. The case of the transmission method according to the prior art will be described.

  FIG. 12 is a diagram showing a data string of serial data transmitted to the receiving side in the case of the transmission method according to the prior art, and FIG. 13 is a diagram showing a data string obtained by parallel-converting the serial data shown in FIG.

  In the case of the transmission method according to the prior art, all the bits x1 to x7 are valid bits, and are transmitted to the communication transmission on the receiving side as serial data strings in the order of x1 to x7 as shown in FIG. This serial data string is serial / parallel converted by the receiver circuit of the communication device on the receiving side to become parallel data of bits x1 to x7 as shown in FIG. All the bits of the parallel data of these bits x1 to x7 are handled as valid data and output from the receiver circuit.

  FIG. 14 is a diagram showing a data string of serial data transmitted to the receiving side in the case of the transmission method according to the embodiment of the present invention, and FIG. 15 is a diagram showing a data string obtained by parallel-converting the serial data shown in FIG.

  Also in the case of the transmission method according to the embodiment of the present invention, as shown in FIG. 14, as in the case of the prior art, transmission data is transmitted as serial data strings in the order of bits x1 to x7 within one clock cycle. Sent to. This serial data string is serial / parallel converted by the receiver circuit of the communication device on the receiving side to be parallel data of bits x1 to x7 as shown in FIG.

  In the case of the transmission method according to the embodiment of the present invention, of the 7 bits of data to be transmitted, only 2 bits x2 and x5 are valid data. When this data string is serial / parallel converted by the receiver circuit in the communication apparatus on the receiving side, it is as shown in FIG. In this case, since only 2 bits x2 and x5 are valid data, only this data is output from the receiver.

  In the above, when the receiver circuit as the communication device on the receiving side is built in the FPGA and left, only valid 2-bit data of x2 and x5 are output to the outside, and the receiver is a general-purpose IC. In this case, it is only necessary to discard the first bit by connecting only the corresponding output pin to the outside.

  FIG. 16 is a diagram for explaining a method of embedding a Mode switching signal in transmission data.

  There are two methods for transmitting the Mode switching signal to the communication device on the receiving side. One of them is a method in which a Mode switching signal is embedded in transmission data and is always transmitted, or a method that can be transmitted whenever necessary, and the other is a series of signals to be transmitted. This is a method of transmitting a Mode switching signal before transmitting the data. The example shown in FIG. 16 is an example when a Mode switching signal is embedded in transmission data.

  When the Mode switching signal is embedded in the transmission data and is always transmitted, as shown in FIG. 16, it can be realized by embedding it in the data that is valid by the receiver circuit that is the communication device on the receiving side. Of course, the data of the Mode switching signal also needs to be transmitted as a block of data of 2 bits or more. In such a mode switching signal transmission method, it is necessary to always ensure at least 2 bits in a series of data to be transmitted for the mode switching signal. It is possible to obtain an advantage that the Mode can be switched even during data transmission.

  On the other hand, when the Mode switching signal is sent before sending a series of data to be transmitted, the transmission rate of the transmission data is faster than the method of constantly sending the Mode switching signal without reducing the transmission rate of the transmission data. This causes a demerit that the Mode cannot be switched during the transmission.

  FIG. 17 is a diagram illustrating a configuration for verifying that transmission data transmitted by the transmission system illustrated in FIG. 1 is normally transmitted.

  A particular problem depends on whether or not the transmission data is normally transmitted when the LVDS receiver in the FPGA 4a constituting the receiver unit of the receiving apparatus does not support SSCG. When the signal subjected to SSCG is not normally output, the image forming apparatus using the transmission system shown in FIG. 1 may affect the image based on the output data such as image dust and vertical stripes. . For this reason, it is necessary to prevent wrong data from being output to the subsequent stage. For this reason, it is necessary to confirm that the transmission waveform is normally transmitted. In the embodiment of the present invention, as a means for that purpose, the comparison circuit is arranged immediately after the LVDS receiver. Such verification may be performed even when the transmission side communication device does not use the SSCG circuit.

  The configuration for verifying that the transmission data shown in FIG. 17 is normally transmitted is such that the comparison circuit 5a is connected to the subsequent stage of the FPGA 4a which is the receiver unit of the system shown in FIG. Then, a test pattern having a predetermined pattern is transmitted a plurality of times immediately before image data is transmitted from the ASIC or FPGA 3a constituting the transmitter unit on the transmission side not shown in FIG. The comparison circuit 5a on the receiver side compares the transmitted test pattern with a predetermined pattern, and when it matches, inputs an enable signal to the LVDS receiver (FPGA) 4a, and a plurality of comparison results are obtained. The disenable signal is input to the LVDS receiver (FPGA) 4a when the number of times does not match (which may be less than the number of times of test pattern transmission). It is assumed that the above-described test pattern is composed of a plurality of data groups having 2 bits out of a plurality of bits as the same continuous data.

  In addition, the above-described enable signal or disenable signal can be transmitted to the ASIC or FPGA 3a that constitutes the transmitter unit on the transmission side, whereby the received enable signal or disenable signal is transmitted on the transmission side. It can be used as a mode switching signal to select whether or not the SSCG circuit can be used. In addition, when an SSCG circuit is not used on the transmission side and a disable signal is received, a test pattern in which the number of consecutive identical data in a plurality of data groups possessed as identical identical data is 3 bits or more It is also possible to perform verification with Then, the communication device on the transmission side sets the test pattern to the same data in which 3 or more bits out of a plurality of bits are continuous, and when the result of verification is normal and an enable signal is received from the reception side, The number of consecutive identical data bits in a plurality of data groups having the same data transmission as the same continuous data is transmitted as 3 or more bits. The communication device on the transmission side sequentially increases the number of bits of the same data in the test pattern, and each time it receives a report that the data cannot be normally received from the communication transmission on the reception side, The minimum number of bits of the same data to be transmitted is increased and transmitted. Further, even if the bit width is increased to the maximum (even when the SSCG circuit is not used), if a signal cannot be transmitted normally, an error can be issued in the form of SC (Serviceman Call).

  In the above description, it has been described that transmission data is normally transmitted by transmitting a test pattern from the communication device on the transmission side. However, this verification should be performed at the time of actual data transmission. You can also. In that case, the image data to be transmitted may be made error-detectable data, and the receiving side may perform error detection on the received image data.

  FIG. 18 is a diagram for explaining a configuration for switching clocks input to the ASIC or FPGA 3a constituting the transmitter unit on the transmission side of the transmission system shown in FIG.

  In the example of the transmission system shown in FIG. 1, the clock signal from the clock oscillator OSC1a is input to the ASIC or FPGA 3a constituting the transmitter unit as the system clock via the SSCG circuit 2a. However, the example shown in FIG. Then, the clock branch circuit 6a is provided in the ASIC or FPGA 3a constituting the transmitter unit on the transmission side, and the clock signal input from the OSC circuit 1a to the ASIC or FPGA 3a is directly input from the OSC circuit 1a, and the SSCG circuit 2a There are two types, one that is input via the.

  These two types of clock signals are input to the clock branch circuit 6a in the ASIC or FPGA 3a, branched in the clock branch circuit 6a, and only one of them is used as the system clock. A clock switching signal is input to the clock branch circuit 6a from the receiver side, and which clock is selected is determined by this switching signal. As the switching signal, the enable signal described with reference to FIG. 17 or the mode switching signal based on the disenable signal can be used.

  FIG. 19 is a diagram illustrating a configuration for switching modes of the SSCG circuit.

  In the example described with reference to FIG. 18, the ASIC or FPGA 3a constituting the transmitter unit has the clock branch circuit 6a and selects whether to use the clock via the SSCG circuit 2a. In the example shown in 19, the mode selection function of the SSCG circuit 2a itself is used to select whether or not the ASIC or FPGA 3a constituting the transmitter unit uses a clock that enables the function of the SSCG circuit 2a. is there.

  Depending on the device, the SSCG circuit 2a may be configured to be able to select a mode for turning on or off the function. In this case, the SSCG circuit 2a has an input pin for setting the mode. Is provided. In the example shown in FIG. 19, the ASIC or FPGA 3a constituting the transmitter unit changes the mode by switching the input (mode switching signal) to the corresponding pin, and the function of the SSCG circuit 2a (the function of frequency-modulating the clock signal) ) Can be turned on or off. As a result, the ASIC or FPGA 3a constituting the transmitter unit can select whether or not to use a clock that enables the function of the SSCG circuit 2a. This mode switching signal is generated in the ASIC or FPGA 3a. Further, the ASIC or FPGA 3a may generate the above-described mode switching signal by receiving the enable signal described with reference to FIG. 17 or the mode switching signal based on the disenable signal from the receiver side, or by referring to FIG. The described enable signal or the mode switching signal by the disable signal may be used as it is.

  In the embodiment of the present invention described above, the communication device on the transmission side transmits the same continuous data over a plurality of bits, and the communication transmission on the reception side is effective for the second bit of the received same data of the plurality of bits. As described above, the present invention can also make the communication transmission on the receiving side valid for any bit after the second bit of the received same data of a plurality of bits.

  Further, according to the present invention, when the communication apparatus on the transmission side does not use an SSCG circuit, a plurality of bits of data are inserted in one clock cycle in the first mode, and at that time, two bits of the plurality of bits are included. When the SSCG circuit is used as a plurality of data groups having the same continuous data as a plurality of data groups, the second mode is used to continue the plurality of data groups having the same continuous data. The number of bits of the same data to be transmitted may be 3 bits or more.

  In addition, the present invention provides a communication apparatus on the transmission side that has the same data as the data in which a plurality of different bits of data are inserted in one clock cycle at the start of data transmission. If it is transmitted to the communication device and a report indicating that all data has been successfully received from the communication transmission on the receiving side is received, the data transmission is continued as it is, and all data is transmitted from the receiving communication device. When receiving a report indicating that the data could not be received normally even once, a plurality of bits of data are inserted in one clock cycle, and at that time, two of the plurality of bits are consecutively identical. A plurality of data groups as data can be transmitted to the receiving communication device.

  Further, according to the present invention, the transmission side communication device inserts a plurality of bits of data in one clock cycle, and at that time, the plurality of data groups having the same two consecutive bits of the plurality of bits as the same data. A plurality of data having the same continuous data when transmitted to the communication device on the reception side and receiving a report indicating that the data could not be normally received multiple times from the communication transmission on the reception side The number of bits of the same continuous data in the group is transmitted as 3 bits or more, and every time a report is received that the data has not been received normally over a plurality of times from the communication transmission on the receiving side, The minimum number of consecutive bits of the same data is increased and transmitted, and the receiving side communication device has any one of the third and subsequent bits in the data group having the same data of 3 or more consecutive bits. The Tsu City of data can be arranged to receive as valid data.

  According to the above-described embodiment of the present invention, it is possible to perform long-distance transmission of signals without reducing the transfer rate of the parallel clock by using a low-cost parallel clock type LVDS IC. Therefore, it is possible to prevent a reduction in processing speed in a system that employs a signal transmission apparatus according to the above, and it is possible to reduce the number of changes in the system, thereby suppressing the cost of the system.

  Further, according to the embodiment of the present invention described above, a signal can be correctly transmitted on the receiving side even when the eye pattern of the first bit is not sufficiently opened or there is a clock skew. Furthermore, according to the above-described embodiment of the present invention, long-distance transmission can be realized even when the SSCG circuit is used, and in addition, when the SSCG circuit is used, the influence of EMI on the transmission of signals. Can be reduced.

  20 is a perspective view showing an external appearance of an image forming apparatus including a transmission device according to an embodiment of the present invention. FIG. 21 is a longitudinal sectional view illustrating the configuration of the image forming apparatus shown in FIG. With reference to FIG. 21, an image forming apparatus including a transmission apparatus according to an embodiment of the present invention will be described. The image forming apparatus shown in FIGS. 20 and 21 is an example of an ink jet recording apparatus.

  The ink jet recording apparatus shown in FIG. 20 is a serial type ink jet recording apparatus, and includes a recording apparatus 100 and a main body frame 170 that supports the recording apparatus 100 as shown in FIG. Inside the recording apparatus 100, a guide rod 110 and a width guide 120 are spanned, and the carriage 151 is held by these guide rod 110 and the sub guide 120 so as to be operable in the arrow A direction (main scanning direction). ing. The carriage 151 is connected to the timing belt 111 and reciprocates in the main scanning direction A by driving the timing belt 111 by the main scanning motor 190 and the driving pulley 280. Tension is applied to the timing belt 111 by the pressure roller 120, and the carriage 150 can be driven without sagging.

  The print medium 150 is intermittently conveyed in the direction of the arrow B (sub-scanning direction) in the lower part where the carriage 151 reciprocates. The print medium 150 has a predetermined amount of ink discharged from a recording head mounted on the carriage 151. An image is formed.

  The recording apparatus 100 also includes a cartridge 160 that supplies ink and a maintenance mechanism 126 that cleans the recording head.

  Further, an encoder sensor is disposed in the carriage 151, and the carriage 151 is driven while detecting the position in the main scanning direction by continuously reading the encoder sheets that are stretched in the main scanning direction.

  Referring to FIG. 21, in the image forming apparatus shown in FIG. 21, a guide rod 110 and a sub guide 120 are spanned between left and right side plates 203 and 204, and a carriage 151 is bearing on these guide rod 110 and sub guide 120, It is held by the sub guide receiving portion 212 and is slidable in the main scanning direction of the arrow A shown in FIG.

  The carriage 515 has recording heads 221 and 222 that discharge black (K) ink droplets, and recording heads 223, 224, and 225 that discharge yellow (Y), magenta (M), and cyan (C) ink droplets. Is installed.

  The main scanning mechanism that moves and scans the carriage 151 includes a main scanning motor 190 disposed on one side in the main scanning direction, a drive pulley 207 that is rotationally driven by the main scanning motor 190, and the other side in the main scanning direction. The driven pulley 214 is arranged, and a timing belt 209 is provided between the drive pulley 207 and the driven pulley 214. The driven pulley 214 is tensioned outward (in a direction away from the drive pulley 20) by a tension spring (not shown). A part of the timing belt 209 is fixedly held by a belt holding unit 211 provided on the back side of the carriage 151, thereby pulling the carriage 151 in the main scanning direction. The carriage 151 and the apparatus main body are electrically connected by a flexible flat cable (FFC) 215 that connects the carriage side substrate 206 and the main body side substrate 210 on which a control circuit or the like is placed. It is designed to withstand the movement.

  An encoder sheet 200 is arranged along the main scanning direction of the carriage 151, and the encoder sheet 213 is read by the encoder sensor 213 provided on the carriage 151. Thereby, the position of the carriage 151 in the main scanning direction can be detected. Of the main scanning area of the carriage 151, the recording area includes a paper (print medium 150) in a direction (sub-scanning) indicated by an arrow B in FIG. 20 which is orthogonal to the main scanning direction of the carriage 151 by a paper feed mechanism (not shown). Direction).

  The image forming apparatus configured as described above moves the carriage 151 in the main scanning direction, and drives the recording heads 221 to 225 according to image information while intermittently feeding paper as a printing medium (not shown). A desired image can be formed on the print medium by ejecting the droplets.

  Then, for the recording head driving to be transmitted from the control circuit on the main body side substrate 210 to the recording heads 221 to 225 on the carriage 151 via the FFC 215 connecting the carriage side substrate 206 and the main body side substrate 210 in the image forming apparatus described above. For the transmission of the data, the transmission method and the transmission apparatus described with reference to FIGS. The embodiments of the present invention described with reference to FIGS. 5 to 16 have been described by showing only one line for transmitting FFC3 data. However, when used in the image forming apparatus as described above, the FFC3 data is used. Are provided corresponding to a plurality of recording heads, and each line is connected to the Mux of the LVDS driver and the LVDS receiver.

1 FPGA (Field Programmable Gate Array)
2 LVDS (Low Voltage Differential Signal) driver 2a SSCG (Spread Spectrum Clock Generator) circuit 3 FFC (Flat Flexible Cable)
4 LVDS receiver 10, 45 Input latch 11, 46 Control unit 12, 44 PLL (Phase Locked Loop) circuit 13, 43 Mux circuit 14, 15, 16 Differential driver circuit 20 FIFO MEMORY
21 Selector 22 LVDS driver 41, 42 Differential receiver circuit

JP 7-87138 A JP 2010-68131 A

Claims (15)

In the transmission device that transmits the data signal in parallel with the clock signal between the communication device on the transmission side and the communication device on the reception side,
The transmission-side communication apparatus inserts a plurality of bits of data in one clock cycle, and at that time, the reception-side communication apparatus as a plurality of data groups having at least two consecutive bits of the plurality of bits as the same data To
The receiving-side communication device receives any one bit of data after the second bit as valid data in the data group having the same data of at least two consecutive bits of the received data. Transmission equipment. The transmission apparatus according to claim 1,
The transmission-side communication apparatus inserts a plurality of bits of data in one clock cycle, and at that time, the reception-side communication apparatus as a plurality of data groups having at least two consecutive bits of the plurality of bits as the same data And a second mode in which data in which a plurality of different bits of data are inserted in one clock cycle are transmitted to the communication device on the receiving side, can be switched. Transmission equipment. The transmission apparatus according to claim 2, wherein when the communication apparatus on the receiving side receives the data transmitted in the first mode, the communication apparatus on the data side has the same data of the at least two consecutive bits of the received data. When any one bit data after the second bit is received as valid data and the data transmitted in the second mode is received, all of the data of a plurality of different bits received in one clock cycle Is received as effective data. The transmission apparatus according to claim 2 or 3,
The transmission-side communication device embeds and transmits a mode switching signal for switching between the first mode and the second mode in data to be transmitted to the reception-side communication device. A transmission apparatus that instructs a communication apparatus to switch modes. The transmission apparatus according to claim 2 or 3,
The transmission-side communication device receives the same data as the data obtained by inserting a plurality of different bits of data in one clock cycle a plurality of times at the start of data transmission in the second mode. When receiving a report indicating that all data has been successfully received from the communication transmission on the receiving side, the data transmission in the second mode is continued, A transmission characterized by switching to the first mode and transmitting data when receiving a report from the receiving side communication device that the data could not be normally received even once. apparatus. The transmission apparatus according to claim 3, wherein
The communication device on the transmission side inserts a plurality of bits of data in one clock cycle in the first mode, and at that time, as a plurality of data groups having two consecutive bits as the same data. When receiving the report that the data was not successfully received over a plurality of times from the communication transmission on the receiving side, the plurality of possessed as the same continuous data Each time the number of bits of the same data in the data group is transmitted as 3 bits or more, every time a report is received that the data has not been normally received multiple times from the communication transmission on the receiving side, Increase the minimum number of bits of the same continuous data and transmit,
The receiving-side communication device receives any one bit of data from the third bit onward as valid data in a data group having the same data of three or more consecutive bits. The transmission apparatus according to claim 3, wherein
The transmission-side communication device has an SSCG circuit that modulates the frequency of a clock signal. When the SSCG circuit is not used, a plurality of bits of data are inserted in one clock cycle according to the first mode. When the SSCG circuit is used as a plurality of data groups having 2 bits of the plurality of bits as the same continuous data, and the SSCG circuit is used, the continuous same data is transmitted in the second mode. A transmission apparatus characterized by transmitting the number of consecutive bits of the same data of a plurality of data groups as 3 bits or more. The transmission apparatus according to claim 3, wherein
The transmission-side communication apparatus includes an SSCG circuit that modulates a frequency of a clock signal, and uses the SSCG circuit to insert a plurality of bits of data in one clock cycle according to the first mode. Transmitting data to the receiving side communication device as a plurality of data groups having 2 bits out of a plurality of bits as the same continuous data, and data cannot be normally received multiple times from the receiving side communication transmission When receiving a report to the effect, the SSCG circuit is not used. The transmission apparatus according to claim 8, wherein
The communication device on the transmission side has a clock branching circuit. When the clock branching circuit receives a report indicating that data cannot be normally received from the communication transmission on the reception side, the communication device from the OSC circuit A transmission apparatus characterized by validating a clock signal input from an OSC among an input clock signal and a clock signal via the SSCG circuit. The transmission apparatus according to claim 8, wherein
When the communication device on the transmitting side receives a report indicating that data could not be normally received from the communication transmission on the receiving side, the SSCG circuit receives the report, and the clock signal of its own circuit A transmission apparatus characterized by stopping the function of modulation. The transmission device according to any one of claims 1 to 10,
A transmission apparatus, wherein transmission of a data signal is performed using a differential transmission method between the transmission-side communication apparatus and the reception-side communication apparatus. In the transmission method for transmitting the data signal in parallel with the clock signal between the communication device on the transmission side and the communication device on the reception side,
The transmission-side communication apparatus inserts a plurality of bits of data in one clock cycle, and at that time, the reception-side communication apparatus as a plurality of data groups having at least two consecutive bits of the plurality of bits as the same data To
The receiving-side communication device receives any one bit of data after the second bit as valid data in the data group having the same data of at least two consecutive bits of the received data. Transmission method. In an image forming apparatus configured with a plurality of recording heads,
12. A transmission apparatus according to claim 1, comprising a transmission circuit for transmitting drive signals between a control circuit for driving the plurality of recording heads and the plurality of recording heads. Image forming apparatus. In the transmission device that transmits the data signal along with the clock signal to the reception device,
The transmitting apparatus inserts a plurality of bits of data in one clock cycle, and transmits the data as a plurality of data groups having at least two consecutive bits of the plurality of bits as the same data. . In the receiving device that receives the data signal in parallel with the clock signal from the transmitting device,
The receiving apparatus receives any 1-bit data from the second bit onward as valid data in a data group having at least two consecutive identical bits of received data.