JP2012209416A - Solid-state imaging device, method for manufacturing the same, and electronic information equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve charge voltage conversion ratio to obtain an image signal of higher image quality by reducing capacity of an electronic charge detection part even when a pixel size becomes small.SOLUTION: A P-type well 3 is provided at an upper part of an N-type substrate 2, an embedded photodiode 6 and an electric charge detection part 7 are provided in the P-type well 3, and the P-type well 3 at a lower part of the electric charge detection part 7 is completely depleted. Thus, junction capacity C of the electric charge detection part 7 is sharply reduced by depleting the P-type well 3 sandwiched between the electric charge detection part 7 and the N-type substrate 2.

Description

  The present invention relates to a solid-state imaging device configured by a semiconductor element that photoelectrically converts image light from a subject and images the same, and a manufacturing method thereof, for example, a digital video camera and a digital device using the solid-state imaging device as an image input device in an imaging unit. The present invention relates to an electronic information device such as a digital camera such as a still camera, an image input camera such as a surveillance camera, a scanner device, a facsimile device, a television phone device, and a camera-equipped mobile phone device.

  2. Description of the Related Art Conventionally, as an amplification type solid-state imaging device, an amplification type solid-state imaging device has been proposed which has a pixel unit having an amplification function and a scanning circuit around the pixel unit and reads pixel data by the scanning circuit. In particular, there is known an APS (Active Pixel Sensor) type image sensor constituted by CMOS (Complementary Metal Oxide Semiconductor) which is advantageous for integrating a pixel configuration with a peripheral driving circuit and a signal processing circuit.

  In the APS type image sensor, it is usually necessary to form a photoelectric conversion unit, a reset unit, an amplification unit, and a pixel selection unit in one pixel unit. For this reason, in the APS type image sensor, 3 to 4 MOS transistors are usually used in addition to the photoelectric conversion unit made of a photodiode.

  However, if 3 to 4 MOS transistors are required per pixel portion, it becomes a restriction for downsizing the pixel size. Therefore, a method for reducing the number of transistors per pixel portion is proposed in Patent Document 1, for example. Has been.

  FIG. 10 is a longitudinal sectional view schematically showing an example of the configuration of the main part of a conventional amplification type solid-state imaging device.

  In FIG. 10, the conventional amplification type solid-state imaging device 100 is provided with a P-type well 102 on a P-type substrate 101. A buried photodiode 105 that is buried in the surface high-concentration diffusion layer 104 under the surface oxide film 103 for each pixel portion in the P-type well 102 and photoelectrically converts incident light to generate a signal charge, and the buried photodiode A gate 107 a to which a charge transfer control voltage is applied in order to transfer the signal charge accumulated in 105 to the charge detection unit 106 is provided on the channel region between the embedded photodiode 105 and the charge detection unit 106 via the surface oxide film 103. The charge transfer transistor 107 and the gate 108a to which a reset control voltage is applied to reset the detection voltage corresponding to the signal charge transferred to the charge detection unit 106 to the reference voltage are connected to the charge detection unit 106 and the VDD A surface oxide film 103 is interposed on the channel region between the diffusion layers 109 to which the power supply potential is applied. And a reset transistor 108 provided. The surface high-concentration diffusion layer 104, the buried photodiode 105, and the periphery of each of the transistors 107 and 108 are element-isolated for each pixel portion by an element isolation oxide film 103 (for example, STI).

  Here, although not specified because of the existing technology, an amplifier (amplification transistor circuit) such as a source follower circuit is connected from the charge detection unit 106, and the detection voltage corresponding to the signal charge transferred to the charge detection unit 106 is determined. The amplification transistor amplifies the detection voltage and outputs an image pickup signal for each pixel. It is known that the photodiode 105 is a buried type, and if signal charge transfer from the photodiode 105 is complete, noise can be extremely reduced and a high-quality image signal can be obtained.

In this charge detection unit 106, the charge voltage conversion efficiency η for converting the signal charge ΔQsig from the photodiode 105 into the voltage signal ΔVsig is:
η = G ・ △ Vsig / △ Qsig = G / CFD
It becomes. Here, G is the gain of the amplifier (amplification transistor), and usually shows a value (˜0.9) slightly smaller than 1 when a source follower circuit is used. In order to increase the charge-voltage conversion efficiency η, it is necessary to reduce the capacitance CFD of the charge detection unit 106. The capacitance CFD of the charge detection unit 106 is the junction capacitance between the drain side junction capacitance of the charge transfer transistor 107 connected to the charge detection unit 106, the input capacitance of the amplifier (amplification transistor), and the substrate (in this case, the P well 102), This is the total coupling capacitance between wirings. Since the conversion voltage signal Vsig = Qsig (signal charge) / capacitance CFD of the charge detection unit 106, the smaller the capacitance CFD of the charge detection unit 106, the larger the value of the conversion voltage V and the charge-voltage conversion rate η. Get better.

  Therefore, as the number of photodiodes 105 and charge transfer transistors 107 connected to the common signal charge storage unit increases, the junction between the drain-side junction capacitance of the charge transfer transistor 107 connected to the charge detection unit 106 and the P well 102 is increased. There is a problem in that the capacitance and the coupling capacitance between the wirings are increased, thereby reducing the charge-voltage conversion rate η.

  Patent Document 1 proposes a method for reducing the junction capacitance between the charge detection unit 106 and the P well 102 in order to reduce the capacitance CFD of the charge detection unit 106. As an example of this, as shown in FIG. 11, in the conventional amplification type solid-state imaging device 100A, the low-concentration diffusion layer 106A (electric field relaxation layer N−) is continuously and directly below the high-concentration diffusion layer of the charge detection unit 106. Forming.

JP 2004-289134 A

In the conventional configuration disclosed in Patent Document 1, the N + concentration of 10 ²⁰ / cm ³ of the high concentration diffusion layer, the P well concentration of 10 ¹⁶ / cm ^{3 of} the charge detection unit 106, and the N− concentration of the low concentration diffusion layer 106 A are used. When the concentration is 10 ¹⁶ / cm ³ , the depletion layer between the charge detection unit 106 and the P well 102 in FIG. 10 is 0.66 μm, but in FIG. 11, it is 0.86 μm, and the width of the depletion layer is The junction capacitance between the charge detection unit 106 and the P-type substrate 101 is inversely proportional to the width of the depletion layer and can be reduced to 77%, but the junction between the charge detection unit 106 and the P-type substrate 101 is increased by 1.3 times. The capacity can only be reduced to 77 percent. The PN reverse bias voltage at this time is 3.0V.

  The present invention solves the above-described conventional problems, and further improves the charge-voltage conversion rate by further reducing the capacitance of the charge detection unit even when the pixel size is reduced and the sensitivity is lowered, thereby further improving the image quality. It is an object of the present invention to provide a solid-state imaging device capable of obtaining the image signal and a manufacturing method thereof, and an electronic information device such as a camera-equipped mobile phone device using the solid-state imaging device as an image input device in an imaging unit.

  The solid-state imaging device of the present invention is a solid-state imaging device in which a plurality of light-receiving portions that photoelectrically convert incident light to provide an image is provided in a two-dimensional manner to form a plurality of pixel portions. A first conductivity type photoelectric conversion unit, and a first conductivity type signal detection unit that converts a signal charge transferred from the first conductivity type photoelectric conversion unit into a signal voltage. A second conductivity type well is provided in the upper part, and the first conductivity type photoelectric conversion unit and the first conductivity type signal detection unit are provided in the second conductivity type well, and the first conductivity type signal detection unit is provided. The second conductivity type well below is completely depleted, thereby achieving the above object.

  Preferably, the first conductivity type is located at a position below the first conductivity type signal detection unit in the solid-state imaging device according to the present invention and including a boundary between the first conductivity type substrate and the second conductivity type well. A first conductivity type diffusion layer having a lower concentration than the impurity concentration of the signal detection unit is provided.

  Still preferably, in the solid-state imaging device according to the present invention, the first conductivity type diffusion layer having a low concentration has the first conductivity type well so that the second conductivity type well is interposed between the first conductivity type signal detection unit and the first conductivity type signal detection unit. A deep field relaxation layer is provided at a position away from the bottom of the conductivity type signal detection unit in the depth direction.

  Further, preferably, the second conductivity type well below the first conductivity type photoelectric conversion unit in the solid-state imaging device of the present invention is completely depleted.

  More preferably, the depth position of the boundary between the second conductivity type well below the first conductivity type photoelectric conversion unit and the first conductivity type substrate in the solid-state imaging device of the present invention is the second conductivity type well. It is formed shallower than the case where the neutral region exists.

  More preferably, the second conductivity type well below the first conductivity type signal detection unit in the solid-state imaging device of the present invention is set to have a shallower depth and a lower impurity concentration than the surrounding second conductivity type well. Yes.

  Further preferably, in the solid-state imaging device according to the present invention, at the boundary between the second conductivity type well below the first conductivity type signal detection unit and the first conductivity type substrate, it is flat on the first conductivity type signal detection unit side. The cross-sectional protrusion part protruded from the part is formed.

  More preferably, the boundary between the second conductivity type well below the first conductivity type photoelectric conversion portion and the first conductivity type substrate in the solid-state imaging device of the present invention is a stepped portion recessed from a flat portion.

  Further preferably, the solid-state imaging device of the present invention further includes an amplifier that amplifies and outputs a signal according to a signal voltage corresponding to the signal charge transferred to the first conductivity type signal detection unit.

  Further preferably, in the solid-state imaging device of the present invention, the first conductivity type is an N type, and the second conductivity type is a P type.

  Still preferably, in a solid-state imaging device according to the present invention, the first conductivity type photoelectric conversion unit includes a second conductivity type surface high-concentration diffusion layer provided on the surface side of the first conductivity type photoelectric conversion unit, and the first conductivity type photoelectric conversion unit. It is composed of a buried photodiode surrounded by the second conductivity type well provided on the first conductivity type substrate side of the conductivity type photoelectric conversion unit.

  The method for manufacturing a solid-state imaging device according to the present invention is the method for manufacturing a solid-state imaging device according to the present invention, wherein the signal charge transferred from the first conductivity type photoelectric conversion unit that performs photoelectric conversion of incident light to capture an image is used as a signal voltage. A first conductivity type impurity is ion-implanted in a region below the region to be converted to the first conductivity type signal detection unit, and the first conductivity type impurity is ion-implanted at a position including the boundary between the first conductivity type substrate and the second conductivity type well. It has a first conductivity type diffusion layer forming step for forming a first conductivity type diffusion layer having a lower concentration than the impurity concentration of the conductivity type signal detection unit, thereby achieving the above object.

  The method for manufacturing a solid-state imaging device according to the present invention is the method for manufacturing a solid-state imaging device according to the present invention, wherein the signal charge transferred from the first conductivity type photoelectric conversion unit that performs photoelectric conversion of incident light to capture an image is used as a signal voltage. A second conductivity type well for a circuit is formed by ion-implanting a second conductivity type impurity in a region other than a region below the region to be converted into a first conductivity type signal detection unit, and then heat diffusion treatment to form a second conductivity type well for the circuit. A circuit second conductivity type well forming step for forming a cross-sectional protrusion projecting toward the first conductivity type signal detection unit as a cross-sectional structure of a boundary between the second conductivity type well and the first conductivity type substrate; The second conductive type well for the photoelectric conversion unit and the first conductive type well are formed by ion-implanting the second conductive type impurity under the region to be the conductive photoelectric conversion unit to form the second conductive type well for the photoelectric conversion unit. As a cross-sectional structure at the boundary with the conductive substrate Those having a second conductivity type well formation step photoelectric conversion unit for forming the cross-sectional stepped portion recessed on the first conductive type substrate, the object can be achieved.

  The electronic information device of the present invention uses the solid-state imaging device of the present invention as an image input device in an imaging unit, and thereby achieves the above object.

  With the above configuration, the operation of the present invention will be described below.

  In the present invention, for each pixel unit, a first conductivity type photoelectric conversion unit of a light receiving unit, a first conductivity type signal detection unit that converts signal charge transferred from the first conductivity type photoelectric conversion unit into a signal voltage, and A second conductivity type well is provided on the first conductivity type substrate, a first conductivity type photoelectric conversion unit and a first conductivity type signal detection unit are provided in the second conductivity type well, The second conductivity type well below the one conductivity type signal detection unit is completely depleted.

  As a result, the second conductivity type well below the first conductivity type signal detection unit is completely depleted, so that the junction capacitance C of the first conductivity type signal detection unit can be greatly reduced, and the pixel size is reduced. Further, by further reducing the junction capacitance C of the first conductivity type signal detector, it is possible to further improve the charge-voltage conversion rate and obtain a higher quality image signal.

  As described above, according to the present invention, since the second conductivity type well below the first conductivity type signal detector is completely depleted, the junction capacitance C of the first conductivity type signal detector is greatly reduced. Even if the pixel size is reduced, it is possible to further improve the charge-voltage conversion rate by further reducing the junction capacitance C of the first-conductivity-type signal detection unit to obtain a higher-quality image signal. Can do.

It is a top view which shows typically the example of a principal part structure containing the ion implantation planar view pattern of the deep electric field relaxation layer N- in the two-dimensional amplification type solid-state image sensor of Embodiment 1 of this invention. FIG. 2 is a longitudinal sectional view taken along line AA ′ of FIG. 1. FIG. 3 is a potential diagram from the charge detection unit in the depth direction of the N-type substrate in the two-dimensional amplification type solid-state imaging device of FIG. 2. It is a top view which shows typically the principal part structural example containing the ion implantation planar view pattern of the deep part electric field relaxation layer N- in the two-dimensional amplification type solid-state image sensor of Embodiment 2 of this invention. FIG. 2 is a longitudinal sectional view taken along line BB ′ in FIG. 1. It is a longitudinal cross-sectional view which shows typically the example of a principal part structure in the two-dimensional amplification type solid-state image sensor of Embodiment 3 of this invention. (A)-(c) is a principal part longitudinal cross-sectional view to each process (the 1) for demonstrating the method to manufacture the two-dimensional amplification type solid-state image sensor of FIG. (A)-(c) is a principal part longitudinal cross-sectional view to each process (the 2) for demonstrating the method to manufacture the two-dimensional amplification type solid-state image sensor of FIG. It is a block diagram which shows the schematic structural example of the electronic information apparatus which used either of the solid-state image sensors of Embodiment 1-3 of this invention for the imaging part as Embodiment 4 of this invention. It is a longitudinal cross-sectional view which shows typically the example of a principal part structure of the conventional amplification type solid-state image sensor. It is a longitudinal cross-sectional view which shows typically the example of another principal part structure of the conventional amplification type solid-state image sensor.

  Embodiments 1 to 3 of the solid-state imaging device of the present invention and implementation of an electronic information device such as a mobile phone device with a camera using the solid-state imaging device of Embodiments 1 to 3 as an image input device in an imaging unit will be described below. The third embodiment will be described in detail with reference to the drawings. In addition, each thickness, length, etc. of the structural member in each figure are not limited to the structure to illustrate from a viewpoint on drawing preparation.

(Embodiment 1)
FIG. 1 is a plan view schematically showing a configuration example of a main part including an ion implantation planar view pattern of a deep electric field relaxation layer N− in the two-dimensional amplification type solid-state imaging device of Embodiment 1 of the present invention. 2 is a longitudinal sectional view taken along line AA ′ of FIG.

  In FIG. 1, the two-dimensional amplification type solid-state imaging device 1 of Embodiment 1 includes a plurality of photodiodes 6 as first conductivity type (here, N-type) photoelectric conversion units, which are two-dimensionally arranged in a planar view matrix direction. They are arranged in a matrix. Each photodiode 6 protrudes with a predetermined width from one corner on the lower right side of the quadrangle in a plan view along one side, and a charge transfer transistor 8, a charge detection unit 7, The reset transistor 9 and the diffusion layer 10 to which the VDD power supply potential is connected are arranged in this order. Thus, they are formed in an L shape in plan view. On the right side of the photodiode 6 in plan view, charge transfer to the charge detection unit 7 is performed above the arrangement of the charge transfer transistor 8, the charge detection unit 7, the reset transistor 9, and the diffusion layer 10 to which the VDD power supply potential is connected. An amplifier 13 including an amplifying transistor for amplifying a signal and outputting a signal in accordance with a detection voltage corresponding to the signal charge thus arranged is arranged. A deep electric field surrounded by a dotted line larger than the outline of the charge detection unit 7 in plan view is provided at a lower position in the depth direction of the charge detection unit 7 in order to reduce the junction capacitance CFD and greatly improve the charge-voltage conversion rate. A relaxation layer 12 is provided.

  In FIG. 2, the two-dimensional amplification type solid-state imaging device 1 of the first embodiment has a P-type well 3 on the upper side of an N-type substrate 2. An embedded photodiode as an N-type photoelectric conversion unit that is buried in the surface high-concentration diffusion layer 5 under the surface oxide film 4 for each pixel unit in the P-type well 3 and photoelectrically converts incident light to generate signal charges. 6 and a gate 8 a to which a charge transfer control voltage is applied to transfer the signal charge accumulated in the embedded photodiode 6 to the charge detection unit 7, is a channel between the embedded photodiode 6 and the charge detection unit 7. A charge transfer transistor 8 provided on the region via the surface oxide film 4 and a gate to which a reset control voltage is applied to reset the detection voltage corresponding to the signal charge transferred to the charge detection unit 7 to the reference voltage 9a is a reset transistor provided on the channel region between the charge detection unit 7 and the diffusion layer 10 to which the VDD power supply potential is applied via the surface oxide film 4 And it has a door. The surface high-concentration diffusion layer 5, the buried photodiode 6, and the transistors 8 and 9 are separated from each other by a device isolation oxide film 11 (for example, STI) for each pixel portion.

  An amplifier (amplification transistor circuit) such as a source follower circuit is connected from the charge detection unit 7, and the amplification transistor amplifies the imaging signal in accordance with the detection voltage corresponding to the signal charge transferred to the charge detection unit 7. Output.

  A deep electric field relaxation layer 12 is provided at a position including the bottom of the P-type well 3 corresponding to the lower part of the charge detection unit 7 so that the P-type well 3 is interposed between the charge detection unit 7 paths. Therefore, the capacitance CFD of the charge detection unit 7 can be greatly reduced, and the charge-voltage conversion rate η can be improved to obtain a high-quality image signal. In short, the deep electric field relaxation layer 12 is provided at a position away from the bottom of the charge detection unit 7 in the depth direction.

  In the conventional example, the P-side substrate is used. However, in the first embodiment, the N-type substrate 2 is used, and the N-layer is formed as a deep electric field relaxation layer 12 at a lower position of the charge detection unit 7 with high energy. It is formed by ion implantation.

  When a constant PN reverse bias potential is applied to the charge detection unit 7, the P-type well 3, and the N-type substrate 2, a depletion layer spreads between the charge detection unit 7 and the P-type well 3, If a depletion layer spreads between the deep electric field relaxation layers 12 and the neutral region having the GND potential in the P-type well 3 disappears due to the depletion layer generated in the P-type well 3, eventually, the charge detection unit 7 And the neutral region (in this case, the N-type substrate 2) are the sum of the respective depletion layers described above, and the junction capacitance between the charge detector 7 and the N-type substrate 2 is greatly reduced. it can.

Here, for example, the density of the P layer or the N layer of each layer is set such that the N + concentration of the charge detection portion 7 is 10 ²⁰ / cm ³ , the concentration of the P-type well 3 is 10 ¹⁶ / cm ³ , and the deep electric field relaxation layer 12 is When the N− concentration is 10 ¹⁶ / cm ³ , the depletion layer on the P-type well 3 side of the PN junction between the charge detection unit 7 and the P-type well 3 is 0.6 μm. Further, since the charge detector 7 side has a high concentration, the occurrence of a depletion layer is small and is 0.06 μm. The depletion layer on the P-type well 3 side of the PN junction between the P-type well 3 and the N-layer of the deep field relaxation layer 12 is 0.43 μm, and the depletion layer on the deep field relaxation layer 12 side is 0.43 μm. Become. However, the reverse bias potential of PN is 3V.

  In the P-type well 3 below the charge detection unit 7, the depletion layer from the charge detection unit 7 and the depletion layer from the deep electric field relaxation layer 12 are expanded (in this case, 0.6 μm and 0.43 μm). When the neutral region of the mold well 3 is completely eliminated, the P-type well 3 is completely depleted.

  The condition is that the distance in the depth direction of the P-type well 3 sandwiched between the charge detection unit 7 and the deep electric field relaxation layer 12 in FIG. 2 is about 1.0 μm or less. Under this condition, the P-type well 3 as the second conductivity type well is interposed between the N-type charge detection unit 7 as the first conductivity type signal detection unit and the N-type substrate 2 as the first conductivity type substrate. If provided, an N− layer having a lower concentration than the N-type impurity concentration of the charge detection unit 7 at a position below the charge detection unit 7 and including the boundary between the N-type substrate 2 and the P-type well 3. By providing the (first conductivity type diffusion layer), the P-type well 3 is completely depleted.

  FIG. 3 is a potential diagram from the charge detection unit 7 in the depth direction of the N-type substrate 2 in the two-dimensional amplification type solid-state imaging device 1 of FIG.

  As shown in FIG. 3, the distance between the charge detection unit 7 and the neutral region (in this case, the N-type substrate 2) is 0.66 μm of the depletion layer between the charge detection unit 7 and the P-type well 3, The sum of the depletion layer between the P-type well 3 and the deep field relaxation layer 12 is 0.86 μm, and the junction capacitance C is 43% at 0.66 μm / 1.52 μm = 0.43 compared to the conventional case. As a result, the junction capacitance C can be significantly reduced as compared with the prior art, and the charge-voltage conversion rate is greatly improved.

Next, for example, the density of the P layer or the N layer of each layer is set such that the N + concentration of the charge detection unit 7 is 10 ²⁰ / cm ³ , the concentration of the P-type well 3 below it is 10 ¹⁶ / cm ³ , and the deep electric field relaxation layer 12. When the N concentration is 10 ¹⁵ / cm ³ , the depletion layer on the P-type well 3 side of the PN junction between the charge detection unit 7 and the P-type well 3 is 0.6 μm. Since the charge detector 7 side has a high concentration, the occurrence of a depletion layer is small and is 0.06 μm. Further, the depletion layer on the P-type well 3 side of the PN junction between the P-type well 3 and the N-layer of the deep field relaxation layer 12 is 0.18 μm, and the depletion layer on the deep field relaxation layer 12 side is 1.84 μm. Become. However, the reverse bias potential of PN is 3V.

  In the P-type well 3 below the charge detection unit 7, a depletion layer from the charge detection unit 7 and a depletion layer from the deep electric field relaxation layer 12 are expanded (in this case, 0.6 μm and 0.18 μm). When the neutral region of the well 3 is completely eliminated, the P-type well 3 is completely depleted. The condition is that the distance in the depth direction of the P-type well 3 sandwiched between the charge detection unit 7 and the deep electric field relaxation layer 12 in FIG. 2 is about 0.78 μm or less.

  The distance between the charge detector 7 and the neutral region (in this case, the N-type substrate 2) is 0.66 μm of the depletion layer between the charge detector 7 and the P-type well 3, and the P-type well 3 and the deep electric field. This is the sum of 2.02 μm of the depletion layer between the relaxation layer 12 and the junction capacitance C is reduced to 25% at 0.66 μm / 2.68 μm = 0.25 compared to the conventional case. As a result, the junction capacitance C can be significantly reduced as compared with the above case, and the charge-voltage conversion rate η can be greatly improved.

  In addition, since the deep field relaxation layer 12 is not implanted with impurity ions except under the charge detection unit 7, the neutral region of the P-type well 3 is sufficiently secured, and the same operation as in the conventional case can be guaranteed. Become.

  As described above, according to the first embodiment, the P-type well 3 is provided on the N-type substrate 2, and the embedded photodiode 6 and the charge detection unit 7 are provided in the P-type well 3. The P-type well 3 below 7 is completely depleted.

  In this way, by depleting the P-type well 3 sandwiched between the charge detection unit 7 and the N-type substrate 2, the junction capacitance C of the charge detection unit 7 is greatly reduced, and the pixel size is small and the charge-voltage conversion is performed. It is possible to improve the rate η and obtain a high-quality image signal.

(Embodiment 2)
FIG. 4 is a plan view schematically showing a configuration example of a main part including an ion implantation planar view pattern of the deep electric field relaxation layer N− in the two-dimensional amplification type solid-state imaging device according to the second embodiment of the present invention. 5 is a longitudinal sectional view taken along line BB ′ of FIG. 4 and FIG. 5, members having the same operational effects as the constituent members of FIG. 1 and FIG. 2 are described with the same reference numerals.

  4 and 5, in the two-dimensional amplification type solid-state imaging device 1 </ b> A according to the second embodiment, a plurality of photodiodes 6 as photoelectric conversion units are arranged in a two-dimensional matrix in the matrix direction in plan view. . Each photodiode 6 protrudes with a predetermined width from one corner on the lower right side of the quadrangle in a plan view along one side, and a charge transfer transistor 8, a charge detection unit 7, The reset transistor 9 and the diffusion layer 10 to which the VDD power supply potential is connected are arranged in this order. Thus, it is formed in an L shape in plan view. On the right side of the photodiode 6 in plan view, the charge transfer transistor 8, the charge detection unit 7, the reset transistor 9, and the diffusion layer 10 to which the VDD power supply potential is connected are transferred to the charge detection unit 7. An amplifier 13 including an amplifying transistor that amplifies a signal according to a detection voltage corresponding to the signal charge and outputs the signal is disposed. In the lower position in the depth direction of the charge detection unit 7, in order to reduce the junction capacitance C and greatly improve the charge-voltage conversion rate, a deep electric field relaxation layer having substantially the same size as the plan view outline of the charge detection unit 7 12A is provided.

  In the first embodiment, the neutral region exists in the P-type well 3 below the embedded photodiode 6, but in the second embodiment, the P-type well 3A below the embedded photodiode 6 is completely depleted. In short, the boundary position between the P-type well 3 and the N-type substrate 2 in the first embodiment is formed deeper than the boundary position between the P-type well 3A and the N-type substrate 2 in the second embodiment. That is, the boundary position between the P-type well 3A and the N-type substrate 2 according to the second embodiment is higher than that when the neutral region exists in the P-type well 3 as in the first embodiment. It is formed to be overwhelmingly shallower than the boundary position between the mold well 3 and the N-type substrate 2. This is effective in reducing crosstalk between adjacent pixel portions. As described above, since the boundary between the P-type well 3A and the N-type substrate 2 is shallower than in the first embodiment, the ion implantation position of the deep field relaxation layer 12A is shallow and easy to control, and the ion implantation energy is low. The distance in the depth direction of the P-type well 3 sandwiched between the charge detection unit 7 and the deep electric field relaxation layer 12A is smaller than that in the first embodiment, which is advantageous in terms of complete depletion. In short, even when two stages of ion implantation are required in the first embodiment, only one stage of ion implantation is required because the depth of the deep electric field relaxation layer 12A is shallow.

  As described above, according to the second embodiment, the P-type well as the second conductivity type well between the embedded photodiode 6 as the first conductivity type photoelectric conversion unit and the N-type substrate 2 as the first conductivity type substrate. Since the boundary position between the P-type well 3A and the N-type substrate 2 of the second embodiment is set so that 3A is completely depleted, the P-type well 3A and the N-type substrate 2 of the second embodiment are set. Is formed to be overwhelmingly shallower than the boundary position between the P-type well 3 and the N-type substrate 2 in the first embodiment. As a result, the crosstalk between adjacent pixel portions is reduced, the depth position of the deep field relaxation layer 12A is shallow, and the ion implantation energy is small, and the size of the deep field relaxation layer 12A is also narrow in plan view. This is more advantageous than the case of the first embodiment in that the P-type well 3A is completely depleted.

  Therefore, by depleting the P-type well 3A sandwiched between the charge detection unit 7 and the N-type substrate 2 more reliably, the junction capacitance C of the charge detection unit 7 can be greatly reduced, and the pixel size can be reduced. A high-quality image signal can be obtained with a small charge-voltage conversion rate η.

  In the first and second embodiments, the manufacturing method of the solid-state imaging device is not particularly described. However, charge transfer is performed from the embedded photodiode 6 serving as a first conductivity type photoelectric conversion unit that performs photoelectric conversion of incident light and images it. The P-type well 3 or 3A as the second conductivity type well is completely depleted in a region below the region that becomes the charge detection unit 7 as the first conductivity type signal detection unit that converts the signal charge that has been converted into a signal voltage. In this way, the first conductivity type impurity is ion-implanted at a predetermined distance, and the charge detection unit is located at a position including the boundary between the N type substrate 2 or 2A as the first conductivity type substrate and the P type well 3 or 3A. A first conductivity type diffusion layer forming step of forming the deep electric field relaxation layer 12 or 12A as the first conductivity type diffusion layer having a lower concentration than the impurity concentration of 7.

(Embodiment 3)
FIG. 6 is a vertical cross-sectional view schematically showing an example of the configuration of the main part of the two-dimensional amplification type solid-state imaging device according to Embodiment 3 of the present invention. In FIG. 6, the same reference numerals are given to members having the same operational effects as the constituent members of FIG. 2.

  As shown in FIG. 6, in the P-type well 3B of the two-dimensional amplification type solid-state imaging device 1B of Embodiment 3, the circuit P-well 14A and the photodiode P-well 15 are separately formed. The well structure of the P-type well 3B is also effective in reducing crosstalk in each pixel portion.

  The circuit P well 14A as the second conductivity type well below the signal detection unit 7 as the first conductivity type signal detection unit is deeper than the photodiode P well 15 as the second conductivity type well around it. Is shallow and the impurity concentration is set thin. The boundary between the circuit P-well 14A as the second conductivity type well below the signal detection unit 7 and the N-type substrate 2B protrudes to the signal detection unit 7 side. In short, in the circuit P-well 14A, a protruding portion 21B is formed so that the region of the N-type substrate 2B protrudes from the flat portion 22B above the charge detecting portion 7 side. Further, in the P-type well 15 for the photodiode, a stepped portion 23B is formed to be deep from the flat portion 22B at the boundary with the N-type substrate 2B. In these cases, the circuit P-well 14A of the P-type well 3B between the signal detection unit 7 and the protrusion 21B is completely depleted. Also, the photodiode P-well 15 in the second conductivity type well 3B between the embedded photodiode 6 and the N-type substrate 2B is completely depleted.

  This eliminates the need for ion implantation of N-type impurities into deep portions for the formation of the deep electric field relaxation layers 12 and 12A as in the first and second embodiments, and makes the manufacturing process easier. .

  Here, a manufacturing method of the two-dimensional amplification type solid-state imaging device 1B of Embodiment 3 will be described.

  7 (a) to 7 (c) and FIGS. 8 (a) to 8 (c) show the essential steps up to each step for explaining the method of manufacturing the two-dimensional amplification type solid-state imaging device 1B of FIG. FIG.

  First, as shown in FIG. 7A, an element isolation oxide film 11 (for example, STI) is formed on the surface side of the N-type substrate 2B together with the surface oxide film. The element isolating oxide film 11 isolates the surroundings of the surface high-concentration diffusion layer 5, the buried photodiode 6, the transistors 8 and 9, and the like in plan view for each pixel unit (unit pixel unit).

  Next, as shown in FIG. 7B, P-type impurities are ion-implanted to form a circuit P-type well 14 below the transistors 8 and 9. In this case, the ion implantation region is ion-implanted into a region other than the lower region 2 a of the region serving as the charge detection unit 7. That is, ion implantation of P-type impurities is not performed in the region to be the charge detection unit 7 and the lower region 2a.

  Subsequently, as shown in FIG. 7C, the circuit P-type well 14 is thinly formed in a region other than the lower region 2 a of the region serving as the charge detection unit 7, so that the circuit P-type well 14 is formed. Diffusion processing. As a result, the lower region 2a between the circuit P-type wells 14 on both sides is eliminated, and the circuit P-type wells 14A are formed integrally with each other. At a position corresponding to the lower region 2a of the circuit P-type well 14A, a protruding portion 21B is formed so that the region of the N-type substrate 2B protrudes from the flat portion 22B on the region side to be the charge detecting portion 7.

  Thereafter, as shown in FIG. 8A, further ion implantation of P-type impurities is performed in order to form the P-type well 15 for the photodiode under the region where the surface high-concentration diffusion layer 5 and the buried photodiode 6 are formed. To do. In the P-type well 15 for the photodiode, a stepped portion 23B is formed deeper by being recessed from the flat portion 22B at the boundary with the N-type substrate 2B.

  Further, as shown in FIG. 8B, the gate 8a of the charge transfer transistor 8, the gate 9a of the reset transistor 9, and the gate of the amplifying transistor, which are not shown here, are formed at predetermined positions.

  Finally, as shown in FIG. 8C, the surface high-concentration diffusion layer 5, the buried photodiode 6, the charge detection unit 7, and the diffusion layer 10 are formed by ion implantation. As a result, the two-dimensional amplification type solid-state imaging device 1B of Embodiment 3 can be manufactured.

  In short, the manufacturing method of the two-dimensional amplification type solid-state imaging device 1B of Embodiment 3 uses the signal charge transferred from the embedded photodiode 6 as the first conductivity type photoelectric conversion unit that performs photoelectric conversion of incident light and images it. The second conductivity type for circuit is formed by ion-implanting a second conductivity type impurity into a region other than the lower region immediately below the region that becomes the charge detection unit 7 as the first conductivity type signal detection unit that converts the signal voltage into a second voltage. By forming the circuit P-type well 14A as a well, a cross-sectional protrusion 21B protruding toward the charge detection unit 7 is formed as a cross-sectional structure of the boundary between the circuit second conductivity type well 14A and the N-type substrate 2B. A second conductivity type well forming step for the circuit and a second conductivity type impurity ion-implanted under the region to be the buried photodiode 6 to photo-diode as the second conductivity type well for the photoelectric conversion unit By forming the P-type well 15 for Aode, a cross-sectional step portion 23B recessed toward the N-type substrate 2B is formed as a cross-sectional structure of the boundary between the P-type well 15 for photodiode and the N-type substrate 2B. A second conductivity type well formation step.

  As described above, according to the third embodiment, the deep field relaxation layers 12 and 12A are not formed as in the first and second embodiments, but the P-type well 3B sandwiched between the charge detection unit 7 and the N-type substrate 2B. Can be depleted. As a result, the junction capacitance C of the charge detection unit 7 can be greatly reduced, and the pixel size can be reduced and the charge-voltage conversion rate η can be improved to obtain a high-quality image signal.

(Embodiment 4)
FIG. 9 is a block diagram illustrating a schematic configuration example of an electronic information device using any of the solid-state imaging devices according to Embodiments 1 to 3 of the present invention as an imaging unit as Embodiment 4 of the present invention.

  In FIG. 9, the electronic information device 90 of the third embodiment includes a solid-state imaging device 91 that obtains a color image signal by performing predetermined signal processing on the imaging signal of any of the solid-state imaging devices of the first to third embodiments. A memory unit 92 such as a recording medium that enables data recording after the color image signal from the solid-state image pickup device 91 is processed for a predetermined signal for recording, and the color image signal from the solid-state image pickup device 91 for a predetermined display. A display unit 93 such as a liquid crystal display device that can be displayed on a display screen such as a liquid crystal display screen after signal processing, and a color image signal from the solid-state imaging device 91 is subjected to predetermined signal processing for communication and then communication processing is performed. A communication unit 94 such as a transmission / reception device that can be enabled, a printer that can perform print processing after performing a predetermined print signal processing for color image signals from the solid-state imaging device 91 for printing, and the like And an image output unit 95. The electronic information device 90 is not limited to this, but in addition to the solid-state imaging device 91, at least one of a memory unit 92, a display unit 93, a communication unit 94, and an image output unit 95 such as a printer. You may have.

  As described above, the electronic information device 90 includes, for example, a digital camera such as a digital video camera and a digital still camera, an in-vehicle camera such as a surveillance camera, a door phone camera, and an in-vehicle rear surveillance camera, and a video phone camera. An electronic device having an image input device such as an image input camera, a scanner device, a facsimile device, a camera-equipped mobile phone device, and a portable terminal device (PDA) is conceivable.

  Therefore, according to the third embodiment, based on the color image signal from the solid-state imaging device 91, it can be displayed on the display screen, or can be printed out on the paper by the image output unit 95. (Printing), communicating this as communication data in a wired or wireless manner, performing a predetermined data compression process in the memory unit 92 and storing it in a good manner, or performing various data processings satisfactorily Can do.

  Although not described in detail in Embodiments 1 to 3, a plurality of light receiving units that photoelectrically convert incident light to provide an image is provided in a two-dimensional manner to form a plurality of pixel units. In the solid-state imaging device, for each pixel unit, a first conductivity type photoelectric conversion unit of the light receiving unit, and a first conductivity type signal detection unit that converts a signal charge transferred from the first conductivity type photoelectric conversion unit into a signal voltage. A second conductivity type well is provided above the first conductivity type substrate, and a first conductivity type photoelectric conversion unit and a first conductivity type signal detection unit are provided in the second conductivity type well, Since the second conductivity type well below the first conductivity type signal detection unit is completely depleted, the pixel size is reduced and the capacitance of the charge detection unit is further reduced, thereby further increasing the charge-voltage conversion rate. It is possible to improve and obtain a higher quality image signal. It can achieve the object of the invention.

  As mentioned above, although this invention has been illustrated using preferable Embodiment 1-4 of this invention, this invention should not be limited and limited to this Embodiment 1-4. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range from the description of specific preferred embodiments 1 to 4 of the present invention based on the description of the present invention and the common general technical knowledge. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a solid-state imaging device configured by a semiconductor element that photoelectrically converts image light from a subject and images the same, and a manufacturing method thereof, for example, a digital video camera and a digital device using the solid-state imaging device as an image input device in an imaging unit. In the field of electronic information equipment such as digital cameras such as still cameras, image input cameras such as surveillance cameras, scanner devices, facsimile devices, television telephone devices, and mobile phone devices with cameras, even if the pixel size is reduced, the above By further reducing the capacity of the charge detection unit, the charge-voltage conversion rate can be further improved and an image signal with higher image quality can be obtained.

DESCRIPTION OF SYMBOLS 1, 1A, 1B Two-dimensional amplification type solid-state image sensor 2, 2A, 2B N-type substrate 3, 3A, 3B P-type well 4 Surface oxide film 5 Surface high concentration diffusion layer 6 Embedded photodiode 7 Charge detection part 8 Charge transfer transistor 8a, 9a Gate 9 Reset transistor 10 Diffusion layer 11 Element isolation oxide film 12, 12A Deep field relaxation layer 13 Amplifier including amplification transistor 14, 14A P-type well for circuit 15 P-type well for photodiode

Claims (14)

In a solid-state imaging device in which a plurality of light receiving units that photoelectrically convert incident light to provide an image are two-dimensionally provided and a plurality of pixel units are configured.
Each pixel unit includes a first conductivity type photoelectric conversion unit of the light receiving unit and a first conductivity type signal detection unit that converts the signal charge transferred from the first conductivity type photoelectric conversion unit into a signal voltage. And
A second conductivity type well is provided on the first conductivity type substrate, and the first conductivity type photoelectric conversion unit and the first conductivity type signal detection unit are provided in the second conductivity type well. A solid state imaging device in which the second conductivity type well below the one conductivity type signal detection unit is completely depleted.   A lower concentration than the impurity concentration of the first conductivity type signal detector at a position below the first conductivity type signal detector at a position including the boundary between the first conductivity type substrate and the second conductivity type well. The solid-state imaging device according to claim 1, wherein a first conductivity type diffusion layer is provided.   The low-concentration first conductivity type diffusion layer is separated from the first conductivity type signal detector in the depth direction so that the second conductivity type well is interposed between the first conductivity type signal detector and the first conductivity type signal detector. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is provided as a deep electric field relaxation layer at a certain position.   The solid-state imaging device according to claim 2, wherein the second conductivity type well below the first conductivity type photoelectric conversion unit is completely depleted.   The depth position of the boundary between the second conductivity type well below the first conductivity type photoelectric conversion portion and the first conductivity type substrate is compared with the case where the neutral region exists in the second conductivity type well. The solid-state imaging device according to claim 4, which is formed shallow.   2. The solid-state imaging device according to claim 1, wherein the second conductivity type well below the first conductivity type signal detection unit is set to have a shallower depth and a lower impurity concentration than the surrounding second conductivity type well.   At the boundary between the second conductivity type well below the first conductivity type signal detection unit and the first conductivity type substrate, a cross-sectional protrusion that protrudes from the flat portion is formed on the first conductivity type signal detection unit side. The solid-state imaging device according to claim 6.   8. The solid-state imaging device according to claim 6, wherein a boundary between the second conductivity type well below the first conductivity type photoelectric conversion portion and the first conductivity type substrate is a stepped portion recessed from a flat portion.   The solid-state imaging device according to claim 1, further comprising an amplifier that amplifies and outputs a signal in accordance with a signal voltage corresponding to the signal charge transferred to the first conductivity type signal detection unit.   The solid-state imaging device according to claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type. The first conductivity type photoelectric conversion unit includes:
A second conductivity type surface high-concentration diffusion layer provided on the surface side of the first conductivity type photoelectric conversion unit; and the second conductivity provided on the first conductivity type substrate side of the first conductivity type photoelectric conversion unit. The solid-state imaging device according to claim 1, comprising a buried photodiode surrounded by a mold well. In the manufacturing method of the solid-state image sensing device according to claim 1,
The first conductivity type impurity is ionized in a region below the region serving as the first conductivity type signal detection unit that converts the signal charge transferred from the first conductivity type photoelectric conversion unit that performs photoelectric conversion of incident light to image the signal voltage. The first conductivity type diffusion layer having a concentration lower than the impurity concentration of the first conductivity type signal detection unit is formed at a position including the boundary between the first conductivity type substrate and the second conductivity type well by implantation. A method for manufacturing a solid-state imaging device, comprising a step of forming one conductivity type diffusion layer. In the manufacturing method of the solid-state image sensing device according to claim 1,
The second conductivity type is formed in a region other than the region below the region serving as the first conductivity type signal detection unit that converts the signal charge transferred from the first conductivity type photoelectric conversion unit that photoelectrically converts incident light to image the signal voltage. The impurity is ion-implanted and then thermally diffused to form a circuit second conductivity type well, thereby forming the first conductivity type as a cross-sectional structure at the boundary between the circuit second conductivity type well and the first conductivity type substrate. A second conductivity type well forming step for forming a cross-sectional protruding portion protruding to the signal detecting portion side;
A second conductive type well for a photoelectric conversion unit is formed by ion-implanting a second conductive type impurity under a region to be the first conductive type photoelectric conversion unit, thereby forming a second conductive type well for the photoelectric conversion unit and A method of manufacturing a solid-state imaging device, comprising: a step of forming a second conductive type well for a photoelectric conversion unit that forms a stepped portion of a cross section recessed toward the first conductive type substrate as a cross-sectional structure at a boundary with the first conductive type substrate.   The electronic information apparatus which used the solid-state image sensor in any one of Claims 1-11 as an image input device for the imaging part.

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