JP2012255978A - Sampling clock generating device and sampling clock generating system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the degradation of an image, when an external environmental temperature and a scanner frequency change, by coinciding an optical scanning range with an electrical scanning range without adding means to detect an optical scanning position.SOLUTION: The sampling clock generating device is equipped with: a PLL sine wave generation part 2 generating a position signal S2 corresponding to a synchronization signal S1 which is synchronized with vibration of a resonance scanner vibrating and simultaneously reflecting or refracting a light from a light source, and radiating the light on a sample; an absolute value processing part 7 generating an absolute value speed signal S7 by converting a speed signal S5 into an absolute value; a VCO10 generating SC with a frequency corresponding to the value of the absolute value speed signal S7; a DE generation part 16 generating a section information of an imaging section including a prescribed number of SC based on the generated SC; a second PD17 calibrating a phase of the position signal S2 so that a scanning range of the resonance scanner coincides with an imaging section range when the displacement occurs between the scanning range and the imaging section range.

Description

  The present invention relates to a sampling clock generation device and a sampling clock generation system.

  Conventionally, as a sampling clock generator for a scanning observation apparatus using a scanner that reflects or refracts light and irradiates a sample while vibrating, a sine wave voltage representing a scanner speed signal is input to a VCO (Voltage Controlled Oscillator). An apparatus that generates a sampling clock at a frequency corresponding to a voltage value is known (see, for example, Patent Document 1 and Patent Document 2).

  In a scanning observation apparatus, a scanning range in which light is scanned on a sample by a scanner (hereinafter referred to as “optical scanning range”) and an observation image range to be sampled according to a sampling clock (hereinafter referred to as “electric scanning range”). However, there is a problem that the phase of the electrical scanning range fluctuates and the image deteriorates due to a change in external environmental temperature or a change in scanner frequency.

  With respect to such a problem, the sampling clock device described in Patent Document 1 stores a correction value for each temperature and responds to a temperature change so that the optical scanning range and the electrical scanning range match. Thus, image deterioration is prevented by correcting the phase of the sampling clock. In addition, the sampling clock generation device described in Patent Document 2 is provided with a detection unit that detects an optical scanning range, and the electrical scanning position matches the optical scanning position detected by the detection unit. Image correction is prevented by correcting the sampling clock in real time.

JP 2003-270562 A JP 2009-145826 A

  However, when the sampling clock is corrected based on the correction value for each temperature as in the sampling clock generation device described in Patent Document 1, the temperature characteristics vary individually, and thus variations in individual temperature characteristics occur. In addition, there is an inconvenience that the correction value must be obtained individually and the work becomes complicated. Further, the sampling clock generator described in Patent Document 1 has a problem that even if it can correct a change in temperature, it cannot correct a change in scanner frequency. In addition, the sampling clock generator described in Patent Document 2 has a disadvantage that a condensing lens, a pinhole plate, a photodetector, an amplifier, and the like must be separately provided as detection means for detecting the optical scanning position.

  The present invention has been made in view of the above-described circumstances, and even if the external environment temperature and the scanner frequency change, the optical scanning range and the electrical scanning range are not provided without separately providing means for detecting the optical scanning position. It is an object of the present invention to provide a sampling clock generation device and a sampling clock generation system capable of preventing deterioration of an image by making them coincide with each other.

In order to achieve the above object, the present invention provides the following means.
The present invention includes a speed signal generation unit that generates a speed signal corresponding to a synchronization signal synchronized with the vibration of a scanning unit that reflects or refracts light from a light source while vibrating or irradiates a sample, and the speed signal generation unit An absolute value speed signal generation unit that generates an absolute value speed signal by converting the speed signal generated by the absolute value, and a sampling clock having a frequency according to the value of the absolute value speed signal generated by the absolute value speed signal generation unit A sampling clock oscillating unit for generating a section information, a section information generating unit for generating section information of an imaging section including a predetermined number of sampling clocks based on the sampling clock generated by the sampling clock oscillating unit, and the section information generating Specified by the imaging section range specified by the section information generated by the section and the synchronization signal output from the synchronization signal output section. A sampling clock generator comprising: a phase correction unit that corrects the phase of the velocity signal so that the scanning range and the imaging section range coincide with each other when a deviation occurs in the scanning range of the scanning means I will provide a.

  According to the present invention, the section information generation unit generates the section information of the imaging section including a predetermined number of sampling clocks, thereby sampling the image information in the imaging section in which scanning by the scanning unit is effectively performed. It is possible to accurately generate a clear image based on the sampled image information.

  In this case, the scanning range of the scanning means is always constant at a specific phase position of the synchronization signal regardless of the external environment temperature and the frequency of the scanning means, whereas the imaging section range is the external environmental temperature and scanning. When the frequency of the means changes, the phase changes due to the change in the phase of the speed signal. The present invention corrects the phase of the velocity signal by the phase correction unit when the deviation between the scanning range by the scanning unit and the imaging section range occurs, so that the phase of the sampling clock generated by the sampling clock oscillation unit is The scan range and the imaging section range are matched with each other. Therefore, even if the phase of the imaging section range fluctuates due to a change in the external environment temperature, a frequency change of the scanning means, etc., the phase of the sampling clock is corrected without providing a means for detecting the scanning range separately, It is possible to prevent the image from deteriorating by matching the imaging section range with the scanning range of the scanning means.

  In the above invention, an address clock oscillating unit that generates an address clock having a frequency multiplied by the synchronizing signal, an address counter that counts an address clock generated from the address clock oscillating unit, and a predetermined count counted by the address counter A phase comparison pulse generation unit that generates a phase comparison pulse signal in synchronization with the address clock of the value, and the speed signal generation unit associates the phase of the speed signal with the phase comparison pulse signal and outputs the speed signal. Generating and comparing the phase difference between the synchronization signal and the speed signal, and when the phase difference changes, the phase comparison is performed so that the phase difference maintains a predetermined value. The predetermined count value for generating the pulse signal may be changed.

  By configuring in this way, since the phase of the speed signal generated by the speed signal generation unit is associated with the phase comparison pulse signal, by changing the count value of the address clock that generates the phase comparison pulse signal, The phase of the speed signal is changed. Therefore, even if the phase of the speed signal fluctuates due to a change in the external environmental temperature or a change in the frequency of the scanning means, the phase correction unit causes the phase difference between the synchronization signal and the speed signal to be imaged with the scanning range by the scanning means. By changing the count value of the address clock so that the value when the interval range matches is maintained, the phase of the speed signal can be returned to an appropriate value.

In the above invention, the phase correction unit may adjust the phase of the speed signal during a stop period of the light source and / or a blanking period of the scanning unit.
If the phase correction unit operates during image acquisition, the image will be adversely affected, so by correcting the phase of the speed signal during the light source stop period and / or the scanning means return period, which is the timing at which the image is not acquired, It is possible to avoid adversely affecting the image.

  In the above invention, the absolute value speed signal generation unit includes an A / D conversion unit for A / D converting the speed signal generated by the speed signal generation unit, and an A / D conversion unit by the A / D conversion unit. A digital operation unit that converts the converted speed signal into an absolute value and a D / A conversion unit that performs D / A conversion on the speed signal converted into an absolute value by the digital operation unit may be provided.

  With this configuration, as in the case of processing an analog signal by the digital arithmetic unit, it is not necessary to generate asymmetric distortion in the signal waveform after absolute value conversion at the rising and falling portions of the signal. . As a result, there is no distortion in the analog absolute value speed signal generated in the D / A converter from the digital absolute value speed signal without asymmetric distortion, and it is generated at a frequency corresponding to the analog absolute value speed signal value. The interval between the sampling clocks to be changed does not change asymmetrically. Therefore, even if an image is formed by using both signals acquired on the forward path side and the backward path side of the scanning unit, a clear image without image shift can be acquired.

Moreover, in the said invention, the said absolute value speed signal production | generation part is good also as performing the linearity correction | amendment calculation which adjusts the offset amount of the said absolute value speed signal.
With this configuration, the frequency of the sampling clock generated by the sampling clock oscillation unit is increased or decreased by raising or lowering the absolute value speed signal input to the sampling clock oscillation unit according to the offset amount to be applied. The waveform of the absolute speed signal can be adjusted to adjust the value. As a result, the sampling clock is generated by suppressing the symmetrical change of the sampling clock due to the non-linearity caused by the individual difference of the scanning means and acquiring a clear image with no image shift. be able to.

Moreover, in the said invention, the said absolute value speed signal production | generation part is good also as generating an absolute value speed signal by carrying out the averaging of the said some speed signal.
With this configuration, it is possible to generate a sampling clock that removes noise from the generated speed signal and can acquire a clear image with high accuracy and no image displacement.

  The present invention also provides two sampling clock generators connected in parallel for outputting the sampling clock and the section information of the imaging period in the forward scanning period and the backward scanning period of the scanning means, and the sampling clock generation Provided is a sampling clock generation system comprising a sampling clock and section information in the forward scanning period output by the apparatus and a clock information combining unit that combines the sampling clock and section information in the backward scanning period.

  According to the present invention, since two sampling clock generators connected in parallel are used in the forward scanning period and the backward scanning period, when the scanning means has different speeds in the forward path and the backward path, in each scanning period, A separate sampling clock can be generated. Then, the generated sampling clock and the imaging interval are synthesized in the clock information synthesis unit, thereby generating a sampling clock that makes it possible to obtain a clear image with no image displacement over the entire round-trip scanning period. Can be made.

  According to the present invention, the optical scanning range is matched with the electrical scanning range to prevent image deterioration even if the external environmental temperature or the scanner frequency is changed without separately providing means for detecting the optical scanning position. There is an effect that can be.

It is a block diagram which shows the scanning observation apparatus to which the sampling clock generator which concerns on one Embodiment of this invention is applied. It is a block diagram which shows the sampling clock generator which concerns on one Embodiment of this invention. FIG. 3 is a block diagram illustrating a PLL sine wave generation unit in FIG. 2. It is the figure which simulated the frequency characteristic of the gain and phase of BPF. It is a graph which shows the synchronous relationship of the position signal and speed signal which are produced | generated in the sampling clock generator of FIG. (A) is a diagram showing the phase difference between the synchronization signal and the comparator signal when the resonance image is good, and (b) is a diagram showing the phase difference between the synchronization signal and the comparator signal when a deviation occurs in the resonance image. is there. It is a figure which shows the phase relationship of a synchronizing signal and a position signal. It is a figure which shows a mode that the phase of a speed signal is fluctuate | varied by disturbance. It is a figure which shows the phase relationship of a position signal, a speed signal, and a sampling clock when a scanning range and an image segmentation range correspond. It is a figure which shows the phase relationship of a position signal, a speed signal, and a sampling clock when a scanning range and an image segmentation range have shifted | deviated. It is a figure which shows the phase relationship of a position signal, a speed signal, and a sampling clock when making a scanning range and an image segmentation range correspond by correction. 1 is a block diagram illustrating a sampling clock generation system according to an embodiment of the present invention. It is a graph which shows the sampling clock and imaging area information which were produced | generated by the sampling clock generation system of FIG. 12, (a) is a digital absolute value speed signal, sampling clock, and imaging area information of an outward path, (b) Is the digital absolute value speed signal, sampling clock, and imaging section information on the return path side, and (c) is the digital absolute value speed signal, sampling clock, and imaging section information after reciprocal synthesis.

A sampling clock generator 1 according to an embodiment of the present invention will be described below with reference to the drawings.
The sampling clock generator 1 according to this embodiment is used in a scanning observation apparatus 100 as shown in FIG.

  The scanning observation apparatus 100 includes a light source 101 that generates illumination light, a light modulation element 102 that modulates illumination light from the light source 101, a scanning unit 103 that scans illumination light in an XY two-dimensional direction, and scanned illumination light. The pupil projection lens 104, the imaging lens 105, and the objective lens 106, and the return light from the sample A that is collected by the objective lens 106 and returns via the imaging lens 105, the pupil projection lens 104, and the scanning unit 103. Is provided with a dichroic mirror 107 for branching and a photodetector 108 for detecting the branched return light. Reference numeral 109 is a mirror, reference numeral 110 is a barrier filter, reference numeral 111 is a confocal lens, reference numeral 112 is a confocal pinhole, and reference numeral 113 is a stage.

The scanning unit 103 includes a galvano mirror 103b that deflects illumination light in the Y direction and a resonance scanner (scanning means) 103a that deflects the illumination light in the X direction. However, the present invention is not limited to this configuration. For example, the scanning unit 103 may have a configuration in which a scanner for X-direction scanning and a scanner for Y-direction scanning are independent, or a galvanometer mirror may be used for the scanning means 103a that deflects in the X direction.
In the figure, reference numeral 114 denotes a control device that generates an image by controlling the light modulation element 102, the scanning unit 103, the photodetector 108, and the stage 113, and reference numeral 115 denotes a monitor that displays the generated image.

  The sampling clock generator 1 according to this embodiment generates a sampling clock SC synchronized with the operation of the resonance scanner 103a from the synchronization signal S1 output from the resonance scanner 103a, and outputs it to the control device 114. The control device 114 samples and arranges the intensity of the return light from the sample A detected by the photodetector 108 at a timing according to the sampling clock SC sent from the sampling clock generator 1, thereby arranging the sample A. The two-dimensional image is generated.

  The sampling clock generator 1 according to the present embodiment receives a synchronizing signal S1 output from the resonant scanner 103a that is resonantly oscillated at about 8 kHz, and is synchronized with the resonant oscillation, and receives the sampling clock SC and the imaging interval signal ( Hereinafter, it is a device that outputs DE).

  As shown in FIG. 2, the sampling clock generator 1 generates a PLL sine wave that outputs a position signal (speed signal) S2 composed of a sine wave signal synchronized with the synchronization signal S1 when the synchronization signal S1 is inputted. Unit (speed signal generation unit) 2, variable gain adjustment unit 3 that adjusts the gain applied to the position signal S 2 output from the PLL sine wave generation unit 2, and jitter noise is removed from the gain-adjusted input position signal S 3. As described above, a band pass filter (BPF) 4 having a center wavelength at the resonance frequency of the resonance scanner 103a and a position feedback unit 5 that converts the position signal S4 that has passed through the band pass filter 4 into a speed signal S5 are provided.

  As shown in FIG. 3, the PLL sine wave generating unit 2 includes a PLL circuit (address clock oscillating unit) 31 that generates an address clock (address CLK) having a frequency that is an integral multiple (for example, multiplied by 1164) of the synchronization signal S1. An address counter 33 that counts the number of address clocks generated by the PLL circuit 31, a RAM (Random Access Memory) 35 that stores sine wave waveform data, and an address clock with a predetermined count value counted by the address counter 33 The sine wave waveform data stored in the RAM 35 is reproduced with the address clock counted by the decoder (phase comparison pulse generator) 37 and the address counter 33 generating the phase comparison pulse signal S17 in synchronization with Synchronized with the waveform of the sync signal S1 And a position signal generation unit 39 for generating a position signal S2 of sine wave.

The address counter 33 repeats the operation of resetting the count value to zero when the count value of the address clock reaches, for example, 1164.
The decoder 37 is set to generate the phase comparison pulse signal S17 when the count value by the address counter 33 is a predetermined value, for example, the count value is zero.
The position signal generator 39 associates the phase of the position signal S2 with the phase comparison pulse signal S17 generated by the decoder 37 and generates the position signal S2.

  Returning to FIG. 2, the BPF 4 has a frequency-phase characteristic in which the phase of the output position signal S4 changes when the frequency of the input position signal S3 changes with respect to the center frequency. For example, FIG. 4 is a simulation of the gain and phase frequency characteristics of the BPF 4. The center frequency of BPF 4 is 8 KHz. As shown in the figure, it can be seen that when the frequency of the input position signal S3 changes to ± with respect to 8 kHz, the phase of the output position signal S4 also changes. In addition, due to the temperature characteristics of the BPF 4, even if the frequency of the input position signal S3 does not change, the center frequency of the BPF 4 fluctuates due to changes in the external environment temperature, and the phase of the output position signal S4 changes. There are things to do.

  The position feedback unit 5 calculates a speed signal S5 by subtracting a position reproduction signal S11 based on a sampling clock SC output from the VCO 10 described later from the input position signal S4.

Further, the sampling clock generator 1 digitally samples an analog speed signal S5 composed of the generated sine wave signal at a sampling rate of 80 MHz and converts it into a digital speed signal S6 (AD converter: absolute) (Value speed signal generation section) 6 and an absolute value processing section for generating a digital absolute value speed signal S7 by turning the negative amplitude portion of the digital speed signal S6 converted by the A / D converter 6 as a positive amplitude. (Digital operation part: absolute value speed signal generation part) 7, linear correction part (absolute value speed signal generation part) 8 for performing offset processing by an amount preset in the digital absolute value speed signal S 7, and offset processing D / A converter (D / A conversion unit) that generates digital absolute value speed signal S9 by D / A converting digital absolute value speed signal S8 The absolute value speed signal generator) 9, and a VCO (sampling clock oscillating unit) 10 for generating the sampling clock SC having a frequency corresponding to the voltage value of the analog absolute value speed signal S9. Reference numeral 19 indicates an FVC (Frequency to Voltage Converter, frequency / voltage converter).
As a result, the VCO 10 generates unequally spaced sampling clocks SC whose intervals change according to changes in the speed of the resonant scanner 103a.

  The sampling clock generator 1 further includes an up / down counter 11 that counts the sampling clock SC generated by the VCO 10. The up / down counter 11 repeatedly counts the sampling clock SC output from the VCO 10 up to, for example, a count value of 0 to 582 and then down to 0 after 582, as shown in FIG. A reproduction position signal S10 corresponding to the position of the resonant scanner 103a is generated.

  The reproduction position signal S10 generated by the up / down counter 11 is converted into an analog position reproduction signal S11 by being input to the D / A converter 12, and is input to the position feedback unit 5. The up / down counter 11 is also configured to output an up / down signal S12 and a count value S13, each of which is a square wave that is HIGH during up-counting and LOW during down-counting.

  The digital speed signal S6 converted by the A / D converter 6 is also output to the comparator 13. The comparator 13 determines the sign of the input digital speed signal S6, and outputs a comparator signal S14 composed of a rectangular wave that is HIGH when the sign is negative and LOW when the sign is positive.

  The sampling clock generator 1 also detects a phase shift between the comparator signal S14 output from the comparator 13 and the up / down signal S12 output from the up / down counter 11 (hereinafter referred to as a first PD) 14. And a low-pass filter (hereinafter referred to as LPF) 15 that dulls the phase shift detection signal S15 output from the first PD 14 and inputs the detection signal S15 to the variable gain adjustment unit 3.

  As shown in FIG. 5, the comparator signal S14 represents the phase of the digital velocity signal S6 generated from the position signal of the resonant scanner 103a, and the up / down signal S12 is reproduced from the sampling clock SC generated by the VCO 10. It represents the phase of the position signal S10. Therefore, when these phases do not match, the gain of the variable gain adjusting unit 3 is adjusted, and when they match, the gain is fixed to exist in one period of the resonant scanner 103a. The number of sampling clocks SC can be fixed. In the above example, the round-trip count value S13 of the up / down counter 11 fixes 582 + 582 = 1164 sampling clocks SC to a gain that is accurately included in one period of the resonant scanner 103a.

  The sampling clock generator 1 also includes a DE generation unit (section information generation unit) 16 that generates an imaging section signal DE that represents information of an imaging section based on the count value S13 output from the up / down counter 11. I have.

As a result, the sampling clock generator 1 according to the present embodiment includes 1164 sampling clocks SC at unequal intervals synchronized with the operation of the resonant scanner 103a, and a rectangular wave indicating an imaging interval within the sampling clock SC. The imaging section signal DE is output.
By sampling the return light from the sample A detected by the photodetector 108 of the scanning observation apparatus 100 according to the sampling clock SC in the imaging section generated by the sampling clock generator 1, the reciprocating operation of the resonant scanner 103a. In both cases, image information can be acquired.

  The sampling clock generator 1 compares the phase difference between the synchronization signal S1 and the comparator signal (speed signal) S14 output from the comparator 13, and generates a PLL sine wave so that the phase difference maintains a predetermined value. A phase correction unit (hereinafter referred to as a second PD) 17 that controls the address counter 33 of the unit 2 is provided.

  When the phase difference between the synchronization signal S1 and the comparator signal S14 changes, the second PD 17 uses the scanning range of the resonant scanner 103a specified by the synchronization signal S1 and the imaging section signal DE generated by the DE generation unit 16. The count value for generating the phase comparison pulse signal S17 of the address counter 33 is changed so as to maintain a predetermined phase difference when the specified imaging section range coincides.

  Since the phase of the position signal S2 generated by the position signal generation unit 39 is associated with the phase comparison pulse signal S17, the position signal generation unit is changed when the count value of the address clock that generates the phase comparison pulse signal S17 is changed. The read position of the sine wave waveform data from the RAM 35 by 39 is changed, and the phase of the position signal S2 changes. As a result, the phase of the speed signal S5 generated by the position feedback unit 5 is changed, and the phase of the sampling clock SC generated by the VCO 10 is also changed. As a result, when a deviation occurs between the scanning range of the resonant scanner 103a and the imaging section range, the phase of the position signal S2 is corrected by the second PD 17 so that the scanning range and the imaging section range coincide with each other. It is like that.

  The phase difference between the synchronization signal S1 and the comparator signal S14 is determined by, for example, setting an appropriate chart sample in the microscope field of view in the microscope observation, and then acquiring an image with a scanning microscope observation image (LSM image) with the sample set in the state. In this case, the chart sample image can be obtained by detecting the phase difference between the synchronization signal S1 and the comparator signal S14 in a state in which the image section range on the LSM image side is adjusted so that the microscope observation image and the LSM image coincide with each other. . At this predetermined phase difference, the scanning range and the imaging interval range are the same.

  Resonance images are always good when the phase difference is zero (scanning range and imaging interval range) due to various optical deviation factors and electrical delay factors such as microscope optical system tolerance and detection to electrical delay of image display means. Is not the same.) There is an aircraft difference. Therefore, an optimum predetermined phase difference for each airframe is set as the adjustment value in the second PD 17.

  For example, as shown in FIG. 6A, it is assumed that the phase difference between the synchronization signal S1 and the comparator signal S14 is the address count value 6 when the resonance image is good. In this case, as shown in FIG. 6B, when the resonance image is shifted and the phase difference between the synchronization signal S1 and the comparator signal S14 is changed (for example, the phase difference is changed to the address count value 3), these are changed. The address counter 33 is controlled by the second PD 17 so that the phase difference returns to the address count value 6.

  Further, the second PD 17 adjusts the phase of the speed signal S5 by changing the count value for generating the phase comparison pulse signal S17 during the stop period of the light source 101 and the blanking period of the resonant scanner 103a.

The operation of the sampling clock generator 1 according to this embodiment configured as described above will be described below.
In order to observe the sample A by the scanning observation apparatus 100, illumination light is generated from the light source 101, and the sample A is made by the objective lens 106 via the light modulation element 102, the scanning unit 103, the pupil projection lens 104, and the imaging lens 105. Illuminate with illumination light. In this case, the illumination light is scanned two-dimensionally on the sample A by the operation of the scanning unit 103. The return light returning from the sample A returns in the reverse direction through the objective lens 106, the imaging lens 105, the pupil projection lens 104, and the scanning unit 103, and is branched from the illumination light by the dichroic mirror 107 and is detected by the photodetector 108. Detected.

  In the sampling clock generator 1, an address clock synchronized with the operation of the resonance scanner 103a is generated from the synchronization signal S1 output from the resonance scanner 103a of the scanning unit 103. Specifically, in the PLL sine wave generator 2, as shown in FIG. 7, the PLL circuit 31 generates an address clock that is an integral multiple of the synchronization signal S <b> 1 (galvano sync) (in this embodiment, multiplied by 1164). Generated. Next, the address counter 33 counts the number of address clocks, and when the address counter value reaches 1164, the operation of resetting to zero is repeated.

  The decoder 37 generates a phase comparison pulse signal S17 when the address counter value is zero, and the phase comparison pulse signal S17 is controlled so as to follow the rising edge of the input synchronization signal S1. When the rising edge of the phase comparison pulse signal S17 does not coincide with the rising edge of the synchronization signal S1, the control for changing the clock frequency so as to coincide is repeated.

  Next, the sine wave waveform data stored in the RAM 35 is reproduced by the position signal generator 39 using the address counter value as an address. As a result, a position signal S2 that is synchronized with the synchronization signal S1 and whose phase is associated with the phase comparison pulse signal S17 is generated. Since the phase of the position signal S2 is related to the phase comparison pulse signal S17, when the address counter value for generating the phase comparison pulse signal S17 is changed, the read address of the RAM 35 is changed and the phase of the position signal S2 is shifted (phase shift adjustment). )

  The position signal S2 generated by the position signal generation unit 39 is input to the position feedback unit 5 via the variable gain adjustment unit 3 and the BPF 4, and is converted into a speed signal S5 by the position feedback unit 5. Next, the speed signal S5 is converted into a digital speed signal S6 by the A / D converter 6 and converted into the digital absolute value speed signal S7 by the absolute value processing unit 7, and then D / A converted through the linear correction unit 8. The signal is input to the unit 9 and converted into an analog absolute value speed signal S9. When the analog absolute value speed signal S 9 is input to the VCO 10, the sampling clock SC is generated by the VCO 10 and sent to the control device 114.

  The control device 114 samples and arranges the intensity of the return light from the sample A detected by the photodetector 108 at a timing according to the sampling clock SC sent from the sampling clock generator 1. Thereby, a two-dimensional image of the sample A is generated.

  According to the sampling clock generator 1 according to the present embodiment, the DE generation unit 16 generates the imaging interval signal DE including a predetermined number of sampling clocks, so that the scanning by the resonance scanner 103a is effectively performed. In the section, image information can be sampled with high accuracy, and a clear image can be generated based on the sampled image information. Thereby, the sample A can be observed favorably.

  Here, the speed signal S4 output by the BPF 4 is a change in the external environment temperature or a change in the scanner frequency due to the characteristics of the BPF 4 (for example, when the scanning means is a resonant scanner, the resonance frequency changes due to the environmental temperature change). The phase may change due to the influence. For example, as shown in FIG. 8, the phase change of the position signal S4 after passing through the BPF 4 (the signal in the fifth stage from the top of the figure. The solid line shows the signal before the phase change, and the chain line shows the phase change. The latter signal indicates that the velocity signals S5 and S6, the absolute value signals S7, S8, and S9, the sampling clock SC, and the imaging interval signal DE in the subsequent stage are also affected as phase fluctuations.

  As a result, the phase of the scanning range of the resonant scanner 103a is always constant at a specific phase position of the synchronization signal S1 regardless of the external environment temperature and the scanner frequency, whereas the phase of the imaging section range is a PLL sine wave. Even if the processing by the generating unit 2 follows the synchronization signal S1 synchronously, if the external environment temperature or the scanner frequency changes, the phase of the speed signal S5 changes.

  In the sampling clock generator 1 according to the present embodiment, the second PD 17 compares the phase difference between the synchronization signal S1 and the comparator signal S14, and the position signal S2 generated by the PLL sine wave generator 2 according to the comparison result. Is corrected. For example, as shown in FIG. 9, when the sampling clock SC is generated using the phase comparison pulse signal S17 generated with the address clock count value 0, the synchronization signal S1 and the comparator signal S14 have a predetermined phase difference. If this is maintained, the scanning range of the resonant scanner 103a and the imaging section range coincide.

  However, when the phase of the speed signal S5, the sampling clock SC, the image valid section signal DE, and the like changes due to disturbance such as a change in external temperature, the scanning range of the resonant scanner 103a and the imaging section range are shifted as shown in FIG. Occurs. In this case, as the phase difference between the synchronization signal S1 and the comparator signal S14 changes, the second PD 17 changes the address count value for generating the phase comparison pulse signal S17 to, for example, the count value 5, as shown in FIG. The phase of the position signal S2 (RAM waveform data) generated by the position signal generation unit 39 is shifted.

  Thereby, the phase relationship of the signals after the position signal S2 is uniformly shifted, and the phases of the final sampling clock SC and the image valid section signal DE are also shifted. When the time difference between the rising edge of the synchronization signal S1 and the rising edge of the comparator signal S14 is returned to a predetermined phase difference, the imaging section range is matched with the scanning range of the resonant scanner 103a.

  The phase adjustment of the position signal S2 by the second PD 17 is performed in the stop period of the light source 101 and the blanking period of the resonance scanner 103a. If the second PD 17 operates during image acquisition, the image is adversely affected. Therefore, it is possible to avoid adversely affecting the image by correcting the phase of the position signal S2 at the timing when the image is not acquired. The phase adjustment of the position signal S2 may be performed during the stop period of the light source 101 or the blanking period of the resonance scanner 103a.

  As described above, according to the sampling clock generator 1 according to the present embodiment, the phase of the position signal S2 is corrected by the second PD 17 when a deviation occurs between the scanning range by the resonant scanner 103a and the imaging section range. Thus, the phase of the sampling clock SC generated by the VCO 10 is returned to an appropriate value, and the scanning range and the imaging section range are matched. Therefore, even if the phase of the imaging section range fluctuates due to a change in the external environmental temperature or a change in the frequency of the scanning means, the phase of the sampling clock SC is corrected without providing a means for detecting the scanning range. Thus, it is possible to prevent the image from deteriorating by matching the imaging section range with the scanning range of the resonant scanner 103a.

  Further, when the analog absolute value speed signal S9 to be input to the VCO 10 is generated, it is converted into an absolute value by digital signal processing without using analog signal processing. Therefore, the rising and falling portions of the signal generated in the analog signal processing It is also possible to prevent the slight distortion of the speed signal waveform after the absolute value in FIG.

  As a result, it is possible to prevent the interval of the sampling clock SC generated by the VCO 10 at a frequency corresponding to the analog absolute value speed signal S9 from changing asymmetrically. Accordingly, there is an advantage that a clear image without image displacement can be acquired even when an image is formed using both signals acquired on the forward path side and the return path side of the resonance scanner 103a.

  Further, there is an advantage that the linear correction unit 8 can easily add an offset to the digital absolute value speed signal S7 converted into an absolute value by digital signal processing by digital signal processing. For example, when the offset amount is increased, the amplitude of the digital absolute value speed signal S7 at that moment also increases by the offset amount, so that the number of sampling clocks SC in one period of the resonant scanner 103a output from the VCO 10 is also 1164. That's it. However, as described above, control is performed to feed back to the variable gain adjusting unit 3 so that the number of sampling clocks SC in one cycle of the resonant scanner 103a is exactly 1164. The gain is adjusted so that the amplitude of the input position signal S4 is immediately reduced.

  As a result, the absolute speed signal input to the VCO 10 is raised or lowered according to the applied offset amount, and the number of sampling clocks SC in one cycle of the resonant scanner 103a is kept at 1164. The waveform of the absolute value speed signal can be adjusted so as to adjust the frequency. By doing so, it is possible to obtain a clear image with no image shift by suppressing the symmetrical change of the sampling clock SC due to the nonlinearity caused by the individual difference of the resonant scanner 103a. The sampling clock SC to be generated can be generated. The setting of the offset amount may be performed manually or may be configured to be performed automatically.

  In the present embodiment, the phase difference between the synchronization signal S1 and the comparator signal S14 is compared. However, in order to detect drift (phase fluctuation) in the imaging section range, the signal phase before the occurrence of drift due to temperature or the like is detected. The phase shift amount may be detected by comparing (the phase of the signal before passing through BPF4) with the signal phase after the occurrence of drift (the phase of the signal after passing through BPF4). Therefore, the signal to be compared may be selected before and after the passage of the BPF 4, but it is more digital circuit to compare the phase of the square wave signal than to compare the phase of the sine wave signal. There is a merit that is easy to realize.

  The PLL sine wave generator 2 generates the position signal S2 composed of a sine wave having a phase that matches the synchronization signal S1 output from the resonance scanner 103a. However, after the synchronization signal S1 is input, the PLL sine wave generation unit 2 generates the position signal S2. A delay time that cannot be ignored occurs before the final sampling clock SC is generated. There is also a delay time between the actual position of the resonant scanner 103a and the synchronization signal S1. Furthermore, a delay time also occurs in the control device 114 that samples the intensity of the return light detected by the photodetector 108 based on the sampling clock SC. Therefore, the PLL sine wave generator 2 may adjust the phase of the position signal S2 output from the PLL sine wave generator 2 in consideration of these various delay times. Thereby, the influence of the delay time on the finally obtained image can be suppressed.

  In this embodiment, the single sampling clock generator 1 generates the forward and backward sampling clocks SC and the imaging section information DE of the resonant scanner 103a. Instead, as shown in FIG. 12, a sampling clock generation system 20 in which two sampling clock generators 1A and 1B are connected in parallel may be employed.

  The sampling clock generation system 20 combines the forward and backward sampling clocks SCA and SCB generated by the sampling clock generators 1A and 1B with the forward and backward imaging section information DEA and DEB. A combining unit 21 is provided. As a result, as shown in FIGS. 13A and 13B, the forward and backward sampling clocks SCA and SCB and the imaging section information DEA and DEB are generated separately, and the subsequent synthesizing unit 21 performs FIG. As shown in (c), the synthesized round-trip sampling clock SC and imaging interval information DE can be output.

  According to such a sampling clock generation system 20, even if the scanning time and speed change of the resonant scanner 103a are different between the forward path and the backward path, different gain adjustment and offset amount adjustment are performed on the forward path side and the backward path side, and the forward path is performed. There is an advantage that it is possible to acquire a good image with no image shift using the light intensity of the return light acquired in step 1 and the light intensity of the return light acquired in the return path.

  In this embodiment, the speed signal S5 is digitally sampled, A / D converted, and subjected to absolute value processing. However, noise may be added to the signal at the time of digital sampling. Alternatively, each digital speed signal S6 may be generated by averaging the plurality of speed signal values. For example, the digital speed signal S6 (T) at the time T may be obtained by averaging the two or more digital signals S6 (T-1) and S6 (T-2) before the time T.

As a result, noise in the generated digital speed signal S6 and digital absolute value speed signal S7 can be greatly reduced.
In this case as well, since a delay time occurs, the influence of the delay time on the finally obtained image is suppressed by adding the adjustment to the delay time in this calculation to the adjustment of the phase of the position signal S2. You can do it.

  In the present embodiment, absolute value conversion and linear correction are performed in a state converted into a digital signal. However, digital signal processing is not limited to absolute value conversion and linear correction, and various methods can be performed relatively easily. Signal adjustment can be performed.

A Sample SC Sampling clock DE Imaging section signal (imaging section information)
S1 Sync signal S2 Position signal (speed signal)
S5 Speed signal S7 Digital absolute value speed signal S9 Analog absolute value speed signal 1, 1A, 1B Sampling clock generator 2 PLL sine wave generator (speed signal generator)
6 A / D converter (A / D converter: absolute value speed signal generator)
7 Absolute value processing unit (digital operation unit: absolute value speed signal generation unit)
8 Linear correction part (digital operation part)
9 D / A converter (D / A converter: absolute value speed signal generator)
10 VCO (sampling clock oscillator)
16 DE generator (section information generator)
17 Second PD (Phase Correction Unit)
20 sampling clock generation system 21 synthesis unit (clock information synthesis unit)
37 Decoder (Phase comparison pulse generator)
101 Light source 103a Resonant scanner (scanning means)

Claims (7)

A speed signal generation unit that generates a speed signal corresponding to a synchronization signal synchronized with the vibration of the scanning unit that irradiates the sample while reflecting or refracting light from the light source while vibrating;
An absolute value speed signal generating unit that generates an absolute value speed signal by converting the speed signal generated by the speed signal generating unit into an absolute value;
A sampling clock oscillator for generating a sampling clock having a frequency according to the value of the absolute value speed signal generated by the absolute value speed signal generator;
A section information generation unit that generates section information of an imaging section including a predetermined number of sampling clocks based on the sampling clock generated by the sampling clock oscillation unit;
When a deviation occurs between the imaging section range specified by the section information generated by the section information generation unit and the scanning range of the scanning unit specified by the synchronization signal output from the synchronization signal output unit, A sampling clock generator comprising: a phase correction unit that corrects the phase of the speed signal so that the scanning range and the imaging section range match. An address clock oscillator for generating an address clock having a frequency multiplied by the synchronization signal;
An address counter for counting an address clock generated from the address clock oscillation unit;
A phase comparison pulse generator for generating a phase comparison pulse signal in synchronization with the address clock of a predetermined count value counted by the address counter,
The speed signal generating unit associates the phase of the speed signal with the phase comparison pulse signal to generate the speed signal;
The phase correction unit compares the phase difference between the synchronization signal and the speed signal, and changes the phase comparison pulse signal so that the phase difference maintains a predetermined value when the phase difference changes. The sampling clock generator according to claim 1, wherein the predetermined count value to be generated is changed.   The sampling clock generator according to claim 1 or 2, wherein the phase correction unit adjusts the phase of the speed signal during a stop period of the light source and / or a blanking period of the scanning unit. The absolute value speed signal generation unit, an A / D conversion unit for A / D converting the speed signal generated by the speed signal generation unit;
A digital operation unit for converting the speed signal A / D converted by the A / D conversion unit into an absolute value;
The sampling clock generator according to any one of claims 1 to 3, further comprising a D / A converter that performs D / A conversion on the velocity signal converted into an absolute value by the digital arithmetic unit.   5. The sampling clock generator according to claim 1, wherein the absolute value speed signal generation unit performs a linearity correction calculation for adjusting an offset amount of the absolute value speed signal.   The sampling clock generator according to claim 1, wherein the absolute value speed signal generation unit generates an absolute value speed signal by averaging the plurality of speed signals. 7. The sampling clock generator according to claim 1, wherein the sampling clock generator is connected in parallel to output a sampling clock and section information of an imaging section in the forward scanning period and the backward scanning period of the scanning unit, respectively. When,
A sampling clock generating system comprising: a clock information synthesizing unit that synthesizes a sampling clock and interval information in the forward scanning period output from the sampling clock generator and a sampling clock and interval information in the backward scanning period.

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