JP2012118821A - Data transfer apparatus, printer and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that it is necessary to reduce power consumption of an inter-chip interface in a data transfer apparatus where a data output section and a data control section which executes image processing, are connected by an inter-chip bus using the inter-chip interface.SOLUTION: In a system where a receiving side has a command interface which shifts an inter-chip interface to a power saving state, when data transfer is completed, a command to shift a receiving-side interface to a low power consumption state is transmitted in the data transfer completion. On the basis of timing to start data transfer, a command for shifting to power saving is issued in the case where the time until starting transferring the next data is longer than the time required for shifting to the power saving state and recovery from the power saving state.

Description

  The present invention relates to a data transfer system, and more particularly to a data transfer apparatus, a data transfer method, or a program for transferring data to an output device for outputting (printing, displaying, etc.) digital image data.

  In recent years, output images of digital image processing apparatuses have been increased in speed and definition. In addition, the final output unit must always output image data at regular intervals. Therefore, the final output unit requires a buffer memory.

  On the other hand, in recent years, a high-speed connection standard has been defined for chip-to-chip connection, and a method for performing data transfer using this high-speed connection standard has also been proposed (for example, Patent Document 1).

  In PCI-Express used in Patent Document 1, a link state of L0 / L0s / L1 / L2 is defined in the standard in order to keep power consumption low. L0 is a normal state, L0s to L2 are power saving states, and power consumption is defined to decrease in order from L0s to L2. In Patent Document 1, in a system for transferring image data in synchronization with a line synchronization signal or a frame synchronization signal, each packet interval in a series of transfers activated in line synchronization is a power saving defined in the PCI-Express standard. A technique for making the transition time to the state L0s or less is disclosed. According to Patent Document 1, the power saving effect can be improved by lengthening the time of the L0s power saving state as a whole without performing unnecessary transition to L0s during a series of data transfers.

JP2006-201909

“Outline of the PCI-Express standard” Interface magazine, July 2003, Naoshi Satomi (pages 80-92) “PCI Express System Architecture”, MindShare, Inc. (Pp. 567-645)

  However, since the method described in Patent Document 1 uses the L0s state having a low power saving effect among the power saving states defined by the PCI-Express standard, a significant improvement in the power saving effect cannot be expected. In addition, since the power saving transition defined in the PCI-Express standard changes based on the time during which the data transfer is not performed (logical idle), it is saved after the data transfer is completed. It took extra time to shift to the power state.

  Accordingly, an object of the present invention is to provide a data transfer device, a data transfer method, or a program that quickly shifts power consumption during a period in which the data transfer system does not perform data transfer to a state where the power saving effect is higher.

  In order to solve the above-described problem, a data transfer apparatus according to the present invention includes a memory, timing instruction means for indicating a start timing of output of data from the memory, and data held in the memory based on the timing instruction means. A first interface that outputs data, a second interface that transfers data from the first interface to a buffer, a start timing of data output indicated by the timing instruction means, and the first and second interfaces. Control means for issuing a command for shifting the first and second interfaces to the power saving state based on the total time required for shifting to the power saving state and returning from the power saving state. It is characterized by that.

  By using the present invention, the high-speed interface between the transfer data transmission side and the reception side can be shifted to a power saving state during a period from the completion of a series of data transfer to the start of the next series of data transfer.

1 is an overall schematic diagram of a data transfer apparatus according to the present invention. It is a flowchart explaining the operation | movement outline | summary of the transmission side of this invention. 4 is a timing chart showing a timing signal from the image data output unit 10 and a reception state of the data control unit 1. The structure of a request block circuit is shown. The signal transition regarding a request | requirement block circuit is shown. It is a figure which shows the definition of the link state of PCI-Express. It is a timing chart which shows control of active state power management.

  First, an outline of power saving management of PCI-Express (hereinafter referred to as PCIe) will be described.

  In PCIe, a link state of L0 / L0s / L1 / L2 is defined in order to keep power consumption low as shown in FIG. L0 is a normal mode, and power consumption is lower from L0s to L2, and a higher power saving effect can be expected. FIGS. 7A to 7C are timing charts showing the L2, L1, and L0s states and the data transfer state (normal state). In FIG. 7A, the power saving mode of the L2 state is entered in ms order (the period is indicated by “L2”), and the software-controlled power management is performed. In FIG. 7B, the power saving mode of the L1 state is entered with μs order (the period is indicated by “L1”). In FIG. 7C, the power saving mode is entered in the order of ns (the period is indicated by “L0s”). L0s and L1 perform power management by hardware control.

  Time is required to shift to the power saving mode of these L0s / L1 / L2 states and to return to the L0 state (normal mode) from each power saving mode. In L0s where this time is the shortest, the time required for recovery is 16 ns to 4 μs. As a condition for transition to the power saving state, the PCIe standard defines that transition is performed when a state in which no communication exists on the link (logical idle state) continues for a device-specific period.

  Next, an outline of the transition to the L1 state and its return will be described. Transition to the power saving control (Active State Power Management, hereinafter referred to as ASPM) L1 state by hardware control is requested from the downstream component (reception side in this example), and the transition processing is started. The downstream component attempting to start the transition to ASPM_L1 transmits an L1 transition request (Data Link Layer Packet defined as PM_Active_State_Request_L1) to the upstream component (the transmitting side in this example).

  If the upstream component accepts the L1 transition request, the upstream component sends a receipt notification (Data Link Layer Packet defined as PM_Request_Ack) to the downstream component. The downstream component that receives the receipt notification transitions the link to an electrical idle state. The upstream component confirms that the link (between the downstream components) has transitioned to an electrical idle state, and itself is also in an electrical idle state (DC Common Mode Voltage on both the TX and TX terminals that are operational outputs). State that outputs DC voltage within the defined range.) The state transition to the L1 state is completed by the sequence as described above.

  On the other hand, the standard stipulates that the return from L1 can be started from either the upstream component or the downstream component. It is defined in the standard that a component that wants to communicate via a link in the L1 state starts communication after returning its transmitting side to the L0 state. The standard also defines the procedure for returning from the L1 state to the L0 state.

(Embodiment 1)
FIG. 1 shows an overall schematic block diagram of an information processing apparatus (printer) according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a data control unit that receives and holds print data from a host computer (not shown). The data control unit 1 functions as a data transmission side in this embodiment. A host interface 2 communicates with the host computer. A central processing unit (hereinafter referred to as a CPU) 3 controls the entire printer. Reference numeral 4 denotes a direct memory access unit (hereinafter referred to as a DMA unit) that transfers data from the data control unit 1 to an image data output unit 10 (functioning as a receiving side in the present invention) described later. Reference numeral 5 denotes a memory control unit, and reference numeral 6 denotes a memory device controlled by the memory control unit 5. 7 is a timer circuit (timing instruction means) for measuring the time interval and notifying the start timing of the output of data held in the memory 6, and 8 is an interrupt receiving circuit for receiving a timing signal from the image data output unit 10. It is. Reference numeral 9 denotes an inter-chip interface (first interface) for inter-chip bus connection on the data control unit 1 side. Reference numeral 10 denotes an image data output unit that actually controls the printing process. Reference numeral 11 denotes an inter-chip interface (second interface, hereinafter referred to as inter-chip IF) for inter-chip bus connection on the image data output unit side. An image data output interface (third interface) 12 outputs image data to a print engine (not shown). An image data output control unit 13 controls each circuit of the image data output unit 10 and the print engine. Reference numeral 14 denotes a request block circuit that blocks an access request from the image data output unit 10 to the data control unit 1 using the inter-chip IF 11.

  FIG. 2 is a flowchart showing the processing of the data control unit 1, and FIG. 3 shows the timing signal from the image data output unit 10 and the reception state of the data control unit 1.

The operation of the data control unit 1 of this embodiment will be described with reference to FIG.
First, when the printer system is initialized, the data control unit 1 acquires information on the image data output unit 10 from the image data output unit 10 (S21). The information acquired here includes the size of the image buffer of the image data output interface 12, the image output data rate, the time required for transition to the power saving state (first required time), and the time required for returning from the power saving state ( Data specific to the image output unit 10 including information such as (second required time).

  Here, the data control unit 1 calculates the amount of data that can be held by the image data output unit 10 based on the data acquired from the image data output unit 10 before the image data output unit 10 starts outputting the image data. . Then, the interval of data transfer from the data control unit 1 to the image data output unit 10 and the size of the data to be transferred in one normal transfer operation (second data transfer amount) are determined.

  The data control unit 1 that has received a print instruction from a host computer (not shown) via the host interface 2 makes a transition as having output (S22, YES). Then, the data output unit 1 calculates the data transfer start count based on the transfer interval, the data transfer amount at the start of one data transfer, and the page data amount, and sets them (S23). In this embodiment, the CPU unit 3 sets the transfer interval in the timer circuit 7 and the data transfer amount in the DMA unit 4, and the CPU unit 3 holds the number of data transfer activations. After making these settings, the data control unit 1 performs initial data transfer to the image data output unit 10, and instructs the image data output unit 10 to start outputting (printing) image data (S24).

Here, the data transfer amount (first data transfer amount) transferred in the initial data transfer can be determined as follows according to the information acquired in S21.
Initial data transfer amount ≤ Image data buffer size transfer interval is
Transfer interval ≤ Image data buffer size / Image output data rate In reality, there is a delay associated with data transfer between chips, so it is necessary to provide a sufficient margin for the transfer interval.
The transfer amount transferred in one data transfer (second data transfer amount) is
Transfer amount = Image output data rate * Transfer interval can be determined. Actually, a transfer amount specified by Max_Payload_Size, a parameter set by the inter-chip IF software, is considered, and a combination of the transfer amount and the transfer interval is determined.
If the transfer amount is obtained, the number of transfers (the number of activations of the DMA unit necessary for transferring one page of data) can be obtained from the data size of the output page by the following equation.
Transfer count * Transfer amount ≧ Page data size The data control unit 1 performs the above setting, starts the image data output process of the image data output interface unit 12, and waits for an output start signal indicating that image output has started (S25). ). The output start signal can be received by the interrupt receiving circuit 8 using inter-chip communication. When receiving the output start signal, the interrupt receiving circuit 8 notifies the CPU unit 3 of the interrupt signal. Receiving the interrupt notification, the CPU unit 3 instructs the timer circuit 7 to start the count operation (S26).

  The timer circuit 7 performs notification at intervals corresponding to preset transfer intervals (S27). This notification may be directly used as an activation signal for the DMA unit 4 or may be input to the CPU 3 as an interrupt signal to activate the DMA unit 4 by software. The DMA unit 4 activated from the timer circuit 7 or the CPU unit 3 performs transfer by a preset transfer amount (S28). The DMA unit 4 that has transferred the transfer amount issues a power saving transition command for shifting the inter-chip IFs 9 and 11 to the power saving state to the image data output control unit 13 via the inter-chip IFs 9 and 11.

  In this embodiment, the DMA unit 4 notifies the CPU unit 3 every time transfer of the transfer amount is completed, and the CPU unit 3 issues a command each time the notification is received. May be issued directly from The CPU unit 3 that has received the notification from the DMA unit 4 shifts to power saving if the time until the next transfer start is longer than the time required to shift and return the inter-chip IFs 9 and 11 to the power saving state. It is determined that the time is sufficient (S29, YES).

  Then, the data control unit 1 issues a power saving transition command (S30), and increments the transfer number counter by 1 (S31). Then, a preset transfer count (transfer count calculated previously) is compared with the value of the transfer count counter to check whether or not a predetermined amount of transfer has been completed (S32).

  If the predetermined amount of transfer is not completed (S32, NO), the process returns to step S27 and waits for the next transfer time. Even if the transfer is completed, if the waiting time until the next data transfer is shorter than the time required to enter or return to the power saving state, the transfer count counter is not issued without issuing the power saving command. Increment. When the transfer of a predetermined amount is completed, the count operation of the timer circuit 7 is stopped (S32), and the reception of a data output end signal from the image output interface 12 is waited (S33). This signal can be received by the interrupt receiving circuit 8 and handled as an interrupt signal to the CPU unit 3.

  In the present embodiment, a configuration in which a series of data transfer is started at each time interval set by the timer circuit 7 is shown. The time required for shifting to the power saving state (first required time) and the time required for returning from the power saving state (second required time) have been acquired from the image data output unit 10 in advance. Therefore, the time interval determination as to whether or not to shift to the power saving state can be easily determined by checking and comparing information corresponding to the remaining time of the timer circuit 7. At this time, the timer circuit 7 is provided with a down counter so that it is notified every time the set transfer interval is counted down to 0, and is reset and reset again to count down the set transfer interval. The remaining time can be easily acquired from the timer circuit 7. (Note that an up-counter may be arranged in the timer circuit 7. In that case, the remaining time may be interpreted as the count value increases.)

  In the image data output unit 10, the image data transferred from the data control unit 1 is transferred to a buffer in the image data output interface 12 via the inter-chip IF 11. On the other hand, the power saving transition command is transferred to the image data output control unit 13 and is output from the image data output control unit 13 to the request block circuit 14 as an L1 request signal.

  Here, the request block circuit 14 has a function of blocking a communication request from each module in the image data output unit 10 to the data control unit 1 according to the mode, and the request block circuit 14 sets the inter-chip IF 11 to L1. A transition instruction signal for shifting to the state is output to the inter-chip IF 11. In the present embodiment, the image data output control unit 13 and the request signal block circuit 14 have a function as a power saving transition command interface.

  FIG. 3 is a timing chart showing various signals related to the data control unit 1 after receiving the output start signal reception in step S25 of FIG. In FIG. 3, the data control unit 1 receives the output start signal from the image data output unit 10 at (t0), and starts the timer circuit 7. At (t1), the time set by the timer circuit 7 is counted and notified to the DMA unit 4. With the notification from the timer circuit 7, the DMA unit 4 performs data transfer for the set transfer amount, and when the transfer is completed, notifies the CPU unit 3 that the transfer has been completed.

  The CPU unit 3 that has received the completion notification indicating the completion of the data transfer reads the time until the next transfer start from the timer circuit 7, and the time required for the power saving transition and recovery read from the image data output unit 10 in advance. Make a comparison. If the time until the start of the next transfer is longer than the time required for power saving, the CPU 3 issues a power saving transition command to the image data output controller 13 (t1 ′). Then, the image data output control unit 13 receives the power saving transition command from the CPU unit 3, and instructs the inter-chip IF 11 via the request block circuit 14 for the command (reception notification). The inter-chip IF 11 conforms to the PCIe standard. Transition to the low power consumption state (L1 state). Although FIG. 3 shows a transition to L1, when the remaining time until the start of the next transfer is sufficiently long, a transition to a further power saving state may be performed.

  When the timer circuit 7 counts the set time and notifies the DMA unit 4 (t2), the DMA unit 4 starts data transfer of the set transfer amount. Then, the inter-chip IF 9 on the transmitting side that has received the data transfer request starts a return sequence from the power saving state in accordance with the PCIe standard. Accordingly, the inter-chip IF 11 on the receiving side similarly starts a return sequence from the power saving state in accordance with the PCIe standard, and both return to the normal state (L0 state) (link is reestablished). Then, the inter-chip IF 9 on the transmitting side that has received the request from the DMA unit 4 performs data transfer via the inter-chip IFs 9 and 11 based on the received request.

  Next, the request block circuit 14 in the image data output unit 10 will be described in detail. PCIe stipulates that recovery from the low power consumption state L1 to the normal state L0 may be started from either side (transmission side, reception side). Therefore, a sufficient power saving effect may not be obtained unless communication from the image data output unit 10 to the data control unit 1 via the inter-chip IF 11 is limited. Therefore, the request block circuit 14 blocks a communication request (request other than a request for transition to the power saving state) from the image data output unit 10 to the inter-chip IF unit 11.

  FIG. 4 shows details of the request block circuit. The power saving transition command issued from the data control unit 1 is received by the image data output unit 13 of the image data output unit 10, and the image data output unit 13 transmits it to the request block circuit 14 as an L1 request signal. In the request block circuit 14, this signal is held by an RS flip-flop and given to the inter-chip IF unit 11 as a transition request signal (toL1 signal) to L1.

  On the other hand, a signal requesting a communication request via the inter-chip IF 11 (Request signal) is masked using the toL1 signal, and converted to a signal that makes it appear that there is no request until it returns to the L0 state (Masked Request signal). When the inter-chip IF unit 11 shifts to the L1 state and receives a signal (L1 to L0 signal) indicating that it has returned to the L0 state again, the toL1 signal held in the RS flip-flop is canceled.

  FIG. 5 shows a timing chart for explaining these operations. In FIG. 5, even if a communication request (Request) for communication via the inter-chip IF occurs while the toL1 signal is being fermented by the L1 request signal (in the L1 state), L1 is returned by the return request (L1toL0). The communication request is masked until the state is released.

  In the above embodiment, the transfer amount can be acquired based on the image data output rate of the image data output means 10. Further, after receiving the transfer completion notification from the DMA unit 4, the CPU unit 3 reads the remaining time of the timer circuit 7 and compares it with a value indicating the time required for power saving to determine whether or not to shift to the power saving state. The approximate time required for the PCIe power saving transition / recovery is held in a register (not shown) in the data control unit according to the power saving state (L0s, L1, L2), and the CPU unit 3 reads from the register. Alternatively, a command for shifting to power saving may be issued to the image data output unit 10 based on the total required time.

  In the above-described embodiment, the first required time and the second required time are separately acquired from the image data output interface 12, but the total value of the first required time and the second required time is omitted. It may be registered in advance in the image data output interface 12 as the power saving time required for power control, and the data control unit 1 may acquire the power saving time and perform the processing of the above-described embodiment.

  In addition, although the above-mentioned embodiment demonstrated along the specification of PCIe, the same effect can be acquired by applying this invention also in another specification.

Claims (9)

Memory,
Timing instruction means for indicating the start timing of data output from the memory;
A first interface for outputting data held in the memory based on the timing instruction means;
A second interface for transferring data from the first interface to a buffer;
Based on the start timing of data output indicated by the timing instruction means, and the total time required to shift the first and second interfaces to the power saving state and return from the power saving state, A data transfer apparatus comprising: control means for issuing a command for causing the first and second interfaces to shift to a power saving state.   The control means issues a command to shift to a power saving state when the time until the output start timing of the next data indicated by the timing instruction means is longer than the total of the required times. Item 4. The data transfer device according to Item 1.   3. The data transfer apparatus according to claim 1, wherein the first and second interfaces are connected by PCI-Express.   4. The data transfer apparatus according to claim 3, wherein the power saving state is a PCI-Express L1 state. Output means for outputting a request signal for causing the first and second interfaces to transition to a power saving state based on a command of the control means;
5. The apparatus according to claim 1, further comprising: a block unit that blocks a request other than a request for transition to the power saving state for the second interface while the request signal is output. The data transfer apparatus according to item 1. A third interface for outputting the buffer data;
6. The data transfer device according to claim 1, wherein the control unit acquires the required time from the third interface. A printer having a data control unit having a memory control unit for holding and managing data, and a data output unit connected to the data control unit via an inter-chip bus and outputting data from the data control unit,
The data control unit
Timing instruction means for indicating the start timing of data output from the memory;
A first interface for outputting data held in the memory based on the timing instruction means;
The start timing of data output indicated by the timing instruction means, the first required time required to shift the first interface and the data output unit to the power saving state, the first interface and the data output unit, Control means for issuing a command for shifting the first interface and the data output unit to a power saving state based on a second required time required for returning from the power saving state; Is
A buffer for holding data from the data control unit;
A second interface for transferring data from the first interface to the buffer;
And a third interface for outputting the data held in the buffer for printing. A method of controlling a data transfer device having a memory, a first interface, and a second interface,
A timing instruction step indicating a start timing of data output from the memory;
An output step in which the first interface outputs data held in the memory based on the start timing;
A transfer step in which the second interface transfers data from the first interface to a buffer;
The output start timing of data shown in the timing instruction step, the first required time required for shifting the first and second interfaces to the power saving state, and the first and second interfaces as the power saving. And a control step of issuing a command to shift the first and second interfaces to a power saving state based on a second required time required for returning from the state. A printer control method comprising: a data control unit having a memory control unit for holding and managing data; and a data output unit connected to the data control unit via an inter-chip bus and outputting data from the data control unit. And
The data control unit is
A timing instruction step indicating a start timing of data output from the memory;
An output step of outputting data held in the memory based on a start timing indicated by the timing instruction step;
The start timing of data output indicated by the timing instruction step, the first required time required to shift the data control unit and the data output unit to the power saving state, the first interface, and the data output unit are A control step of issuing a command to shift the data control unit and the data output unit to a power saving state based on a second required time required for returning from the power saving state;
The data output unit is
A holding step of holding data from the data control unit in a buffer;
A transfer step of transferring data from the data control unit to the buffer;
A printing step of outputting the data held in the buffer for printing;
A printer control method characterized by comprising:

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