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JP2012109331A - Interposer - Google Patents

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Publication number
JP2012109331A
JP2012109331A JP2010255548A JP2010255548A JP2012109331A JP 2012109331 A JP2012109331 A JP 2012109331A JP 2010255548 A JP2010255548 A JP 2010255548A JP 2010255548 A JP2010255548 A JP 2010255548A JP 2012109331 A JP2012109331 A JP 2012109331A
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Prior art keywords
interposer
solder connection
connection portion
electronic device
thermal expansion
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JP2010255548A
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JP5819598B2 (en
Inventor
Akira Murakami
明 村上
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NEC Network Products Ltd
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NEC Network Products Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an interposer capable of relieving thermal stress onto a solder connection portion and securing connection reliability even in using substrate material with low costs.SOLUTION: An interposer 1 is disposed between an electronic device 6 and a mother board 7 via solder connection portions 4 and 5. Notches are provided at least at opposing two corners of four corners of the interposer.

Description

本発明は、本発明は、インターポーザーに関し、特に電子デバイスと、マザーボードとのはんだ接続部を有するインターポーザーに関する。   The present invention relates to an interposer, and more particularly to an interposer having a solder connection between an electronic device and a motherboard.

図５を用いて、インターポーザーについて説明する。   The interposer will be described with reference to FIG.

インターポーザー１は、インターポーザー上面２上に１つもしくは複数の電子デバイス６を搭載し、インターポーザー下面３にはマザーボード７との接続部５を有する構造をしている。   The interposer 1 has a structure in which one or a plurality of electronic devices 6 are mounted on the interposer upper surface 2, and the interposer lower surface 3 has a connection portion 5 to the mother board 7.

インターポーザー１と電子デバイス６は、はんだ接続部４で接続されインターポーザー１とマザーボード７は、はんだ接続部５で接続されている。   The interposer 1 and the electronic device 6 are connected by a solder connection portion 4, and the interposer 1 and the mother board 7 are connected by a solder connection portion 5.

電子デバイス６、インターポーザー１、マザーボード７は、それぞれ熱膨張係数が異なるため、高温時の伸び量の差がはんだ接続部４とはんだ接続部５に熱応力として加わる。   Since the electronic device 6, the interposer 1, and the motherboard 7 have different coefficients of thermal expansion, the difference in elongation at high temperatures is applied to the solder connection portion 4 and the solder connection portion 5 as thermal stress.

そこでこのインターポーザー１では、はんだ接続部４とはんだ接続部５への熱応力を緩和するため、２つの対策を施している。   Therefore, in the interposer 1, two measures are taken in order to relieve the thermal stress applied to the solder connection portion 4 and the solder connection portion 5.

まずはんだ接続部４の熱応力緩和について説明する。   First, thermal stress relaxation of the solder connection portion 4 will be described.

理想的には、インターポーザー１の熱膨張係数を電子デバイス６の熱膨張係数と一致させることが望ましいが、電子デバイス６の種類によって熱膨張係数が異なり、また複数の電子デバイス６をインターポーザー１上に実装するケースもあり、熱膨張係数を完全に一致させることは困難である。   Ideally, it is desirable to make the thermal expansion coefficient of the interposer 1 coincide with the thermal expansion coefficient of the electronic device 6, but the thermal expansion coefficient differs depending on the type of the electronic device 6, and a plurality of electronic devices 6 are connected to the interposer 1. In some cases, it is difficult to make the thermal expansion coefficients completely coincide.

完全一致は難しいまでも、インターポーザーの材料として電子デバイス６の熱膨張係数値に近い値の材料を選択することが望ましく、電子デバイス６に多く用いられるＢＴレジンやポリイミドよりも低熱膨張係数が小さな素材を用いることによって熱応力の発生を抑えている。   Although it is difficult to achieve perfect matching, it is desirable to select a material having a value close to the coefficient of thermal expansion of the electronic device 6 as the material for the interposer, and the coefficient of thermal expansion is lower than that of BT resin and polyimide often used for the electronic device 6 Generation of thermal stress is suppressed by using a material.

一方、はんだ接続部５の熱応力緩和については、マザーボード７の基板材料をインターボーザー１と同じ低熱膨張率係数材料を用いることで熱応力をなくしている。   On the other hand, for the thermal stress relaxation of the solder connection portion 5, the thermal stress is eliminated by using the same low thermal expansion coefficient material as the interposer 1 as the substrate material of the mother board 7.

更に、特許文献１や、特許文献２に記載されているように、熱応力に対する対策として、マザーボードとインターポーザーとの間に空間を設け、上下する構造とすることにより応力を吸収する構造もある。   Furthermore, as described in Patent Document 1 and Patent Document 2, as a countermeasure against thermal stress, there is a structure that absorbs stress by providing a space between the mother board and the interposer and moving up and down. .

特開２００６−３０３２３９（図１）JP 2006-303239 (FIG. 1) 特開２００８−１３０６７８（図１）JP2008-130678 (FIG. 1)

図５に示すインターポーザーの問題点は、インターポーザー１およびマザーボード７共に高価な低熱膨張係数材料を使用しなければならないことである。   The problem with the interposer shown in FIG. 5 is that both the interposer 1 and the motherboard 7 must use expensive low thermal expansion coefficient materials.

更に、インターポーザー１に低熱膨張係数材料を使用した場合、基板が高弾性となるため電子デバイス６の反りには追従することができず、はんだ接続部４へ応力が加わることがある。   Furthermore, when a low coefficient of thermal expansion material is used for the interposer 1, the substrate becomes highly elastic and cannot follow the warp of the electronic device 6, and stress may be applied to the solder connection portion 4.

特許文献１は、インターポーザー自身が振動するためバンプに大きな応力がかかる問題点を有し、更に、バンプが２辺のみで接続されているので、振動に対して弱い構造であるとともに、信号線の数も少なくなるという問題点もある。   Patent Document 1 has a problem that a large stress is applied to the bump because the interposer itself vibrates. Further, since the bump is connected by only two sides, the structure is weak against vibration and the signal line There is also the problem that the number of

特許文献２もインターポーザー自身が上下するためバンプに大きな応力がかかる問題点を有している。
［発明の目的］
本発明の目的は、インターポーザーに安価な基板材料を使用しながらもはんだ接続部への熱応力を軽減し、接続信頼性を確保することにある。 Patent Document 2 also has a problem that a large stress is applied to the bump because the interposer itself moves up and down.
[Object of invention]
An object of the present invention is to reduce the thermal stress on the solder connection portion and ensure connection reliability while using an inexpensive substrate material for the interposer.

本発明によるインターポーザーは、電子デバイスとマザーボードと間にはんだ接続部を介して設けられるインターポーザーであって、インターポーザーの四隅のうち少なくとも対向する２つの隅に切欠き部を設けることを特徴とする。   An interposer according to the present invention is an interposer that is provided between an electronic device and a mother board via a solder connection portion, and is characterized in that a cutout portion is provided at at least two opposing corners among the four corners of the interposer. To do.

インターポーザーにマザーボードとの間の熱応力を吸収できる構造を有しているため、マザーボードとインターポーザーの熱膨張係数を一致させる必要がない効果を輸している。   Since the interposer has a structure capable of absorbing the thermal stress between the motherboard and the interposer, the effect of not having to match the thermal expansion coefficients of the motherboard and the interposer is transferred.

インターポーザーの上面及び側面から見た外形図である。It is the external view seen from the upper surface and side surface of the interposer. インターポーザー状に電子デバイスを搭載したときの上面及び側面から見た外形図である。It is the external view seen from the upper surface and side surface when an electronic device is mounted in the shape of an interposer. インターポーザーとマザーボードの熱膨張係数が一致する場合の、インターポーザーの動作を説明するための図である。It is a figure for demonstrating operation | movement of an interposer when the coefficient of thermal expansion of an interposer and a motherboard corresponds. インターポーザーとマザーボードの熱膨張係数が不一致の場合の、インターポーザーの動作を説明するための図であるIt is a figure for demonstrating operation | movement of an interposer when the coefficient of thermal expansion of an interposer and a motherboard does not correspond. インターポーザーを説明するための外形図である。It is an external view for demonstrating an interposer.

次に、本発明の実施の形態について図面を参照して詳細に説明する。   Next, embodiments of the present invention will be described in detail with reference to the drawings.

図１を参照すると、本発明の一実施の形態としてのインターポーザーが示されている。インターポーザーは、電子デバイスやマザーボードに熱が加わった際の熱応力（膨張収縮力）を吸収するしなやかさ（低弾性率）が必要とする。熱応力は、電子デバイスの種類やマザーボードの材質によっても変わり、どのような電子デバイスとマザーボードを選ぶかによって、インターポーザーに求められる弾性率は変わる。従って弾性率は、その電子デバイスやマザーボードの熱応力を吸収できる値、例えば、ＦＲ−４材の弾性率（２２〜２５ＧＰａ／２５℃）よりも大幅に小さな値（例えば５ＧＰａ以下の低弾性率）とし、１０〜３０ｐｐｍ／℃の熱膨張係数を有することにより実現できる。インターポーザーを低弾性率とすることにより、熱応力を吸収することが可能となるが、本発明では更に、インターポーザーがたわむことによる応力を吸収するためにインターポーザーの形状に特徴を持たせた。   Referring to FIG. 1, an interposer as an embodiment of the present invention is shown. The interposer needs to be flexible (low elastic modulus) to absorb thermal stress (expansion / shrinkage force) when heat is applied to the electronic device or the motherboard. The thermal stress also varies depending on the type of electronic device and the material of the motherboard, and the elastic modulus required for the interposer varies depending on the type of electronic device and motherboard selected. Therefore, the elastic modulus is a value that can absorb the thermal stress of the electronic device or the motherboard, for example, a value that is significantly smaller than the elastic modulus of the FR-4 material (22-25 GPa / 25 ° C.) (for example, a low elastic modulus of 5 GPa or less). And having a thermal expansion coefficient of 10 to 30 ppm / ° C. By making the interposer have a low elastic modulus, it becomes possible to absorb thermal stress. However, in the present invention, in order to absorb the stress caused by bending of the interposer, the shape of the interposer is characterized. .

すなわち、インターポーザー１の形状は、四隅を切欠いた十字型の形状である。インターポーザー１とマザーボード７間の接続信号数が少ない場合は、切欠き部が片方の対角のみで構成する形状でも可能である。   That is, the shape of the interposer 1 is a cross shape with four corners cut out. In the case where the number of connection signals between the interposer 1 and the mother board 7 is small, it is possible to have a shape in which the notch portion is constituted by only one diagonal.

このように四隅を切り欠く形状とすることにより、角１点に集中する応力が分散され、熱応力に対して、より強い構造となっている。   Thus, by making it the shape which notches four corners, the stress concentrated on one corner is disperse | distributed and it has a stronger structure with respect to a thermal stress.

インターポーザー１の形状や大きさは、搭載する電子デバイス６の面積やマザーボード７との接続信号数に応じて、全て四隅を全て切欠く形状とするか、片方の対角のみ切り欠くか選択することができる。   The shape and size of the interposer 1 are selected depending on the area of the electronic device 6 to be mounted and the number of connection signals to the mother board 7, so that all four corners are cut out or only one diagonal is cut out. be able to.

インターポーザー上面２には、電子デバイス６を搭載するためのはんだ接続部４がある。   On the upper surface 2 of the interposer, there is a solder connection portion 4 for mounting the electronic device 6.

はんだ接続部４は、四隅を切欠いた延長線上を結んだエリアのことである。   The solder connection portion 4 is an area connected on an extended line with four corners cut out.

電子デバイス６の搭載エリアは、はんだ接続部４に限定する。但しインターポーザー１を小型化する目的においては、搭載高が低い部品に限ってはんだ接続禁止部へ搭載することができる。   The mounting area of the electronic device 6 is limited to the solder connection portion 4. However, for the purpose of reducing the size of the interposer 1, only parts having a low mounting height can be mounted on the solder connection prohibited portion.

但しその場合は、インターポーザー１を低弾性化した効果は薄くなる。   However, in that case, the effect of reducing the elasticity of the interposer 1 is reduced.

一方インターポーザー下面３には、マザーボード７と接続するためのはんだ接続部５がある。   On the other hand, the interposer lower surface 3 has a solder connection portion 5 for connection to the mother board 7.

はんだ接続部５は、十字形状の向かい合う４辺を割り当てる。   The solder connection portion 5 is assigned with four sides facing each other in a cross shape.

はんだ接続部５のパット形状は、円、楕円、正方形、長方形などがある。はんだの供給方法は、はんだボールやはんだ印刷などがある。   The pad shape of the solder connection portion 5 includes a circle, an ellipse, a square, a rectangle, and the like. Solder supply methods include solder balls and solder printing.

またはんだ接続部５の裏面に当たる領域は、マザーボード７とのはんだ接続を禁止するはんだ接続禁止部１２とする。   An area corresponding to the back surface of the solder connection portion 5 is a solder connection prohibition portion 12 that prohibits solder connection with the mother board 7.

インターポーザー１の振動耐性を高める必要がある場合は、中心点Ｃのみマザーボード７とはんだ接続をする。   When it is necessary to increase the vibration resistance of the interposer 1, only the center point C is connected to the mother board 7 by soldering.

その他対振動性を高める方法として、低弾性樹脂でインターポーザー１とマザーボード７を接着する方法もある。   As another method for improving vibration resistance, there is a method of bonding the interposer 1 and the mother board 7 with a low elastic resin.

はんだ接続部５とはんだ接続禁止部１２に挟まれた領域は、応力吸収代８である。   A region sandwiched between the solder connection portion 5 and the solder connection prohibition portion 12 is a stress absorption allowance 8.

応力吸収代８の幅は、インターポーザー１とマザーボード７の熱膨張係数差から求める。   The width of the stress absorption allowance 8 is obtained from the difference in thermal expansion coefficient between the interposer 1 and the mother board 7.

応力吸収代８については、はんだ接続部よりも基板層数を減らすことによって、更なる低弾性化が図られ、はんだ接続部５への熱応力を減らすことができる。   The stress absorption allowance 8 can be further reduced in elasticity by reducing the number of substrate layers as compared with the solder connection portion, and the thermal stress on the solder connection portion 5 can be reduced.

次に、具体的な実施例を用いて本発明を実施するための最良の形態の構成及び動作
を説明する。 Next, the configuration and operation of the best mode for carrying out the present invention will be described using specific examples.

図２に示す通り、インターポーザー１の基板素材は、数ＧＰａ以下の低弾性率を有し、１０〜３０ｐｐｍ／℃程度の熱膨張係数を有する。   As shown in FIG. 2, the substrate material of the interposer 1 has a low elastic modulus of several GPa or less and a thermal expansion coefficient of about 10 to 30 ppm / ° C.

形状は、四隅を切欠いた十字型の形状である。切り欠き部が片方の対角のみで構成しても良い。   The shape is a cross shape with four corners cut out. You may comprise a notch part by only one diagonal.

インターポーザー上面２には、電子デバイス６を搭載するための領域がある。   The interposer upper surface 2 has a region for mounting the electronic device 6.

一方インターポーザー下面３には、マザーボード７と接続するためのはんだ接続部５がある。   On the other hand, the interposer lower surface 3 has a solder connection portion 5 for connection to the mother board 7.

はんだ接続部５は、十字形状の向かい合う４辺を割り当てる。   The solder connection portion 5 is assigned with four sides facing each other in a cross shape.

はんだ接続部５のパット形状は、円、楕円、正方形、長方形などがあるが、インターポーザー下面３に電子デバイス６を搭載しない場合には、はんだ印刷にて低く強固に接続可能な長方形が望ましい。またインターポーザー下面３に電子デバイス６を搭載する場合には、電子デバイス６の実装空間を確保できるはんだボールでの接続があり、パット形状は円が望ましい。   The pad shape of the solder connection portion 5 includes a circle, an ellipse, a square, a rectangle, and the like. However, when the electronic device 6 is not mounted on the lower surface 3 of the interposer, a rectangle that can be firmly and securely connected by solder printing is desirable. When the electronic device 6 is mounted on the lower surface 3 of the interposer, there is a connection with a solder ball that can secure a mounting space for the electronic device 6, and the pad shape is preferably a circle.

またはんだ接続部５の裏面に当たる領域では、インターポーザー１とマザーボード７をはんだ接続せず、電子デバイス６とマザーボード７間の熱応力干渉を防ぐ。   Further, in a region corresponding to the back surface of the solder connection portion 5, the interposer 1 and the mother board 7 are not connected by soldering, and thermal stress interference between the electronic device 6 and the mother board 7 is prevented.

インターポーザー１の振動耐性を高める必要がある場合は、中心点Ｃのみマザーボード７とはんだ接続をする。   When it is necessary to increase the vibration resistance of the interposer 1, only the center point C is connected to the mother board 7 by soldering.

その他対振動性を高める方法として、低弾性樹脂でインターポーザー１とマザーボード７を接着する方法もある。   As another method for improving vibration resistance, there is a method of bonding the interposer 1 and the mother board 7 with a low elastic resin.

４箇所ある応力吸収代８は、他の部分よりも基板層数を減らすことによって、更なる低弾性化が図られ、はんだ接続部５への熱応力を減らすことができる。   The stress absorption allowances 8 at four locations can be further reduced in elasticity by reducing the number of substrate layers as compared with other portions, and the thermal stress on the solder connection portion 5 can be reduced.

次に、図３と図４を用いて、インターポーザーの動作について説明する。   Next, the operation of the interposer will be described with reference to FIGS.

電子デバイス６、インターポーザー１、マザーボード７は、固有の熱膨張係数を
有しており、高温時の膨張量や膨張のしかたはそれぞれ異なる。 The electronic device 6, the interposer 1, and the motherboard 7 have specific thermal expansion coefficients, and the amount of expansion at the time of high temperature and the manner of expansion are different.

インターポーザー１は、電子デバイス６とマザーボード７の中間に位置し自身の熱膨張ではんだ接続部４に熱応力を与えないことはもちろんのこと、電子デバイス６とマザーボード７の挙動の違いを吸収する役割を果たす。   The interposer 1 is located between the electronic device 6 and the mother board 7 and absorbs the difference in behavior between the electronic device 6 and the mother board 7 as well as does not apply thermal stress to the solder connection portion 4 by its own thermal expansion. Play a role.

まず始めに図３を用いて、インターポーザーの熱膨張係数１０とマザーボードの熱膨張係数１１を一致する場合の、電子デバイス６とインターポーザー１とマザーボード７の動きについて説明する。   First, the movement of the electronic device 6, the interposer 1, and the motherboard 7 when the thermal expansion coefficient 10 of the interposer and the thermal expansion coefficient 11 of the motherboard coincide with each other will be described with reference to FIG.

電子デバイス６とインターポーザー１の関係については、双方の熱膨張係数を一致させることは難しいため、はんだ接続部４には、必ず熱応力が加わる可能性を秘めているが、インターポーザー１を低弾性化することにより、はんだ接続部４へ加わる熱応力が低減できる。   Regarding the relationship between the electronic device 6 and the interposer 1, it is difficult to make the thermal expansion coefficients coincide with each other. Therefore, there is a possibility that thermal stress is always applied to the solder connection portion 4. By making it elastic, the thermal stress applied to the solder connection portion 4 can be reduced.

またインターポーザー１を低弾性化することにより、電子デバイス６の反りにも追従する。   Further, the warping of the electronic device 6 is also followed by reducing the elasticity of the interposer 1.

一方インターポーザー１とマザーボード７の関係については、双方の熱膨張係数が一致した場合、高温時の伸びも一致するため、はんだ接続部５へ熱応力は加わらない。   On the other hand, regarding the relationship between the interposer 1 and the mother board 7, when the thermal expansion coefficients of both match, the elongation at high temperature also matches, so no thermal stress is applied to the solder connection portion 5.

更に電子デバイス６とマザーボード７の関係については、インターポーザー１が低弾性でありかつ電子デバイス６の下面にインターポーザー１と、マザーボード７のはんだ接続箇所５がないことにより、双方の挙動が互いに影響しない状況を作り出している。   Further, regarding the relationship between the electronic device 6 and the mother board 7, the interposer 1 has low elasticity, and since the interposer 1 and the solder connection portion 5 of the mother board 7 are not provided on the lower surface of the electronic device 6, the behaviors of the two influence each other. It creates a situation that does not.

次に図４を用いて、インターポーザー１の熱膨張係数１０とマザーボード７の熱膨張係数１１が一致しない場合の、インターポーザー１の応力吸収構造が熱膨張量の差を吸収し、はんだ接続部５に加わる熱応力を吸収する仕組みについて説明する。   Next, referring to FIG. 4, when the thermal expansion coefficient 10 of the interposer 1 and the thermal expansion coefficient 11 of the motherboard 7 do not match, the stress absorption structure of the interposer 1 absorbs the difference in thermal expansion amount, and the solder connection portion A mechanism for absorbing the thermal stress applied to 5 will be described.

インターポーザーの熱膨張係数１０がマザーボードの熱膨張係数１１より大きい場合、高温時にはインターポーザー１はマザーボード７よりも伸び量が大きい。背景技術ではこの伸び量の差がはんだ接続部５へ熱応力として加わっていたが、本発明では応力吸収代８を支点にインターポーザー１が上下に可動できるしくみを設けることで、Ｂ面はんだ接続部７への熱応力の印加を防いでいる。   When the thermal expansion coefficient 10 of the interposer is larger than the thermal expansion coefficient 11 of the motherboard, the interposer 1 is larger in elongation than the motherboard 7 at a high temperature. In the background art, this difference in elongation is applied to the solder connection portion 5 as thermal stress. However, in the present invention, by providing a mechanism by which the interposer 1 can move up and down with the stress absorption margin 8 as a fulcrum, Application of thermal stress to the portion 7 is prevented.

１ インターポーザー
２ インターポーザー上面
３ インターポーザー下面
４ はんだ接続部
５ はんだ接続部
６ 電子デバイス
７ マザーボード
８ 応力吸収代
１０ インターポーザーの熱膨張係数
１１ マザーボードの熱膨張係数
１２ はんだ接続禁止部 DESCRIPTION OF SYMBOLS 1 Interposer 2 Interposer upper surface 3 Interposer lower surface 4 Solder connection part 5 Solder connection part 6 Electronic device 7 Motherboard 8 Stress absorption allowance 10 Interposer thermal expansion coefficient 11 Motherboard thermal expansion coefficient 12 Solder connection prohibition part

Claims (6)

電子デバイスとマザーボードと間にはんだ接続部を介して設けられるインターポーザーであって、前記インターポーザーの四隅のうち少なくとも対向する２つの隅に切欠き部を設けることを特徴とするインターポーザー。   An interposer provided between an electronic device and a mother board through a solder connection portion, wherein an interposer is provided with notches at at least two opposing corners among the four corners of the interposer. 前記インターポーザーの４辺にはんだ接続部を設けたことを特徴とする請求項１記載のインターポーザー。   The interposer according to claim 1, wherein solder connection portions are provided on four sides of the interposer. 前記インターポーザーの中心部に更にはんだ接続部を設けたことを特徴とする請求項２記載のインターポーザー。   The interposer according to claim 2, further comprising a solder connection portion at a center portion of the interposer. 前記インターポーザーの四隅全てに切欠き部を設けたことを特徴とする請求項１記載のインターポーザー。   The interposer according to claim 1, wherein notches are provided at all four corners of the interposer. 前記インターポーザーが低弾性であることを特徴とする請求項１記載のインターポーザー。   The interposer according to claim 1, wherein the interposer has low elasticity. 電子デバイスとマザーボードと間にはんだ接続部を介して設けられるインターポーザーであって、前記インターポーザーの四隅に切欠き部を設け、前記インターポーザーの４辺にのみ前記マザーボードとのはんだ接続部を設けたことを特徴とするインターポーザー。   An interposer provided between the electronic device and the motherboard via a solder connection portion, provided with notches at four corners of the interposer, and provided with a solder connection portion with the motherboard only on the four sides of the interposer. Interposer characterized by that.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019013028A1 (en) * 2017-07-13 2019-01-17 株式会社村田製作所 Semiconductor device and piezoelectric oscillator
JP2020191323A (en) * 2019-05-20 2020-11-26 凸版印刷株式会社 Wiring board for semiconductor package, semiconductor package, and manufacturing method thereof

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07169794A (en) * 1993-12-15 1995-07-04 Nec Corp Film carrier package for semiconductor device
JPH09172042A (en) * 1995-12-18 1997-06-30 Seiko Epson Corp Semiconductor device
JPH1098072A (en) * 1996-09-20 1998-04-14 Hitachi Ltd Semiconductor device and manufacturing method thereof
JPH10150117A (en) * 1996-11-20 1998-06-02 Hitachi Ltd Tape type ball grid array semiconductor device
JPH11506274A (en) * 1996-03-28 1999-06-02 インテル・コーポレーション Peripheral matrix ball grid array circuit package with distribution center
US6339534B1 (en) * 1999-11-05 2002-01-15 International Business Machines Corporation Compliant leads for area array surface mounted components
JP2005093551A (en) * 2003-09-12 2005-04-07 Genusion:Kk Package structure of semiconductor device, and packaging method
JP2006303239A (en) * 2005-04-21 2006-11-02 Matsushita Electric Works Ltd Semiconductor device and its manufacturing method
JP2007281374A (en) * 2006-04-11 2007-10-25 Nec Corp Semiconductor chip mounting substrate, semiconductor package equipped with the same substrate, electronic equipment and method for manufacturing semiconductor package

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07169794A (en) * 1993-12-15 1995-07-04 Nec Corp Film carrier package for semiconductor device
JPH09172042A (en) * 1995-12-18 1997-06-30 Seiko Epson Corp Semiconductor device
JPH11506274A (en) * 1996-03-28 1999-06-02 インテル・コーポレーション Peripheral matrix ball grid array circuit package with distribution center
JPH1098072A (en) * 1996-09-20 1998-04-14 Hitachi Ltd Semiconductor device and manufacturing method thereof
JPH10150117A (en) * 1996-11-20 1998-06-02 Hitachi Ltd Tape type ball grid array semiconductor device
US6339534B1 (en) * 1999-11-05 2002-01-15 International Business Machines Corporation Compliant leads for area array surface mounted components
JP2005093551A (en) * 2003-09-12 2005-04-07 Genusion:Kk Package structure of semiconductor device, and packaging method
JP2006303239A (en) * 2005-04-21 2006-11-02 Matsushita Electric Works Ltd Semiconductor device and its manufacturing method
JP2007281374A (en) * 2006-04-11 2007-10-25 Nec Corp Semiconductor chip mounting substrate, semiconductor package equipped with the same substrate, electronic equipment and method for manufacturing semiconductor package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019013028A1 (en) * 2017-07-13 2019-01-17 株式会社村田製作所 Semiconductor device and piezoelectric oscillator
JP2020191323A (en) * 2019-05-20 2020-11-26 凸版印刷株式会社 Wiring board for semiconductor package, semiconductor package, and manufacturing method thereof
JP7451880B2 (en) 2019-05-20 2024-03-19 Ｔｏｐｐａｎホールディングス株式会社 Semiconductor package and manufacturing method

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