JP2012164717A - Semiconductor substrate, semiconductor device, and method of manufacturing semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve problems that, although a GaN-based semiconductor is epitaxially grown on a (111)-oriented silicon substrate, since a difference between a lattice constant of GaN and a lattice constant of a silicon (111) plane is as large as about 17%, dislocation more than 10cmis introduced to the grown GaN, which causes increase in a leakage current of a transistor using GaN and reduction in mobility of the transistor.SOLUTION: A semiconductor substrate has a silicon substrate and a nitride semiconductor layer epitaxially grown on a (150) plane of the silicon substrate.

Description

  The present invention relates to a semiconductor substrate, a semiconductor device, and a method for manufacturing a semiconductor substrate.

  Nitride compound semiconductors are expected as materials for high voltage devices because they have larger band gap energy and higher breakdown voltage than silicon semiconductors. As a device using a nitride compound semiconductor, an AlGaN / GaN-HFET in which a breakdown voltage is increased by adding carbon to the nitride compound semiconductor is known (for example, see Patent Document 1).

There are the following documents as related prior art documents.
Patent Document 1 JP 2007-251144 A Non-Patent Document 1 JE Northrup, “Screw dislocations in GaN: The Ga-filled core model”, Appl. Phys. Lett., American Institute of Physics, 2001, Vol. 78, Issue 16, p. 2288
Non-Patent Document 2 Debdeep Jana, et. Al., "Effect of scattering by strain fields surrounding edge dislocations on electron transport in two-dimensional electron gases", Appl. Phys. Lett., American Institute of Physics, 2002, Vol. 80 , Issue 1, p. 64

A gallium nitride (GaN) -based semiconductor can be epitaxially grown on a silicon substrate having a plane orientation (111), but the difference between the lattice constant of GaN and the lattice constant of the silicon (111) plane is as large as about 17%. The dislocation density of exceeds 10 ¹⁰ cm ⁻² . Dislocations introduced into GaN include screw dislocations and edge dislocations. When the density of screw dislocation increases, the leakage current of a transistor using GaN increases (see, for example, Non-Patent Document 1). When the leakage current increases, the withstand voltage of the transistor cannot be increased. Further, when the density of edge dislocations increases, the mobility of a transistor using GaN decreases (for example, see Non-Patent Document 2).

  Even when carbon is added to the nitride compound semiconductor to increase the breakdown voltage, the leakage current due to screw dislocation cannot be reduced. Further, the decrease in mobility due to edge dislocation cannot be eliminated.

  In order to solve the above-mentioned problems, according to a first aspect of the present invention, there is provided a semiconductor substrate comprising a silicon substrate and a nitride semiconductor layer epitaxially grown on a (150) plane of the silicon substrate.

  In a second aspect of the present invention, there is provided a semiconductor substrate manufacturing method including a nitride semiconductor layer forming step of epitaxially growing a nitride semiconductor layer made of a nitride semiconductor on a (150) plane of a silicon substrate.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

It is a schematic diagram showing the relationship between the crystal axes of the Si (1k0) plane and the nitride semiconductor (0001) plane. 6 is a graph showing the relationship between crystal plane orientation and lattice matching. It is sectional drawing of a semiconductor substrate provided with a silicon substrate, an AlN buffer layer, an intermediate buffer layer, a GaN buffer layer, an electron transit layer, and an electron supply layer. It is the graph which showed the relationship between the repetition frequency of lamination | stacking of an intermediate | middle buffer layer, and the half value width of the X-ray diffraction (symmetrical diffraction) of a nitride semiconductor layer. It is the graph which showed the relationship between the repetition frequency of lamination | stacking of an intermediate | middle buffer layer, and the half value width of the X-ray diffraction (asymmetrical diffraction) of a nitride semiconductor layer. It is sectional drawing of a semiconductor substrate provided with a silicon substrate, a SiN layer, an AlN buffer layer, an intermediate buffer layer, a GaN buffer layer, an electron transit layer, and an electron supply layer. It is the graph which showed the relationship between nitriding time and a half value width. It is the schematic diagram which showed the curvature of the semiconductor substrate. 1 is a cross-sectional view of an HFET according to a first embodiment of the present invention. It is sectional drawing of HFET which concerns on the 2nd Embodiment of this invention. It is sectional drawing of the Schottky barrier diode which concerns on the 3rd Embodiment of this invention. It is a graph which shows the characteristic of a Schottky barrier diode. It is sectional drawing of MOSFET which concerns on the 4th Embodiment of this invention.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows the relationship between the crystal axes of the Si (1k0) plane and the nitride semiconductor (0001) plane. k is an integer of 1 or more. The thick dotted line represents the crystal axis of the Si (1k0) plane. A thin solid line represents the crystal axis of the (0001) plane of the nitride semiconductor. When the nitride semiconductor (0001) plane is stacked on the Si (1k0) plane, the <k-10> axis of Si and the a axis of the nitride semiconductor are aligned. In addition, the <001> axis of Si and the m axis of the nitride semiconductor are aligned. The nitride semiconductor may be, for example, GaN, AlN, or AlGaN.

  The difference between the spacing of the Si (001) plane and the spacing of the m-plane of the nitride semiconductor is 1.7%. In general, there is a large difference between the spacing of the Si (k-10) plane and the spacing of the a-plane of the nitride semiconductor. However, when the (1k0) plane of Si and the nitride semiconductor (0001) plane are aligned, long-period alignment is allowed. This is because the Si (1k0) plane has two-fold symmetry.

  FIG. 2 shows the result of calculating how much the interstitial distance is matched when the Si (1k0) plane and the GaN (0001) plane are matched. As a comparison, the case where the Si (111) plane and the GaN (0001) plane are aligned is also shown. In FIG. 2, the horizontal axis represents the plane orientation of Si. The black circles in FIG. 2 correspond to the left axis and indicate values when the difference between the spacing of the a-plane of GaN and the spacing of the Si (k-10) plane is minimized. A white circle corresponds to the right axis, and indicates the number of periods of Si when the distance between the a-planes of GaN and the distance between the Si (k-10) planes are minimized.

  As shown in FIG. 2, compared with the case where the Si (111) plane and the GaN (0001) plane are aligned with each other, the Si (1 k0) plane with k = 1 to 6 and the GaN a plane spacing and Si ( It can be seen that the lattice constant difference decreases with a long period when the k-10) plane is matched. When a Si (1k0) plane other than k = 1 to 6 is used, the matching period becomes too large (12 or more), and a good GaN crystal cannot be grown.

  As shown in FIG. 2, when the GaN (0001) plane is formed on the Si (150) plane among the Si (1k0) planes, the interval between the GaN a plane and the Si (5-10) plane is 6 cycles. Is minimized. The difference in lattice spacing at that time is 0.19%. Since the difference in lattice spacing is small, when the GaN (0001) plane is epitaxially grown on the Si (150) plane, screw dislocations and edge dislocations (collectively “dislocations”) are compared to the case of epitaxial growth on other Si planes. A GaN layer with less is formed. Since epitaxially grown GaN has a crystal structure, dislocations are reduced due to a small difference in interstitial distance.

  Similar results are obtained for AlN and AlGaN. That is, when an AlN (0001) plane or an AlGaN (0001) plane is epitaxially grown on the Si (150) plane, an AlN layer or an AlGaN layer with few dislocations is formed.

  FIG. 3 is a schematic cross-sectional view of the semiconductor substrate 100. The semiconductor substrate 100 includes a silicon substrate 102, an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron transit layer 112, and an electron supply layer 116.

  The AlN buffer layer 106 is epitaxially grown on the (150) plane of the silicon substrate 102. The intermediate buffer layer 108 is epitaxially grown on the AlN buffer layer 106. The intermediate buffer layer 108 may be epitaxially grown by alternately stacking layers made of GaN and layers made of AlN from the silicon substrate 102 side.

  The GaN buffer layer 110 is epitaxially grown on the intermediate buffer layer 108. The GaN buffer layer 110 is made of GaN. The electron transit layer 112 is epitaxially grown on the GaN buffer layer 110. The electron transit layer 112 is made of GaN. The electron supply layer 116 is epitaxially grown on the electron transit layer 112. The electron supply layer 116 is made of AlGaN.

  Since the nitride semiconductor layer formed on the semiconductor substrate 100 is epitaxially grown, it has a crystal structure. In FIG. 3, the nitride semiconductor layer refers to the AlN buffer layer 106, the intermediate buffer layer 108, the GaN buffer layer 110, the electron transit layer 112, and the electron supply layer 116. As shown in FIG. 2, since the nitride semiconductor layer has good lattice matching with the Si (150) plane, the dislocation density of the nitride semiconductor layer is low.

  The silicon substrate 102 may be a silicon substrate having a thickness of 1 mm grown by a CZ (chocolate ski) method. A silicon substrate grown by the CZ method has a higher residual oxygen concentration than a silicon substrate grown by the FZ method. Along with this, the mechanical properties are different. When the nitride semiconductor layer is formed on the silicon substrate 102 grown by the CZ method, cracks are less likely to occur in the nitride semiconductor layer than the silicon substrate 102 grown by the FZ method. For example, if the GaN buffer layer 110 and the electron transit layer 112 are formed with a total thickness exceeding 500 nm on the silicon substrate 102 grown by the FZ method, cracks may occur in the nitride semiconductor layer. Therefore, the total thickness is preferably 500 nm or less.

  The plane orientation of the silicon substrate 102 may be shifted from the (150) plane by a predetermined shift amount or less. This is because the dislocation density of the nitride semiconductor formed on the silicon substrate 102 is low when the amount of slip is small. The deviation amount may be an error that is normally included when a substrate is cut out from a silicon ingot. For example, it is ± 2 degrees or less.

The AlN buffer layer 106 may be formed of AlN having a thickness of 40 nm. Since AlN has good lattice matching with the Si (150) plane, the dislocation density is low. The AlN buffer layer 106 is obtained by placing the silicon substrate 102 in the MOCVD apparatus and then introducing trimethylaluminum (TMAl) and NH ₃ into the chamber of the MOCVD apparatus at a flow rate of 175 μmol / min and 35 L / min, respectively. May be epitaxially grown. The growth temperature is 1000 ° C., for example.

  The intermediate buffer layer 108 may be formed by repeatedly laminating a layer made of GaN and a layer made of AlN 4 to 12 times from the silicon substrate 102 side. Since AlN and GaN have good lattice matching with the Si (150) plane, the dislocation density is low. The intermediate buffer layer 108 can suppress cracks generated in the epitaxial film and control the amount of warpage of the semiconductor substrate 100.

  The layer made of GaN of the intermediate buffer layer 108 may have a thickness of 180 nm. The layer made of AlN of the intermediate buffer layer 108 may have a thickness of 20 nm. In FIG. 3, the thickness of the layer made of GaN is thicker than the thickness of the AlN buffer layer 106 and the layer made of AlN of the intermediate buffer layer 108. Therefore, the lattice matching between the GaN layer of the intermediate buffer layer 108 and silicon has a greater influence on the dislocation density than the lattice matching between the AlN buffer layer 106 and the AlN layer of the intermediate buffer layer 108 and silicon. Since the lattice matching between the GaN (0001) plane and the Si (150) plane is good, the intermediate buffer layer 108 has a low dislocation density.

The layer made of GaN of the intermediate buffer layer 108 may be epitaxially grown by introducing TMGa and NH ₃ at flow rates of 58 μmol / min and 12 L / min, respectively. The layer made of AlN of the intermediate buffer layer 108 may be epitaxially grown by introducing TMAl and NH ₃ at flow rates of 195 μmol / min and 12 L / min, respectively.

The GaN buffer layer 110 may be formed of GaN having a thickness of 600 nm. Since GaN has good lattice matching with the Si (150) plane, the dislocation density is low. The GaN buffer layer 110 may be epitaxially grown at a growth temperature of 1050 ° C. and a pressure of 50 Torr by introducing TMGa and NH ₃ at flow rates of 58 μmol / min and 12 L / min, respectively.

The electron transit layer 112 may be formed of GaN having a thickness of 100 nm. Since GaN has good lattice matching with the Si (150) plane, the dislocation density is low. The electron transit layer 112 may be epitaxially grown at a growth temperature of 1050 ° C. and a pressure of 200 Torr by introducing TMGa and NH ₃ at flow rates of 19 μmol / min and 12 L / min, respectively.

The electron supply layer 116 may be formed of AlGaN having a thickness of 30 nm. Since AlGaN has good lattice matching with the Si (150) plane, it has a low dislocation density. The electron supply layer 116 may be epitaxially grown at a growth temperature of 1050 ° C. by introducing TMAl, TMGa, and NH ₃ at flow rates of 100 μmol / min, 19 μmol / min, and 12 L / min, respectively. When AlGaN of the electron supply layer 116 was evaluated by X-ray diffraction, the Al composition ratio was 0.22.

  The semiconductor substrate 100 may be a wafer-like substrate. A silicon wafer may be used as the silicon substrate 102 to form a wafer-like semiconductor substrate 100. Further, the semiconductor substrate 100 may be a chip-shaped substrate. A silicon chip may be used as the silicon substrate 102 to form the chip-shaped semiconductor substrate 100.

  FIG. 4 shows the relationship between the number of repetitions of stacking of the intermediate buffer layer 108 and the full width at half maximum (FWHM) of the X-ray diffraction of the nitride semiconductor layer. A triangle mark indicates the half width of the nitride semiconductor layer of the semiconductor substrate 100 shown in FIG. That is, the half width of the X-ray diffraction of the nitride semiconductor layer epitaxially grown on the (150) plane of the silicon substrate 102. With respect to the graph of FIG. 4, the nitride semiconductor layer refers to a stack of the AlN buffer layer 106, the intermediate buffer layer 108, the GaN buffer layer 110, the electron transit layer 112, and the electron supply layer 116. The horizontal axis represents the number of times that the lamination of the GaN layer and the AlN layer of the intermediate buffer layer 108 is repeated (referred to as “repetition count”). The vertical axis represents the half width of a peak having a (0002) plane as a diffraction plane (half width of symmetrical diffraction (0002)).

  In FIG. 4, the full width at half maximum of the X-ray diffraction of the nitride semiconductor layer formed on the (110) plane of the silicon substrate 102 is indicated by square marks. Further, the half width of the X-ray diffraction of the nitride semiconductor layer formed on the Si (111) surface of the silicon substrate 102 is indicated by a circle.

  The nitride semiconductor layer epitaxially grown on the Si (150) plane has a smaller half width of symmetric diffraction (0002) than the nitride semiconductor layer epitaxially grown on the Si (111) plane or Si (110) plane. Further, when the number of repetitions of the intermediate buffer layer 108 is increased, the half width of the symmetric diffraction (0002) is reduced.

  The half width of the symmetric diffraction (0002) correlates with the screw dislocation density. The screw dislocation density is correlated with the leakage current. Therefore, the nitride semiconductor layer epitaxially grown on the Si (150) plane has a smaller screw dislocation density and a smaller leakage current than the nitride semiconductor layer epitaxially grown on the Si (111) plane or Si (110) plane. Can be formed. Further, when the number of repetitions of the intermediate buffer layer 108 is increased, the screw dislocation density is reduced and a semiconductor device with a small leakage current can be formed.

  When the intermediate buffer layer 108 is repeated 12 times, the half width of the symmetric diffraction (0002) of the nitride semiconductor layer formed on the Si (150) surface is reduced to 500 seconds. When the number of repetitions is 8, it is 700 seconds, and when it is 4 times, it is 740 seconds. When the nitride semiconductor layer is epitaxially grown on the (150) plane of the silicon substrate 102, the half width of the symmetric diffraction (0002) is reduced by 20% or more compared to the case of the silicon (111) plane.

  FIG. 5 shows the relationship between the number of repetitions of stacking of the intermediate buffer layer 108 and the full width at half maximum (FWHM) of the X-ray diffraction of the nitride semiconductor layer. A triangular mark indicates the half width of the nitride semiconductor layer of the semiconductor substrate 100. The horizontal axis represents the number of times that the intermediate buffer layer 108 is repeatedly laminated with a layer made of GaN and a layer made of AlN. The vertical axis represents the half width of a peak having a (30-32) plane as a diffraction plane (the half width of asymmetric diffraction (30-32)). The full width at half maximum of the X-ray diffraction of the nitride semiconductor layer formed on the (110) plane of the silicon substrate 102 is indicated by a square mark. The full width at half maximum of the X-ray diffraction of the nitride semiconductor layer formed on the Si (111) surface of the silicon substrate 102 is indicated by a circle.

  The nitride semiconductor layer epitaxially grown on the Si (150) plane has a half-width of asymmetric diffraction (30-32) greater than that of the nitride semiconductor layer epitaxially grown on the Si (111) plane or Si (110) plane. small. Further, when the number of repetitions of the lamination of the intermediate buffer layer 108 is increased, the half width of the asymmetric diffraction (30-32) is reduced.

  The half width of asymmetric diffraction (30-32) correlates with the edge dislocation density. The edge dislocation density is correlated with the mobility. Therefore, the nitride semiconductor layer epitaxially grown on the Si (150) plane has a lower edge dislocation density and mobility than the nitride semiconductor layer epitaxially grown on the Si (111) plane or Si (110) plane. Large semiconductor devices can be formed. Further, when the number of repetitions of the intermediate buffer layer 108 is increased, the edge dislocation density is reduced and a semiconductor device with high mobility can be formed.

  When the number of repetitions of the stacking of the intermediate buffer layer 108 is 12, the half width of the asymmetric diffraction (30-32) of the nitride semiconductor layer formed on the Si (150) plane is reduced to 2550 seconds. When the number of repetitions is 8, it is 3300 seconds, and when it is 4 times, it is 3400 seconds. When the nitride semiconductor layer is epitaxially grown on the (150) plane of the silicon substrate 102, the half width of the asymmetric diffraction (30-32) is reduced by 20% or more compared to the case of the (111) plane of silicon.

  FIG. 6 is a schematic cross-sectional view of the semiconductor substrate 130. In FIG. 6, elements denoted by the same reference numerals as those in FIG. 3 may have the same functions and configurations as the elements described in FIG. The semiconductor substrate 130 includes a silicon substrate 102, a SiN layer 104, an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron transit layer 112, and an electron supply layer 116. Except for the provision of the SiN layer 104, it has the same configuration as the semiconductor substrate 100 of FIG.

  A SiN layer 104 is formed on the silicon substrate 102. Since N atoms exist on the surface, the epitaxial growth of the nitride semiconductor is facilitated. The SiN layer 104 preferably has a thickness of 2 atomic layers or less. The SiN layer 104 may have a thickness of one atomic layer or less. The SiN layer 104 thinner than one atomic layer means that the entire surface of the silicon substrate 102 is not covered with the SiN layer 104 for one atomic layer.

The SiN layer 104 may be formed by nitriding the surface of the (150) plane of the silicon substrate 102. For example, after the silicon substrate 102 is installed in the MOCVD apparatus, NH ₃ is introduced into the chamber of the MOCVD apparatus at a flow rate of 35 L / min, and the SiN layer 104 is formed. The SiN layer 104 may be formed by a CVD method.

FIG. 7 shows the half width of the X-ray diffraction of the nitride semiconductor layer of the semiconductor substrate 130 shown in FIG. With respect to the graph of FIG. 7, the nitride semiconductor layer refers to a stack of the AlN buffer layer 106, the intermediate buffer layer 108, the GaN buffer layer 110, the electron transit layer 112, and the electron supply layer 116. The number of repetitions of the lamination of the intermediate buffer layer 108 is eight. The abscissa represents the time during which NH ₃ was flown into the MOCVD apparatus provided with the silicon substrate 102 for nitriding. The vertical axis on the left is the half width of the peak with the (0002) plane as the diffraction plane (the half width of the symmetrical diffraction (0002)). The black circle corresponds to the left vertical axis. The vertical axis on the right is the half width of a peak (half width of asymmetric diffraction (30-32)) with the (30-32) plane as the diffraction plane. The white square corresponds to the right vertical axis.

At 0.25 minutes on the horizontal axis, the half width of the symmetric diffraction (0002) and the half width of the asymmetric diffraction (30-32) are minimized. 0.25 minutes on the horizontal axis corresponds to nitriding the silicon substrate 102 with NH ₃ for 0.25 minutes. At this time, the thickness of the SiN layer 104 is a thickness of one atomic layer to two atomic layers. Even if the thickness of the SiN layer 104 is thinner than one atomic layer to two atomic layers, the half width is smaller than when the SiN layer 104 is not formed. Therefore, by forming the SiN layer 104 on the surface of the Si (150) surface, the semiconductor substrate 130 on which a semiconductor device with a small leakage current is formed can be obtained. Further, by forming the SiN layer 104 on the surface of the Si (150) surface, a semiconductor substrate 130 on which a semiconductor device with high mobility is formed can be obtained.

  7 is compared with the half width in the case of the nitride semiconductor layer formed on the Si (111) plane in FIGS. 4 and 5, the SiN layer 104 has a thickness of one atomic layer to two atomic layers. It can be seen that the full width at half maximum is narrowed by 30% or more. When the nitriding time exceeds 1.5 minutes, the effect of reducing the half width is small. In the example shown in FIG. 7, since the half width of the symmetric diffraction (0002) is increased, the screw dislocation density is increased and a semiconductor substrate on which a semiconductor device with a small leakage current is formed cannot be obtained.

  FIG. 8 shows a state in which the warp of the semiconductor substrate 130 is measured. The semiconductor substrate 130 includes a silicon substrate 102, a SiN layer 104, an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron transit layer 112, and an electron supply layer 116. The semiconductor substrate 130 has the configuration shown in FIG. The warpage amount h is the height of the end portion of the semiconductor substrate 130 from the horizontal plane including the central portion of the substrate. The curvature radius r is a radius of a circle passing through the bottom surface of the substrate.

A nitride semiconductor layer is formed on the (150) plane of the silicon substrate 102. The silicon substrate 102 may be a substrate having a diameter of 4 inches and a thickness of 1 mm grown by the CZ method. The SiN layer 104 may be formed at 1000 ° C. by introducing NH ₃ at a flow rate of 35 L / min into the MOCVD apparatus provided with the silicon substrate 102. The AlN buffer layer 106 may be formed of AlN having a thickness of 40 nm.

  The intermediate buffer layer 108 may be formed by alternately stacking a layer made of GaN and a layer made of AlN six times from the silicon substrate 102 side. The thickness from the layer made of GaN formed on the AlN buffer layer 106 to the layer made of AlN formed under the GaN buffer layer 110 may be as follows in order from the bottom. 290 nm (GaN), 50 nm (AlN), 330 nm (GaN), 50 nm (AlN), 390 nm (GaN), 50 nm (AlN), 470 nm (GaN), 50 nm (AlN), 580 nm (GaN), 50 nm (AlN), 740 nm (GaN), 50 nm (AlN).

  The thickness of the layer made of GaN included in the intermediate buffer layer 108 may be increased from the side closer to the silicon substrate 102 toward the far side. Thereby, the effect of suppressing cracks and the effect of suppressing warpage are increased, and the epitaxial film can be laminated thicker.

  The GaN buffer layer 110 may be formed of GaN having a thickness of 100 nm. The GaN buffer layer 110 may be formed similarly to the semiconductor substrate 100 of FIG. The electron transit layer 112 may be made of GaN having a thickness of 100 nm. The electron supply layer 116 may be formed of AlGaN having a thickness of 30 nm. As a result of evaluation by X-ray diffraction, the composition ratio of Al was 0.23. The AlN buffer layer 106, the intermediate buffer layer 108, the GaN buffer layer 110, the electron transit layer 112, and the electron supply layer 116 may be formed in the same manner as the semiconductor substrate 100 of FIG.

  Table 1 shows the warpage amount h and the radius of curvature r of the semiconductor substrate 130. As a comparative example, the warpage amount h and the radius of curvature r of the semiconductor substrate 130 in which the nitride semiconductor layer is formed on the (111) plane of silicon are shown. The nitride semiconductor layer formed on the (111) plane of silicon is the same as the nitride semiconductor layer formed on the (150) plane of the silicon substrate 102. In the semiconductor substrate 130, the nitride semiconductor layer includes the AlN buffer layer 106, the intermediate buffer layer 108, the GaN buffer layer 110, the electron transit layer 112, and the electron supply layer 116.

  The semiconductor substrate 130 in which the nitride semiconductor layer is formed on the (150) plane of the silicon substrate 102 has a smaller amount of warp h and a radius of curvature than the semiconductor substrate 130 in which the nitride semiconductor layer is formed on the (111) plane of the silicon substrate 102. Is big. Therefore, the warpage of the semiconductor substrate 130 in which the nitride semiconductor layer is formed on the (150) plane of the silicon substrate 102 is reduced compared to the semiconductor substrate 130 in which the nitride semiconductor layer is formed on the (111) plane of silicon.

  The semiconductor substrate 130 in which the nitride semiconductor layer was formed on the (150) plane of the silicon substrate 102 had a warp amount of 15 μm or less and a curvature radius of 20 m or more. A reduction in warpage is preferable because it leads to a small crystal distortion. Accordingly, when the semiconductor substrate 130 is formed or etched, the substrate is uniformly processed.

  FIG. 9 is a schematic cross-sectional view of the HFET 140 according to the first embodiment of the present invention. In FIG. 9, elements denoted by the same reference numerals as those in FIG. 6 may have the same functions and configurations as the elements described in FIG. HFET 140 includes silicon substrate 102, SiN layer 104, AlN buffer layer 106, intermediate buffer layer 108, GaN buffer layer 110, electron transit layer 112, alloy scattering suppression layer 114, electron supply layer 116, source electrode 118, drain electrode 120, In addition, a gate electrode 122 is provided.

  The silicon substrate 102 is a substrate made of silicon having a plane orientation (150). Except for the alloy scattering suppression layer 114, the source electrode 118, the drain electrode 120, and the gate electrode 122, it has the same configuration as the semiconductor substrate 130 of FIG.

  The alloy scattering suppression layer 114 is epitaxially grown on the electron transit layer 112. An electron supply layer 116 is epitaxially grown on the alloy scattering suppression layer 114. By forming the alloy scattering suppression layer 114 between the electron transit layer 112 and the electron supply layer 116, the alloy scattering of the two-dimensional electron gas is suppressed, and the mobility is improved in the HFET 140.

  The electron transit layer 112 may be formed of GaN. The alloy scattering suppression layer 114 may be formed of AlN. The alloy scattering suppression layer 114 may be 1 nm thick. The electron supply layer 116 may be formed of AlGaN.

  The source electrode 118, the drain electrode 120, and the gate electrode 122 are formed on the electron supply layer 116. The source electrode 118 and the drain electrode 120 may be in ohmic contact with the electron supply layer 116. The gate electrode 122 may be Schottky bonded to the electron supply layer 116. Since the nitride semiconductor layer is formed on the (150) plane of the silicon substrate 102, the dislocation density of the nitride semiconductor layer is low. The nitride semiconductor layers in the HFET 140 are the AlN buffer layer 106, the intermediate buffer layer 108, the GaN buffer layer 110, the electron transit layer 112, the alloy scattering suppression layer 114, and the electron supply layer 116.

The SiN layer 104 may be formed by nitriding the surface of the (150) plane of the silicon substrate 102. After the silicon substrate 102 is installed in the MOCVD apparatus, NH ₃ is introduced into the chamber of the MOCVD apparatus at a flow rate of 35 L / min for 0.3 minutes to form the SiN layer 104 at a temperature of 1000 ° C. Good.

The AlN buffer layer 106 may be formed of AlN having a thickness of 40 nm. The AlN buffer layer 106 may be epitaxially grown by introducing TMAl and NH ₃ at flow rates of 175 μmol / min and 35 L / min, respectively. The growth temperature is 1000 ° C., for example.

The intermediate buffer layer 108 may be formed by repeatedly laminating a layer made of GaN and a layer made of AlN 12 times from the silicon substrate 102 side. The layer made of GaN of the intermediate buffer layer 108 may have a thickness of 180 μm. The layer made of AlN in the intermediate buffer layer 108 may be 20 nm thick. The layer made of GaN of the intermediate buffer layer 108 may be epitaxially grown by introducing TMGa and NH ₃ at flow rates of 58 μmol / min and 12 L / min, respectively. The layer made of AlN of the intermediate buffer layer 108 may be epitaxially grown by introducing TMAl and NH ₃ at flow rates of 195 μmol / min and 12 L / min, respectively. Both growth temperatures may be 1050 ° C. Any pressure may be 50 Torr.

The GaN buffer layer 110 may be formed of GaN. The GaN buffer layer 110 may be epitaxially grown by introducing TMGa and NH ₃ at flow rates of 58 μmol / min and 12 L / min, respectively, at a growth temperature of 1050 ° C. and a pressure of 50 Torr.

The electron transit layer 112 may be formed of GaN having a thickness of 100 nm. The electron transit layer 112 functions as an electron transit layer of the HFET 140. The electron transit layer 112 may be epitaxially grown by introducing TMGa and NH ₃ at flow rates of 19 μmol / min and 12 L / min, respectively, at a growth temperature of 1050 ° C. and a pressure of 200 Torr.

The electron supply layer 116 may be formed of AlGaN. The electron supply layer 116 may be 32 nm thick. The electron supply layer 116 functions as an electron supply layer of the HFET 140. The electron supply layer 116 may be epitaxially grown at a growth temperature of 1050 ° C. by introducing TMAl, TMGa, and NH ₃ at flow rates of 100 μmol / min, 19 μmol / min, and 12 L / min, respectively. When AlGaN of the electron supply layer 116 was evaluated by X-ray diffraction, the Al composition ratio was 0.24.

  The source electrode 118 and the drain electrode 120 may be formed of a layer made of Ti. The source electrode 118 and the drain electrode 120 may have a layer made of Al on a layer made of Ti. The layer made of Ti is in ohmic contact with the electron supply layer 116 in contact therewith. Heat treatment may be performed after the source electrode 118 and the drain electrode 120 are formed. The ohmic characteristics are improved by the heat treatment. The heat treatment may be performed at 700 ° C. for 30 minutes. The source electrode 118 and the drain electrode 120 may be formed by sputtering or vapor deposition.

  The gate electrode 122 may be formed of a layer made of Ni. The gate electrode 122 may have a layer made of Au on a layer made of Ni. A layer made of Ni is in contact with the electron supply layer 116 to form a Schottky junction. The gate electrode 122 may be formed by sputtering or vapor deposition.

  Table 2 shows the characteristics of the HFET 140 shown in FIG. As a comparative example, the characteristics of the HFET 140 formed on the (111) plane of the silicon substrate 102 are shown. The HFET 140 has a gate length of 2 μm, a gate width of 200 μm, and a source-drain distance of 15 μm. The gate length is the length of the gate electrode 122 in a direction parallel to the current flowing through the electron transit layer 112. The gate width is the width of the gate electrode 122. The distance between the source and the drain is a distance between the end of the source electrode 118 on the gate electrode 122 side and the end of the drain electrode 120 on the gate electrode 122 side. The leakage current is a value when the voltage between the source electrode 118 and the drain electrode 120 is 200V.

Since the HFET 140 has good lattice matching between the (150) plane of silicon and the nitride semiconductor layer, the dislocation density of the epitaxially grown crystal is low. Since the HFET 140 has a lower screw dislocation density than the comparative example, the leakage current is lower and the breakdown voltage is higher. Since the HFET 140 has a lower edge dislocation density than the comparative example, the mobility is higher. The HFET 140 has a mobility of 1400 cm ² / Vs or higher. The HFET 140 has a leak current of 4.0 × 10 ⁻⁸ A / mm or less. The HFET 140 has a breakdown voltage of 900V or higher.

  FIG. 10 is a schematic cross-sectional view of an HFET 150 according to the second embodiment of the present invention. 10, elements denoted by the same reference numerals as those in FIG. 9 may have the same functions and configurations as the elements described in FIG. The HFET 140 includes a silicon substrate 102, a SiN layer 104, an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron transit layer 112, an electron supply layer 116, a source electrode 118, a drain electrode 120, and a gate electrode 122. Prepare. The HFET 150 is the same as the HFET 140 shown in FIG. 9 except that the alloy scattering suppression layer 114 is not provided. Since the alloy scattering suppression layer 114 is not provided, the electron supply layer 116 is formed on the electron transit layer 112.

  In the HFET 150, since the nitride semiconductor layer is formed on the (150) plane of the silicon substrate 102, the dislocation density of the nitride semiconductor layer is low. The nitride semiconductor layers in FIG. 10 are the AlN buffer layer 106, the intermediate buffer layer 108, the GaN buffer layer 110, the electron transit layer 112, and the electron supply layer 116. Since the HFET 150 has good lattice matching between the (150) plane of silicon and the nitride semiconductor layer, the dislocation density of the epitaxially grown crystal is low. Since the HFET 150 has a lower screw dislocation density than the HFET formed on the silicon (111) surface, the leakage current is low and the breakdown voltage is high. Since the HFET 150 has a lower edge dislocation density than the HFET formed on the silicon (111) surface, it has a high mobility.

  FIG. 11 is a schematic cross-sectional view of a Schottky barrier diode 160 according to the third embodiment of the present invention. In FIG. 11, elements denoted by the same reference numerals as those in FIG. 6 may have the same functions and configurations as the elements described in FIG. The Schottky barrier diode 160 includes a silicon substrate 102, an SiN layer 104, an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron transit layer 162, an ohmic electrode 164, and a Schottky electrode 166.

  A silicon substrate 102 shown in FIG. 11 is a substrate made of silicon having a plane orientation (150). The SiN layer 104, the AlN buffer layer 106, the intermediate buffer layer 108, and the GaN buffer layer 110 have the same configuration as the HFET 140 of FIG. An electron transit layer 162 is formed on the GaN buffer layer 110. An ohmic electrode 164 and a Schottky electrode 166 are formed on the electron transit layer 162. The ohmic electrode 164 is in ohmic contact with the electron transit layer 162. The Schottky electrode 166 is Schottky joined to the electron transit layer 162.

  In the Schottky barrier diode 160, since the nitride semiconductor layer is formed on the (150) plane of the silicon substrate 102, the dislocation density of the nitride semiconductor layer is low. The nitride semiconductor layers in FIG. 11 are the AlN buffer layer 106, the intermediate buffer layer 108, the GaN buffer layer 110, and the electron transit layer 162.

The electron transit layer 162 may be formed of n-GaN. The electron transit layer 162 may be n-GaN doped with silicon. The carrier concentration of the electron transit layer 162 may be 2 × 10 ¹⁶ cm ⁻³ .

The electron transit layer 162 may be n-GaN having a thickness of 500 nm. The electron transit layer 162 is epitaxially grown at a growth temperature of 1050 ° C. and a pressure of 200 Torr by introducing TMGa, NH ₃ and SH ₄ at a predetermined flow rate of 19 μmol / min, 12 L / min, respectively. Good.

  The ohmic electrode 164 may be formed of a layer made of Ti. The ohmic electrode 164 may have a layer made of Al on the layer made of Ti. The layer made of Ti is in ohmic contact by contacting the electron transit layer 162. Heat treatment may be performed after the ohmic electrode 164 is formed. The ohmic characteristics are improved by the heat treatment. The heat treatment may be performed at 700 ° C. for 30 minutes. The ohmic electrode 164 may be formed by sputtering or vapor deposition.

  The Schottky electrode 166 may be formed of a layer made of Ni. The electron supply layer 116 may have a layer made of Au on a layer made of Ni. A layer made of Ni is in contact with the electron transit layer 162 to form a Schottky junction. The Schottky electrode 166 may be formed by sputtering or vapor deposition.

  FIG. 12 shows the characteristics of the Schottky barrier diode 160 shown in FIG. The solid line corresponds to the Schottky barrier diode 160 shown in FIG. The Schottky electrode 166 was circular with a diameter of 160 μm. The distance between the ohmic electrode 164 and the Schottky electrode 166 was 10 μm, and the ohmic electrode 164 was formed concentrically with the Schottky electrode 166. As a comparative example, the characteristics of a Schottky barrier diode 160 formed in the same manner on the silicon (111) surface are indicated by broken lines.

  The Schottky barrier diode 160 shown in FIG. 11 has a mobility 1.5 times that of the Schottky barrier diode 160 formed in the same manner on the silicon (111) surface. This is because the Schottky barrier diode 160 has a low dislocation density because the nitride semiconductor layer is formed on the (150) plane of the silicon substrate 102. This is particularly because the edge dislocation density is lowered. In the Schottky barrier diode 160, a current of 15 mA flowed at a voltage of 1V.

  FIG. 13 is a schematic cross-sectional view of a MOSFET 170 according to the fourth embodiment of the present invention. In FIG. 13, elements denoted by the same reference numerals as those in FIG. 6 may have the same functions and configurations as the elements described in FIG. The MOSFET 170 includes a silicon substrate 102, a SiN layer 104, an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an inversion layer 172, a gate oxide film 176, a source electrode 178, a gate electrode 180, and a drain electrode 182. The inversion layer 172 is made of p-GaN. The inversion layer 172 has a contact region 174 in contact with the source electrode 178 and the drain electrode 182. As a result, the source electrode 178 and the drain electrode 182 are in ohmic contact with the inversion layer 172.

  A silicon substrate 102 shown in FIG. 13 is a substrate made of silicon having a plane orientation (150). The SiN layer 104, the AlN buffer layer 106, the intermediate buffer layer 108, and the GaN buffer layer 110 have the same configuration as the HFET 140 of FIG. An inversion layer 172 is formed on the GaN buffer layer 110. A gate oxide film 176 is formed on the inversion layer 172. Gate electrode 180 is formed on gate oxide film 176.

  In MOSFET 170, since the nitride semiconductor layer is formed on the (150) plane of silicon substrate 102, the dislocation density of the nitride semiconductor layer is low. The nitride semiconductor layers shown in FIG. 13 are the AlN buffer layer 106, the intermediate buffer layer 108, the GaN buffer layer 110, and the inversion layer 172. The MOSFET 170 formed on the (150) plane of the silicon substrate 102 shown in FIG. 13 has a lower interface state, lower on-resistance, higher mobility, and higher withstand voltage than the MOSFET 170 similarly formed on the Si (111) plane. Is expensive. This is because the dislocation density of the nitride semiconductor layer is low.

The inversion layer 172 may be p-GaN doped with magnesium. The p-type dopant may be Zn or Be. The carrier concentration of the inversion layer 172 may be 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . The thickness of the inversion layer 172 may be 300 nm.

The inversion layer 172 introduces TMGa, NH ₃ and biscyclopentadienyl magnesium (Cp2Mg) at 19 μmol / min, 12 L / min and a predetermined flow rate, respectively, and a growth temperature of 1050 ° C. and a pressure of 200 Torr. Below, it may be epitaxially grown.

Contact region 174 may be an n + GaN region. n + GaN refers to a region where the concentration of n-type carriers is higher than the n-type carrier concentration of n-GaN or the p-type carrier concentration of p-GaN. The carrier concentration of the n + GaN region may be 1 × 10 ¹⁸ cm ⁻³ or more. The contact region 174 may be formed by doping the inversion layer 172 with an n-type dopant. The doping may be performed by ion implantation of an n-type dopant. In the contact region 174, the inversion layer 172 may be doped with Si at an acceleration voltage of 150 keV to have a carrier concentration of 5 × 10 ¹⁸ cm ⁻³ .

The gate oxide film 176 may be formed of an oxide film. Gate oxide film 176 may be formed of SiO _2. The gate oxide film 176 may be formed with a thickness of 60 nm to 100 nm. The gate oxide film 176 may be formed by plasma CVD. After the gate oxide film 176 is formed, it may be heated and annealed. By the annealing treatment, the density of interface states at the interface between the inversion layer 172 and the gate oxide film 176 is reduced. The annealing treatment may be performed at 800 ° C. to 1000 ° C. for 30 minutes.

  The gate electrode 180 may be formed of a conductor. The gate electrode 180 may be formed of polysilicon. The source electrode 178 and the drain electrode 182 may be formed of a material that makes ohmic contact with the contact region 174. The source electrode 178 and the drain electrode 182 may be formed of a layer made of Ti. The source electrode 178 and the drain electrode 182 may have a layer made of Al on the layer made of Ti. The layer made of Ti is in ohmic contact by contacting the electron transit layer 162. Heat treatment may be performed after the source electrode 178 and the drain electrode 182 are formed. The ohmic characteristics are improved by the heat treatment. The heat treatment may be performed at 700 ° C. for 30 minutes. The source electrode 178 and the drain electrode 182 may be formed by sputtering or vapor deposition.

  The gate-source distance and the gate-drain distance may be the same. The gate-source distance is the distance between the end of the gate electrode 180 on the source electrode 178 side and the end of the source electrode 178 on the gate electrode 180 side. The gate-drain distance is the distance between the end of the gate electrode 180 on the drain electrode 182 side and the end of the drain electrode 182 on the gate electrode 180 side. The gate-source distance and the gate-drain distance may be 10 μm.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  100 semiconductor substrate, 102 silicon substrate, 104 SiN layer, 106 AlN buffer layer, 108 intermediate buffer layer, 110 GaN buffer layer, 112 electron transit layer, 114 alloy scattering suppression layer, 116 electron supply layer, 118 source electrode, 120 drain electrode 122 gate electrode, 130 semiconductor substrate, 140 HFET, 150 HFET, 160 Schottky barrier diode, 162 electron transit layer, 164 ohmic electrode, 166 Schottky electrode, 170 MOSFET, 172 inversion layer, 174 contact region, 176 gate oxide film 178 Source electrode, 180 Gate electrode, 182 Drain electrode

Claims (17)

A silicon substrate;
A semiconductor substrate comprising: a nitride semiconductor layer epitaxially grown on a (150) plane of the silicon substrate.   The semiconductor substrate according to claim 1, further comprising a silicon nitride layer formed between the silicon substrate and the nitride semiconductor layer.   The semiconductor substrate according to claim 2, wherein the silicon nitride layer has a thickness of 2 atomic layers or less.   4. The semiconductor substrate according to claim 1, wherein the nitride semiconductor layer is any one of GaN, AlGaN, and AlN, or a layer in which these are laminated. 5.   The semiconductor substrate according to claim 1, wherein a growth surface of the nitride semiconductor layer is a (0001) plane.   The semiconductor substrate according to any one of claims 1 to 5, wherein the silicon substrate is cut out from a silicon single crystal grown by a CZ method.   A semiconductor device formed on the semiconductor substrate according to claim 1. The nitride semiconductor layer is an electron transit layer in which electrons travel,
The semiconductor device according to claim 7, wherein the semiconductor device is a field effect transistor. The semiconductor device according to claim 8, wherein the mobility is 1400 cm ² / Vs or higher.   The semiconductor device according to claim 7, wherein the semiconductor device is any one of a Schottky barrier diode and a MOS transistor.   A method of manufacturing a semiconductor substrate comprising a nitride semiconductor layer forming step of epitaxially growing a nitride semiconductor layer made of a nitride semiconductor on a (150) plane of a silicon substrate.   The method of manufacturing a semiconductor substrate according to claim 11, further comprising a step of nitriding the (150) plane of the silicon substrate to form a silicon nitride layer before the nitride semiconductor layer forming step.   The method for manufacturing a semiconductor substrate according to claim 12, wherein the silicon nitride layer has a thickness of 2 atomic layers or less.   The method for manufacturing a semiconductor substrate according to claim 11, wherein the nitride semiconductor layer is any one of GaN, AlGaN, and AlN, or a layer in which these are stacked.   The method for manufacturing a semiconductor substrate according to claim 11, wherein a growth surface of the nitride semiconductor layer is a (0001) plane.   The method for manufacturing a semiconductor substrate according to claim 11, wherein the silicon substrate is cut out from a silicon single crystal grown by a CZ method.   A semiconductor device formed on a semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 11.

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