JP2012163457A - Radio correction clock - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a radio correction clock in which a main control circuit can be reduced in size, and which can be reduced entirely in size as a result.SOLUTION: A radio correction clock includes a decode IC 210 and a microcomputer 200 for clock. The decode IC 210 inputs a reference signal and acquires and outputs decode information by discriminating one code signal from among a plurality of code signals contained in a radio signal on the basis of the inputted reference signal. The microcomputer 200 for clock is comprised of a circuit different from the decode IC 210, inputs the reference signal, adjusts a frequency of the inputted reference signal, counts time information for notification on the basis of the adjusted reference signal, inputs the decode information and corrects the counted time information for notification on the basis of the inputted decode information. The microcomputer 200 for clock outputs a reset signal which is generated on the basis of the adjusted reference signal, and the decode IC 210 resets the reference signal in accordance with the reset signal.

Description

  The present invention relates to a radio-controlled timepiece that receives a standard radio wave and corrects the time.

  2. Description of the Related Art Conventionally, there is a so-called radio-controlled timepiece that includes time indicating hands such as an hour hand, a minute hand, and a second hand, and corrects the time indicated by the time indicating hand to coincide with the time measured by an atomic clock. Such a radio-controlled timepiece has an antenna for receiving a standard radio wave including time information and date information, and forcibly displaces the time indicating hand based on information contained in the standard radio wave received via the antenna. To correct the time.

  Radio-controlled timepieces have become popular in recent years because they can indicate an accurate time as compared to quartz timepieces and can save time and effort. In recent years, there is a tendency for radio-controlled watches to be smaller and thinner for reasons such as emphasis on fashionability. This is especially true for women's watches.

  Conventionally, in a general radio-controlled timepiece, a clock microcomputer performs standard radio wave decoding processing along with control of the entire timepiece. For this reason, there is a limit to downsizing the clock microcomputer.

  In addition, in the conventional radio-controlled timepiece, there is a technology that includes a decoding circuit that decodes a code signal of a standard radio wave separately from the clock circuit, and the decoding circuit outputs the decoded data to the clock circuit (for example, (See Patent Document 1 below.) In the radio-controlled timepiece according to Patent Document 1, the width of the Lo level section starting from the second synchronization position of the standard radio signal is counted by a counter using a crystal oscillator as a reference clock, and this count value is used for time code discrimination. ing.

JP 2005-221505 A

  However, in Patent Document 1, the counting start timing by the counter is determined based on the clock signal of the crystal oscillator. Therefore, when the decoding time is increased, the counting start timing by the counter is also shifted according to the oscillation accuracy of the crystal oscillator. As a result, there is a problem that the code signal of the standard radio wave cannot be accurately decoded.

  An object of the present invention is to provide a radio-controlled timepiece that can decode a standard radio wave more accurately with a simple configuration by using a decode circuit in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object, a radio-controlled timepiece according to the present invention includes a reference signal generating means for generating a reference signal and a receiving means for receiving a radio signal including a plurality of code signals representing time information. And input the reference signal, based on the input reference signal, to determine one code signal from a plurality of code signals included in the radio signal received by the receiving means to obtain decoding information, The decoding means for outputting the decoding information and a circuit different from the decoding means are configured to input the reference signal, adjust the frequency of the input reference signal, and based on the adjusted adjusted reference signal The time information for notification is timed, the decode information is input, and the time information for notification is measured based on the input decode information. Correct time measuring means, wherein the time counting means outputs a reset signal generated based on the adjusted reference signal, the decoding means inputs the reset signal, and the input reset The reference signal is reset by a signal.

  The radio-controlled timepiece according to the present invention is the radio-controlled timepiece according to the above invention, wherein the code signal is transmitted at a predetermined cycle, and the code signal is discriminated in the remaining sections excluding a part of each period. The decoding means detects the start timing of the predetermined period from the radio wave signal received by the receiving means, outputs information about the detected start timing, and the time counting means, Information on the start timing is input, and the reset signal is output in the partial section based on the input information on the start timing.

  The radio-controlled timepiece according to the present invention is characterized in that, in the above-mentioned invention, the decoding means determines the code signal in the remaining section and resets the reference signal in the partial section. To do.

  The radio-controlled timepiece according to the present invention is the radio-controlled timepiece according to the present invention, wherein the time counting means outputs the time information for notification, and the decoding means inputs and inputs the time information for notification. Time information is measured based on the reference signal or a frequency-divided signal of the reference signal, and corrected time information obtained by correcting the time information for notification being timed based on the determination results of the plurality of code signals. The decoding information is used.

  The radio-controlled timepiece according to the present invention is characterized in that, in the above-mentioned invention, the decoding means has means for inputting an output signal of the receiving means and outputting it to the time counting means.

  In the radio-controlled timepiece according to the present invention as set forth in the invention described above, the time counting means outputs all or part of data output to the decoding means in a first communication cycle, and the decoding means The data output to the time measuring means is output in a second communication cycle longer than the first communication cycle.

  According to the radio-controlled timepiece according to the present invention, the decoding process is performed in a circuit separate from the main control circuit, thereby reducing the size of the main control circuit, the size of the radio-controlled timepiece as a whole, and the cost of the clock microcomputer. In addition to reducing the cost, the decoding process can be reliably performed even in a circuit separate from the main control circuit.

It is explanatory drawing which shows the external appearance of the radio-controlled timepiece concerning embodiment of this invention. It is explanatory drawing which shows the hardware constitutions of the radio wave correction timepiece concerning embodiment of this invention. It is explanatory drawing which shows the decoding IC of the radio wave correction clock concerning this Embodiment, and the hardware constitutions of the periphery. It is explanatory drawing which shows the outline | summary of the reception operation | movement of the radio-controlled timepiece of embodiment concerning this invention. It is a flowchart (the 1) which shows the content of operation | movement of the decoding IC of the radio wave correction watch concerning embodiment of this invention. It is a flowchart (the 2) which shows the content of operation | movement of the decoding IC of the radio wave correction watch concerning embodiment of this invention. It is a flowchart (the 1) which shows the content of operation | movement of the timepiece microcomputer of the radio wave correction timepiece concerning embodiment of this invention. It is a flowchart (the 2) which shows the content of operation | movement of the timepiece microcomputer of the radio wave correction timepiece concerning embodiment of this invention. It is a timing chart which shows the content of operation of through mode. It is a timing chart which shows the content of reception initial operation. It is a timing chart which shows the content of the low-speed communication in a reception mode, and a frequency division reset operation. It is explanatory drawing which shows an example (Time_Code: JJY) of the time code of a standard radio wave. It is explanatory drawing which shows an example (Time_Code: DCF77) of the time code of a standard radio wave.

  Exemplary embodiments of a radio-controlled timepiece according to the invention will be described below in detail with reference to the accompanying drawings.

(Appearance of the radio-controlled watch)
FIG. 1 is an explanatory view showing the appearance of a radio-controlled timepiece that is an example of a pointer-type display device according to an embodiment of the present invention. In FIG. 1, the radio-controlled timepiece is a wristwatch-type radio-controlled timepiece composed of a main body 100 and a band (not shown) for mounting the main body 100 on, for example, an arm. A crown 104 and operation buttons 105 are provided on the outer periphery of the main body 100.

  The display part of the main body 100 is provided with normal hands (minute hand 101, hour hand 102, second hand 103) indicating the normal time. In the normal pointer, the second hand 103 rotates in a second cycle, that is, one rotation (one round) in 60 seconds. The minute hand 101 rotates in a minute cycle, that is, makes one rotation (one round) in 60 minutes. The hour hand 102 rotates at a time period, that is, makes one rotation (one turn) in 12 hours. The normal time is displayed by these hands (second hand 103, minute hand 101, hour hand 102). A date display window 106 is provided at the 3 o'clock position.

(Configuration of radio-controlled watch)
Next, the configuration of the radio-controlled timepiece according to the embodiment of the present invention will be described. FIG. 2 is an explanatory diagram showing a hardware configuration of the radio-controlled timepiece according to the embodiment of the present invention. In FIG. 2, the radio wave correction watch body 100 includes a watch microcomputer 200, a RAM 201, a ROM 202, a motor drive circuit 203, a plurality (for example, four) motors 204, and a plurality (for example, four) wheel trains. 205, a reference signal generation unit 206, an antenna 207, a tuning circuit 208, a reception circuit 209, a decode IC 210, a switch unit 211, a switch control circuit 212, a solar cell 213, a secondary battery 214, and a charge A control circuit 215.

  Further, a liquid crystal driving circuit, an LED, an LED driving circuit, an alarm, an alarm driving circuit, etc. (not shown) controlled by a time display control unit 303 described later may be provided.

  The timepiece microcomputer 200 controls the entire radio-controlled timepiece main body 100, and individually controls various components and circuits. The RAM 201 stores various data such as time data including time information or calendar information. The ROM 202 stores various control programs.

  The motor drive circuit 203 drives a plurality of independent motors 204 and drives the hands (dates) independently via the wheel train 205. The motor drive circuit 203 receives a drive signal output from the clock microcomputer 200 and outputs drive pulses corresponding to the input drive signal to the four motors 204, respectively.

  Specifically, the four motors 204 use, for example, step motors, and perform forward (clockwise) or reverse (counterclockwise) rotation operations according to the drive pulses output from the motor drive circuit 203.

  One of the four motors 204 drives the second hand 103 shown in FIG. The second motor drives the minute hand 101 shown in FIG. The third motor drives the hour hand 102 shown in FIG. The fourth motor drives a date plate provided below the dial. Although four motors and four trains are shown, the number may be three or less, or may be five or more. For example, the first motor drives the minute hand 101 and the second hand 103. If the second motor drives the hour hand 102 and the date plate, two motors and two train wheels are sufficient.

  The reference signal generation unit 206 is composed of, for example, an oscillation circuit, and generates a signal having a predetermined frequency serving as a reference for time measurement processing. Further, a DF tone (logical frequency adjustment) processing unit 302 described later in FIG. 3 divides a signal having a predetermined frequency generated from the reference signal generation unit 206.

  The tuning circuit 208 tunes with the antenna 207 and tunes the antenna 207 to a frequency such as 60 kHz (US), 77.5 kHz (Germany), 40 kHz, 60 kHz (Japan), for example, by switching the capacitance of the capacitor. The receiving circuit 209 detects a standard radio wave from the signal received by the antenna 207 and outputs it to the decoding IC 210. Details of the decode IC 210 will be described later.

  The receiving circuit 209 amplifies a signal received by the antenna 207, an amplifying unit (not shown), a filter unit (not shown) that removes components other than desired frequencies (40 kHz, 60 kHz, 77.5 kHz), and a received standard radio wave , A detection unit (not shown), a detection output is converted into a digital output, an AD conversion unit (not shown), a gain control unit (not shown), etc. .

  The switch unit 211 inputs an operation instruction from the operator. Specifically, the crown 104, the operation button 105, and the like shown in FIG. The switch control circuit 212 transmits an input related to an operation instruction from the operator to the clock microcomputer 200 based on a signal from the switch unit 211.

  The charge control circuit 215 converts the light received by the solar cell 213 into electric power and stores it in the secondary battery 214. The charging control circuit 215 also has a voltage detection function for detecting the voltage (value) of the secondary battery 214, a power generation detection function for detecting whether the solar cell 213 is in a power generation state or a non-power generation state, and the like. And the signal regarding a detection result is output with respect to the timepiece microcomputer 200 by these functions. Based on this signal, the remaining charge is displayed.

  The liquid crystal driving circuit drives a display screen (not shown) to display various information. The LED drive circuit drives the LED to illuminate the display screen as a backlight or outputs warning light. Instead of the LED, an EL (Electroluminescence), a lamp, or the like may be used. The alarm driving circuit drives an unillustrated piezoelectric element mounted on the alarm and outputs an alarm (buzzer). At that time, the alarm drive circuit changes the type of sound, the height, the volume, etc., depending on the type of notification.

  FIG. 3 is an explanatory diagram showing a decoding IC of the radio-controlled timepiece according to the embodiment of the present invention and its surrounding hardware configuration. In FIG. 3, the reception IC 300 realizes the processing of the tuning circuit 208 and the reception circuit 209 shown in FIG. The timepiece microcomputer 200 includes a control unit 301, a DF tone processing unit 302, and a time display control unit 303.

  The decode IC 210 is connected to a communication port that controls input / output of signals and data between the four mode units (reception mode unit 310, through mode unit 320, needle hole detection mode unit 330, test mode unit 340) and the clock microcomputer 200. An output control circuit 350, a high-speed data communication unit 360 that processes data sent from the clock microcomputer 200 to the decode IC 210 by high-speed communication, and a low-speed that processes low-speed data sent from the decode IC 210 to the clock microcomputer 200 by low-speed communication A data communication unit 370, a frequency dividing circuit 380, and a power supply circuit 390 are provided.

  Here, the through mode executed by the through mode unit 320 is to output the signal of the reception IC 300 to the clock microcomputer 200 using the decode IC 210 so that the wiring between the clock microcomputer 200 and the reception IC 300 is not increased. Mode. The clock microcomputer 200 monitors the output of the receiving IC 300. Then, when it is detected that the time code output is stable, setting information related to AGC for causing the reception IC 300 to perform appropriate AGC at the time of decoding is output from the clock microcomputer 200 to the reception IC 300. Therefore, the through mode can be executed without overlapping with the decoding processing by the decoding IC 210, so that the through mode unit 320 can be provided in the decoding IC 210.

  The needle hole detection mode executed by the needle hole detection mode unit 330 is a mode for detecting the position of each pointer (the minute hand 101, the hour hand 102, the second hand 103, etc. shown in FIG. 1). A hole is formed in a part of the gear constituting the train wheel, and a light emitting element such as an LED and a light receiving element are arranged above and below the hole, and the light receiving element receives light, thereby the position of the gear hole. (That is, the position of the pointer needled to the pointer shaft based on the position of the gear hole). In the needle hole detection mode, the decoding process by the decode IC 210 and the needle hole detection are performed at different timings. Therefore, the needle hole detection mode unit 330 may be provided with a needle hole detection function in the decode IC 210 in the same manner as the through mode unit 320. it can.

  The test mode executed by the test mode unit 340 is a mode for testing whether or not the decoding IC 210 can correctly decode.

  The reception mode unit 310 includes a reception parameter storage unit 311, a time measuring unit 312, a reception data calculation unit 313, and a reception data storage unit 314. The through mode unit 320 includes a through communication unit 321, and the needle hole detection mode unit 330 includes a needle hole detection circuit 331 and a needle hole result communication unit 332.

  The high-speed data communication unit 360 includes a mode determination unit 361 and a parameter setting unit 362, and receives a request signal output from the clock microcomputer 200 via the communication port input / output control circuit 350. Based on the input request signal, the mode determination unit 361 determines the requested mode and outputs mode determination data to each mode unit. The mode section to which the mode determination data is input starts the operation related to each mode. Also, the parameter setting unit 362 outputs the parameter data for reception to the reception mode unit 310 or the parameter data for needle hole detection to the needle hole detection mode unit 330 based on the request signal.

  The reception parameter storage unit 311 receives and stores (reception) parameter data output from the parameter setting unit 362. Then, the time counting unit 312 reads data related to the reception start time from the reception parameter storage unit 311 and measures the time. The reception data calculation unit 313 reads the reception parameter from the reception parameter storage unit 311.

  The reception data calculation unit 313 inputs the time code output from the reception IC 300 based on the read reception parameter, and executes calculation processing. The result (time code result / reception confirmation time) calculated by the reception data calculation unit 313 is stored in the reception data storage unit 314 and is read by the reception data calculation unit 313 as necessary. Then, the received data calculation unit 313 outputs the calculated result to the low-speed data communication unit 370 as a processing result.

  In addition, the time measuring unit 312 reads the reception confirmation time stored in the reception data storage unit 314, counts the time based on the read reception confirmation time, and outputs it to the low-speed data communication unit 370 as the current time.

  The low-speed data communication unit 370 inputs the request signal output from the clock microcomputer 200 via the communication port input / output control circuit 350 and outputs a reset signal to the frequency dividing circuit 380 based on the input request signal. At the same time, the current time output from the timekeeping unit 312 or the processing result output from the received data calculation unit 313 is output as a response signal to the communication port input / output control circuit 350, and the data signal or The decoded output signal is sent to the clock microcomputer 200.

  The frequency dividing circuit 380 inputs the 32 kHz clock signal output from the clock microcomputer 200 via the communication port input / output control circuit 350 and controls the clock in the decode IC 210 based on the input 32 kHz clock signal. . The frequency dividing circuit 380 does not include the DF adjustment processing unit 302 unlike the timepiece microcomputer 200, so that the accuracy of the clock output from the frequency dividing circuit 380 is lower than the accuracy output from the timepiece microcomputer 200. . Therefore, a frequency dividing circuit to which a 32 kHz clock signal is input by a reset signal (a signal based on a 64 Hz clock signal whose logic frequency is adjusted by the DF adjustment processing unit 302 of the clock microcomputer 200) output from the low speed data communication unit 370. 380 is reset. Details of the reset process will be described later.

  The power supply circuit 390 covers all the power supplies of the decode IC 210. When the enable is turned on by the decode IC enable signal input from the clock microcomputer 200 via the communication port input / output control circuit 350, the power of the decode IC 210 is turned on. When the enable is turned off, the power of the decode IC 210 is turned off. Become.

(Contents of receiving operation)
Next, the reception operation of the radio-controlled timepiece according to the embodiment of the present invention will be described. FIG. 4 is an explanatory diagram showing an outline of the reception operation of the radio-controlled timepiece according to the embodiment of the present invention. In FIG. 4, first, through mode setting data is sent from the clock microcomputer 200 to the decode IC 210 by high-speed communication, and the AGC adjustment is performed in the reception IC 300.

  Then, the time code output from the receiving IC 300 is input to the through communication unit 321 of the through mode unit 320 of the decode IC 210 and output as a through result signal from the through communication unit 321, via the communication port input / output control circuit 350. The data is input to the clock microcomputer 200 as a data signal. Thereafter, the internal time data and reception parameters are sent to the reception mode unit 310 of the decode IC 210, and the second synchronization detection operation is performed in the reception mode unit 310 of the decode IC 210. The data communication from the clock microcomputer 200 to the decode IC 210 is performed by high-speed communication via the high-speed data communication unit 360.

  Thereafter, the decode IC 210 detects second synchronization from the time code output from the reception IC 300, and outputs second synchronization data in response to a request every second from the clock microcomputer 200. Similarly, the decode IC 210 analyzes the time code output from the reception IC 300 to detect minute synchronization, and outputs minute synchronization data in response to a request every 10 seconds from the clock microcomputer 200.

  Thereafter, the decode IC 210 analyzes the time code output from the reception IC 300 and acquires time data. In the meantime, every minute “01 seconds”, “11 seconds”, “21 seconds”, “31 seconds”, “41 seconds”, “51 seconds”, according to the request from the clock microcomputer 200, the received level data Output decoding progress data. Here, the reception level data is information related to time code noise. The decoding progress data is data representing how far the decoding has progressed (for example, “proceeding to second synchronization”, “advancing to minute synchronization”, etc.).

  When the time data is determined, the time measurement time data is output in response to a request from the clock microcomputer 200 at “01 seconds”. The output of these second synchronization data, minute synchronization data, reception level / decoding progress status data, and timekeeping time data is output as a decode output signal from the low-speed data communication unit 370 via the communication port input / output control circuit 350 through low-speed communication. It is sent to the clock microcomputer 200.

  FIGS. 5A and 5B are flowcharts showing the contents of the operation of the decoding IC of the radio-controlled timepiece according to the embodiment of the present invention. In the flowchart of FIG. 5A, the decode IC 210 first turns on the enable in response to a decode IC enable signal input from the clock microcomputer 200 to the power supply circuit 390 (step S501). Thereafter, the input of high-speed communication data is waited (step S502: No), and when high-speed communication data is input (step S502: Yes), the mode of the high-speed data communication unit 360 is determined from the content of the input high-speed communication data. The determination unit 361 determines the mode.

  It is determined whether or not the determined mode is “through mode” (step S503). If it is “through mode” (step S503: Yes), the through communication unit 321 of the through mode unit 320 transmits a through result signal. Is continuously output (step S504). After that, the power supply circuit 390 waits for the decode IC enable signal to be turned off (step S505). If turned off (step S505: Yes), the output of the through result signal is stopped and the operation in the through mode is performed. finish.

  In step S503, when the determined mode is not the “through mode” (step S503: No), it is determined whether the determined mode is the “needle hole detection mode” (step S506). Here, when the determined mode is “needle hole detection mode” (step S506: Yes), the needle hole detection circuit 331 of the needle hole detection mode unit 330 performs the needle hole detection operation, and the needle hole result communication unit. 332 outputs a needle hole detection result signal (step S507). Then, it waits for the decode IC enable signal to be turned off to the power supply circuit 390 (step S508: No), and if turned off (step S508: Yes), the needle hole detection operation is terminated.

  If the determined mode is not the “needle hole detection mode” in step S506 (step S506: No), it is determined whether or not the determined mode is the “test mode” (step S509). If the determined mode is “test mode” (step S509: Yes), the test mode unit 340 performs a test operation and outputs a test result signal (step S510). Then, it waits for the decode IC enable signal to be turned off to the power supply circuit 390 (step S511: No), and when it is turned off (step S511: Yes), the test operation is terminated.

  In step S509, when the determined mode is not “test mode” (step S509: No), it is determined whether or not the determined mode is “reception mode” (step S512). Here, when the determined mode is the “reception mode” (step S512: Yes), the process proceeds to step S551 in the flowchart of FIG. On the other hand, if the determined mode is not “reception mode” in step S512 (step S512: No), the process returns to step S502.

  In the flowchart of FIG. 5B, first, the parameter setting unit 362 of the high-speed data communication unit 360 sets reception parameters from the contents of the high-speed communication data input in step S502 of FIG. 5A (step S551), and the time Code analysis is started (step S552).

  Next, the second synchronization acquisition operation is performed to determine whether the second synchronization has been acquired (step S553). If second synchronization cannot be acquired (step S553: No), the acquisition operation is repeated until acquisition is possible. When acquisition is possible (step S553: Yes), after waiting for the request signal from the clock microcomputer 200 to be input to the low-speed data communication unit 370 (step S554: No), the request signal is input. In the case (step S554: Yes), the low-speed data communication unit 370 outputs a reset signal based on the clock included in the request signal to the frequency dividing circuit 380 and resets the frequency dividing circuit 380 (step S555).

  Then, after the frequency dividing circuit 380 is reset, the reception data calculation unit 313 outputs the processing result to the low-speed data communication unit 370, and the low-speed data communication unit 370 outputs a response signal based on the processing result, so that the communication port Second synchronization position information is sent to the clock microcomputer 200 via the input / output control circuit 350 (step S556).

  Thereafter, an acquisition operation for minute synchronization is performed to determine whether or not minute synchronization has been acquired (step S557). If minute synchronization cannot be acquired (step S557: No), the acquisition operation is repeated until acquisition is possible. When acquisition is possible (step S557: Yes), it waits for the request signal from the clock microcomputer 200 to be input to the low-speed data communication unit 370 (step S558: No), and the request signal is input ( In step S558: Yes), the low-speed data communication unit 370 outputs a reset signal based on the clock included in the request signal to the frequency dividing circuit 380 and outputs the frequency-divided clock of the frequency dividing circuit 380 as in step S555. Reset (step S559).

  Then, after resetting the divided clock, the reception data calculation unit 313 outputs the processing result to the low-speed data communication unit 370, and the low-speed data communication unit 370 outputs a response signal based on the processing result. Minute synchronization position information is sent to the clock microcomputer 200 via the output control circuit 350 (step S560).

  Thereafter, a time information determination operation is performed to determine whether the time information has been determined (step S561). If the time information cannot be determined (step S561: No), the time determination operation is repeated until it can be determined. If the time information is not confirmed, the step is not shown, but the decode IC 210 transmits the reception level data and the decode progress data to the clock microcomputer 200 at the timing of “01” seconds. If the time information can be confirmed (step S561: Yes), the time information is corrected (step S562).

  Then, after waiting for the request signal from the clock microcomputer 200 to be input to the low-speed data communication unit 370 (step S563: No), when the request signal is input (step S563: Yes), the low-speed data communication unit Similarly to step S555, 370 outputs a reset signal based on the clock included in the request signal to frequency dividing circuit 380, and resets the frequency dividing clock of frequency dividing circuit 380 (step S564).

  After resetting the divided clock, the time counting unit 312 outputs the current time to the low-speed data communication unit 370, and the low-speed data communication unit 370 outputs a response signal, so that the time is passed through the communication port input / output control circuit 350. The correction information is sent to the clock microcomputer 200 (step S565). Thereafter, when the decode IC enable OFF signal is input to the power supply circuit 390, the decode IC 210 is enabled OFF (step S566), and the series of processing ends.

  FIGS. 6A and 6B are flowcharts showing the contents of the operation of the timepiece microcomputer of the radio-controlled timepiece according to the embodiment of the present invention. In the flowchart of FIG. 6A, the clock microcomputer 200 outputs a control signal to the reception IC 300, turns on the reception IC 300 to enable (step S601), and stabilizes the reception operation by the reception IC 300 for a predetermined stabilization time. Wait (step S602).

  Thereafter, mode determination data (through mode setting data) is input to the through mode unit 320 of the decode IC 210 via the mode determination unit 361 to start the through mode operation, and is output from the through communication unit 321 of the through mode unit 320. The through result signal is input (step S603), and the setting of the receiving IC 300 is changed (step S604). Then, after an elapse of a predetermined stable time, the enable signal of the decode IC 210 input to the power supply circuit 390 is turned ON at the timing of 1 Hz of the clock of the clock microcomputer 200 (step S605).

  Next, the mode determination data is input to the reception mode unit 310 of the decode IC 210 via the mode determination unit 361, the reception parameters (internal time data, reception parameters, etc.) are input, and the reception mode operation is started (step S606). ). Then, after waiting for the request timing (step S607: No), when the request timing is reached (step S607: Yes), a request signal is transmitted to the decode IC 210 (step S608). The request timing here is every second (1 second interval).

  Then, it is determined whether or not the second synchronization result is obtained for the transmitted request signal, that is, whether or not the second synchronization position information signal is transmitted from the decode IC 210 (step S609), and the second synchronization result is obtained. If not (step S609: No), the process returns to step S607, and steps S607 to S609 are repeated. If the second synchronization result is obtained in step S609 (step S609: Yes), the process proceeds to step S651 in the flowchart of FIG.

  In the flowchart of FIG. 6B, the request timing is changed from every second to 10 seconds. When changing to the 10-second interval, the request timing is set so that a request signal is transmitted in a time code non-determination section, which will be described later, based on the second synchronization position information signal. Then, after waiting for the request timing (step S652: No), that is, waiting for 10 seconds from the previous request and reaching the request timing (step S652: Yes), the request signal is sent to the decode IC 210. Is transmitted (step S653).

It is determined whether or not a minute synchronization result is obtained for the transmitted request signal, that is, whether or not a minute synchronization position information signal is transmitted from the decode IC 210 (step S654), and the minute synchronization result is not obtained. If it is (Step S654: No), the process returns to Step S652, and Steps S652 to S654 are repeated.

  When the minute synchronization result is obtained in step S654 (step S654: Yes), the request timing is further changed (step S655). In step S652, the interval was simply 10 seconds, but here, since the minute synchronization result was obtained, the interval was 10 seconds, but "01" seconds, "11" seconds, "21" seconds, The timing is changed so that the request is made at “31” seconds, “41” seconds, and “51” seconds.

  Then, waiting for the request timing (step S656: No), that is, based on the minute synchronization result, every minute “01” seconds, “11” seconds, “21” seconds, “31” seconds, “41” When the request timing comes after waiting for “seconds” and “51” seconds (step S656: Yes), a request signal is transmitted to the decode IC 210 (step S657). It is determined whether or not a time correction result is obtained for the transmitted request signal, that is, whether or not a time correction information signal is transmitted from the decode IC 210 (step S658), and the time correction result is not obtained. In the case (step S658: No), the process returns to step S656, and steps S656 to S658 are repeated.

  However, in the present embodiment, the time correction information is transmitted only at the timing of “01” seconds per minute, and other request timings (“11” seconds, “21” seconds, “31”). In the second, “41” seconds, and “51” seconds), the decoding IC 210 transmits information such as the code progress status, the reception level, and the noise amount instead of the time correction information.

  If the time correction result is obtained in step S658 (step S658: Yes), the reception operation is terminated (step S659), and the decode IC enable OFF signal is output to the decode IC 210, thereby enabling the power supply circuit 390. The time is turned off (step S660), the time adjustment operation is performed (step S661), and the series of processing ends.

  FIG. 7 is a timing chart showing the contents of the operation in the through mode. In the timing chart of FIG. 7, the decode IC enable signal is a signal input to the power supply circuit 390 from the clock microcomputer 200 via the communication port input / output control circuit 350 as shown in FIG. 3 is a signal that is input from the clock microcomputer 200 to the low-speed data communication unit 370 via the communication port input / output control circuit 350 as shown in FIG.

  Also, as shown in FIG. 3, the decode output signal is an output signal output from the communication port input / output control circuit 350 of the decode IC 210 to the clock microcomputer 200, and the data signal is also shown in FIG. Thus, the data signal is between the clock microcomputer 200 and the communication port input / output control circuit 350 of the decode IC 210. When the decode output signal is OFF, the data signal is transmitted from the clock microcomputer 200 to the decode IC 210, and when the decode output signal is ON, the data signal is transmitted from the decode IC 210 to the clock microcomputer 200.

  As shown in FIG. 3, the time code is code data input from the reception IC 300 to the reception data calculation unit 313 of the decode IC 210 and the through communication unit 321 of the through mode unit 320.

  First, at the time of (1), the enable signal of the decode IC 210 is turned on (rises), and then a data signal for setting the through mode is transmitted from the clock microcomputer 200 as an input port by high-speed communication. A request signal having the same rectangular shape as this data signal is generated. When the mode determination unit 361 of the decode IC 210 reads data at each falling edge of the 1 ms request signal and determines that the data is through mode setting data, the data is read by the number of bits corresponding to the through mode setting parameter. .

  When the request signal is input, the decode output signal rises at time (2), and the data signal is transmitted from the decode IC 210 to the clock microcomputer 200 as a through result signal from the decode IC 210 having the same rectangular shape as the time code. In this way, the timepiece microcomputer 200 can input the time code output from the receiving IC 300 through the decoding IC 210.

  In the through mode of FIG. 7, although detailed contents are omitted, in the through mode, the clock microcomputer 200 monitors the output of the receiving IC 300 and detects that the time code output is stable. AGC-related setting information for performing AGC is output from the clock microcomputer 200 to the receiving IC 300.

  FIG. 8 is a timing chart showing the contents of the initial reception operation. In the timing chart of FIG. 8, the reception IC enable signal is a signal included in a control signal sent from the clock microcomputer 200 to the reception IC 300, and controls the reception operation of the reception IC 300, that is, the output / non-output of the time code. . The decode IC enable signal, decode output signal, data signal, and time code are the same as those shown in FIG. VAGC indicates an automatic gain control (AGC) voltage, and the receiving IC 300 outputs a time code after stabilizing VAGC.

  At time (1), the timepiece microcomputer 200 raises the reception IC enable signal and sets the parameters of the reception IC 210, whereby the time code is output from the reception IC 300. At the time of (2), the decode IC enable signal is raised and the through mode is set, and the decode output signal is raised, so that the data signal has the same rectangular shape as the time code from the high-speed communication signal input port. Output port. That is, as described with reference to FIG. 7, the through mode is set from the time point (2) to the time point (3) when the decode IC enable signal and the decode output signal fall.

  At time (3), the time code is output, but no data signal is generated. Then, at the time of (4), after the decode IC 210 enable signal is raised, the data for receiving mode setting and the data for receiving mode setting, that is, the data such as internal time data, receiving parameter, value, etc. are sent as data signals. Output from the clock microcomputer 200.

  The reception parameters are set in accordance with the specifications of the decoding IC 210, and are data that collectively output the data used for the decoding processing of the decoding IC 210 before the decoding processing is performed. Has a larger data amount than the second synchronization data, minute synchronization data, reception level, and decoding progress data output from the decode IC 210 to the microcomputer 200 during reception. After the decode IC enable signal is raised, the reception parameter and internal time data are output by high-speed communication, so that the operation in the reception mode can be executed quickly even if the amount of data is large. Thereafter, the decoding IC 210 executes the operation in the reception mode.

  Here, the period from (1) to (2) indicates the stable time of step S602 in the flowchart of FIG. 6-1, and the period from (3) to (4) is the stable time of step S605. Shows time.

  FIG. 9 is a timing chart showing the contents of low-speed communication and frequency division reset operation in the reception mode. In the timing chart of FIG. 9, the time code is “High” in the time code determination section, and the time code is “Low” in the non-determination section of the time code. That is, at time (1), the time code falls from High to Low, and at this point, the time code determination section switches to the time code non-determination section.

  The request signal rises at the time (2) and falls at the time (3) in accordance with the rectangle of the microcomputer DF-tuned 64 Hz signal adjusted by the DF tone processing unit 302 of the clock microcomputer 200. A reset signal is generated based on this request signal (see the frequency divider reset signal in FIG. 9), and the frequency divider 380 is reset. Further, the decode output signal rises at the fall timing of the request signal (time point (3)), and the data signal can be output from the decode IC 210.

  Then, response data by low-speed communication is output in a state where the decode output signal is High. The low-speed communication is performed in the cycle of the 64 Hz signal of the decode IC 210 that is longer than the communication interval of the 1 mS cycle of the high-speed communication. Thereafter, before the time code non-determination period ends, the low-speed communication of the response data ends and the decode output signal falls. Thus, based on the second synchronization detection result, the clock microcomputer 200 can output a request signal in accordance with the time code non-determination interval, and the request signal and response data are generated within the time code non-determination interval. Does not affect the determination of the time code.

  However, when timekeeping time data is output as response data (“01 seconds”), the data is long, and all data may not be output within the time code non-determination section. In that case, the data is output outside the time code determination section. This is because the time has already been determined, and there is no problem even if the determination of the time code is affected.

  In this way, in order to maintain the normal timekeeping accuracy by the clock microcomputer 200, the DF adjustment is performed at a cycle of once every 10 seconds, so that a request signal (every minute every 10 seconds) The reference signal of the decode IC 210 can be synchronized with the reference signal of the clock microcomputer 200 by resetting the peripheral circuit.

  An example of the standard time code is shown in FIGS. 10-1 and 10-2. FIG. 10-1 is an explanatory diagram illustrating an example (Time_Code: JJY) of a standard radio wave time code, and FIG. 10-2 is an explanatory diagram illustrating an example of a time code of a standard radio wave (Time_Code: DCF77).

  Time_Code: JJY shown in FIG. 10-1 is a time code of a standard radio wave in Japan, and the time code can be determined in the first half of 800 ms in one second. This section is set as the time code determination section, and the latter half of 200 ms. Is a time code non-determined section. Therefore, in Japanese standard radio waves, a request signal is output during the latter 200 ms, the 32 kHz signal of the frequency dividing circuit 380 is reset, and response data is transmitted at a low speed.

  On the other hand, Time_Code: DCF77 shown in FIG. 10-2 is a time code of a standard radio wave in Europe. A time code can be determined in the first half of 500 ms in one second. This section is set as a time code determination section. 500 ms is a time code non-determination section. Therefore, in the European standard radio wave, a request signal is output during the latter half of 500 ms, the 32 kHz signal of the frequency dividing circuit 380 is reset, and response data is transmitted at low speed.

  If a request signal is transmitted in the time code determination section and the frequency dividing circuit 380 is reset, the timing of the time code sampling performed by the decoding IC is shifted by these processes, and the clock microcomputer 200 and the decoding IC 210 Due to the influence of noise generated by communication, correct code determination may not be possible. In the present embodiment, communication between the clock microcomputer 200 and the decode IC 210 and resetting of the frequency dividing circuit 380 of the decode IC 210 are performed in the time code non-determining section, so that such a problem does not occur.

  As described above, the radio-controlled timepiece according to the embodiment of the present invention receives the reference signal generating unit 206 as the reference signal generating means for generating the reference signal and the radio signal including a plurality of code signals representing time information. An antenna 207 as a receiving means, a receiving IC 300 (tuning circuit 208, receiving circuit 209), and a reference signal are input, and a plurality of code signals included in the radio signal received by the receiving means based on the input reference signal Decoding as a decoding means for determining one code signal from (JJY 0, 1, P code or DCF 0, 1, M code), obtaining decoding information such as time data, and outputting the decoding information IC210. Here, the decode information is not limited to the clock time data, but may be a code signal such as 0, 1, P, M or the like.

  Furthermore, it is constituted by a circuit different from the decoding means, inputs a reference signal, adjusts the frequency of the input reference signal, and counts time information for notification based on the adjusted adjusted reference signal, A timepiece microcomputer 200 is provided as timekeeping means for inputting the decode information and correcting the time information for notification based on the input decode information.

  Then, the clock microcomputer 200 outputs a request signal including a reset signal generated based on the adjusted reference signal, the decode IC 210 inputs a request signal including the reset signal, and the reference signal is reset by the reset signal. To do.

  Therefore, according to the radio-controlled timepiece according to the embodiment of the present invention, the reference signal of the decode IC 210 can be synchronized with the adjusted reference signal of the timepiece microcomputer 200. As a result, the decode IC 210 can accurately sample the time code using a signal synchronized with the adjusted reference signal (for example, a 64 Hz signal obtained by dividing the 32 kHz signal).

  In the radio-controlled timepiece according to the embodiment of the present invention, the code signal is transmitted so as to rise or fall at a predetermined period, that is, as shown in FIG. 10-1 or 10-2. In addition, in the remaining section (time code determination section) excluding a part of the period (time code non-determination section) in each cycle, the code signal can be discriminated. The start timing (for example, the second head) of a predetermined cycle is detected from the received radio wave signal, information on the detected start timing is output, and the clock microcomputer 200 inputs information on the start timing, and the input start Based on the timing-related information, a reset signal is output in a partial section (time code non-determination section).

  In the radio-controlled timepiece according to the embodiment of the present invention, the decode IC 210 determines the code signal in the remaining section (time code determination section) and the reference signal in a part of the section (time code non-determination section). To reset.

  Therefore, according to the radio-controlled timepiece according to the embodiment of the present invention, the reference signal reset operation of the decode IC 210 can be performed without affecting the time code determination operation.

  In the radio-controlled timepiece according to the embodiment of the present invention, the clock microcomputer 200 outputs time information for notification, the decode IC 210 inputs time information for notification, and the input time information is The time counting unit 312 measures the time based on the reference signal or the frequency-divided signal of the reference signal, and decodes the corrected time information obtained by correcting the time information for notification being timed based on the determination results of the plurality of code signals. And

  Therefore, according to the radio-controlled timepiece according to the embodiment of the present invention, the timepiece microcomputer 200 can easily correct the time by simply replacing the current time according to the input correction time information with the current time being timed. can do.

  In the radio-controlled timepiece according to the embodiment of the present invention, the through mode unit 320 of the decode IC 210 outputs a radio signal (time code), and the clock microcomputer 200 outputs the radio signal (time) output by the decode IC 210. Code).

  Therefore, according to the radio-controlled timepiece according to the embodiment of the present invention, the timepiece microcomputer 200 can acquire the time code output from the reception IC 300 via the decode IC 210, and the timepiece microcomputer 200 creates timing. be able to. Further, the output timing of the request signal to the decode IC 210 can be measured based on the acquired time code.

  In the radio-controlled timepiece according to the embodiment of the present invention, all or part of the data output from the clock microcomputer 200 to the decode IC 210 is transmitted in the first communication cycle (“high-speed communication” shown in FIG. 4). The decoding IC 210 outputs the data to be output to the clock microcomputer 200 in a second communication cycle (“low speed communication” shown in FIG. 4) longer than the first communication cycle (“high speed communication”).

  Therefore, according to the radio-controlled timepiece according to the embodiment of the present invention, the decoding IC 210 can start the receiving operation more quickly by high-speed communication, while the decoding output is performed by low-speed communication. The processing of the microcomputer 200 is not burdened.

  As described above, according to the radio-controlled timepiece according to the embodiment of the present invention, the decoding process is performed by a circuit (decoding IC 210) separate from the timepiece microcomputer 200, thereby reducing the size of the timepiece microcomputer 200 and accompanying it. The entire radio-controlled watch can be reduced in size. Further, along with the downsizing of the timepiece microcomputer 200, it is possible to reduce the cost of the timepiece microcomputer 200 by taking more timepiece microcomputers 200 from one wafer.

  At the same time, even if the accuracy of the clock output from the frequency dividing circuit 380 of the decode IC 210 that does not have the logical frequency adjustment function is lower than the accuracy output from the clock microcomputer 200 that has the logical frequency adjustment function, Since the time code sampling is performed by resetting the signal adjusted by the logic frequency of the microcomputer for clock 200, the code determination can be performed accurately and the clock microcomputer 200 can be easily synchronized with the clock microcomputer 200. Therefore, the decoding process can be surely performed by the clock microcomputer 200 and a separate circuit (decoding IC 210).

  As described above, the radio-controlled timepiece according to the present invention is useful for a radio-controlled timepiece that receives a standard radio wave and corrects the time. In particular, the radio-controlled timepiece that is required to be downsized and inexpensive like a wristwatch. Suitable for watches.

100 radio wave correction watch body 200 clock microcomputer 206 reference signal generator 207 antenna 210 decoding IC
300 Receiver IC
302 DF adjustment (logic frequency adjustment) processing unit 310 reception mode unit 320 through mode unit 350 communication port input / output control circuit 360 high speed data communication unit 370 low speed data communication unit 380 frequency divider circuit

Claims (6)

A reference signal generating means for generating a reference signal;
Receiving means for receiving a radio signal including a plurality of code signals representing time information;
The reference signal is input, and based on the input reference signal, one code signal is discriminated from a plurality of code signals included in the radio signal received by the receiving means to obtain decode information, and the decode information is obtained. Decoding means for outputting information;
Consists of a circuit different from the decoding means, inputs the reference signal, adjusts the frequency of the input reference signal, and counts time information for notification based on the adjusted adjusted reference signal A time counting means for inputting the decode information and correcting the time information for timekeeping based on the input decode information;
With
The time counting means outputs a reset signal generated based on the adjusted reference signal;
The radio-controlled timepiece, wherein the decoding means inputs the reset signal and resets the reference signal by the input reset signal. The code signal is a signal that is transmitted at a predetermined period and is capable of discriminating the code signal in the remaining sections excluding a part of the sections in each period.
The decoding means detects the start timing of the predetermined period from the radio signal received by the receiving means, and outputs information on the detected start timing,
The said time measuring means inputs the information regarding the said start timing, and outputs the said reset signal in the said one part area based on the input information regarding the said start timing. Radio correction clock.   3. The radio-controlled timepiece according to claim 2, wherein the decoding means determines the code signal in the remaining section and resets the reference signal in the partial section. The time counting means outputs the time information for notification,
The decoding means inputs the time information for notification, measures the input time information based on the reference signal or a divided signal of the reference signal, and based on the determination results of the plurality of code signals. The radio-controlled timepiece according to claim 1, wherein corrected time information obtained by correcting the time information for notification being timed is used as the decode information.   5. The radio-controlled timepiece according to claim 1, wherein the decoding unit includes a unit that inputs an output signal of the receiving unit and outputs the signal to the time counting unit. The time counting means outputs all or part of the data to be output to the decoding means in a first communication cycle,
The radio wave according to any one of claims 1 to 5, wherein the decoding means outputs data to be output to the timekeeping means in a second communication cycle longer than the first communication cycle. Correction clock.

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