JP2012039001A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a wafer test without destroying an oxide film directly under bonding pads.SOLUTION: A semiconductor device comprises: a semiconductor substrate 9; five wiring layers formed on the semiconductor substrate 9; a plurality of bonding pads 5e that are formed on an uppermost fifth wiring layer 5 in the five wiring layers and in which a part of each of them is exposed; and active elements, for example, transistor elements that are formed on the semiconductor substrate 9, are disposed at the positions overlapping the bonding pads 5e under the pads in plan view, and are electrically connected to the bonding pads 5e. A buffer film 7 in which any wiring layer of the five wiring layers is not provided is formed directly under the bonding pads 5e.

Description

  The present invention relates to a semiconductor device, and more particularly, to a technique effective when applied to a semiconductor chip in which an active element is disposed under a bonding pad.

  An input / output circuit is formed on a semiconductor substrate, a ground wiring and a power supply wiring pass through it, a conductor layer for a bonding pad is formed thereon, and the input / output circuit has a MISFET element and a resistor functioning as a protection element A structure formed by an element and a diode element is described (see, for example, Patent Document 1).

JP 2007-150150 A

  In recent years, semiconductor chips (hereinafter simply referred to as “chips”) may be reduced in order to reduce costs. In order to reduce the size of semiconductor chips, wiring is disposed under bonding pads. There is a need.

  However, if the wiring is arranged directly under the bonding pad, there is a problem that the glass (oxide film, insulating film) immediately below the bonding pad is broken due to damage caused by probing in the wafer test process. That is, when strong damage (high needle pressure) is applied by probing, a crack is formed in the glass immediately below the bonding pad, and moisture or the like permeates from the crack, resulting in a decrease in reliability.

  Therefore, in the five-layer wiring product, an active element is not disposed under the bonding pad.

  In order to reduce the size of the semiconductor chip, it is possible to increase the number of wiring layers to six or more, that is, increase the number of wiring layers and dispose an active layer under the bonding pad. The increase in chip manufacturing costs must be sacrificed.

  In addition, it is possible to place wiring under the bonding pad after severely constraining the conditions so that the probing in the wafer test and assembly process is damage-free, but at that time, at the expense of yield reduction. There must be.

  That is, the problem is that the semiconductor chip cannot be reduced in size, cost, and reliability cannot be improved without sacrificing an increase in chip manufacturing cost and a decrease in yield.

  Note that the above-mentioned Patent Document 1 (Japanese Patent Laid-Open No. 2007-150150) discloses a structure of a semiconductor chip in which an active element such as a resistance element is disposed under a bonding pad.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of performing a wafer test without damaging an oxide film directly under a bonding pad.

  Another object of the present invention is to provide a technique capable of reducing the size of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a representative embodiment is formed on a semiconductor substrate, a plurality of wiring layers formed on the semiconductor substrate, and the wiring layer at the uppermost layer among the plurality of wiring layers, each of which is partially A plurality of exposed bonding pads; and an active element formed on the semiconductor substrate and disposed at a position overlapping the bonding pads in a plan view below the bonding pads, and further electrically connected to the bonding pads; And a first insulating film in which any of the plurality of wiring layers is not provided is formed immediately below the bonding pad.

  Further, another semiconductor device according to a representative embodiment is formed on a semiconductor substrate, a plurality of wiring layers formed on the semiconductor substrate, and the wiring layer at the uppermost layer among the plurality of wiring layers, A plurality of bonding pads each partially exposed; a plurality of vias that are located under the bonding pads and electrically connect the uppermost wiring of the plurality of wiring layers and the bonding pads; An active element formed on a semiconductor substrate and disposed at a position overlapping with the bonding pad in plan view under the bonding pad, and further electrically connected to the bonding pad. Below, the lowermost wiring portion of the plurality of wiring layers arranged in a position overlapping with the bonding pad in plan view, , A constant width, and is intended to be constituted by a plurality of wires arranged at predetermined intervals.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The wafer test can be performed without breaking the oxide film directly under the bonding pad of the semiconductor device.

  Further, the semiconductor device can be reduced.

It is a top view which shows an example of the pad arrangement | sequence of the semiconductor device of Embodiment 1 of this invention. FIG. 2 is an enlarged partial cross-sectional view showing an example of a structure cut along line AA in FIG. 1. It is an expanded partial sectional view which shows an example of the structure cut | disconnected along the BB line of FIG. FIG. 2 is a circuit block diagram illustrating an example of a circuit under a pad of the semiconductor device of FIG. 1. FIG. 7 is a plan view illustrating an example of a structure of a fifth metal wiring layer and a pad opening of the semiconductor device of FIG. 1. FIG. 3 is a plan view showing an example of a structure of a third via layer of the semiconductor device of FIG. 1. FIG. 4 is a plan view showing an example of a structure of a third metal wiring layer of the semiconductor device of FIG. 1. FIG. 3 is a plan view showing an example of a structure of an upper second via layer of the semiconductor device of FIG. 1. FIG. 3 is a plan view showing an example of a structure of a second metal wiring layer of the semiconductor device of FIG. 1. FIG. 3 is a plan view showing an example of a structure of a lower second via layer of the semiconductor device of FIG. 1. FIG. 2 is a plan view showing an example of a structure of a first metal wiring layer of the semiconductor device of FIG. 1. FIG. 2 is a plan view illustrating an example of a structure of a first via layer of the semiconductor device of FIG. 1. FIG. 2 is a plan view showing an example of a structure of an active region and a polysilicon electrode layer of the semiconductor device of FIG. 1. FIG. 2 is a transmission plan view illustrating an example of a structure of wiring of each layer of the semiconductor device of FIG. 1 viewed from above. It is a permeation | transmission top view which shows the structure which looked at the wiring of each layer in the modification of Embodiment 1 of this invention from upper direction. It is a fragmentary sectional view which shows an example of the structure cut | disconnected along the AA line of FIG. It is a fragmentary sectional view which shows an example of the structure cut | disconnected along the BB line of FIG. It is a fragmentary sectional view showing an example of a pad of a semiconductor device of Embodiment 2 of the present invention, and a structure under a pad. It is a top view which shows an example of the structure of the 4th metal wiring layer of the structure of FIG. It is a top view which shows an example of the structure of the contact via layer of the structure of FIG. It is a top view which shows an example of the structure of the 3rd metal wiring layer of the structure of FIG. It is a top view which shows an example of the structure of the 2nd metal wiring layer of the structure of FIG. It is a top view which shows an example of the structure of the 1st metal wiring layer of the structure of FIG.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  Further, in the following embodiments, regarding constituent elements and the like, when “consisting of A”, “consisting of A”, “having A”, and “including A” are specifically indicated that only those elements are included. It goes without saying that other elements are not excluded except in the case of such cases. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a plan view showing an example of a pad arrangement of the semiconductor device according to the first embodiment of the present invention, FIG. 2 is an enlarged partial sectional view showing an example of a structure cut along the line AA in FIG. FIG. 4 is an enlarged partial sectional view showing an example of a structure cut along the line BB in FIG. 1, and FIG. 4 is a circuit block diagram showing an example of a circuit under the pad of the semiconductor device in FIG.

  The semiconductor device according to the first embodiment shown in FIG. 1 includes, for example, dicing after various semiconductor integrated circuits and bonding pads 5e are formed on the semiconductor substrate (semiconductor wafer) 9 shown in FIG. Thus, the semiconductor substrate 9 is formed by separating the semiconductor substrate 9 into chip-like semiconductor devices (semiconductor chips). Therefore, the semiconductor device is the semiconductor chip 10.

  As shown in FIG. 1, a core region (cell portion, internal circuit formation region) 10 b is disposed in the central portion of the main surface 10 a of the semiconductor chip (semiconductor device) 10. Various semiconductor integrated circuits (internal circuits) are formed in the core region 10b. For example, a core region 10b is configured by arranging a large number of basic cells, each of which is formed by combining a predetermined number of N-channel type MISFETs (Metal Insulator Semiconductor Field Effect Transistors) and P-channel type MISFETs, in each basic cell. A desired logic function is realized by connecting the MISFET and the basic cell based on the logic design.

  A plurality of bonding pads (pad electrodes, external terminals, external connection terminals) 5e are arranged on the main surface 10a of the semiconductor chip 10 along the outer periphery. Each bonding pad 5e can function as an external terminal (external connection terminal, input / output terminal) of the semiconductor chip 10 for electrical connection with an external device.

  The plurality of bonding pads 5e provided on the main surface 10a of the semiconductor chip 10 are arranged in two rows on the outer peripheral portion along each side of the semiconductor chip 10, and the positions of the bonding pads 5e are shifted by a half pitch between the rows. They are arranged in a so-called staggered arrangement. For example, the bonding pads 5e on the side close to the end of the semiconductor chip 10 and the bonding pads 5e located near the inside of the semiconductor chip 10 are alternately arranged. If the bonding pads 5e are arranged in a staggered arrangement, the effective pitch of the bonding pads 5e is reduced. Therefore, a larger number of bonding pads 5e can be formed on the same size semiconductor chip 10, and the semiconductor chips The number of terminals can be increased to 10. The bonding pads 5e may be arranged in a single row.

  In addition, on the outside of the core region 10b of the main surface 10a of the semiconductor chip 10, an input / output (I / O) GND wiring 10c (see part D in FIG. 1) and a power supply wiring 10d (see part C in FIG. 1). Are arranged, and all extend along the outer peripheral portion of the main surface 10a of the semiconductor chip 10.

  Next, the bonding pad 5e in the semiconductor chip 10 and the cross-sectional structure under the bonding pad 5e will be described with reference to FIGS.

  As shown in FIGS. 2 and 3, the semiconductor chip (semiconductor device) 10 according to the first embodiment includes a semiconductor substrate 9, a plurality of wiring layers formed on the semiconductor substrate 9, and the plurality of wiring layers. Among them, a plurality of bonding pads 5e that are formed on the uppermost wiring layer, each partially exposed, are formed on the semiconductor substrate 9, and are arranged under the bonding pads 5e so as to overlap the bonding pads 5e in plan view. Furthermore, it further includes a transistor element 9f (see FIG. 4) which is an active element electrically connected to the bonding pad 5e.

  That is, the semiconductor chip 10 has a structure in which the active element is arranged in a region below the bonding pad 5e (hereinafter also simply referred to as a region under the pad).

  Further, as shown in FIGS. 2 and 3, a buffer film (buffer layer) which is a first insulating film in which any of the plurality of wiring layers is not provided immediately below the bonding pad 5e. 7 is formed.

  That is, the first wiring layer 1, the second wiring layer 2, and the third wiring layer 3 are sequentially stacked from the bottom on the semiconductor substrate 9 as a base, and the buffer layer and the third wiring layer 3 are formed on the third wiring layer 3. A buffer film 7 is formed, a fifth wiring layer 5 is formed on the buffer film 7, and a bonding pad 5 e is formed on the fifth wiring layer 5. That is, only the insulating film (first insulating film) layer is formed in the region where the fourth wiring layer is originally formed in the region immediately below the bonding pad 5e, and the buffer film 7 is formed without forming the wiring. ing. Therefore, the semiconductor chip 10 has a five-layer wiring structure in which no wiring is formed on the buffer film 7 immediately below the pad.

  Here, FIG. 4 is an example of an I / O buffer circuit arranged at a position below the bonding pad 5e, and four transistor elements 9f electrically connected to the bonding pad 5e are shown in FIGS. The semiconductor substrate 9 is disposed in a region below the bonding pad 5e. These four transistor elements 9f are electrically connected to a logic circuit 11 (or a level shifter or the like) as shown in FIG.

  By disposing the I / O buffer circuit under the bonding pad 5e in this way, the chip area can be used effectively and the semiconductor chip (semiconductor device) 10 can be reduced.

  Next, the detailed shape of the wiring of each wiring layer of the semiconductor chip 10 will be described.

  5 is a plan view showing an example of the structure of the fifth metal wiring layer and the pad opening of the semiconductor device of FIG. 1, and FIG. 6 is a plan view showing an example of the structure of the third via layer of the semiconductor device of FIG. 7 is a plan view showing an example of the structure of the third metal wiring layer of the semiconductor device of FIG. 1, FIG. 8 is a plan view showing an example of the structure of the upper second via layer of the semiconductor device of FIG. 1, and FIG. FIG. 10 is a plan view showing an example of a structure of a second lower via layer of the semiconductor device of FIG. 1. 11 is a plan view showing an example of the structure of the first metal wiring layer of the semiconductor device of FIG. 1, FIG. 12 is a plan view showing an example of the structure of the first via layer of the semiconductor device of FIG. 1 is a plan view showing an example of the structure of the active region and the polysilicon electrode layer of the semiconductor device of FIG. 1, and FIG. 14 is a transmission plan view showing an example of the structure of the wiring of each layer of the semiconductor device of FIG.

  First, the wiring of the uppermost fifth wiring layer 5 shown in FIG. 5 will be described. The section AA in FIG. 5 corresponds to the fifth metal wiring 5a in FIG. 2, and the section BB in FIG. 5 corresponds to the fifth metal wiring 5a in FIG. 5 shows the metal layout of the fifth wiring layer 5 (uppermost layer) of the single bonding pad 5e, and the bonding pad 5e is the fifth metal wiring 5a of the fifth wiring layer 5 as shown in FIG. It has become a part of. Further, the outer periphery of the bonding pad 5 e is covered and protected by the protective film 6, but the central part is exposed by the opening 6 a of the protective film 6 and serves as a connection terminal.

  Further, as shown in FIGS. 3 and 5, there are a power supply wiring 5b insulated from the bonding pad 5e, an output buffer output wiring 5c electrically connected to the bonding pad 5e, Wirings such as the GND wiring 5d and the logic circuit 11 (or level shifter) are arranged.

  Next, the wiring of the third via layer shown in FIG. 6 will be described. The AA cross section in FIG. 6 corresponds to the layer of the third via 3a in FIG. 2, and the BB cross section in FIG. 6 corresponds to the layer of the third via 3a in FIG.

  As shown in FIGS. 3 and 6, a plurality of third vias 3a are arranged in the third via layer. That is, a plurality of power supply vias 3b for electrically connecting the power supply wiring 5b arranged around the bonding pad 5e in the fifth wiring layer 5 and the power supply wiring 3f of the third wiring layer 3 are provided. A plurality of output buffer output vias 3c electrically connecting the output buffer output wiring 5c electrically connected to the bonding pad 5e in the fifth wiring layer 5 and the output buffer output wiring 3g of the third wiring layer 3 are provided. Is provided.

  In the third via layer, wirings such as a plurality of GND vias 3d and a logic circuit 11 (or a level shifter) are also arranged as shown in FIG.

  However, as shown in FIGS. 2 and 3, no wiring is formed in the buffer film 7 in the region under the pad of the layer in which the plurality of third vias 3a are formed (third via layer).

  Next, the wiring of the third wiring layer 3 shown in FIG. 7 will be described. The AA cross section in FIG. 7 corresponds to the third metal wiring 3e in FIG. 2, and the BB cross section in FIG. 7 corresponds to the third metal wiring 3e in FIG.

  As shown in FIG. 7, the third wiring layer 3 includes a power supply wiring 3f which is a plurality of stripe-shaped third metal wirings 3e in a region located below the bonding pad 5e of the fifth wiring layer 5 (uppermost layer). Is provided. The plurality of stripe-shaped power supply wirings 3f are arranged so as to extend in a direction intersecting with the sliding direction R of the probe brought into contact with the bonding pad 5e at the time of probe inspection, for example. Thereby, the dispersion | distribution of the stress by a probe load is aimed at. The reason why the probe is slid on the bonding pad 5e is to remove the oxide film on the pad surface.

  In the third wiring layer 3, a plurality of stripe-shaped GND wirings 3 h are provided in a region other than under the pad. The striped GND wiring 3h extends in the same direction as the striped power wiring 3f. Further, wiring such as other power wiring 3f, output buffer output wiring 3g, other GND wiring 3h, and logic circuit 11 (or level shifter) is arranged around the striped power wiring 3f and GND wiring 3h. Yes. As shown in FIG. 3, the other power supply wiring 3f in the region other than under the pad is electrically connected via the power supply wiring 5b in the fifth wiring layer 5 and the plurality of power supply vias 3b in the third via 3a layer. Similarly, the GND wiring 3h other than the region under the pad is connected to the GND wiring 5d of the fifth wiring layer 5 shown in FIG. 5 and the plurality of GND vias 3d of the third via 3a shown in FIG. Are electrically connected.

  Since the power supply wiring 3f in the region under the pad is formed in a stripe shape, the stress applied to the power supply wiring 3f under the pad can be dispersed when a load is applied to the bonding pad 5e in the probe inspection. , Stress concentration can be reduced and load resistance can be increased.

  Further, since the GND wiring 3h in a region other than under the pad is formed in a stripe shape, it is possible to mitigate stable operation impediment factors such as a voltage drop.

  As an example, the striped power supply wiring 3f and the GND wiring 3h in the third wiring layer 3 have a line (L) / space (S) of 0.24 μm / 0.24 μm. In other words, by reducing the width of the line (wiring) to 0.24 μm, it is possible to reduce the bending due to the wiring (aluminum), and by reducing the width of the space to 0.24 μm, the wiring used for GND The occupation ratio can be increased to improve the ESD (Electro Static Discharge).

  Next, the wiring of the upper second via layer shown in FIGS. 8 and 3 will be described. The AA cross section in FIG. 8 corresponds to the layer of the upper second via 2a in FIG. 2, and the BB cross section in FIG. 8 corresponds to the layer of the upper second via 2a in FIG. Yes.

  As shown in FIGS. 8 and 3, a plurality of upper second vias 2a are arranged in the upper second via layer. That is, a plurality of upper sides that electrically connect the stripe-shaped power supply wiring 3 f arranged in the region below the pad in the third wiring layer 3 and the power supply wiring 2 f of the second metal wiring 2 e of the second wiring layer 2. A power supply via 2b is provided, and further, a plurality of upper output buffer output vias 2c for electrically connecting the output buffer output wiring 3g of the third wiring layer 3 and the output buffer output wiring 2g of the second wiring layer 2 are provided. ing. In addition, a plurality of upper GND vias that electrically connect another power supply wiring 3f in a region other than under the pad of the third wiring layer 3 and another power supply wiring 2f in a region other than under the pad of the second wiring layer 2 2d is provided.

  Also, in the upper second via layer, as shown in FIG. 8, wirings such as a plurality of upper GND vias 2d and logic circuits 11 (or level shifters) are also arranged in regions other than under the pads.

  Next, the wiring of the second wiring layer 2 shown in FIG. 9 will be described. The AA section in FIG. 9 corresponds to the second wiring layer 2 in FIG. 2, and the BB section in FIG. 9 corresponds to the second metal wiring 2e in FIG.

  As shown in FIG. 9, in the second wiring layer 2, a plurality of stripe-shaped power supply wirings 2f are formed in a grid pattern in a region under the pad. The line (L) / space (S) here is, for example, 1.68 μm / 0.72 μm, and the wiring is thickened to the limit at which cracks do not occur to increase the ESD. That is, the width of the second metal wiring 2e is thicker than the width of the third metal wiring 3e (line (L): 0.24 μm), thereby increasing the occupancy of the line (wiring) and increasing ESD. .

  In the second wiring layer 2, a plurality of stripe-shaped GND wirings 2h are also formed in a grid pattern in a region other than under the pad. The line (L) / space (S) here is also the same as in the case of the power supply wiring 2f. For example, the line (L) / space (S) is 1.68 μm / 0.72 μm. ) Can be increased to increase ESD.

  Around the grid-like power supply wiring 2f and GND wiring 2h, wiring such as other power supply wiring 2f, output buffer output wiring 2g, other GND wiring 2h, and logic circuit 11 (or a level shifter) is arranged. Yes.

  Next, the wiring of the lower second via layer shown in FIGS. 10, 2 and 3 will be described. 10 corresponds to the layer of the second lower via 2i on the lower side in FIG. 2, and the section BB in FIG. 10 corresponds to the layer of the second lower via 2i in FIG. is doing.

  As shown in FIG. 10, a plurality of lower second vias 2i are arranged in the lower second via layer. That is, a plurality of lower power supply vias 2j, a lower output buffer output via 2k, and a lower GND via 2m are arranged. Further, wiring such as a logic circuit 11 (or a level shifter) is also arranged in the lower second via layer.

  Next, the wiring of the first wiring layer 1 shown in FIGS. 11, 2, and 3 will be described. 11 corresponds to the layer of the first metal wiring 1e in FIG. 2, and the section BB in FIG. 11 corresponds to the layer of the first metal wiring 1e in FIG. Yes. As shown in FIG. 11, the first wiring layer 1 is provided with a power supply wiring 1f, an output buffer output wiring 1g, an output buffer input wiring 1h, and a GND wiring 1i.

  The first metal wiring 1e of the first wiring layer 1 is arranged so as to extend in a direction intersecting with the second metal wiring 2e and the third metal wiring 3e, and each wiring extends in a stripe shape in the region under the pad. Are arranged. Further, the output buffer input wiring 1h is arranged in a ring shape so as to surround the output buffer output wiring 1g, the power supply wiring 1f, and the GND wiring 1i. That is, the output buffer output wiring 1g, the power supply wiring 1f, and the GND wiring 1i are formed in a stripe shape inside the ring-shaped output buffer input wiring 1h.

  The first wiring layer 1 is also provided with wiring such as a logic circuit 11 (or a level shifter).

  Next, the wiring of the first via 1a shown in FIGS. 12, 2, and 3 will be described. The AA cross section in FIG. 12 corresponds to the first via 1a layer in FIG. 2, and the BB cross section in FIG. 12 corresponds to the first via 1a layer in FIG.

  As shown in FIG. 12, a plurality of power supply vias 1b, output buffer output vias 1c, output buffer input vias 1j, and GND vias 1d are arranged in the first via 1a layer.

  Here, as shown in FIG. 2, the plurality of power supply vias 1 b electrically connect the power supply wiring 1 f of the first wiring layer 1 and the active region 9 b (source electrode) of the main surface 9 a of the semiconductor substrate 9. Also, as shown in FIG. 3, the plurality of output buffer output vias 1c electrically connect the output buffer output wiring 1g of the first wiring layer 1 and the active region 9b (drain electrode) of the main surface 9a of the semiconductor substrate 9. Connected.

  Note that wiring such as a logic circuit 11 (or a level shifter) is also arranged in the layer of the first via 1a.

  Next, the wiring of the active layer in the region under the pad of the main surface 9a of the semiconductor substrate 9 shown in FIGS. 13 and 2 will be described. The AA cross section in FIG. 13 corresponds to the active layer (polysilicon layer 9d) in FIG. 2, and the BB cross section in FIG. 13 corresponds to the active layer in FIG.

  As shown in FIGS. 2 and 13, the polysilicon layer 9d (active layer) in the region under the pad on the main surface 9a of the semiconductor substrate 9 has an active region 9b of the source electrode and an active region 9b of the drain electrode. It is formed on both sides of a polysilicon electrode 9e which is a gate electrode on the gate oxide film 9c. That is, as shown in FIG. 13, in the active region 9b, a P-channel source electrode 9g and a P-channel drain electrode 9h are formed on both sides of a polysilicon electrode 9e that is a gate electrode (one side of the polysilicon electrode 9e). A P channel source electrode 9g is formed on the other side, and a P channel drain electrode 9h is formed on the other side).

  Therefore, an active element (transistor element 9f shown in FIG. 4) is formed under the bonding pad 5e.

  Further, as shown in FIG. 13, in the region other than under the pad on the main surface 9a of the semiconductor substrate 9, an N channel source electrode 9i and an N channel are formed on both sides of the polysilicon electrode 9e as the gate electrode in the active region 9b. A drain electrode 9j is formed (an N channel source electrode 9i is formed on one side of the polysilicon electrode 9e, and an N channel drain electrode 9j is formed on the other side).

  Next, FIG. 14 shows a pad arrangement of a plurality of bonding pads 5e on the main surface 10a of the semiconductor chip (semiconductor device) 10, and a plurality of bonding pads 5e are arranged in a staggered manner. Furthermore, the power supply wiring 5b or the GND wiring 5d is arranged on both sides of each bonding pad 5e, whereby the power supply / GND can be reinforced.

  Next, the buffer film 7 which is the first insulating film immediately below the bonding pad 5e in the semiconductor chip (semiconductor device) 10 of the first embodiment will be described. In the semiconductor chip 10, at least the buffer film 7 directly under the pad is formed of glass having a low Young's modulus. An example of a glass having a low Young's modulus is undoped silicate glass (USG), and its Young's modulus is, for example, 72 GPa. However, it goes without saying that USG may also be used for the insulating film in regions other than under the pad.

  Further, in the semiconductor chip 10, the thickness of the buffer film 7 immediately below the bonding pad 5 e is thicker than the thickness of the second insulating film disposed between the wiring layers at a position below the buffer film 7. For example, as shown in FIG. 3, the thickness (T2) of the buffer film 7 under the pad (the insulating film of the layer of the third via 3a) is set so that the lower second via 2i layer and the upper second It is thicker than the thickness (T1) of the interlayer insulating film (second insulating film) 8 such as the layer of the two vias 2a (T1 <T2).

  Here, it is said that the glass is broken by the tensile stress, and the tensile stress is maximized on the lower surface when the glass layer is bent.

  Therefore, in the semiconductor chip 10 according to the first embodiment, the glass (buffer film 7) immediately below the bonding pad 5e is thickened (T2> T1), whereby the tensile stress on the lower surface is reduced. Use the effect. In other words, the metal (wiring) is not formed on the buffer film 7 under the pad, and only the glass (insulating film) is formed. Since the rate is low (the Young's modulus of tungsten is, for example, 406.9 GPa), the tensile stress on the lower surface can be reduced to reduce or prevent the formation of cracks in the buffer film 7 during probe inspection.

  In addition, since each via electrically connecting the metal wirings of each wiring layer in the thickness direction of the semiconductor substrate 9 is made of tungsten, the Young's modulus of tungsten is high and the load resistance is high as described above. It is possible to prevent the wiring at the terminal from being poorly connected.

  The metal wiring in each wiring layer including the bonding pad 5e is made of a metal wiring mainly composed of aluminum. Thereby, miniaturization of wiring can be achieved. The metal wiring may be, for example, copper or copper alloy wiring.

  According to the semiconductor device (semiconductor chip 10) of the first embodiment, in the semiconductor chip 10 in which the active element (transistor element 9f or the like) is arranged in the region under the pad, the buffer film 7 made of an insulating film directly under the pad is formed. Since the wiring is not formed, when the test is performed by applying a probe to the bonding pad 5e in the wafer test process of the semiconductor chip 10, the buffer film 7 which is an insulating film (oxide film) immediately below the bonding pad 5e is formed. A wafer test can be performed without breaking.

  Thereby, the reliability of the semiconductor chip 10 can be improved.

  In the semiconductor chip 10 of the first embodiment, as an example of the probe condition, 4.7 gf × single 15 times of probe inspection can be OK.

  Further, since an active element such as the transistor element 9f can be disposed under the bonding pad 5e, the semiconductor chip 10 can be reduced in size.

  Furthermore, since the semiconductor chip 10 can be reduced in size, the cost of the semiconductor chip 10 can be reduced.

  Next, a modification of the first embodiment will be described.

  FIG. 15 is a transparent plan view showing the structure of the wiring of each layer as viewed from above in the modification of the first embodiment of the present invention, and FIG. 16 is a portion showing an example of the structure cut along the line AA in FIG. FIG. 17 is a partial sectional view showing an example of a structure cut along the line BB in FIG.

  15 to 17, column vias 9n that are electrically connected to the bonding pad 5e at four locations (four corners) of the bonding pad 5e and have a column structure are arranged. A column structure is constructed on the polysilicon base electrode 9m in the same layer as the polysilicon electrode 9e (transistor element 9f) used for the active layer disposed on the insulating layer 9k on the surface of the semiconductor substrate 9. That is, the polysilicon base is electrically connected to the four corners of the outer peripheral portion of the bonding pad 5e shown in FIG. 15, and is the same layer as the polysilicon electrode 9e on the surface of the semiconductor substrate 9 shown in FIGS. Four post vias 9n electrically connected to the electrode 9m are provided.

  As shown in FIGS. 16 and 17, the support vias 9n are electrically connected to the first metal wiring 1e, the second metal wiring 2e, and the third metal wiring 3e through the connection pads 12 in the respective wiring layers. Has been.

  By providing the support via 9n, the strength of the buffer film 7 under the pad for the probe inspection can be further increased.

(Embodiment 2)
18 is a partial cross-sectional view showing an example of the pad and under-pad structure of the semiconductor device according to the second embodiment of the present invention, and FIG. 19 is a plan view showing an example of the structure of the fourth metal wiring layer in the structure of FIG. 20 is a plan view showing an example of the structure of the contact via layer having the structure of FIG. 18, FIG. 21 is a plan view showing an example of the structure of the third metal wiring layer having the structure of FIG. 18, and FIG. FIG. 23 is a plan view showing an example of the structure of the first metal wiring layer having the structure of FIG. 18.

  The second embodiment shows a structure under the pad of the semiconductor chip (semiconductor device) 13 in the case where the first embodiment has five wiring layers, whereas the fourth wiring layer has four wiring layers. .

  As shown in FIGS. 18 and 19, a bonding pad which is a part of the fourth metal wiring 4a is formed on the uppermost layer (fourth wiring layer 4) among the four wiring layers formed on the semiconductor substrate 9. 4b is formed. As shown in FIG. 18, the outer periphery of the bonding pad 4 b is covered and protected by the protective film 6, but the central part is exposed by the opening 6 a of the protective film 6 and serves as a connection terminal. .

  Further, in the interlayer insulating film 8 immediately below the bonding pad 4b, a plurality of output buffer output vias 3c electrically connected to the bonding pad 4b are arranged in a stripe shape as shown in FIG. The stripe-shaped output buffer output via 3c extends in a direction intersecting with the sliding direction R of the probe. The output buffer output via 3c is made of tungsten, for example.

  As described above, in the semiconductor chip 13 according to the second embodiment, the output buffer output via 3c, which is a plurality of vias, is disposed in the interlayer insulating film 8 immediately below the bonding pad 4b.

  Further, below the plurality of output buffer output vias 3c, an output buffer output wiring 3g which is the third metal wiring 3e shown in FIG. 21 of the third wiring layer 3 electrically connected to these output buffer output vias 3c. Is arranged.

  Further, below the output buffer output wiring 3g of the third wiring layer 3, the second metal wiring 2e shown in FIG. 22 of the second wiring layer 2 with the output buffer output wiring 3g and the interlayer insulating film 8 interposed therebetween. A power supply wiring 2f is provided. A plurality of power supply wirings 2 f are arranged in a stripe shape, and extend in a direction intersecting with the probe sliding direction R, like the output buffer output via 3 c of the third wiring layer 3.

  The striped power supply wiring 2f of the second wiring layer 2 has a line (L) / space (S) of 0.32 μm / 0.26 μm as an example.

  Further, under the power supply wiring 2f of the second wiring layer 2, the power supply wiring 1f shown in FIG. 23, which is the first metal wiring 1e of the first wiring layer 1, with the power supply wiring 2f and the interlayer insulating film 8 interposed therebetween, The output buffer output wiring 1g and the output buffer input wiring 1h are provided in stripes. The striped power supply wiring 1f, the output buffer output wiring 1g, and the output buffer input wiring 1h extend in a direction along the sliding direction R of the probe.

  Note that the line (L) / space (S) of the wiring portion including the stripe-shaped power supply wiring 1 f, the output buffer output wiring 1 g, and the output buffer input wiring 1 h of the first wiring layer 1 is, for example, 2. It is 3 μm or less / 1.05 μm or more.

  That is, under the bonding pad 4b, the striped wiring portions including the lowermost power supply wiring 1f, the output buffer output wiring 1g, and the output buffer input wiring 1h, which are arranged at positions overlapping the bonding pad 4b in plan view, The width of the wiring is 2.3 μm or less, and each wiring is provided at an interval of 1.05 μm or more.

  As shown in FIG. 18, in the active layer of the main surface 9a of the semiconductor substrate 9, a plurality of polysilicon electrodes 9e, which are gate electrodes formed on the gate oxide film 9c, are formed. That is, a plurality of polysilicon electrodes 9e serving as active elements such as transistors are formed at a position below the bonding pad 4b and at a position overlapping the bonding pad 4b in plan view, for example, as in the first embodiment. ing.

  The fourth metal wiring 4 a including the bonding pad 4 b of the fourth wiring layer 4, the third metal wiring 3 e of the third wiring layer 3, the second metal wiring 2 e of the second wiring layer 2, and the first wiring layer 1 of the first wiring layer 1. The one metal wiring 1e is made of, for example, aluminum.

  In the structure under the pad of the semiconductor chip (semiconductor device) 13 of the second embodiment, the power supply layer is reduced to one (power supply wiring 2f of the second wiring layer 2) and the first wiring layer 1 at the lowest layer is reduced. The line (L) / space (S) of the wiring (power supply wiring 1f, output buffer output wiring 1g and output buffer input wiring 1h) is, for example, 2.3 μm or less / 1.05 μm or more, and the maximum value of the width and interval of the wiring By defining the above, the rigidity of the Q portion shown in FIG. 18 can be reduced.

  Therefore, when considering the stress applied to the P portion (interlayer insulating film 8) of FIG. 18 with respect to the probe load from above (on the bonding pad 4b), the stress applied to the P portion is also small because the rigidity of the Q portion is small. It can be made small, and the load resistance against the probe load can be enhanced.

  As described above, also in the semiconductor device (semiconductor chip 13) of the second embodiment, since the load resistance against the probe load of the interlayer insulating film 8 immediately below the pad can be improved, the bonding pad is used in the wafer test process of the semiconductor chip 13. When the probe is applied to 4b and the test is performed, the wafer test can be performed without breaking the interlayer insulating film 8 which is an insulating film (oxide film) immediately below the bonding pad 4b.

  Thereby, the reliability of the semiconductor chip 13 can be improved.

  In the semiconductor chip 13 according to the second embodiment, as an example of the probe condition, 12 gf × single 17 times of probe inspection can be accepted.

  Since the other structure of the semiconductor chip (semiconductor device) 13 of the second embodiment is the same as that of the semiconductor chip 10 of the first embodiment, a duplicate description thereof is omitted.

  Furthermore, since other effects obtained by the semiconductor chip 13 of the second embodiment are the same as the effects obtained by the semiconductor chip 10 of the first embodiment, the duplicate description thereof is omitted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the first and second embodiments, the case of the transistor element has been described as an example of the active element provided in the active layer under the pad. However, the active element is a resistor element, a diode element, or the like other than the transistor element. There may be.

  The present invention is suitable for a semiconductor device having a bonding pad in which an active element is disposed in a lower layer.

DESCRIPTION OF SYMBOLS 1 1st wiring layer 1a 1st via 1b Power supply via 1c Output buffer output via 1d GND via 1e 1st metal wiring 1f Power supply wiring 1g Output buffer output wiring 1h Output buffer input wiring 1i GND wiring 1j Output buffer input via 2 Second wiring Layer 2a Upper second via 2b Upper power supply via 2c Upper output buffer output via 2d Upper GND via 2e Second metal wiring 2f Power wiring 2g Output buffer output wiring 2h GND wiring 2i Lower second via 2j Lower power via 2k Lower Output buffer output via 2m Lower GND via 3 Third wiring layer 3a Third via 3b Power supply via 3c Output buffer output via 3d GND via 3e Third metal wiring 3f Power supply wiring 3g Output buffer output wiring 3h GND wiring 4 Fourth wiring layer 4a 4th metal wiring 4b Bonding pad 5 fifth wiring layer 5a fifth metal wiring 5b power wiring 5c output buffer output wiring 5d GND wiring 5e bonding pads 6 protective film 6a opening 7 buffer film (first insulating film)
8 Interlayer insulation film (second insulation film)
DESCRIPTION OF SYMBOLS 9 Semiconductor substrate 9a Main surface 9b Active region 9c Gate oxide film 9d Polysilicon layer 9e Polysilicon electrode 9f Transistor element (active element)
9g P channel source electrode 9h P channel drain electrode 9i N channel source electrode 9j N channel drain electrode 9k Insulating layer 9m Polysilicon pedestal electrode 9n Post via 10 Semiconductor chip (semiconductor device)
10a main surface 10b core region 10c GND wiring 10d power supply wiring 11 logic circuit 12 connection pad 13 semiconductor chip (semiconductor device)

Claims (15)

A semiconductor substrate;
A plurality of wiring layers formed on the semiconductor substrate;
A plurality of bonding pads formed on the uppermost wiring layer of the plurality of wiring layers, each partially exposed;
An active element formed on the semiconductor substrate and disposed under the bonding pad at a position overlapping the bonding pad in plan view, and further electrically connected to the bonding pad;
Have
A semiconductor device, wherein a first insulating film not provided with any wiring layer of the plurality of wiring layers is formed immediately below the bonding pad.   2. The semiconductor device according to claim 1, wherein the first insulating film is an undoped silicate glass film.   3. The semiconductor device according to claim 2, wherein the bonding pad and the wiring of the wiring layer are made of aluminum.   4. The semiconductor device according to claim 3, wherein the plurality of vias that electrically connect the aluminum wirings in the thickness direction of the semiconductor substrate are made of tungsten.   5. The semiconductor device according to claim 4, wherein the thickness of the first insulating film immediately below the bonding pad is that of the second insulating film disposed between the wiring layers at a position below the first insulating film. A semiconductor device characterized by being thicker than the thickness.   6. The semiconductor device according to claim 5, wherein the plurality of wiring layers are five-layer wiring layers.   7. The semiconductor device according to claim 6, wherein a plurality of stripe-shaped wirings are provided between the lowermost wiring layer and the first insulating film among the plurality of wiring layers and at a position below the bonding pad. A semiconductor device provided.   8. The semiconductor device according to claim 7, further comprising a column via that is electrically connected to an outer peripheral portion of the bonding pad and electrically connected to a polysilicon pedestal electrode on a surface of the semiconductor substrate. A featured semiconductor device.   9. The semiconductor device according to claim 8, wherein the plurality of bonding pads are provided in a staggered arrangement on the outer peripheral portion of the main surface.   10. The semiconductor device according to claim 9, wherein the active element is a transistor. A semiconductor substrate;
A plurality of wiring layers formed on the semiconductor substrate;
A plurality of bonding pads formed on the uppermost wiring layer of the plurality of wiring layers, each partially exposed;
A plurality of vias located under the bonding pad and electrically connecting the uppermost wiring of the plurality of wiring layers and the bonding pad;
An active element formed on the semiconductor substrate and disposed under the bonding pad at a position overlapping the bonding pad in plan view, and further electrically connected to the bonding pad;
Have
Below the bonding pad, the lowermost wiring portion of the plurality of wiring layers arranged at a position overlapping the bonding pad in plan view has a predetermined width and is arranged at a predetermined interval. A semiconductor device comprising a plurality of wirings.   12. The semiconductor device according to claim 11, wherein the first insulating film immediately below the bonding pad is an undoped silicate glass film.   13. The semiconductor device according to claim 12, wherein the bonding pad and the wiring of the wiring layer are made of aluminum.   14. The semiconductor device according to claim 13, wherein the plurality of vias that electrically connect the aluminum wirings in the thickness direction of the semiconductor substrate are made of tungsten.   15. The semiconductor device according to claim 14, wherein the lowermost wiring portion of the plurality of wiring layers has a width of 2.3 μm or less and a plurality of the wirings provided at intervals of 1.05 μm or more. A semiconductor device characterized by being configured.

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