JP2012023225A - Semiconductor device, design method and design device for semiconductor device, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a resist pattern for forming a dummy gate pattern from collapsing.SOLUTION: A dummy gate pattern 220 comprises a plurality of first dummy gate electrodes 222 and a second dummy gate electrode 224. The first dummy gate electrodes 222 face in the same direction as a gate electrode 112. The second dummy gate electrode 224 faces in a direction different from the direction in which the first dummy gate electrodes 222 face, for example a direction perpendicular to the first dummy gate electrodes 222, and connects a first dummy gate electrode 222 to another first dummy gate electrode 222. In an embodiment, every first dummy gate electrode 222 is connected to another first dummy gate electrode 222 by the second dummy gate electrode 224.

Description

  The present invention relates to a semiconductor device having a dummy gate pattern, a semiconductor device design method, a semiconductor device design apparatus, and a program.

  As one of semiconductor device design methods, there is a standard cell method as described in Patent Document 1, for example. The standard cell method is a method for designing a semiconductor device using a logic basic cell and a fill cell. The logic basic cell is a circuit pattern of logic parts such as a 2-input NAND circuit, an inverter circuit, and a flip-flop circuit, and the fill cell is a pattern for filling a gap between the logic parts. The fill cell is provided with a dummy gate pattern. Patent Document 1 describes a plurality of patterns extending parallel to each other as dummy gate patterns.

Japanese Patent Laid-Open No. 2004-288685

  In recent years, since the miniaturization of the semiconductor device has progressed, the width of the dummy gate pattern is also narrowed. On the other hand, when forming a resist pattern corresponding to the dummy gate pattern, the width of the resist pattern may be narrower than the design width due to the optical proximity effect. In such a case, the resist pattern corresponding to the dummy gate pattern may fall down and cause a defect in the semiconductor device.

According to the present invention, a first gate electrode and a second gate electrode that are arranged side by side and face the same direction;
A dummy gate pattern located between the first gate electrode and the second gate electrode;
With
The dummy gate pattern is
A plurality of first dummy gate electrodes facing the same direction as the first gate electrode;
A second dummy gate electrode that faces a different direction from the first dummy gate electrode and connects the first dummy gate electrode to the other first dummy gate electrode;
A semiconductor device is provided.

  According to the present invention, the first dummy gate electrode is connected to the other first dummy gate electrode by the second dummy gate electrode. For this reason, the resist pattern for forming the dummy gate pattern also has a pattern corresponding to the first dummy gate electrode and the second dummy gate electrode. Therefore, the resist pattern is suppressed from falling.

According to the present invention, a step of arranging a plurality of logic basic cells each having a gate electrode of a transistor in the same direction;
Disposing a fill cell having a dummy gate pattern between the logic basic cells;
With
The dummy gate pattern is
A plurality of first dummy gate electrodes facing the same direction as the gate electrode;
A second dummy gate electrode that faces a different direction from the first dummy gate electrode and connects the first dummy gate electrode to the other first dummy gate electrode;
A method of designing a semiconductor device is provided.

According to the present invention, a cell data storage unit that stores logic basic cell data that is design data of a circuit pattern of a logic component, and fill cell data that is design data of a fill cell having a dummy gate pattern;
A design processing unit for generating design data of a semiconductor device by combining the logic basic cell data and the fill cell data;
With
The dummy gate pattern is
A plurality of first dummy gate electrodes facing in the same direction;
A second dummy gate electrode that faces a different direction from the first dummy gate electrode and connects the first dummy gate electrode to the other first dummy gate electrode;
An apparatus for designing a semiconductor device is provided.

According to the present invention, there is provided a program for causing a computer to function as a semiconductor device design apparatus,
In the computer,
A function of storing logic basic cell data, which is design data of a circuit pattern of a logic component, and fill cell data, which is design data of a fill cell having a dummy gate pattern;
A function of generating design data of a semiconductor device by combining the logic basic cell data and the fill cell data;
Realized,
The dummy gate pattern is
A plurality of first dummy gate electrodes facing in the same direction;
A second dummy gate electrode that faces a different direction from the first dummy gate electrode and connects the first dummy gate electrode to the other first dummy gate electrode;
A program is provided.

  According to the present invention, it is possible to prevent the resist pattern for forming the dummy gate pattern from falling.

1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. FIG. 2 is a block diagram illustrating a functional configuration of a design apparatus used for designing the semiconductor device illustrated in FIG. 1. It is a top view explaining the manufacturing method of the semiconductor device shown in FIG. It is a top view explaining the manufacturing method of the semiconductor device shown in FIG. It is a top view explaining the manufacturing method of the semiconductor device shown in FIG. It is a top view which shows the structure of the semiconductor device which concerns on 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a plan view showing the configuration of the semiconductor device according to the first embodiment. This semiconductor device includes a plurality of gate electrodes 112 (first and second gate electrodes) and a dummy gate pattern 220. The plurality of gate electrodes 112 are arranged side by side and face the same direction. The dummy gate pattern 220 is located between the first gate electrode and the second gate electrode. The dummy gate pattern 220 includes a plurality of first dummy gate electrodes 222 and a second dummy gate electrode 224. The first dummy gate electrode 222 faces the same direction as the gate electrode 112. The second dummy gate electrode 224 is oriented in a different direction from the first dummy gate electrode 222, for example, a direction orthogonal thereto, and connects the first dummy gate electrode 222 to the other first dummy gate electrode 222. ing. In the present embodiment, all the first dummy gate electrodes 222 are connected to the other first dummy gate electrodes 222 by the second dummy gate electrodes 224. The gate electrode 112 and the dummy gate pattern 220 are made of, for example, polysilicon. Details will be described below.

  The semiconductor device according to this embodiment is designed using a standard cell system. Specifically, this semiconductor device has a portion in which a fill cell 200 is disposed between a plurality of logic basic cells 100. In this semiconductor device design process, first, a plurality of logic basic cells 100 are arranged, and then a fill cell 200 is arranged between the plurality of logic basic cells 100.

  The logic basic cell 100 is a circuit pattern of logic components such as a 2-input NAND circuit, an inverter circuit, and a flip-flop circuit, and includes a transistor 110 and wirings 230 and 232. The transistor 110 has a gate electrode 112 and source / drain regions 114. The wirings 230 and 232 are wirings constituting the first wiring layer. The wiring 230 extends in a direction perpendicular to the gate electrode 112. The wiring 232 branches from the wiring 230 in a direction parallel to the gate electrode 112 and is connected to the source / drain region 114 of the transistor via a contact (not shown).

  The fill cell 200 has a dummy gate pattern 220. The dummy gate pattern 220 may be located on the element isolation film. The first dummy gate electrode 222 of the dummy gate pattern 220 has the same shape as the gate electrode 112. When viewed in the extending direction of the gate electrode 112, both ends of the first dummy gate electrode 222 are at the same position as both ends of the gate electrode 112. That is, both ends of the plurality of first dummy gate electrodes 222 are aligned.

  The second dummy gate electrode 224 connects the ends of the two first dummy gate electrodes 222 adjacent to each other. The width of the second dummy gate electrode 224 is wider than the width of the first dummy gate electrode 222. Note that the widths of the first dummy gate electrode 222 and the gate electrode 112 are the minimum wiring width in the layer in which the gate electrode 112 is formed, for example, 70 nm or less.

  FIG. 2 is a block diagram showing a functional configuration of a design apparatus used for designing the semiconductor device shown in FIG. This design apparatus includes a cell data storage unit 410, an input unit 420, a design processing unit 430, and a design data storage unit 440. The cell data storage unit 410 stores design data for various logic basic cells 100 and design data for the fill cells 200. The input unit 420 receives circuit data necessary for designing a semiconductor device. The design processing unit 430 generates design data for the semiconductor device by combining the design data stored in the cell data storage unit 410 based on the data input from the input unit 420. The design data storage unit 440 stores design data generated by the design processing unit 430.

  Each component of the design apparatus shown in FIG. 2 is not a hardware unit configuration but a functional unit block. Each component of the design apparatus includes a CPU, a memory of an arbitrary computer, a program that realizes the components of this figure loaded in the memory, a storage unit such as a hard disk that stores the program, and a network connection interface. It is realized by any combination of software and software. There are various modifications of the implementation method and apparatus.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described using the plan views of FIGS. First, as shown in FIG. 3, an element isolation film 20 is formed on a semiconductor substrate 10 such as a silicon substrate. The element isolation film 20 isolates a region where the transistor 110 is formed from other regions. Then, a gate insulating film (not shown) is formed in a region where the transistor 110 is formed in the semiconductor substrate 10.

  Next, as shown in FIG. 4, a conductive film 30 to be a gate electrode, for example, a polysilicon film is formed on the gate insulating film and the element isolation film 20. Next, a resist film is formed on the conductive film 30, and this resist film is exposed and developed. As a result, resist patterns 310 and 320 are formed on the conductive film 30. The resist pattern 310 has a planar shape similar to that of the gate electrode 112, and the resist pattern 320 has a planar shape similar to that of the dummy gate pattern 220. Specifically, the resist pattern 320 has a pattern 322 corresponding to the first dummy gate electrode 222 and a pattern 324 corresponding to the second dummy gate electrode 224. For this reason, the resist pattern 320 is difficult to fall down.

  Next, as shown in FIG. 5, the conductive film 30 is etched using the resist patterns 310 and 320 as a mask. As a result, the conductive film 30 is selectively removed, and the gate electrode 112 and the dummy gate pattern 220 are formed.

  Thereafter, source / drain regions 114 are formed. At this time, extension regions and sidewalls may be formed as necessary. Next, interlayer insulating films, vias, and wirings 230 and 232 are formed.

  Next, the effect of this embodiment will be described. According to this embodiment, the first dummy gate electrode 222 is connected to the other first dummy gate electrode 222 by the second dummy gate electrode 224. Therefore, the resist pattern 320 for forming the dummy gate pattern 220 also has patterns 322 and 324 corresponding to the first dummy gate electrode and the second dummy gate electrode. Therefore, the resist pattern 320 can be prevented from falling.

  Further, the second dummy gate electrode 224 is wider than the width of the first dummy gate electrode 222. For this reason, since the width of the pattern 324 is also widened, the resist pattern 320 can be further prevented from falling.

(Second Embodiment)
FIG. 6 is a plan view showing the configuration of the semiconductor device according to the second embodiment. The semiconductor device according to the present embodiment is the same as the semiconductor device according to the first embodiment except that the second dummy gate electrode 224 connects the centers of the two first dummy gate electrodes 222 adjacent to each other. The configuration is the same as that of the apparatus.
Also according to this embodiment, the same effect as that of the first embodiment can be obtained.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 20 Element isolation film 30 Conductive film 100 Logic basic cell 110 Transistor 112 Gate electrode 114 Source / drain region 200 Fill cell 220 Dummy gate pattern 222 Dummy gate electrode 224 Dummy gate electrode 230 Wiring 232 Wiring 310 Resist pattern 320 Resist pattern 322 Pattern 324 Pattern 410 Cell data storage unit 420 Input unit 430 Design processing unit 440 Design data storage unit

Claims (8)

A first gate electrode and a second gate electrode, arranged side by side and facing in the same direction;
A dummy gate pattern located between the first gate electrode and the second gate electrode;
With
The dummy gate pattern is
A plurality of first dummy gate electrodes facing the same direction as the first gate electrode;
A second dummy gate electrode that faces a different direction from the first dummy gate electrode and connects the first dummy gate electrode to the other first dummy gate electrode;
A semiconductor device comprising: The semiconductor device according to claim 1,
The width of the second dummy gate electrode is a semiconductor device wider than the width of the first dummy gate electrode. The semiconductor device according to claim 1 or 2,
When viewed in the direction in which the first dummy gate electrode extends, the plurality of first dummy gate electrodes have ends aligned with each other,
The second dummy gate electrode is a semiconductor device that connects the end portions of two adjacent first dummy gate electrodes. The semiconductor device according to claim 1 or 2,
When viewed in the direction in which the first dummy gate electrode extends, the plurality of first dummy gate electrodes have ends aligned with each other,
The second dummy gate electrode is a semiconductor device that connects the centers of two adjacent first dummy gate electrodes. Arranging a plurality of logic basic cells having gate electrodes of transistors in the same direction;
Disposing a fill cell having a dummy gate pattern between the logic basic cells;
With
The dummy gate pattern is
A plurality of first dummy gate electrodes facing the same direction as the gate electrode;
A second dummy gate electrode facing in a different direction from the first dummy gate electrode and connecting the first dummy gate electrode to the other first dummy gate electrode;
A method for designing a semiconductor device comprising: The method for designing a semiconductor device according to claim 5,
A method of designing a semiconductor device, wherein the width of the second dummy gate electrode is wider than the width of the first dummy gate electrode. A cell data storage unit for storing logic basic cell data which is design data of a circuit pattern of a logic component and fill cell data which is design data of a fill cell having a dummy gate pattern;
A design processing unit for generating design data of a semiconductor device by combining the logic basic cell data and the fill cell data;
With
The dummy gate pattern is
A plurality of first dummy gate electrodes facing in the same direction;
A second dummy gate electrode that faces a different direction from the first dummy gate electrode and connects the first dummy gate electrode to the other first dummy gate electrode;
A semiconductor device design apparatus comprising: A program for causing a computer to function as a semiconductor device design device,
In the computer,
A function of storing logic basic cell data, which is design data of a circuit pattern of a logic component, and fill cell data, which is design data of a fill cell having a dummy gate pattern;
A function of generating design data of a semiconductor device by combining the logic basic cell data and the fill cell data;
Realized,
The dummy gate pattern is
A plurality of first dummy gate electrodes facing in the same direction;
A second dummy gate electrode that faces a different direction from the first dummy gate electrode and connects the first dummy gate electrode to the other first dummy gate electrode;
A program with

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