JP2012051774A - Compound semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce, in a compound semiconductor substrate using an Si single crystal substrate, the deterioration of mechanical strength and heat conductivity of the compound semiconductor substrate by dopant concentration control of the Si single crystal substrate.SOLUTION: The compound semiconductor substrate includes an intermediate layer and a device active layer on the Si single crystal substrate. The Si single crystal substrate includes, from the surface of one main surface on the intermediate layer side to the depth direction, a region 1 in which the dopant concentration is 1×10atoms/cmor more and 1×10atoms/cmor less, a transition region 1 in which the dopant concentration is continuously reduced, a region 2 in which the dopant concentration is 1×10atoms/cmor more and 5×10atoms/cmor less, a transition region 2 in which the dopant concentration is continuously increased, and a region 3 in which the dopant concentration is 1×10atoms/cmor more and 1×10atoms/cmor less.

Description

The present invention relates to a compound semiconductor substrate used for a compound semiconductor such as a nitride semiconductor having a HEMT (High Electron Mobility Transistor) structure for light emitting diodes, laser light emitting elements, and other various electronic elements.

Compound semiconductors, especially wide bandgap nitride semiconductor devices made of gallium nitride (GaN), aluminum nitride (AlN), etc., are used for light emitting devices with short wavelengths such as blue and ultraviolet, and heterojunction interfaces. High-speed and high-voltage electronic devices for switching power supplies that take advantage of the high electron mobility of the two-dimensional electron gas generated in the material and the high heat resistance of the material itself, and ultra-high-speed electronic devices for high-frequency amplifiers The application of is expected.

As an example, the nitride semiconductor substrate used for the nitride semiconductor can be manufactured by a method of forming a nitride semiconductor crystal as a thin film on a dissimilar substrate such as sapphire, 6H-SiC, Si, etc. Is preferable in that a high-quality crystal can be stably supplied and a large-area substrate can be obtained at a low price compared to other types of substrates. Hereinafter, a nitride semiconductor crystal formed on such a different material substrate is referred to as a compound semiconductor substrate.

By the way, when a nitride semiconductor crystal is formed on a Si substrate, warpage of the substrate due to a difference in thermal expansion coefficient between Si and the nitride semiconductor, cracking of the nitride semiconductor single crystal film, and Si substrate There are problems such as the introduction of slip defects. Various methods have been considered for solving this problem, and several methods for optimally designing the substrate characteristics of the Si substrate have been tried.

  Specifically, it is conceivable to control the concentration of various substances in Si, for example, oxygen concentration, nitrogen concentration, carbon concentration, defect concentration such as oxygen precipitates, and dopant concentration. In particular, when the concentration of various elements such as boron (B), phosphorus (P), and arsenic (As) contained as dopants is increased, the mechanical strength of the Si substrate is improved. It is possible to greatly reduce the frequency of defect introduction.

For example, Patent Document 1 aims to provide a silicon substrate capable of suppressing the curvature of the silicon substrate even when a layer of a semiconductor material having a thermal expansion coefficient larger than that of the silicon substrate is epitaxially grown, and a method for manufacturing the same. A concentration distribution of nitrogen impurities that decreases continuously or stepwise from one main surface or from a predetermined depth in the vicinity of the main surface to the back surface, and a distribution approximately corresponding to the concentration distribution of the nitrogen impurities. There is disclosed a technique of a silicon substrate characterized by having oxygen precipitates.

Further, Patent Document 2 does not relate to the solution of the problems of warpage and cracking and the introduction of slip defects to the Si substrate, but a nitride-based semiconductor element having a forward voltage (Vf) lower than that of the prior art. For the purpose of providing, in a nitride semiconductor device using Si for a substrate, the active region includes at least a part of the Si substrate and a nitride semiconductor layer, and the conductivity type of the active region in the Si substrate is p-type, Alternatively, a technique of a nitride-based semiconductor element in which the impurity concentration of the active region in the Si substrate is 1E + 18 atoms / cm ³ or more and 1E + 22 atoms / cm ³ or less is disclosed.

By the way, about the dopant density | concentration in Si, for example, the nonpatent literature 1 is disclosing that the thermal conductivity of Si will fall, if the dopant density | concentration in Si becomes high.

JP 2008-251704 A WO2006-120908

M.M. Asheghi, et. al. : J. Appl. Phys. , Vol. 91 no. 8 15. April 2002 5079

In the method described in Patent Document 1, a method of controlling the warpage of the compound semiconductor substrate by utilizing the expansion force at the time of generation of oxygen precipitation is disclosed, but this method is performed after the formation of the compound semiconductor layer. Since oxygen precipitates are generated by a predetermined heat treatment and the warpage is controlled, the stress generated during the formation of the compound semiconductor layer is the same as in the prior art. Therefore, no effect is obtained with respect to the introduction of slip defects to the Si substrate that occurs during the formation of the compound semiconductor layer.

Patent Document 2 describes that the impurity concentration of the Si substrate in contact with the interface between the Si substrate and the GaN layer, that is, the dopant concentration is increased for the purpose of providing a nitride-based semiconductor element having a lower forward voltage (Vf) than the conventional one. It is suggested that the impurity concentration of the Si substrate affects the characteristics of the nitride semiconductor. However, it is considered that it is not clear only by the description of Patent Document 2 how the form of the dopant concentration in the Si substrate affects the problems of warpage and cracking, and the frequent occurrence of dislocations and crystal defects. It is done.

In general, when the dopant concentration in Si is increased, mechanical strength is improved, that is, the critical shear stress value is improved, which is effective in suppressing slip generation and warpage. On the other hand, when the dopant concentration is high, as described in Non-Patent Document 1, the thermal conductivity of the Si single crystal is lowered, and the compound semiconductor substrate is used as a nitride semiconductor optical / electronic device. It is not preferable. Since there is a trade-off relationship between mechanical strength and thermal conductivity in high-concentration doping, optimal design is necessary for the dopant concentration and distribution in the depth direction, but sufficient studies have been made so far. It's hard to say.

The present invention has been made in view of these problems, and effectively achieves the prevention of dislocation generation and the reduction of the warpage of the substrate while minimizing the decrease in thermal conductivity to a necessary minimum. A compound semiconductor substrate using a Si single crystal substrate is provided.

The compound semiconductor substrate according to the present invention includes a Si single crystal substrate, an intermediate layer made of a compound semiconductor formed on one main surface of the Si single crystal substrate, and a device activity made of a compound semiconductor formed on the intermediate layer. The Si single crystal substrate has an average dopant concentration of 1 × 10 ¹⁹ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ^{3 in the} thickness direction from the surface of one main surface on the intermediate layer side. The following region 1, the transition region 1 formed following the region 1 where the dopant concentration continuously decreases, and the average dopant concentration formed following the transition region 1 is 1 × 10 ¹² atoms / cm ³ or more and 5 × ¹⁰ 17 atoms / cm ³ regions 2 or less, a transition region 2 in which the dopant concentration is subsequently formed on the region 2 increases continuously, connection to the transition region 2 And region 3 average dopant concentration is formed to the surface of the other main surface is 1 × ¹⁰ 21 atoms / cm ³ or less 1 × ¹⁰ 19 atoms / cm ³ or more of the Si single crystal substrate Te are sequentially formed, further wherein The thickness of each of the region 1 and the region 3 is in the range of 15% to 35% with respect to the total thickness of the Si single crystal substrate. By adopting such a configuration, it is possible to obtain a compound semiconductor substrate that efficiently combines the effects of preventing the occurrence of dislocation such as slip in the substrate, reducing the warpage of the substrate, and suppressing the decrease in thermal conductivity of the substrate.

The dopant in the compound semiconductor substrate according to the present invention is boron (B), phosphorus (P), antimony (Sb), arsenic (As), aluminum (Al), gallium (Ga), germanium (Ge), More preferably, any one kind or plural kinds. By adopting such a configuration, it is possible to obtain the effects of preventing the occurrence of dislocation such as slip in the substrate, reducing the warpage of the substrate, and suppressing the decrease in the thermal conductivity of the substrate easily and at low cost. Since these elements are substituted into the lattice positions of Si and are dissolved, the mechanical strength of the Si substrate, that is, the critical shear stress can be improved by solid solution strengthening.

In the compound semiconductor substrate according to the present invention, the intermediate layer and the device active layer are preferably made of a nitride semiconductor containing aluminum (Al) and gallium (Ga). By adopting such a configuration, it is possible to realize a semiconductor device utilizing the characteristics of the wide band gap material, and it is possible to exhibit an excellent substrate warpage reduction effect by combining them.

The compound semiconductor substrate according to the present invention has the effects of preventing defects such as slips, reducing the warpage of the substrate, and suppressing the decrease in thermal conductivity in the substrate thickness direction, which are important in the compound semiconductor substrate, with a simple substrate structure. Therefore, it is possible to provide a compound semiconductor substrate that can be realized in a proper and balanced manner and has excellent characteristics.

Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a conceptual diagram showing the structure of a compound semiconductor substrate according to an embodiment of the present invention. FIG. 2 is a conceptual diagram showing the relationship between regions 1 and 2 in the thickness direction of a Si single crystal substrate according to the present invention. FIG. 3 is a conceptual diagram showing another form of the dopant concentration profile in the transition region in the thickness direction of the Si single crystal substrate according to the present invention, and FIG. 4 is a view of each region of the Si single crystal substrate according to the present invention. FIG. 5 is a schematic diagram showing the relationship between the stress and bending moment of the Si single crystal substrate according to the present invention.

The conceptual diagram which shows the structure of the compound semiconductor substrate based on one Embodiment of this invention. The conceptual diagram which shows one form of the transition area | region of the dopant concentration profile in the thickness direction of Si single crystal substrate based on this invention. The conceptual diagram which shows the other form of the dopant concentration profile of the transition area | region in the thickness direction of Si single crystal substrate based on this invention. Schematic which shows the form of each area | region of Si single crystal substrate based on this invention. The formula and conceptual diagram which show the relationship between the stress and bending moment of Si single crystal substrate based on this invention.

A compound semiconductor substrate according to the present invention includes a Si single crystal substrate, an intermediate layer made of a compound semiconductor formed on one main surface of the Si single crystal substrate, and a device made of a compound semiconductor formed on the intermediate layer. The Si single crystal substrate is composed of an active layer, and the Si single crystal substrate has an average dopant concentration of 1 × 10 ¹⁹ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ^{3 in the} thickness direction from the surface of one main surface on the intermediate layer side. A region 1 that is ³ or less, a transition region 1 that is formed following the region 1 and the dopant concentration continuously decreases, and an average dopant concentration that is formed following the transition region 1 is 1 × 10 ¹² atoms / cm ^3. or a 5 × ¹⁰ 17 atoms / cm ³ regions 2 or less, a transition region 2 in which the dopant concentration is subsequently formed on the region 2 increases continuously, the transition region 2 There the average dopant concentration is formed to the surface of the other main surface is 1 × ¹⁰ 19 atoms / cm ³ or more 1 × ¹⁰ 21 atoms / cm ³ region 3 is less than the Si single crystal substrate is sequentially formed, further wherein The thickness of each of the region 1 and the region 3 is in the range of 15% to 35% with respect to the total thickness of the Si single crystal substrate.

The Si single crystal substrate is used as a base for forming a compound semiconductor, but the basic manufacturing method and crystal structure are not particularly limited, and a wide variety of known Si single crystal substrates for manufacturing semiconductor devices can be used. . For example, the CZ method or the FZ method may be used as the Si single crystal growth method, and wafers that have been subjected to various heat treatments as the substrate processing treatment can also be applied. Further, the finished state such as the surface orientation of the substrate, the bevel shape, and the surface roughness of the main surface and the back surface on which the compound semiconductor is formed can be appropriately selected according to the specifications of the compound semiconductor substrate to be designed.

An intermediate layer made of a compound semiconductor formed on one main surface of a Si single crystal substrate is generated due to mismatch between the Si substrate and the compound semiconductor which is a device active layer due to a difference in lattice constant or a difference in thermal expansion coefficient. It works to relieve stress. The structure of the intermediate layer is not particularly limited, but it is preferably a multilayer structure composed of a stack of compound semiconductors having an arbitrary thickness and composition because it can be manufactured relatively easily.

A device active layer made of a compound semiconductor is formed on the intermediate layer. Various materials can be applied as the compound semiconductor, and for example, a nitride semiconductor crystal such as AlGaN is used.

In the Si single crystal substrate, a region in which an average dopant concentration is 1 × 10 ¹⁹ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ³ or less in the thickness direction from the surface of one main surface on the intermediate layer side. 1, a transition region 1 formed following the region 1 where the dopant concentration continuously decreases, and an average dopant concentration formed following the transition region 1 of 1 × 10 ¹² atoms / cm ³ or more 5 × 10 ¹⁷ a region 2 that is atoms / cm ³ or less, a transition region 2 that is formed following the region 2 and in which the dopant concentration continuously increases, and a surface of the other principal surface of the Si single crystal substrate following the transition region 2 The region 3 having an average dopant concentration of 1 × 10 ¹⁹ atoms / cm ^{3 to} 1 × 10 ²¹ atoms / cm ³ is formed sequentially.

In the present invention, the average dopant concentration in the region 1 to the region 3 is, for example, in the case of the region 1, a value obtained by averaging the dopant concentrations at points obtained by arbitrarily dividing a section in the depth direction from the surface of one main surface. It is expressed by The dopant concentration is several points, preferably several tens of points in the depth direction of the Si single crystal substrate, for example, by a measuring method such as a spreading resistance (SR) measurement method or a secondary ion mass spectrometry (SIMS) method. Obtained by measuring above. At the same time, the thickness of each region is also measured, but the thickness can also be measured by another method. The depth direction is synonymous with the thickness direction of the Si single crystal substrate, and refers to a direction from one main surface to a direction substantially perpendicular to the other main surface.

In the present invention, the average value of the dopant concentration only needs to be within the implementation range of the present invention. For example, 20 points are measured in the region 1, and the measured value of the dopant concentration of 1 point is within the concentration range of the region 2. There is no particular problem. As a guide in this case, if 90% or more, more preferably 95% or more of the measurement points are in the range of the region 1, the effect of the present invention can be obtained even if all other measurement points are in the concentration range of the region 2. It does not have a big influence on.

Furthermore, a dopant concentration profile can be obtained by plotting the dopant concentration in the thickness direction, but the shape of the dopant concentration profile in each region from region 1 to region 3 requires a shape that does not necessarily maintain a constant dopant concentration value. For example, a shape in which the dopant concentration value gradually decreases or increases in the depth direction may be used, or a mountain shape in which the dopant concentration value once decreases and then decreases.

Next, each area will be described. In the region 1, the average dopant concentration is 1 × 10 ¹⁹ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ³ or less in the thickness direction from the surface of one main surface on the intermediate layer side.

When a nitride semiconductor crystal is formed on a Si substrate, the substrate is warped due to the difference in thermal expansion coefficient between Si and the nitride semiconductor, the nitride semiconductor single crystal film is cracked, and further to the Si substrate. Problems such as the introduction of slip defects occur. In particular, since the stress increases as the device active layer becomes thicker, it is necessary to increase the dopant concentration of the Si single crystal substrate in order to have a critical shear stress corresponding to this stress.

In the present invention, the average dopant concentration in the region 1 necessary for providing a critical shear stress corresponding to this stress is 1 × 10 ¹⁹ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ³ or less. If the average dopant concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , the necessary critical shear stress cannot be obtained, whereas if it exceeds 1 × 10 ²¹ atoms / cm ³ , the improvement of the critical shear stress is hardly observed. , Both of which are unfavorable because there is concern about segregation and deterioration of crystallinity due to the presence of excessive dopant.

The transition region 1 is formed in the depth direction of the substrate subsequent to the region 1, and the dopant concentration continuously changes. FIG. 2 is a conceptual diagram showing one form of the dopant concentration profile of the transition region 1 formed between the region 1 and the region 2.

FIG. 3 shows another form of the dopant concentration profile in the transition region 1 according to the present invention. In the present invention, as long as the dopant concentration is continuously changed, a so-called step-like form that changes abruptly in a very short depth direction may be used. Further, although not shown, the reduction rate of the dopant concentration per unit depth direction does not need to be constant, and may change gradually after abrupt change, or vice versa.

As will be described later, the thickness of the transition region 1 in the depth direction is affected by the thickness of each of the regions 1, 2, and 3, which contributes to the warpage and thermal conductivity of the compound semiconductor. It is preferable that the thickness is as small as possible. The range of the controllable thickness of the transition region 1 varies depending on the manufacturing method, but in the most general surface thermal diffusion method from the surface layer, bonding of substrates having different impurity concentrations, manufacturing method such as Si epi, It can be said that the thickness of the transition region 1 in the depth direction is preferably in the range of 0.1 μm to 100 μm.

Region 2 is formed following transition region 1 and has an average dopant concentration of 1 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less.

  When the entire depth direction of the Si single crystal substrate is set to the dopant concentration in the region 1, the critical shear stress is improved. However, the Si single crystal substrate having a high dopant concentration has a low thermal conductivity due to an increase in phonon scattering. The thermal resistance in the thickness direction of the compound semiconductor substrate also increases. As a result, when various device structures are fabricated and operated on this compound semiconductor substrate, the device temperature during operation rises and the lifetime and reliability of the device decrease.

  FIG. 5 is an equation and a conceptual diagram showing the relationship between the stress and bending moment of the Si single crystal substrate, which is a model in which the bending of the substrate is simplified. One of the shear stresses is a tensile stress from the neutral line in the cross-sectional thickness direction, and the other is a compressive stress in the opposite direction. Since slip occurs when the critical shear stress is exceeded, if there is a region of dopant concentration having a shear stress higher than that where slip occurs on the surface of the substrate, the vicinity of the center in the thickness direction of the Si single crystal substrate is less than this. Even in the region of the dopant concentration having a small shear stress, the strength of the substrate against the occurrence of slip is not affected.

Therefore, if a high dopant concentration layer and a low dopant concentration layer 2 are present in an appropriate ratio in the depth direction of the Si single crystal substrate, the Si single crystal substrate having an excellent balance between critical shear stress and thermal conductivity can be obtained. It becomes possible to do. In the present invention, an average dopant concentration of 1 × 10 ¹² atoms / cm ³ or more is synonymous with an average dopant concentration of a non-doped Si single crystal substrate that does not substantially contain a dopant.

The transition region 2 is a region that is formed following the region 2 and in which the dopant concentration continuously increases, and has a role of joining and partitioning the region 3 to be formed next. Basically, the transition region 1 has the same structure and function. However, the transition region 1 and the transition region 2 do not necessarily have the same structure, that is, the concentration, shape, and region thickness of the dopant concentration profile. Regarding the dopant concentration, there may be a difference within the scope of the present invention, and the thickness may be about 1 to 3 μm.

The region 3 is formed up to the surface of the other main surface of the Si single crystal substrate following the transition region 2, and has an average dopant concentration of 1 × 10 ¹⁹ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ³ or less. The region 3 is also formed for the purpose of ensuring the mechanical strength of the Si single crystal substrate in conformity with the region 1 in terms of the basic structure and operational effects.

  Furthermore, the present invention is characterized in that the thickness of each of the regions 1 and 3 is in the range of 15% to 35% with respect to the total thickness of the Si single crystal substrate. This is because there is a range in which one of the characteristics is significantly impaired depending on the ratio of the region 1 and the region 3 excellent in critical shear stress and the region 2 having a high thermal conductivity. If the thickness of each of the regions 1 and 3 is less than 15%, the mechanical strength is greater than 35%, and if the thickness exceeds 35%, the decrease in thermal conductivity is significant. A more preferable range is 20% or more and 25% or less. FIG. 4 is a conceptual diagram schematically representing each region and its form.

Note that the regions 1 and 3 do not necessarily have the same thickness as the dopant concentration profile shape. For example, the thicknesses of the regions 1 and 3 are within the scope of the present invention. If it is. In addition, depending on the purpose, forming various layers and films on the back side of the Si single crystal substrate, that is, the side on which the compound semiconductor layer is not formed also has a favorable balance of mechanical strength and thermal conductivity. This is not excluded unless the effects of the present invention are impaired.

In the present invention, various types of elements used as Si single crystal dopants can be used as the type of dopant, but boron (B), phosphorus (P), antimony (Sb), arsenic are used because of the ease of substrate manufacture. It is preferable to apply one or more of (As), aluminum (Al), gallium (Ga), and germanium (Ge). However, considering the influence on the compound semiconductor substrate, it is more preferable to use boron (B) or arsenic (As) alone.

As the compound semiconductor substrate according to the present invention, the intermediate layer and the device active layer include aluminum (Al) and gallium (Ga), specifically represented by the composition Al _x Ga _1-x N (0 ≦ x ≦ 1). More preferably, the nitride semiconductor is used. These are because the compatibility with the Si single crystal substrate is good, and the effects of the invention can be obtained easily and reliably by applying the configuration of the present invention.

The Si single crystal substrate according to the present invention is manufactured by a widely known manufacturing method. For example, an epitaxial method in which a high dopant concentration layer is formed by vapor deposition on a low dopant concentration Si single crystal substrate, a low dopant concentration Si single crystal substrate and a high dopant concentration Si single crystal substrate are prepared. A bonding method for bonding, an ion implantation method, or the like can be applied. However, the thickness of the regions 1 to 3 and the shape of the dopant concentration profile of the transition regions 1 and 2 can be controlled relatively inexpensively and precisely. A so-called diffusion wafer, which is formed and then manufactured by thermally diffusing the dopant to a predetermined depth in a heat treatment apparatus such as a diffusion furnace, is preferably used.

From the above, the compound semiconductor substrate according to the present invention has the effects of preventing the occurrence of defects such as slips that are important in the compound semiconductor substrate, reducing the warpage of the substrate, and suppressing the decrease in thermal conductivity in the substrate thickness direction. The structure can be realized efficiently and in a balanced manner, and a compound semiconductor substrate having excellent characteristics can be provided.

Hereinafter, preferred embodiments of the present invention will be described based on examples, but the present invention is not limited to these examples.

A non-doped Si single crystal substrate manufactured by the CZ method and having a plane orientation (111), a diameter of 4 inches, a thickness of 625 μm was prepared. Then, using boron or arsenic as a dopant, regions 1 and 3 are formed by diffusing the dopant in the depth direction from both sides of the Si single crystal substrate by a thermal diffusion method using a horizontal heat treatment furnace. did. And about the dopant density | concentration and the thickness of each area | region, each sample was produced by the content shown in Table 1. FIG. The region 1 (t _a ) and the region 3 (t _c ) have the same thickness, and the thicknesses of the transition region 1 and the transition region 2 are both in the range of 70 μm to 100 μm.

Next, a nitride semiconductor substrate was fabricated by depositing an intermediate layer made of a nitride semiconductor and a device active layer on each sample by a vapor deposition method. The nitride semiconductor intermediate layer and the device active layer have the structure shown in FIG.

The Si single crystal substrate 1 was set in an MOCVD apparatus, and an AlN single crystal layer 21 having a thickness of 100 nm was formed by vapor phase growth at 1100 ° C. using trimethylaluminum (TMA) and NH ₃ as raw materials. Further thereon, trimethylgallium (TMG), TMA and NH ₃ are used as raw materials, and an Al _0.1 Ga _0.9 N single crystal layer 22 having a thickness of 200 nm is stacked by vapor phase growth at 1000 ° C. These two layers were used as the initial buffer area.

Next, an AlN single crystal layer 23 having a thickness of 5 nm is laminated on the initial buffer region by vapor phase growth at 1000 ° C. using TMA and NH ₃ as raw materials, and then a GaN single crystal having a thickness of 20 nm. Layer 24 was laminated. The AlN single crystal layer 23 and the GaN single crystal layer 24 were alternately repeated in the same process, and the number of stacked layers was set to 50 to form the first multilayer buffer region 25. Furthermore, on the first multilayer buffer region 25, an AlN single crystal layer 26 having a thickness of 5 nm and a GaN single crystal layer 27 having a thickness of 250 nm are alternately stacked repeatedly, and the number of stacks is set to 24. A second multilayer buffer region 28 was formed in the same process as the formation of the first multilayer buffer region 25.

On the second multilayer buffer region 28, TMG and NH ₃ are used as raw materials, and by vapor phase growth at 1000 ° C., a GaN single crystal layer 31 having a thickness of 2000 nm, and subsequently, TMG, TMA as raw materials. The electron supply layer 3 was formed by stacking the Al _0.25 Ga _0.75 N single crystal layer 32 having a thickness of 20 nm by vapor phase growth at 1000 ° C. using NH ₃ and NH ₃ . Note that the thickness of each layer formed by vapor phase growth was adjusted by adjusting the gas flow rate and the supply time. Further, the source, gate, and drain electrodes were formed on the electron supply layer 3 by EB vapor deposition to obtain a HEMT (High Electron Mobility Transistor) device.

Next, the produced nitride semiconductor substrate was evaluated for the occurrence of slip and the thermal conductivity in the substrate thickness direction.

For the presence or absence of slip, the device active layer surface of each sample was inspected under oblique light to confirm whether or not slip occurred visually. The criterion is that if even one slip is confirmed within a visually discriminable range, it is evaluated as “present” and the effect of the present invention was not obtained, and if no slip is confirmed, “no” is determined. It was evaluated that there was an effect.

Evaluation of thermal conductivity is performed by pasting the back surface of the FET element on a heat sink of the same shape, and measuring and comparing the maximum temperature of the element surface with a non-contact thermo viewer when the device is operated under the same conditions. went. Each sample was evaluated as having the effect of the present invention within the range that “the temperature of the element surface was substantially reduced from substantially the same”, and the increased was described as “increase”. It was evaluated that the effects of the invention could not be obtained.

Table 1 shows the production conditions and evaluation results of each sample as described above.

From the results of Table 1, in the implementation range of the present invention, there was no occurrence of slip, and the temperature on the back side of each sample was almost equal or decreased, and the effect of the present invention was obtained. On the other hand, when a part or all of the implementation range of the present invention was deviated, the effect of the present invention was not obtained for at least one of the items of slip or temperature on the back side of each sample. Further, even when the dopant is boron and arsenic, there is no significant difference, and the effect of the present invention was confirmed in the same manner.

  The present invention is a nitride semiconductor substrate having a HEMT (High Electron Mobility Transistor) structure suitably used for a light emitting diode, a laser light emitting element, an electronic element operable at a high speed and a high temperature, and the like. Is preferred.

1 ... Si single crystal substrate, 11 ... region 3, 12 ... region 2, 13 ... region 1, 14 ... transition region 2, 15 ... transition region 1, 2 ... intermediate layer, 21 ... AlN single crystal layer 21, 22 ... Al _0.1 Ga _0.9 N single crystal layer 22, 23 ... AlN single crystal layer, 24 ... GaN single crystal layer, 25 ... first multilayer buffer region, 26 ... AlN single crystal layer, 27 ... GaN single crystal layer, 28 ... second multilayer buffer region, 3 ... device active layer, 31 ... GaN single crystal layer, 32 ... Al _0.25 Ga _0.75 N single crystal layer.

Claims (3)

A Si single crystal substrate; an intermediate layer made of a compound semiconductor formed on one main surface of the Si single crystal substrate; and a device active layer made of a compound semiconductor formed on the intermediate layer. The crystal substrate includes a region 1 having an average dopant concentration of 1 × 10 ¹⁹ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ³ or less from the surface of one principal surface on the intermediate layer side in the thickness direction; Transition region 1 is formed following region 1 and the dopant concentration continuously decreases, and an average dopant concentration formed after the transition region 1 is 1 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ^3. A transition region 2 formed following the region 2 and having a dopant concentration continuously increased; and another main surface of the Si single crystal substrate following the transition region 2. Mean dopant concentration is formed to the surface are sequentially formed and a 1 × ¹⁰ 19 atoms / cm ³ or more 1 × ¹⁰ 21 atoms / cm ³ region 3 or less, further, each thickness of the region 1 and the region 3 Is in the range of 15% to 35% with respect to the total thickness of the Si single crystal substrate.   The dopant is one or more of boron (B), phosphorus (P), antimony (Sb), arsenic (As), aluminum (Al), gallium (Ga), and germanium (Ge). The compound semiconductor substrate according to claim 1. The compound semiconductor substrate according to claim 1, wherein the intermediate layer and the device active layer are made of a nitride semiconductor containing aluminum (Al) and gallium (Ga).