JP2012050234A - Drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit that can set a dead time for each channel of a two-channel signal driving two switching elements connected in series by using a dead time generation circuit and need only one external capacitor in the case of forming into an integrated circuit.SOLUTION: The drive circuit comprises: a delay circuit 2a that adds delay which is shorter than dead time to a signal Va0 using a capacitor 13a; a delay circuit 2b that adds delay which is shorter than the dead time to a signal Vb0 using a capacitor 13b; a dead time generation circuit 3 that generates a dead time generation signal of a period T/2 rising at the timing which is delayed by the dead time from rising edges of the signal Va0 and the signal Vb0 by the use of a capacitor 23; and AND circuits 17a and 17b that generate signals Va7 and Vb7 in which the dead time are set based on the dead time generation signal V6.

Description

  The present invention relates to a drive circuit that alternately drives two switching elements connected in series, such as an H-bridge circuit, and in particular, a drive provided with a dead time for preventing the two switching elements from conducting simultaneously. The present invention relates to a drive circuit that generates a signal.

FIG. 7 is a diagram showing a configuration of a conventional drive circuit.
In the drive circuit 100 that drives a circuit in which two switching elements 4a and 4b are connected in series, referring to FIG. 7A, a dead time that prevents the two switching elements 4a and 4b from conducting simultaneously. In general, dead time generation circuits 110a and 110b are provided for each of the two systems of signals that drive the two switching elements 4a and 4b (see, for example, Patent Document 1).

  The two systems of signals that drive the two switching elements 4a and 4b are a signal X that is a rectangular wave input from the input unit 101 and a signal Y obtained by inverting the signal X by the NOT circuit 102, and the signal X is dead. The signal Y is input to the time generation circuit 110a and the dead time generation circuit 110b. The dead time generation circuit 110a includes a series circuit of a resistor 111a and a capacitor 112a, and a diode 113a is connected in parallel to the resistor 111a in a direction that accelerates discharge of the capacitor 112a, and delays only the rising edge of the input signal X. A drive signal having a dead time is generated. Similarly, the dead time generation circuit 110b includes a series circuit of a resistor 111b and a capacitor 112b, and a diode 113b is connected in parallel with the resistor 111b in a direction to accelerate discharge of the capacitor 112b, and only the rising edge of the input signal Y is delayed. To generate a signal with dead time.

JP 2002-335679 A

  However, in the conventional drive circuit 100, when a relatively long dead time is required, it is necessary to increase the capacitance of the capacitors 112a and 112b for delaying the signal. In such a case, when the drive circuit 100 is integrated as the drive IC 100a, the capacitors 112a and 112b cannot be built in. As shown in FIG. 7B, the two capacitors 112a and 112b are It must be externally attached, requiring two pins for external attachment. Further, there is a problem that a difference occurs in the dead time of the two systems of signals due to variations in characteristics of the two external capacitors 112a and 112b.

  In view of the above problems, an object of the present invention is to provide a dead time for each of two systems of signals that drive two switching elements connected in series using a single dead time generation circuit. Another object of the present invention is to provide a drive circuit that can have one external capacitor when integrated into an IC.

The drive circuit according to the present invention is configured as follows in order to achieve the above object.
The drive circuit according to claim 1 includes two switching elements connected in series alternately with a first signal which is an input rectangular wave and a second signal obtained by inverting the first signal. A drive circuit for providing a dead time for preventing the two switching elements from conducting simultaneously to the first signal and the second signal when the first signal and the second signal are driven. A first delay circuit that delays a time shorter than a dead time; a second delay circuit that delays the second signal for a time shorter than the dead time; and a capacitor for generating a dead time. Generate a dead time generation signal having a period ½ that of the first signal rising at a timing delayed by the dead time from the rising timing of the signal and the second signal Based on the dead time generation circuit, the first signal delayed by the first delay circuit, and the dead time generation signal generated by the dead time generation circuit. A first drive signal generation circuit for generating a first drive signal provided with a dead time; the second signal delayed by the second delay circuit; and the first signal generated by the dead time generation circuit And a second drive signal generation circuit for generating a second drive signal in which the second signal is provided with the dead time based on a dead time generation signal.
Further, the drive circuit according to claim 2 is characterized in that the first delay circuit and the second delay circuit have the same configuration.
Furthermore, the drive circuit according to claim 3 further includes a timing signal generation circuit that generates a timing signal having a period of ½ of the first signal, and the dead time generation circuit is generated by the timing signal generation circuit. The dead time generation signal is generated based on the timing signal thus generated.
5. The drive circuit according to claim 4, wherein the first delay circuit and the second delay circuit respectively delay only rising edges of the first signal and the second signal, respectively. Is an OR circuit that logically sums the outputs of the first delay circuit and the second delay circuit.
The drive circuit according to claim 5, wherein the first delay circuit and the second delay circuit respectively delay only rising edges of the first signal and the second signal, and the timing signal generation circuit Is an EXOR circuit that exclusively ORs the output of the first delay circuit and the first signal.

  According to the present invention, the first delay circuit for delaying the first signal for a time shorter than the dead time, the second delay circuit for delaying the second signal for a time shorter than the dead time, and for generating the dead time A dead time generating signal for generating a dead time generating signal having a period ½ of the first signal rising at a timing delayed by a dead time from the rising timing of the first signal and the second signal. A drive signal in which a dead time is provided in the first signal is generated based on the circuit, the first signal delayed by the first delay circuit, and the dead time generation signal generated by the dead time generation circuit First drive signal generating circuit, second signal delayed by second delay circuit, and dead time generation generated by dead time generation circuit And a second drive signal generation circuit that generates a drive signal in which a dead time is provided in the second signal based on the signal, and is connected in series using one dead time generation circuit. A dead time can be provided for each of the two systems of the first signal and the second signal that drive the two switching elements, and when an IC is formed, one external capacitor can be provided. . In addition, there is an effect that variations in dead time can be eliminated.

It is a figure which shows the structure of 1st Embodiment of the drive circuit which concerns on this invention. It is an operation | movement waveform diagram of 1st Embodiment of the drive circuit which concerns on this invention. It is an operation | movement waveform diagram of 1st Embodiment of the drive circuit which concerns on this invention. It is an operation | movement waveform diagram of 1st Embodiment of the drive circuit which concerns on this invention. It is a figure which shows the structure of the delay circuit of 2nd Embodiment of the drive circuit based on this invention. It is a figure which shows the structure of 3rd Embodiment of the drive circuit based on this invention. It is a figure which shows the structure of the conventional drive circuit.

  Preferred embodiments (examples) of the present invention will be described below with reference to the accompanying drawings.

(First embodiment)
Referring to FIG. 1, the drive circuit 1 according to the first embodiment includes one input unit 10, two delay circuits 2a and 2b, one dead time generation circuit 3, and two outputs. Units 11a and 11b, generating drive signals Va7 and Vb7 for driving the two switching elements 4a and 4b from the signal Va0 input from the input unit 10, respectively, and generating from the two output units 11a and 11b The drive signals Va7 and Vb7 are each output. As the switching elements 4a and 4b connected to the two output units 11a and 11b, for example, an n-type MOSFET constituting an H bridge circuit is used, and the output units 11a and 11b are connected to the gate of the n-type MOSFET.

  The signal Va0 input to the input unit 10 is a rectangular wave with a period T as shown in FIG. A delay circuit 2a composed of a resistor 12a, a capacitor 13a and an AND circuit 14a is connected to the input unit 10, and a delay circuit 2b composed of a resistor 12b, a capacitor 13b and an AND circuit 14b is connected to the input unit 10 via a NOT circuit 15. It is connected. Note that the delay circuit 2a and the delay circuit 2b are circuits having the same configuration that delays only the rise of the signal, and the circuit configuration can be simplified.

  In the delay circuit 2a, one end of the resistor 12a is connected to the input unit 10, and the other end of the capacitor 13a connected in series with the resistor 12a is grounded. In addition, one input terminal of the AND circuit 14 a is connected to a connection point between the resistor 12 a and the capacitor 13 a, and the other input terminal of the AND circuit 14 a is connected to the input unit 10. Thereby, the signal Va0 from the input unit 10 and the signal Va1 shown in FIG. 2 (b) obtained by delaying the signal Va0 by the RC series circuit including the resistor 12a and the capacitor 13a are input to the AND circuit 14a. Accordingly, by taking the logical product of both signals, a signal Va2 obtained by delaying only the rising of the signal Va0 as shown in FIG. 2C is output from the output terminal of the AND circuit 14a.

  An input terminal of the NOT circuit 15 is connected to the input unit 10, and a signal Vb0 obtained by inverting the signal Va0 input from the input unit 10 is output from the output terminal of the NOT circuit 15 as shown in FIG. Is done. The delay circuit 2b has the same configuration as the delay circuit 2a. One end of the resistor 12b is connected to the output terminal of the NOT circuit 15, and the other end of the capacitor 13b connected in series with the resistor 12b is grounded. One input terminal of the AND circuit 14b is connected to a connection point between the resistor 12b and the capacitor 13b, and the other input terminal of the AND circuit 14b is connected to the output terminal of the NOT circuit 15. As a result, the AND circuit 14b receives the signal Vb0 from the output terminal of the NOT circuit 15 and the signal Vb1 shown in FIG. 2B, which is delayed by the RC series circuit composed of the resistor 12b and the capacitor 13b. 2 is input, and by taking the logical product of both signals, the signal Vb2 obtained by delaying only the rising edge of the signal Vb0 as shown in FIG. 2C is output from the output terminal of the AND circuit 14b. .

  The rise delay time Ta by the delay circuits 2a and 2b is set to a time shorter than the dead time Tb generated by the dead time generation circuit 3. The capacitances of the capacitors 13a and 13b used in the delay circuits 2a and 2b, respectively, are set to such an extent that the drive circuit 1 can be built in an IC (for example, several tens of pF). The time that can be delayed by the capacities 13a and 13b is the delay time Ta.

  The output terminal of the AND circuit 14 a and the output terminal of the AND circuit 14 b are connected to the input terminal of the OR circuit 16, and the dead time generating circuit 3 is connected to the output terminal of the OR circuit 16. The OR circuit 16 functions as a timing signal generation circuit that generates a timing signal V3 having a period of ½ of the signal Va0 as shown in FIG. 3A, and takes the logical sum of the signal Va2 and the signal Vb2. Thus, a timing signal V3 having a waveform with a period of T / 2 and a duty ratio of (T-2Ta) / T is output from the output terminal.

  The dead time generation circuit 3 includes a NOT circuit 20, an n-type MOSFET 21, a current source 22, a capacitor 23, and a comparator 24. The input terminal of the NOT circuit 20 is connected to the output terminal of the OR circuit 16, and the output terminal of the NOT circuit 20 is connected to the gate of the n-type MOSFET 21. The output of the NOT circuit 20 is a signal V4 shown in FIG. 3B obtained by inverting the signal V3. The signal V4 is in a Hi state for the delay time Ta at the rising timing of the signal Va0 and the signal Vb0. The MOSFET 21 is turned ON for the delay time Ta at the rising timing of the signal Va0 and the signal Vb0.

  One end of the current source 22 is connected to the power supply Reg, and the other end of the current source 22 is connected to the drain of the n-type MOSFET 21, one end of the capacitor 23, and the non-inverting input terminal of the comparator 24. The source of the n-type MOSFET 21 and the other end of the capacitor 23 are grounded. Therefore, when the n-type MOSFET 21 is OFF, charges are accumulated in the capacitor 23. When the n-type MOSFET 21 is turned ON, charges accumulated in the capacitor 23 are extracted, and the non-inverting input terminal of the comparator 24 As shown in FIG. 3C, a signal V5 that rises linearly after a delay time Ta from the rise timing of the signals Va0 and Vb0 is input.

  The reference voltage Vref is input to the inverting input terminal of the comparator 24. The comparator 24 compares the signal V5 with the reference voltage Vref, and the signal Va0 and the signal Vb0 as shown in FIG. A signal having a period of T / 2 rising at a timing delayed by the dead time Tb from the rising timing is output from the output terminal of the comparator 24 as a dead time generating signal V6.

  The output terminal of the comparator 24 is connected to one input terminal of the AND circuit 17a, the output terminal of the AND circuit 14a is connected to the other input terminal of the AND circuit 17a, and the output terminal of the AND circuit 17a is connected to the output unit 11a. ing. Therefore, by taking the logical product of the signal Va2 shown in FIG. 2C and the dead time generation signal V6 shown in FIG. 4A, the dead time Tb is provided in the signal Va0 shown in FIG. The drive signal Va7 shown in FIG. 4B is output from the output terminal (output unit 11a) of the AND circuit 17a. That is, the AND circuit 17a functions as a drive signal generation circuit that generates a drive signal for driving the switching element 4a. Since the rise of the signal Va2 output from the AND circuit 14a is delayed by the delay time Ta, the rise timing of the signal Va2 and the fall of the dead time generation signal V6 output from the comparator 24 are displayed. The timing does not overlap, and an unintended pulse is prevented from being superimposed on the drive signal Va7 output from the AND circuit 17a.

  The output terminal of the comparator 24 is connected to one input terminal of the AND circuit 17b, the output terminal of the AND circuit 14b is connected to the other input terminal of the AND circuit 17b, and the output terminal of the AND circuit 17b is connected to the output unit 11b. It is connected. Therefore, by taking the logical product of the signal Vb2 shown in FIG. 2C and the dead time generation signal V6 shown in FIG. 4A, the dead time Tb is provided in the signal Vb0 shown in FIG. The drive signal Vb7 shown in FIG. 4B is output from the output terminal (output unit 11b) of the AND circuit 17b. That is, the AND circuit 17b functions as a drive signal generation circuit that generates a drive signal for driving the switching element 4b. Since the rise of the signal Vb2 output from the AND circuit 14b is delayed by the delay time Ta, the rise timing of the signal Vb2 and the fall of the dead time generation signal V6 output from the comparator 24 are displayed. The timing does not overlap, and an unintended pulse is prevented from being superimposed on the drive signal Vb7 output from the AND circuit 17b.

  The dead time Tb provided by the dead time generation circuit 3 is longer than the delay time Ta by the delay circuits 2a and 2b, and the capacitance of the capacitor 23 that determines the dead time Tb is the case where the drive circuit 1 is integrated into an IC. In addition, it is difficult to incorporate in an IC. Therefore, the capacitor 23 is attached as an external capacitor when the drive circuit 1 is made into an IC, and the dead time Tb can be appropriately set according to the capacitance of the capacitor 23. Thus, since one capacitor 23 can set the dead time Tb for the two systems of signals Va0 and Vb0, it is possible to prevent the time variation of the dead time Tb provided for the two systems of signals Va0 and Vb0. Can do.

  In the first embodiment, the configuration using the current source 22 in the dead time generation circuit 3 is employed. However, a current mirror circuit may be employed as the current source 22, and n-type as in the prior art. A dead time generation circuit that does not use the MOSFET 21 or the current source 22 may be employed. Further, a Schmitt trigger circuit may be employed instead of the comparator 24.

(Second Embodiment)
The second embodiment has a configuration in which the delay circuits 2a and 2b in the drive circuit 1 of the first embodiment are changed, and other configurations are the same as the drive circuit 1 of the first embodiment. is there.

  In the second embodiment, referring to FIG. 5, a delay circuit 2c including a NOT circuit 18c, a resistor 12c, a capacitor 13c, a NOT circuit 19c, and an AND circuit 14c is connected to the input unit 10, and a NOT circuit 18d. A delay circuit 2d including a resistor 12d, a capacitor 13d, a NOT circuit 19d, and an AND circuit 14d is connected to the input unit 10 via the NOT circuit 15.

  In the delay circuit 2c, the input terminal of the NOT circuit 18c is connected to the input unit 10, the output terminal of the NOT circuit 18c is connected to one end of the resistor 12c, and the other end of the capacitor 13c connected in series with the resistor 12c is grounded. ing. Further, the input terminal of the NOT circuit 19c is connected to the connection point between the resistor 12c and the capacitor 13c, the output terminal of the NOT circuit 19c is connected to one input terminal of the AND circuit 14c, and the AND circuit is connected to the input unit 10. The other input terminal of 14c is connected. Thereby, after the signal Va0 from the input unit 10 is inverted by the NOT circuit 18c, it is delayed by the RC series circuit composed of the resistor 12c and the capacitor 13c, and is inverted again by the NOT circuit 19c, so that FIG. Is input to one input terminal of the AND circuit 14c. Further, the signal Va0 from the input unit 10 is input to the other input terminal of the AND circuit 14c, and the signal shown in FIG. 2C is output from the output terminal of the AND circuit 14c as in the first embodiment. Va2 is output.

  The delay circuit 2d has the same configuration as the delay circuit 2c, the input terminal of the NOT circuit 18d is connected to the output terminal of the NOT circuit 15 of the NOT circuit 18d, and the output terminal of the NOT circuit 18d is connected to one end of the resistor 12d. The other end of the capacitor 13d connected in series with the resistor 12d is grounded. Further, the input terminal of the NOT circuit 19d is connected to the connection point between the resistor 12d and the capacitor 13d, the output terminal of the NOT circuit 19d is connected to one input terminal of the AND circuit 14d, and the AND circuit is connected to the input unit 10. The other input terminal of 14d is connected. Thereby, after the signal Vb0 from the output terminal of the NOT circuit 15 is inverted by the NOT circuit 18d, it is delayed by the RC series circuit composed of the resistor 12d and the capacitor 13d, and is inverted again by the NOT circuit 19d. The signal Vb1 shown in (b) is input to one input terminal of the AND circuit 14d. Further, the signal Vb0 from the output terminal of the NOT circuit 15 is input to the other input terminal of the AND circuit 14d, and the output terminal of the AND circuit 14d receives FIG. 2C as in the first embodiment. The signal Vb2 shown in FIG.

(Third embodiment)
In the drive circuit 1a of the third embodiment, referring to FIG. 6, a delay circuit 2e composed of a resistor 12e and a capacitor 13e is connected to the input unit 10, and a delay circuit 2f composed of a resistor 12f and a capacitor 13f The input unit 10 is connected via a NOT circuit 15.

  In the delay circuit 2e, one end of the resistor 12e is connected to the input unit 10, and the other end of the capacitor 13e connected in series with the resistor 12e is grounded. Further, one input terminal of the EXOR circuit 50 is connected to a connection point between the resistor 12e and the capacitor 13e. The other input terminal of the EXOR circuit 50 is connected to the input unit 10. Thereby, the signal Va0 from the input unit 10 and the signal Va1 shown in FIG. 2 (b) obtained by delaying the signal Va0 by the RC series circuit including the resistor 12e and the capacitor 13e are input to the EXOR circuit 50. Accordingly, the signal V4 shown in FIG. 3B is output from the output terminal of the EXOR circuit 50.

  The signal V4 of the EXOR circuit 50 is input to the dead time generation circuit 3a. The dead time generation circuit 3a has a configuration in which the NOT circuit 20 is omitted from the dead time generation circuit 3 of the first embodiment. The output terminal of the EXOR circuit 50 and the gate of the n-type MOSFET 21 are connected to each other, and the dead time is From the generation circuit 3a, a dead time generation signal V6 shown in FIG. 4A is output in the same manner as the dead time generation circuit 3 of the first embodiment.

  The delay circuit 2f has the same configuration as the delay circuit 2e, one end of the resistor 12f is connected to the output terminal of the NOT circuit 15, and the other end of the capacitor 13f connected in series with the resistor 12f is grounded. As a result, the delay circuit 2f outputs the signal Vb1 shown in FIG. 2B in which the signal Vb0 obtained by inverting the signal Va0 by the NOT circuit 15 is delayed by the RC series circuit including the resistor 12f and the capacitor 13f. Will be.

  The dead time generation signal V6 from the dead time generation circuit 3a is connected to one input terminal of the AND circuit 17a, the output terminal of the delay circuit 2e, that is, the connection point between the resistor 12e and the capacitor 13e, and the other input terminal of the AND circuit 17a. And the output terminal of the AND circuit 17a is connected to the output unit 11a. Therefore, by taking the logical product of the signal Va1 shown in FIG. 2B and the dead time generation signal V6 shown in FIG. 4A, the drive circuit 1a provides the drive signal Va7 provided with the dead time Tb. That is, the drive signal Va7 shown in FIG. 4B with a dead time Tb is output from the output terminal (output unit 11a) of the AND circuit 17a with respect to the signal Va0 shown in FIG.

  The dead time generating signal V6 from the dead time generating circuit 3a is connected to one input terminal of the AND circuit 17b, the output terminal of the delay circuit 2f, that is, the connection point between the resistor 12f and the capacitor 13f, and the other terminal of the AND circuit 17b. The output terminal of the AND circuit 17b is connected to the output unit 11b. Therefore, by taking the logical product of the signal Vb1 shown in FIG. 2B and the dead time generation signal V6 shown in FIG. 4A, the drive circuit 1a outputs the drive signal Vb7 provided with the dead time Tb. That is, the drive signal Vb7 shown in FIG. 4 (b) with the dead time Tb is output from the output terminal (output unit 11b) of the AND circuit 17b with respect to the signal Vb0 shown in FIG. 2 (a).

  Note that the present invention is not limited to the above-described embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical idea of the present invention. In addition, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to a suitable number, position, shape, and the like in practicing the present invention. In each figure, the same numerals are given to the same component.

DESCRIPTION OF SYMBOLS 1 Drive circuit 2a, 2b, 2c, 2d, 2e, 2f Delay circuit 3, 3a Dead time generation circuit 4a, 4b Switching element 10 Input part 11a, 11b Output part 12a, 12b, 12c, 12d, 12e, 12f Resistance 13a, 13b, 13c, 13d, 13e, 13f Capacitors 14a, 14b, 14c, 14d AND circuit 15 NOT circuit 16 OR circuit 17a, 17b AND circuit 18c, 18d, 19c, 19d NOT circuit 20 NOT circuit 21 n-type MOSFET
22 Current source 23 Capacitor 24 Comparator 50 EXOR circuit

Claims (5)

When the two switching elements connected in series are alternately driven with the input first signal that is a rectangular wave and the second signal obtained by inverting the first signal, the first switching element And a second drive circuit for providing a dead time for preventing the two switching elements from being conducted simultaneously.
A first delay circuit for delaying the first signal for a time shorter than the dead time;
A second delay circuit for delaying the second signal for a time shorter than the dead time;
Using a dead time generating capacitor, dead time generation with a period ½ of the first signal rising at a timing delayed by the dead time from the rising timing of the first signal and the second signal A dead time generation circuit for generating a signal for use;
The first signal is provided with the dead time based on the first signal delayed by the first delay circuit and the dead time generation signal generated by the dead time generation circuit. A first drive signal generation circuit for generating one drive signal;
The second signal is provided with the dead time based on the second signal delayed by the second delay circuit and the dead time generation signal generated by the dead time generation circuit. A drive circuit comprising: a second drive signal generation circuit that generates a second drive signal.   The drive circuit according to claim 1, wherein the first delay circuit and the second delay circuit have the same configuration. A timing signal generation circuit for generating a timing signal having a period of ½ of the first signal;
The drive circuit according to claim 1, wherein the dead time generation circuit generates the dead time generation signal based on the timing signal generated by the timing signal generation circuit. The first delay circuit and the second delay circuit respectively delay only rising edges of the first signal and the second signal,
4. The drive circuit according to claim 1, wherein the timing signal generation circuit is an OR circuit that logically sums outputs of the first delay circuit and the second delay circuit. 5. . The first delay circuit and the second delay circuit respectively delay only rising edges of the first signal and the second signal,
4. The drive circuit according to claim 1, wherein the timing signal generation circuit is an EXOR circuit that performs an exclusive OR operation between the output of the first delay circuit and the first signal. 5. .

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