JP2012048573A - Semiconductor integrated circuit and data processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor array configuration in which algorithm can be efficiently mounted without increasing a circuit scale.SOLUTION: Efficient mounting is achieved by providing multiple paths in a predetermined direction as one of paths between input/output means of a processor array in accordance with a data processing flow. Instead of providing the multiple paths in the predetermined direction, a path in the opposite direction from the direction is eliminated to prevent the circuit scale from increasing.

Description

  The present invention relates to a semiconductor integrated circuit such as a processor array or a data processing apparatus.

  As disclosed in Patent Document 1, there is a processor array structure in which processors are directly connected to communicate data directly. In such a configuration, each processor must also perform data input / output processing for data communication between the processors.

  Therefore, as shown in Non-Patent Document 1, there is a configuration in which a data arithmetic processing circuit and a data input / output processing circuit are provided, and the arithmetic processing and the input / output processing are separated in a circuit. A processor array configuration represented by Non-Patent Document 1 is shown in FIG.

  The processing element 402 includes at least one arithmetic unit, and is paired via a switching element 401 that changes a data transmission path and signal lines 404 a and 404 b for realizing bidirectional data transmission. Connected with one. The switching element 401 is connected in a grid pattern with signal lines 403a, 403b, 403c, and 403d for realizing bidirectional data transmission with the other switching elements 401 in the east, west, north, and south directions.

  A path 404 a between the switching element 401 and the processing element 402 is connected in the direction from the switching element 401 to the processing element 402. A path 404 b between the switching element 401 and the arithmetic processing unit 402 is connected in the direction from the processing element 402 to the switching element 401.

Japanese Patent No. 0253282

M.M. B. Taylor, et al. , “The RAW Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs,” IEEE Micro, 22 (2): 25-35, Mar. 2002

  In the dynamically reconfigurable processor array, the switching elements are connected by a set of signal lines that realize bidirectional data transmission so that the connection between the processors can be arbitrarily changed. Here, when data is input to the processor array, data to be processed flows mainly from the input end to the output end, so the amount of data flowing from the input end to the output end is larger than the amount of data flowing in the other direction large. Therefore, this point is not taken into consideration by simply connecting the switching elements bidirectionally as in Patent Document 1, and the signal lines mainly in the direction in which data flows and in other directions are wired in the same manner. Therefore, the data transfer efficiency with respect to the circuit scale is not good.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to improve data transfer efficiency with respect to circuit scale in a processor array.

  A data processing apparatus according to the present invention for determining the above-described problems includes a plurality of input / output means, a plurality of processing means, a plurality of first communication lines connecting the plurality of input / output means, and the input / output The band of the plurality of second communication lines connecting the means and the processing means to each other and the band of the first communication line for transmitting data in a predetermined direction are compared with the band of the first communication line in the other direction. It is large.

According to the present invention, it is possible to improve the data transfer efficiency in the processor array without increasing the circuit scale.

It is a figure which shows schematic structure of a processor array. It is a figure which shows the connection relation of a processing element and a switching element. It is a figure which shows the connection relation of an input / output control part. It is a figure which shows schematic structure of the conventional processor array. It is a figure which shows the operation example of a processor array. It is a figure which shows the procedure of the data communication in 1st embodiment. It is a figure which shows the operation | movement in 1st embodiment. It is a figure which shows the example of the processing content in 1st embodiment. It is a figure which shows the example of mounting at the time of connecting with another module in 1st embodiment. It is a figure which shows 2nd embodiment. It is a figure which shows the example of the input / output control means in 2nd embodiment. It is a figure which shows the operation example in 2nd embodiment. It is a figure which shows 3rd embodiment. It is a figure which shows the example of the memory | storage means in 3rd embodiment.

(Embodiment 1)
FIG. 1 shows a schematic configuration of the processor array according to the present embodiment. Although not shown in FIG. 1, there is an input end (input module 902 described later) for inputting data to the processor array at the south end of the processor array, and an output end (output module for outputting data from the processor array at the north end of the processor array). There is an output module 901) described later. Therefore, in the processor array of FIG. 1, the amount of data flowing to the north is larger than the amount of data flowing to the south.

  In the processor array, switching elements 101 as 8-input 8-output input / output processing means are arranged in a two-dimensional lattice, and 4-input 4-output processing elements 102 as arithmetic processing means are arranged in the lattice of the switching elements 101. Has been placed.

  8 inputs and 8 outputs of the switching elements 101a, 101c, 101d, 101f, 101g, and 101i are one input and one output as a set via the other four switching elements 101 and paths (signal lines) 103a and 103b in the east, west, south, and north. They are individually connected to each other. In addition, they are bidirectionally connected to the four northeast, southeast, southwest, and northwest four separate processing elements via paths 104a and 104b. The switching elements 101b, 101e, and 101h are connected to the processing element 102 in the same manner as the other switching elements 101, and are connected to four different processing elements in the northeast, southeast, southwest, and northwest via paths 104a and 104b. It has the structure which was made. Regarding the connection with other switching elements, the connection with the east-west switching element 101 is bidirectionally connected via 103a and 104b.

  However, the connection with the switching element 101 located in the north-south direction has a configuration in which there are two paths 103a in the north direction by changing to the path 104a in the north direction instead of the path 103b in the south direction. Note that the directions of arrows in the paths 103a, 103b, 104a, and 104b in FIG. 1 indicate directions in which data can be transmitted. 101a to 101i have the same configuration, and 102a to 102d have the same configuration. Have.

  In this way, at least one part of the configuration having only two directions 103 but physically having two paths 103 is arranged on the array.

  Here, as a communication protocol for each of the connections 103a, 103b, 104a, and 104b, in this embodiment, a two-wire handshake using a Valid signal and a Ready signal is used. FIG. 6 shows a schematic diagram and a timing chart for handshaking when data is transferred from the module A601 to the module B602 using the two-wire handshake. Both modules A and B may be switching elements or processing elements. When transferring data from module A to module B, a data signal 603 and a valid signal 604 are transmitted from module A to B, while a ready signal 605 is transmitted from module B to A. In addition, although the example which transfers data to one direction is demonstrated for the simplification of description, in order to be able to transfer bidirectionally, a signal line is simply required twice.

  The Valid signal 604 indicates that the module A can transmit data, and the Ready signal 605 indicates that the module B can receive data. The DATA signal 603 is transmitted from the module A 601 to the module B 602 at a timing when both the Valid signal 604 of the module A 601 and the Ready signal 605 from the module B 602 are valid. In the timing chart of FIG. 6, the signal is high and the signal is invalid and the signal is invalid. In the timing chart of FIG. 6, data A is transferred from module A 601 to module B 602 at timing 606a, data B at timing 606b, data C at timing 606c, and data D at timing 606d.

  Next, a connection configuration of the processing element and the switching element is shown in FIG. The processing element 102 has input ports 202ne, 202nw, 202sw and 202se, and output ports 203ne, 203nw, 203sw and 203se. The input ports 202ne, 202nw, 202sw, and 202se are individually connected to 205sw of the switching element 101b, 205se of 101a, 205ne of 101d, and 205nw of 101e with an N-bit data width (bandwidth).

  The output ports 203ne, 203nw, 203sw and 203se are individually connected to the 204sw of the switching element 101b, 204se of the switching element 101a, 204ne of the switching element 101d and 204nw of the switching element 101e, respectively, with an N-bit data width.

  Each of the processing elements 102 has a 4-input 4-output port, and can perform a plurality of operations in parallel on a given input value and output it. FIG. 2 shows a configuration having four arithmetic units 201 as a configuration example of the processing element. The four arithmetic units 201 can operate at high speeds by independently operating in parallel with each input. Note that the arithmetic unit has at least one arithmetic unit. For example, a multi-input arithmetic unit such as an adder / subtracter, a comparator, a multiplier, a divider, a logical arithmetic unit, a selector, etc., an arithmetic unit consisting of a combination thereof, or an arithmetic unit consisting of a combination of these and other arithmetic units Etc. The operation of the arithmetic unit of the processing element 102 is an operation determined by settings stored in advance in a register (not shown) in the processing element 102.

  Next, FIG. 3 shows the configuration of the switching element 101e and the connection relationship with other switching elements and processing elements connected to the switching element 101e. The switching element 101 has input ports 204n, 204s, 204e, 204w, 204ne, 204nw, 204sw and 204se. Similarly, the switching element 101 has output ports 205n, 205s, 205e, 205w, 205ne, 205nw, 205sw, and 205se.

  The input ports 204ne, 204nw, 204sw, and 204se of the switching element 101e are connected to 203sw of the processing element 102b, 203se of 102a, 203ne of 102c, and 203nw of 102d, respectively. The input ports 204n, 204s, 204e, and 204w are connected to 205s of the switching element 101h, 205n of 101h, 205e of 101d, and 205w of 101f, respectively.

  The output ports 205ne, 205nw, 205sw, and 205se of the switching element 101e are connected to 202sw of the processing element 102b, 202se of 102a, 202ne of 102c, and 202nw of 102d, respectively.

  The output ports 205n, 205s, 205e, and 205w are connected to 204s of the switching element 101b, 204n of 101b, 204w of 101f, and 204e of 101d.

  The switching element shown in FIG. 3 has an 8-input 8-output crossbar switch (X-bar Switch) 301. The path setting of the crossbar switch 301 is set in advance from the outside, and the communication of the input / output port set as the path is performed independently.

  An operation example according to the above configuration is shown below. Consider the case where data is transferred through paths 701, 702, 703, 704, and 705 in FIG. In the path 701, data is transferred in the order of the switching elements 101g, 101d, and 101a. In the path 702, data is transferred in the order of the switching elements 101h, 101e, and 101b. In the path 703, data is transferred in the order of the switching elements 101i, 101f, and 101c. In the path 704, data is transferred in the order of the switching elements 101g and 101h and the processing element 102d. In the path 705, data is transferred in the order of the processing element 102d and the switching elements 101e and 101b.

  In the configuration of the conventional example shown in FIG. 5, a path for passing data from the processing element 402d to the switching element 401b via the two elements could not be set. However, in this embodiment, the path 705 can be set so that the two elements are set. The data can be exchanged through the network.

  Next, an example in which the architecture described above is applied to an actual image processing module will be shown. First, FIG. 8 shows a data flow diagram to be applied. In the example of FIG. 8, threshold processing is performed using a feature amount in an image that is data to be processed and a coefficient at each position of the image.

  First, two different feature quantities are input in 801a. In 802a, a threshold value for each feature amount position is input. In step 803a, a weighting coefficient is processed for the input feature value. Next, threshold processing is performed using threshold data corresponding to the feature amounts calculated in the coefficient in 804. Finally, the feature value subjected to threshold processing in 805a is output. The processing shown in FIG. 8 is performed on the image a, and the same processing is performed on the images b and c in parallel. (In the following description, similar processing for images b and c will be denoted as 801b and 801c.)

  Next, the operation when the above-described data flow diagram is executed by the processor array having the configuration shown in FIG. 9 will be described. As shown in FIG. 9, data input from the input module (data input unit) 902 to the processor array unit (data processing device) is processed by the processor array unit and output from the processor array unit to the output module (data output unit) 901. It is configured to be. The signal line 904 from the input module 902 to the processor array unit and the signal line 903 from the processor array unit to the output module 901 are configured so that data can be transferred only from the input module to the output module.

  First, six feature amounts corresponding to 801a, b, and c and threshold values corresponding to 802a, b, and c are input from the input module 902 to the switching elements 101i, 101j, 101k, and 101l via the path 904. .

  Next, the input feature amount is transferred to the processing elements 102d, 102e, and 102f. Each of the processing elements 102d, 102e, and 102f performs weighting coefficient processing on the two feature amounts in parallel. Next, each of the processing elements 102d, 102e, and 102f transfers the feature amount subjected to the weight counting process to the processing elements 102a, 102b, and 102c via 101e, 101f, 101g, and 101h and 101a, 101b, 101c, and 101d. . On the other hand, the threshold corresponding to each feature amount position is transferred from the switching elements 101i, 101j, 101k, 101l to 102a, 102b, 102c via 101e, 101f, 101g, 101h.

  The processing elements 102a, 102b, and 102c perform threshold processing using the threshold value input to the input feature value, and output the result to the output module 901 via the path 903.

  As described above, in the present embodiment, at least one of the paths (communication lines) between the switching elements in the processor array unit is doubly provided in a predetermined direction (direction from the input module to the output module). (The band is widened.) As a result, it is possible to perform processing by a plurality of processing elements while efficiently transferring data in the processor array unit. Further, instead of duplicating the predetermined direction, the route in the direction opposite to the direction is omitted, thereby preventing an increase in circuit scale.

(Embodiment 2)
FIG. 10 shows a schematic configuration of the processor array of this embodiment. In this embodiment, data is transferred between the switching elements 1001a, 1001b, and 1001c using only one unidirectional path 103a described in the first embodiment.

  As described above, the differences from the first embodiment are that the switching elements 1001a, 1001b, and 1001c in FIG. 10 are connected by only one path, and that each switching element 1001 itself. Only for communication between the switching elements 1001a and 1001b and between 1001b and 1001c, a general data bypass mechanism (virtual channel mechanism) is added so that a plurality of data communications can be shared in a time division manner.

  FIG. 11 shows a configuration of a switching element 1001 having a virtual channel mechanism. There are seven input ports 1101, and the input port 1101s is connected to a switching element arranged in the south direction. If this is expressed as “1101s: south”, the other input ports can be expressed as 1101e: east, 1101w: west, 1101nw: northwest, 1101ne: northeast, 1101sw: southwest, 1101se: southeast.

  There are also seven output ports 1102, and the output port 1102n is connected to a switching element arranged in the north direction. When this is expressed as “1102n: north”, the other output ports can be expressed as 1102e: east, 1102w: west, 1102nw: northwest, 1102ne: northeast, 1102sw: southwest, 1102se: southeast.

  The virtual channel mechanism is realized using a buffer 1103 and multiplexers 1104 and 1105. In FIG. 10, switching elements 1001a and 1001b and 1001b and 1001c are connected to input ports 1101s and 1001b of switching element 1001a, and input ports 1101s and 1001c of 1001b, respectively. And a virtual channel mechanism is provided on the path. The path provided with the virtual channel can transfer data from different paths.

When data from a different route is input from the input port 1101s, it is stored in a different buffer 1103 for each route. The multiplexers 1104 and 1105 and the ports of the crossbar switch 1106 connected to the multiplexers change their output destinations by switching paths in a time division manner. Even if one of the output destination paths connected to the path via the crossbar switch 1106 with the virtual channel is stalled, it is possible to communicate with the data of the other path. Is possible.
Instead of providing a virtual channel mechanism, an increase in circuit scale can be suppressed by removing a path in a direction opposite to the direction of the path connected by the virtual channel.

  FIG. 12 shows an operation example according to the configuration shown in FIGS.

  FIG. 12 shows an example in which data is transferred through paths 1201, 1202, 1203, 1204, and 1205. In the path 1201, data is transferred in the order of the switching elements 101g, 101d, and 101a. In the path 1202, data is transferred in the order of the switching elements 101h, 101e, and 101b. In the path 1203, data is transferred in the order of the switching elements 101i, 101f, and 101c. In the path 1204, data is transferred in the order of the switching elements 101g and 101h and the processing element 102d. In the path 1205, data is transferred in the order of the processing element 102d and the switching elements 101e and 101b.

  Here, regarding the transfer from the switching element 1001b to 1001a, the same path is used in the paths 1202 and 1205. However, as described above, this is performed in parallel in a time division multiplexed manner by using the virtual channel mechanism of the switching element 1001a. Data transfer.

  As described above, in this embodiment, only a part of the array is limited to switching elements, and a virtual channel mechanism is added to a part of the input / output ports, thereby increasing the degree of freedom of the path without significantly increasing the circuit scale. be able to.

(Embodiment 3)
In the present embodiment, a configuration is assumed in which a part of the processing element 102 in the first and second embodiments is replaced with a memory element 1301.

  This embodiment will be described below in comparison with FIG. 9 of the first embodiment. FIG. 13 assumes a configuration in which the processing element 102 e in FIG. 9 is replaced with a memory element 1301.

  The internal configuration of the memory element 1301 is shown in FIG. The memory element 1301 has 2 input 6 output ports. 1401a and 1401b are input ports connected to switching elements arranged in the southwest and southeast directions. Reference numeral 1402 denotes an output port, 1402ne1 and 1402ne2 are connected to switching elements arranged in the northeast direction, and 1402nw1 and 1402nw2 are connected to switching elements arranged in the northwest direction. Similarly, 1402se is connected to a switching element arranged in the southeast direction, and 1402sw is connected to a switching element arranged in the southwest direction.

  The memory element 1301 includes one memory controller 1404 and a plurality of (six in this embodiment) memories 1403. A plurality of input data can be sequentially written from a plurality of input ports 1401 to a memory, and the data can be simultaneously read from a plurality of memories 1403 to a plurality of output ports 1402.

  In the present embodiment, data can be read and written in parallel at a time, so that the throughput of data processing is improved.

(Other embodiments)
In the above-described embodiment, the two-dimensional configuration has been described as the signal processing circuit. However, the present invention is not limited to this and can be applied to various dimensional configurations. For example, when applied to a three-dimensional configuration, it is possible to improve the mounting efficiency of processing without increasing the circuit scale, which is a feature of the present invention.
In the embodiment, the configuration including the arithmetic unit that operates in parallel for each input port as the processing element has been described. However, the present invention is not limited to this and can be applied to various processors. For example, it is possible to use a processor that performs general processing.

  In the above description of the embodiment, the relationship between the components has been described using directions for the sake of simplicity. However, this direction defines the logical positional relationship between the components. The physical positional relationship of is not strictly defined. For example, the present invention can be applied even if a plurality of processors are stacked. However, if the length between the switching elements becomes extremely long locally, a large wiring delay occurs locally. Therefore, the wiring between the switching elements is preferably equalized. Similarly, the description of “adjacent” means that it can be expressed as logically adjacent when the wirings are equalized.

  The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

Claims (8)

A plurality of input / output means;
A plurality of processing means;
A plurality of first communication lines connecting the plurality of input / output means;
A plurality of second communication lines interconnecting the input / output means and the processing means;
A data processing apparatus, wherein a band of a first communication line for transmitting data in a predetermined direction is wider than a band of a first communication line in another direction. A plurality of input / output means arranged in a grid and having a plurality of input / output ports;
A plurality of processing means arranged corresponding to the lattice and having a plurality of input / output ports;
The input / output means includes the other input / output means adjacent to each other and a plurality of data communication means for connecting the plurality of input / output ports,
A signal processing circuit having a configuration in which at least one of the plurality of data communication means is multiplexed in a predetermined direction. 3. The signal according to claim 2, wherein the processing unit includes a plurality of storage units, and includes a writing unit that writes data received from the plurality of input / output ports of the processing unit in parallel to the storage unit. Processing circuit. The processing means comprises a plurality of storage means, and further comprises a reading means for reading in parallel a plurality of data written in the storage means to the plurality of input / output ports provided in the processing means. 4. The signal processing circuit according to 2 or 3.   5. The signal processing circuit according to claim 2, wherein at least one of the plurality of data communication means is configured to be physically multiplexed. 6.   6. The signal processing according to claim 2, wherein at least one of the plurality of data communication units is configured to be able to share data communication from the plurality of input / output units. circuit.   7. A data input means is further provided, and at least a part of the data communication means is multiplexed in the direction from the data input means to the input / output means. A signal processing circuit according to 1.   Data output means connected to an input / output means different from the data input means, and at least a part of the data communication means is multiplexed in the direction from the input / output means to the data output means. The signal processing circuit according to claim 7.

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