JP2011216901A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology manufacturing a power MISFET having a desired gate breakdown voltage, while controlling an increase in the parasitic capacitance.SOLUTION: The technology includes: depositing a polycrystalline silicon film on a substrate; after filling groove portions 7, 8 with the polycrystalline silicon film, patterning the polycrystalline silicon film and forming a gate electrode 11 within the groove portion 7 in an active cell area; filling an interior of the groove portion 8 in a gate wiring area and forming a gate extraction electrode 12 electrically connecting with the gate electrode 11 such that a part thereof extends to an exterior of the groove portion 8 continuously out of the interior of the groove portion 8; forming slits 14 extending from the end portion of the gate extraction electrode 12 in the gate extraction electrode 12 in the exterior of the groove portion 8. Then, a silicon oxide film 19 and a BPSG film 20 are deposited on the substrate.

Description

  The present invention particularly relates to a technique effective when applied to a semiconductor device having a power MISFET (Metal Insulator Semiconductor Field Effect Transistor).

  For example, in a semiconductor device having a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a gate electrode is formed inside a groove formed on the surface of the semiconductor substrate, and an interlayer insulating film is formed on the semiconductor substrate in the presence of the gate electrode. A contact hole reaching the gate electrode is formed in the interlayer insulating film, a conductor plug electrically connected to the gate electrode is filled in the contact hole, and a wiring formed on the interlayer insulating film is formed. There is a technique capable of improving the withstand voltage of the vertical MOSFET by using a structure that is electrically connected to the gate electrode through the conductor plug.

JP 2002-368221 A

  Transistors for large power applications that can handle a power of several watts or more are called power transistors, and various structures have been studied. Among these, power MISFETs include so-called vertical and horizontal types, and are further classified into trench (groove) gate type and planar gate type according to the structure of the gate portion. In such a power MISFET, in order to obtain large electric power, for example, a structure in which a large number (for example, several tens of thousands) of MISFETs with fine patterns are connected in parallel is employed.

  The present inventors are examining a technique for reducing the on-resistance of the power MISFET. This is because a large current can be obtained by reducing the on-resistance. The present inventors are also examining a technique for downsizing a semiconductor chip (hereinafter simply referred to as a chip) on which a power MISFET is formed.

  In order to reduce the on-resistance, it is necessary to increase the channel width per unit area. In view of this, the present inventors have studied a technique for increasing the channel width per unit area by adopting a trench gate type structure and further reducing the width of the groove in which the gate portion is formed. By reducing the width of the groove, it is possible to reduce the size of the chip, and it is also possible to reduce the size of the chip by reducing the interval between adjacent grooves as much as possible.

  Here, the present inventors have found that the following problems exist in manufacturing the power MISFET having the trench gate structure.

  That is, the manufacturing process of the power MISFET having the trench gate structure studied by the present inventors includes the following processes. First, as shown in FIG. 21, after the grooves 102 and 103 are formed in the main surface (element formation surface) of a semiconductor substrate (hereinafter simply referred to as a substrate) 101, the gate electrode 104 is formed in the groove 102. A gate wiring 105 is formed in 103. The gate electrode 104 and the gate wiring 105 are integrally formed, and a part of the gate wiring 105 is patterned so as to extend outside the trench 103. Thereafter, an interlayer insulating film 106 is deposited on the substrate 101. Since the interlayer insulating film 106 fills the groove 102 on the gate electrode 104 in the cell region where the gate electrode 104 is formed, the film thickness TC in the cell region is smaller than the film thickness TL in other regions. . Next, the interlayer insulating film 106 on the cell region (excluding the inside of the trench 102) is removed by patterning the interlayer insulating film 106, and the interlayer insulating film 106 on the gate wiring 105 extending to the outside of the trench 103 is removed. Then, an opening 107 reaching the gate wiring 105 is formed (see FIG. 22). The interlayer insulating film 106 remaining in the trench 102 has a function of insulating a wiring formed over the trench 102 and the gate electrode 104 in a later step. At this time, since the film thickness TC in the cell region is thinner than the film thickness TL in the other regions, the interlayer insulating film 106 is etched when the opening 107 is completely opened. There is a problem that the film thickness TG of the interlayer insulating film 106 remaining in 102 is overetched and becomes insufficient to maintain a desired gate breakdown voltage. Conversely, if the film thickness TG of the interlayer insulating film 106 remaining in the trench 102 is set to a film thickness sufficient to maintain a desired gate breakdown voltage, there is a problem that the opening 107 does not reach the gate wiring 105.

  In order to solve the above-described problems, the present inventors have studied a method for securing a sufficient thickness of the interlayer insulating film 106 remaining in the trench 102 by lowering the upper surface of the gate electrode 104. However, when the upper surface of the gate electrode 104 is lowered in the depth direction of the groove 102, the source (semiconductor layer 110) needs to be deepened. When the source (semiconductor layer 110) is deepened, the punch-through breakdown voltage is lowered, so that the channel (semiconductor layer 108) needs to be deepened. When the channel (semiconductor layer 108) is deepened, it is necessary to deepen the groove 102 passing therethrough. As the trench 102 becomes deeper, the parasitic capacitance between the gate and the source increases, resulting in an increase in switching loss. Further, since the depth variation increases when the groove 102 is deeper than when the groove 102 is shallow, the portion of the groove 102 that penetrates the semiconductor layer 108 serving as the channel of the power MISFET and reaches the semiconductor layer 109 serving as the drain increases. As a result, the parasitic capacitance between the gate and the drain generated between the gate electrode 104 and the semiconductor layer 109 increases, resulting in an increase in switching loss of the power MISFET. In addition, in order to deeply form the semiconductor layer 110 serving as the source of the power MISFET and the semiconductor layer 108, the time required for heat treatment for diffusing the impurities forming the semiconductor layer 110 and the semiconductor layer 108 increases, and the semiconductor device is There arises a problem that TAT (Turn Around Time) to be manufactured increases. In addition, since the groove 102 must be formed deeply, it becomes difficult to control the shape of the groove 102, the time required for etching increases, and the TAT (Turn Around Time) for manufacturing the semiconductor device increases. This creates a problem.

  An object of the present invention is to provide a technique capable of manufacturing a power MISFET having a desired gate breakdown voltage while suppressing an increase in parasitic capacitance.

  Another object of the present invention is to provide a technique capable of manufacturing a power MISFET capable of improving reliability.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A method for manufacturing a semiconductor device according to the present invention includes:
(A) forming a first conductivity type first semiconductor layer on a main surface of a first conductivity type semiconductor substrate;
(B) introducing a second conductivity type impurity having a polarity opposite to the first conductivity type into the semiconductor substrate to form a second conductivity type second semiconductor layer;
(C) forming a first groove portion penetrating the second semiconductor layer in a first region and forming a second groove portion penetrating the second semiconductor layer in a second region on the main surface of the semiconductor substrate;
(D) forming a first insulating film in the first groove and in the second groove;
(E) forming a first conductive film on the semiconductor substrate in the presence of the first insulating film, and embedding the first groove and the second groove with the first conductive film;
(F) patterning the first conductive film, and in the first region, the first conductive film outside the first groove and the first depth from the opening of the first groove by a first depth; 1 conductive film is removed, and in the second region, the second groove portion is embedded, leaving the first conductive film extending a predetermined amount outside the second groove portion, and the second region in the second region. Forming a third groove in the first conductive film extending out of the groove;
(G) introducing a first conductivity type impurity into the second semiconductor layer in the first region, and forming a first conductivity type third semiconductor layer in the second semiconductor layer adjacent to the first groove portion; ,
(H) After the step (f), a step of forming a second insulating film filling the first groove on the semiconductor substrate;
(I) patterning the second insulating film, removing the second insulating film outside the first groove in the first region, and forming the second insulating film outside the second groove in the second region. Forming a first opening reaching the first conductive film extending to
(J) After the step (i), a first wiring electrically connected to the third semiconductor layer is formed on the semiconductor substrate in the first region, and the first wiring is formed on the semiconductor substrate in the second region. Forming a second wiring electrically connected to the first conductive film under one opening;
Including
In the first region, the first semiconductor layer is a drain, the second semiconductor layer is a channel, and the third semiconductor layer is a source.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, it is possible to manufacture a power MISFET having a desired gate breakdown voltage while suppressing an increase in parasitic capacitance. Further, since the interlayer insulating film formed on the gate electrode can be formed with a film thickness that ensures a sufficient gate breakdown voltage, the reliability of the power MISFET can be improved.

It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 3 of this invention. FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 4 of this invention. It is a principal part top view in the manufacturing process of the semiconductor device which is Embodiment 4 of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which the present inventors examined. FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21;

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. Further, in the drawings used for the description of the following embodiments, hatching may be given even in a plan view for easy understanding of the positional relationship of members.

(Embodiment 1)
The semiconductor device of the first embodiment has, for example, a p-channel type trench gate type power MISFET. A method of manufacturing the semiconductor device according to the first embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 1, p-type (first conductivity type) impurity (for example, B (boron)) is introduced into the surface (main surface) of p ⁺ -type single crystal silicon substrate 1 into which p (type B) boron is introduced at a high concentration. A semiconductor substrate obtained by epitaxial growth of a p ⁻ type single crystal silicon layer (first semiconductor layer) 2 doped with a p type impurity (for example, B) having a lower concentration than the ⁺ type single crystal silicon substrate 1 (hereinafter simply referred to as a substrate). Prepare). In this substrate, a power MISFET gate electrode, an active cell region (first region) ACA in which active cells including a source and a drain are formed in a later step, and a wiring electrically connected to the gate electrode of the power MISFET are formed. A gate wiring region (second region) GLA and a termination region TNA in which a guard ring region is formed. The p ⁺ type single crystal silicon substrate 1 and the p ⁻ type single crystal silicon layer 2 become drain regions of the power MISFET in a later process. Subsequently, for example, the silicon oxide film 3 is formed by thermally oxidizing the surface (main surface) of the p ⁻ -type single crystal silicon layer 2.

  Next, after depositing a silicon nitride film (not shown) on the silicon oxide film 3, the silicon nitride film is etched using a photoresist film (not shown) patterned by photolithography as a mask. Then, the silicon nitride film is patterned. Subsequently, the field insulating film 4 is formed by performing a thermal oxidation process on the substrate.

Next, an n-type (second conductivity type) impurity (for example, P (phosphorus)) is introduced into the p ⁻ -type single crystal silicon layer 2 using a photoresist film (not shown) patterned by photolithography as a mask. . Subsequently, an n ⁻ type semiconductor region (second semiconductor layer) 5 is formed by performing heat treatment on the substrate. The n ⁻ type semiconductor region 5 formed in the active cell region ACA in which the gate electrode is formed in a later process becomes a channel region of the power MISFET of the first embodiment.

  Next, after the silicon oxide film 6 is deposited on the substrate, the silicon oxide film 6 and the silicon oxide film 3 are etched by using a photoresist film (not shown) patterned by photolithography as a mask. The silicon film 6 and the silicon oxide film 3 are patterned. Subsequently, by etching the substrate using the silicon oxide film 6 and the silicon oxide film 3 as a mask, a groove (first groove) 7 is formed in the active cell region ACA, and a groove (second groove) 8 is formed in the gate wiring region GLA. Form. The groove part 7 is formed so as to be arranged in a plurality in a cross section (first cross section) in a direction intersecting with a direction (first direction) in which the groove part 7 extends.

  Next, after removing the silicon oxide films 6 and 3 by etching, as shown in FIG. 2, a gate oxide film (first insulating film) 9 having a thickness of about 70 nm is formed by subjecting the substrate to thermal oxidation treatment. To do. Subsequently, a polycrystalline silicon film (first conductive film) 10 is deposited on the substrate by a CVD (Chemical Vapor Deposition) method, and the trenches 7 and 8 are filled with the polycrystalline silicon film 10. Next, for example, B (boron) is introduced into the polycrystalline silicon film 10.

  Here, FIG. 3 is a plan view of the main part of the substrate in the next process, and FIGS. 4 and 5 are cross-sectional views taken along lines AA and BB in FIG. 3, respectively. FIG. 4 shows the same cross section as the cross section shown in FIG. 2 used for the description of the previous step. In each of the cross-sectional views for explaining the subsequent steps, the drawing with the symbol A shows the same cross section as FIG. 4, and the drawing with the reference B shows the same cross section as FIG. It is.

  After the polycrystalline silicon film 10 is formed, as shown in FIGS. 3 to 5, the gate wiring region GLA is covered with a photoresist film (not shown) patterned by a photolithography technique, and the photoresist film is formed. The polycrystalline silicon film 10 is etched as a mask. Thereby, in the active cell region ACA, the polycrystalline silicon film 10 is left only in the trench 7, and the gate electrode 11 can be formed from the polycrystalline silicon film 10 in the trench 7. In the gate wiring region GLA, the polycrystalline silicon film 10 is patterned so as to fill in the groove portion 8 and partly remain outside the groove portion 8 continuously from the groove portion 8 and is electrically connected to the gate electrode 11. A lead electrode 12 is formed. Further, a slit (third groove) 14 extending from the end of the gate lead electrode 12 is formed in the gate lead electrode 12 outside the groove portion 8. By making the direction in which the slit 14 extends intersect with the direction in which the grooves 7 and 8 extend (direction in which the gate extraction electrode 12 extends), the gate extraction electrode 12 is divided by the slit 14. A malfunction can be prevented. In the termination region TNA, the polycrystalline silicon film 10 is removed.

  Incidentally, d1 is the film thickness of the polycrystalline silicon film 10 (gate lead electrode 12) outside the groove portion 8, and d2 is the amount by which the polycrystalline silicon film 10 in the groove portion 7 is over-etched, that is, from the opening of the groove portion 7. This is the depth to the surface of the polycrystalline silicon film 10 (gate electrode 11) in the trench 7. In the first embodiment, the width of the slit 14 and the interval between the slits 14 are set so that the volume of the slit 14 and the volume of the groove 7 above the gate electrode 11 are the same.

  Next, as shown in FIG. 6, a silicon oxide film 15 having a thickness of about 20 nm is formed by performing heat treatment on the substrate. At this time, as shown in FIG. 7 in which the vicinity of the trench 7 is enlarged, the gate oxide film 9 and the silicon oxide film 15 are doubled on the side wall 7A from the opening of the trench 7 to the surface of the gate electrode 11. The film is formed in a state.

Subsequently, by introducing a p-type impurity (for example, BF ₂ (boron difluoride)) into the n ⁻ -type semiconductor region 5 using a photoresist film (not shown) patterned by photolithography as a mask, activation is performed. A p ⁺ type semiconductor region (third semiconductor layer) 16 is formed in the n ⁻ type semiconductor region 5 of the cell region ACA, and a p ⁺ type guard ring region 17 is formed in the termination region TNA. The p ⁺ type semiconductor region 16 becomes the source of the trench gate type power MISFET of the first embodiment. The p ⁺ type guard ring region 17 is formed so as to surround the active cell region ACA and the gate wiring region GLA in a plane. In the step of introducing the p-type impurity, as described above, the double silicon oxide film of the gate oxide film 9 and the silicon oxide film 15 is formed on the side wall from the opening of the groove 7 to the surface of the gate electrode 11. Is formed. This prevents p-type impurities from being introduced into the n ⁻ -type semiconductor region 5 from the side wall of the trench 7 and optimizes the concentration profile of the p ⁺ -type semiconductor region 16. That is, it is possible to prevent a problem that an undesirable p ⁺ type semiconductor region 16A (see FIG. 7) is formed below the p ⁺ type semiconductor region 16 in a desired formation range. In addition, it is possible to prevent the p-type impurity from being introduced into the gate electrode 11 from the side wall of the groove portion 7 and to secure the gate breakdown voltage.

Subsequently, an n-type impurity (for example, P (phosphorus)) is introduced into the n ⁻ -type semiconductor region 5 using a photoresist film (not shown) patterned by the photolithography technique as a mask, thereby forming the active cell region ACA. An n ⁺ type semiconductor region 18 is formed in the n ⁻ type semiconductor region 5.

  Next, as shown in FIGS. 8 and 9, a silicon oxide film 19 having a thickness of about 900 to 1100 mm is deposited on the substrate by a CVD method. Subsequently, a BPSG (Boro-Phospho Silicate Glass) film (second insulating film) 20 having a thickness of about 4000 to 5000 mm is deposited on the silicon oxide film (second insulating film) 19 by the CVD method. Subsequently, by subjecting the substrate to a heat treatment at about 900 ° C., the BPSG film 20 is fluidized and the step on the surface of the BPSG film 20 is relaxed.

  Here, since the BPSG film 20 flows into the groove 7 on the gate electrode 11, if the slit 14 (see also FIGS. 3 and 5) is not formed in the gate extraction electrode 12 outside the groove 8, the active region The total film thickness TC1 of the silicon oxide film 15, the silicon oxide film 19 and the BPSG film 20 in the cell area ACA (excluding the inside of the trench 7) is equal to the amount of the flow of the total film thickness TC1, for example, the silicon oxide film 15 in the gate wiring area GLA. The total thickness TL1 of the silicon oxide film 19 and the BPSG film 20 is smaller. On the other hand, in the first embodiment, since the slit 14 is formed, the BPSG film 20 flows into the slit 14. Thereby, for example, the total film thickness TL1 of the silicon oxide film 15, the silicon oxide film 19 and the BPSG film 20 in the gate wiring region GLA is changed to the silicon oxide film 15, the silicon oxide film 19 and the active cell region ACA (except in the trench 7). It becomes possible to make the total thickness TC1 or less of the BPSG film 20. The relationship between the total film thickness of the silicon oxide film 15, the silicon oxide film 19, and the BPSG film 20 in each of these regions and the process will be described in more detail when the next process is described.

Next, as shown in FIGS. 10 to 12, the BPSG film 20, the silicon oxide film 19, and the silicon oxide film 15 are patterned by etching using a photoresist film (not shown) patterned by photolithography as a mask. To do. As a result, in the active cell region ACA, the BPSG film 20, the silicon oxide film 19 and the silicon oxide film 15 are etched back, and the BPSG film 20, the silicon oxide film 19 and the silicon oxide film 15 outside the trench 7 are They are removed, leaving a predetermined amount of them in the groove 7. In the gate wiring region GLA, an opening (first opening) 21 reaching the gate extraction electrode 12 is formed in the BPSG film 20, the silicon oxide film 19, and the silicon oxide film 15 outside the trench 7. In the termination region TNA, an opening 22 reaching the p ⁺ type guard ring region is formed.

  By the way, when the slit 14 is not formed as described above, the total film thickness TC1 of the silicon oxide film 15, the silicon oxide film 19 and the BPSG film 20 in the active cell region ACA (excluding the inside of the trench 7) is the gate It becomes thinner than the total film thickness TL1 of the silicon oxide film 15, the silicon oxide film 19, and the BPSG film 20 in the wiring region GLA. Therefore, when the BPSG film 20, the silicon oxide film 19 and the silicon oxide film 15 are etched and the opening 21 reaches the gate lead electrode 12, the BPSG film 20, the silicon oxide film 19 and the oxide film on the gate electrode 11 are completely removed. The total film thickness of the silicon film 15 may be insufficient to maintain a desired gate breakdown voltage. On the other hand, as described above with reference to FIG. 8, in the first embodiment, the total thickness TL1 of the silicon oxide film 15, the silicon oxide film 19 and the BPSG film 20 in the gate wiring region GLA is set to the active cell region ACA (groove portion 7). The total film thickness TC1 of the silicon oxide film 15, the silicon oxide film 19, and the BPSG film 20 can be set to be equal to or less than the total film thickness TC1. By setting the total film thicknesses TC1 and TL1 of the silicon oxide film 15, the silicon oxide film 19, and the BPSG film 20, the opening 21 is completely formed when the BPSG film 20, the silicon oxide film 19, and the silicon oxide film 15 are patterned. Even when the gate lead-out electrode 12 is reached, the silicon oxide film 15, the silicon oxide film 19 and the BPSG film 20 in the trench 7 can be left completely buried without being etched back. After the opening 21 has completely reached the gate lead electrode 12, the etch back is advanced until the total film thickness TG1 of the silicon oxide film 15, the silicon oxide film 19 and the BPSG film 20 in the groove 7 reaches a desired film thickness. . Thereby, in the trench gate type power MISFET of the first embodiment, a desired gate breakdown voltage can be secured. Further, when the depth d2 (see FIG. 4) from the opening of the trench 7 to the surface of the gate electrode 11 in the trench 7 is equal to the film thickness d1 (see FIG. 4) of the gate extraction electrode 12 outside the trench 8. Appropriately set the width of the slit 14 and the interval at which the slit 14 is arranged, for example, the groove 7 and the width of the slit 14 have the same dimension, and the interval between the adjacent grooves 7 and the interval between the adjacent slits 14 So that the total thickness TL1 of the silicon oxide film 15, the silicon oxide film 19 and the BPSG film 20 in the gate wiring region GLA is changed to the silicon oxide film in the active cell region ACA (except in the trench 7). 15, the total thickness TC1 of the silicon oxide film 19 and the BPSG film 20 can be made equal. Furthermore, the film thickness d1 (see FIG. 4) of the gate lead electrode 12 outside the trench 8 is thicker than the depth d2 (see FIG. 4) from the opening of the trench 7 to the surface of the gate electrode 11 in the trench 7. Is set, the total film thickness TL1 of the silicon oxide film 15, the silicon oxide film 19 and the BPSG film 20 in the gate wiring region GLA is set to the silicon oxide film 15 and the silicon oxide film 19 in the active cell region ACA (except in the trench 7). And the total film thickness TC1 of the BPSG film 20 can be made equal to or less.

Further, the inventors reduce the upper surface of the gate electrode 11 in the depth direction of the groove portion 7 without forming the slit 14, so that the groove portion can be obtained even when the opening 21 reaches the gate extraction electrode 12 completely. 7 has been studied on a technique capable of making the total film thickness TG1 of the silicon oxide film 15, the silicon oxide film 19 and the BPSG film 20 in the film 7 sufficient to ensure a desired gate breakdown voltage. However, if the upper surface of the gate electrode 11 is lowered in the depth direction of the trench 7, it becomes necessary to deepen the p ⁺ type semiconductor region 16 serving as the source. When the source is deepened, the punch-through breakdown voltage is lowered, so that it is necessary to deepen the n ⁻ type semiconductor region 5 serving as a channel. When the n ⁻ type semiconductor region 5 to be a channel is deepened, the groove 7 penetrating the n ⁻ type semiconductor region 5 needs to be deepened. As the trench 7 becomes deeper, the parasitic capacitance between the gate and the source increases, resulting in a problem that the switching loss increases. Further, since the depth variation increases when the groove 7 is deeper than when it is shallow, the p ⁻ type single crystal that penetrates the n ⁻ type semiconductor region 5 that becomes the channel of the trench gate type power MISFET in the groove 7 and becomes the drain. The portion reaching the silicon layer 2 increases. As a result, a parasitic capacitance between the gate and the drain generated between the gate electrode 11 and the p ⁻ -type single crystal silicon layer 2 increases, resulting in an increase in switching loss of the trench gate type power MISFET. Further, p ⁺ -type semiconductor region 16 and the n serving as the source of the trench gate type power MISFET ^- impurities -type semiconductor regions 5 ^- -type semiconductor region to 5 to a deeply formed p ⁺ -type semiconductor region 16 and the n The time required for the heat treatment for diffusion increases, resulting in a problem that the TAT (Turn Around Time) for manufacturing the semiconductor device increases. Further, since the groove portion 7 must be formed deeply, it becomes difficult to control the shape of the groove portion 7, and the time required for etching increases, and TAT (Turn Around Time) for manufacturing a semiconductor device increases. This causes a malfunction. On the other hand, according to the first embodiment, a desired gate breakdown voltage is ensured for the total film thickness TG1 of the silicon oxide film 15, the silicon oxide film 19 and the BPSG film 20 in the groove 7 without forming the groove 7 deeply. Therefore, these problems can be solved. Even when the first embodiment is applied, the slit 14 can be removed simultaneously with the portions other than the gate wiring region GLA and the gate electrode 11 by photolithography after the polycrystalline silicon 10 is formed. , Process steps will not increase.

Next, as shown in FIGS. 13 and 14, a TiW (titanium tungsten) film 23 having a film thickness of about 1000 to 2200 mm is deposited as a barrier conductor film on the substrate by, for example, sputtering, and then the substrate is subjected to heat treatment. Subsequently, an Al (aluminum) film 24 having a thickness of about 26000 to 55000 mm is deposited on the TiW film 23 by, eg, sputtering. The barrier conductor film plays a role of preventing an undesired reaction layer from being formed by contact between Al and the substrate (Si). In the first embodiment, the Al film means a film containing Al as a main component, and may contain other metals. Subsequently, the TiW film 23 and the Al film 24 are etched using the photoresist film patterned by the photolithography technique as a mask, whereby a gate wiring (second wiring) 25 electrically connected to the gate lead electrode 12, power A source pad (source electrode (first wiring)) 26 electrically connected to the p ⁺ type semiconductor region 16 serving as a source region of the MISFET, a wiring 27 electrically connected to the p ⁺ type guard ring region 17, and a gate wiring A gate pad (gate electrode) that is electrically connected to 25 is formed. The gate pad is formed in a region not shown in FIGS.

  Although illustration is omitted, after forming the gate wiring 25, the source pad 26, the wiring 27, and the gate pad, a polyimide resin film, for example, as a protective film is applied to the upper portion of the substrate, and then exposed and developed. The polyimide resin film on the pad and source pad 26 is removed to form an opening.

Next, after protecting the surface of the substrate with a tape or the like, the back surface of the p ⁺ type single crystal silicon substrate 1 is ground with the protective surface on the lower side. After peeling off the tape, for example, a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film are sequentially deposited on the back surface of the p ⁺ type single crystal silicon substrate 1 by a sputtering method. These laminated films are formed. This laminated film becomes an extraction electrode (drain electrode) of the drain (p ⁺ type single crystal silicon substrate 1 and p ⁻ type single crystal silicon layer 2).

  Subsequently, a bump electrode made of, for example, Au or the like is formed on the opening formed in the polyimide resin film, and then the substrate in a wafer state is diced along, for example, divided regions (not shown) to obtain individual chips. Divide into Thereafter, the individual chips are mounted on, for example, a lead frame (mounting plate) having external terminals and sealed (mounted) with a resin or the like to manufacture the semiconductor device of the first embodiment.

(Embodiment 2)
Similar to the semiconductor device of the first embodiment, the semiconductor device of the second embodiment has, for example, a p-channel type power MISFET. A method of manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS.

  The manufacturing process of the semiconductor device of the second embodiment is the same up to the process of forming the BPSG film 20 in the first embodiment (see FIGS. 8 and 9), but the slit 14 ( 3 and 5) is not formed. After that, as shown in FIG. 15, the gate wiring region GLA and the termination region TNA on the substrate are covered with a photoresist film R1 patterned by a photolithography technique, and the BPSG film 20, the silicon oxide film 19 and the oxidation cell in the active cell region ACA are covered. The silicon film 15 is etched. Thereby, in the active cell region ACA, the BPSG film 20, the silicon oxide film 19 and the silicon oxide film 15 outside the trench 7 are removed, and in the trench 7, the silicon oxide film 15, the silicon oxide film 19 and the BPSG film 20 are removed. The total film thickness TG1 is set to a desired film thickness.

  Next, after removing the photoresist film R1, as shown in FIG. 16, regions other than the regions where the openings 21 and 22 are formed on the substrate by the photoresist film R2 newly patterned by the photolithography technique. BPSG film 20, silicon oxide film 19 and silicon oxide film 15 are etched. Thereby, the openings 21 and 22 can be formed without reducing the BPSG film 20 and the silicon oxide film 19 in the groove 7. That is, also in the trench gate type power MISFET of the second embodiment, it is possible to ensure a desired gate breakdown voltage.

  Thereafter, the semiconductor device according to the second embodiment is manufactured through the same steps as those described with reference to FIGS. 13 and 14 in the first embodiment.

  According to the second embodiment as described above, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
The semiconductor device of the third embodiment has, for example, a p-channel type power MISFET, as in the semiconductor devices of the first and second embodiments. A method of manufacturing the semiconductor device according to the third embodiment will be described with reference to FIGS.

  The manufacturing process of the semiconductor device of the third embodiment is the same up to the process of forming the BPSG film 20 in the first embodiment (see FIG. 8 and FIG. 9), but the slit 14 ( 3 and 5) is not formed. Thereafter, as shown in FIG. 17, the BPSG film 20 and the silicon oxide film 19 are etched back, and the BPSG film 20 and the silicon oxide film 19 outside the trench 7 are removed. Here, the total film thickness of the BPSG film 20, the silicon oxide film 19 and the silicon oxide film 15 remaining in the trench 7 is confirmed. Subsequently, as shown in FIG. 18, a silicon oxide film (second insulating film, third insulating film) 19A similar to the silicon oxide film 19 and a BPSG film (second insulating film, similar to the BPSG film 20) are formed on the substrate. Third insulating film) 20A is sequentially deposited, and the substrate is subjected to heat treatment to fluidize BPSG film 20A.

  At this time, when the BPSG film 20 and the silicon oxide film 19 are etched back, the total film thickness of the BPSG film 20, the silicon oxide film 19 and the silicon oxide film 15 remaining in the trench 7 ensures a desired gate breakdown voltage. If sufficient, the BPSG film 20A, the silicon oxide film 19A, and the silicon oxide film 15 are etched to form openings 21 and 22, and then, in the first embodiment, FIG. 13 and FIG. The semiconductor device according to the third embodiment is manufactured through the same process as described with reference to FIG. On the other hand, when the BPSG film 20 and the silicon oxide film 19 are etched back, the total thickness of the BPSG film 20, the silicon oxide film 19 and the silicon oxide film 15 remaining in the trench 7 ensures a desired gate breakdown voltage. If not sufficient, the BPSG film 20A and the silicon oxide film 19A are etched back, and the BPSG film 20A and the silicon oxide film 19A outside the trench 7 are removed. Here, the total film thickness of the BPSG films 20 and 20A, the silicon oxide films 19 and 19A, and the silicon oxide film 15 remaining in the trench 7 is confirmed, and if it is not sufficient to secure a desired gate breakdown voltage, The openings 21 and 22 are formed after repeating the step of depositing the silicon oxide film 19A and the BPSG film 20A and the step of etching back the laminated film until the total film thickness is reached. In such a trench gate type power MISFET of the third embodiment, a desired gate breakdown voltage can be secured.

(Embodiment 4)
The semiconductor device of the fourth embodiment has, for example, a p-channel type power MISFET, like the semiconductor devices of the first to third embodiments. A method of manufacturing the semiconductor device according to the fourth embodiment will be described with reference to FIGS.

  The manufacturing process of the semiconductor device according to the fourth embodiment is almost the same as the manufacturing process of the semiconductor device according to the first embodiment. However, as shown in FIG. Instead of the slits 14 (see FIGS. 3 and 5), a plurality of planar circular openings (third groove portions) 14A are formed. It can be exemplified that the opening diameter of the opening 14 </ b> A is approximately the same as the width of the slit 14. By forming the planar circular opening 14A in place of the slit 14, the area where the gate wiring 25 (see FIGS. 13 and 14) formed in a later process and the gate extraction electrode 12 come into contact can be increased. it can. Thereby, gate resistance can be reduced.

  Further, as shown in FIG. 20, a slit (third groove portion) 14 </ b> B that does not reach the end of the gate extraction electrode 12 may be formed instead of the slit 14. Thus, by forming the slit 14B surrounded by the gate extraction electrode 12 on a plane, the gate extraction electrode 12 can increase the cross-sectional area in the direction perpendicular to the current path, and therefore the gate resistance can be reduced. Can do. Further, from the viewpoint that the cross-sectional area in the direction perpendicular to the current path can be increased, the same effect can be obtained even when the planar circular opening 14A is formed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the manufacturing process of a semiconductor device including a trench gate type power MISFET has been described. Similarly, a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor) having a gate electrode in a groove formed in a substrate. The same manufacturing process can be applied to this manufacturing process.

  The semiconductor device manufacturing method of the present invention can be applied to a manufacturing process of a semiconductor device having, for example, a trench gate type power MISFET.

1 p ⁺ type single crystal silicon substrate 2 p ⁻ type single crystal silicon layer (first semiconductor layer)
3 Silicon oxide film 4 Field insulating film 5 n ^- type semiconductor region (second semiconductor layer)
6 Silicon oxide film 7 Groove (first groove)
7A Side wall 8 Groove (second groove)
9 Gate oxide film (first insulating film)
10 Polycrystalline silicon film (first conductive film)
11 Gate electrode 12 Gate lead electrode 14 Slit (third groove)
14A opening (third groove)
14B Slit (third groove)
15 Silicon oxide film 16 p ⁺ type semiconductor region (third semiconductor layer)
17 p ⁺ type guard ring region 18 n ⁺ type semiconductor region 19 Silicon oxide film (second insulating film)
19A Silicon oxide film (second insulating film, third insulating film)
20 BPSG film (second insulating film)
20A BPSG film (second insulating film, third insulating film)
21 opening (first opening)
22 Opening 23 TiW film 24 Al film 25 Gate wiring (second wiring)
26 Source pad (source electrode (first wiring))
27 Wiring 101 Substrate 102, 103 Groove 104 Gate electrode 105 Gate wiring 106 Interlayer insulating film 107 Openings 108, 109, 110 Semiconductor layer ACA Active cell region (first region)
GLA gate wiring area (second area)
R1, R2 Photoresist film TC, TL, TG film thickness TC1, TL1, TG1 film thickness TNA termination region

Claims (11)

A semiconductor device having a first region in which a MISFET is formed on a semiconductor substrate and a second region in which a wiring to which a gate electrode of the MISFET is electrically connected is formed,
A first conductivity type first semiconductor layer formed on the semiconductor substrate;
A second conductivity type second semiconductor layer formed on the first semiconductor layer and having a conductivity type opposite to the first conductivity type;
A first groove formed to penetrate the second semiconductor layer in the first region;
A second groove formed to penetrate the second semiconductor layer of the second region;
A first insulating film formed in the first groove in the first region;
In the second region, the first insulating film formed in the second trench and on the second semiconductor layer outside the second trench,
A first conductive film formed in the first region by being embedded in the first groove through the first insulating film;
In the second region, the first conductive film formed by being embedded in the second groove portion through the first insulating film and formed on the first insulating film outside the second groove portion When,
A third semiconductor layer of the first conductivity type formed in the second semiconductor layer at a position adjacent to the first groove in the first region;
A second insulating film formed on the first conductive film in the second region;
A first opening formed in the second insulating film so as to reach the first conductive film in the second region;
Have
The first conductive film in the first region constitutes a gate electrode of the MISFET;
The first conductive film in the second region constitutes a wiring electrically connected to the gate electrode of the MISFET,
In the first region, the first conductive film embedded in the first groove is formed so that the surface thereof is lower than the surface of the second semiconductor layer,
In the first region, the second insulating film is formed on the first conductive film so as to fill the first groove portion,
In the second region, a third groove portion is formed in the first conductive film formed outside the second groove portion. The semiconductor device according to claim 1,
In the first region, the first semiconductor layer is a drain of the MISFET, the second semiconductor layer is a channel of the MISFET, and the third semiconductor layer is a source of the MISFET. The semiconductor device according to claim 1 or 2,
In the first region, a first wiring is formed on the third semiconductor layer and the second insulating film so as to be in electrical contact with the third semiconductor layer and not in contact with the first conductive film. Is formed,
In the second region, second wiring is formed on the second insulating film inside the first opening and outside the first opening so as to be in electrical contact with the first conductive film. A featured semiconductor device. The semiconductor device according to any one of claims 1 to 3,
In the first region, the second insulating film is formed in the first groove portion, and is not formed outside the first groove portion. The semiconductor device according to any one of claims 1 to 4,
In the planar shape, the first opening is formed at a position closer to the first region than the third groove. The semiconductor device according to claim 5,
In the planar shape, the direction in which the third groove portion extends is a direction perpendicular to the direction in which the first opening extends. The semiconductor device according to claim 5,
In the planar shape, the third groove portion is formed so as to be surrounded by the first conductive film. The semiconductor device according to claim 7,
In the planar shape, the third groove portion has a circular shape. The semiconductor device according to claim 7,
In the planar shape, the third groove portion is rectangular. The semiconductor device according to any one of claims 1 to 9,
The semiconductor device according to claim 1, wherein the first conductive film is a polycrystalline silicon film. The semiconductor device according to claim 1,
The semiconductor device, wherein the second insulating film is a silicon oxide film.

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